package/rt2x00/src/rt2500usb.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500usb
  23         Abstract: Data structures and registers for the rt2500usb module.
  24         Supported chipsets: RT2570.
  25  */
  26
  27 #ifndef RT2500USB_H
  28 #define RT2500USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF2522                          0x0000
  34 #define RF2523                          0x0001
  35 #define RF2524                          0x0002
  36 #define RF2525                          0x0003
  37 #define RF2525E                         0x0005
  38 #define RF5222                          0x0010
  39
  40 /*
  41  * RT2570 version
  42  */
  43 #define RT2570_VERSION_B                2
  44 #define RT2570_VERSION_C                3
  45 #define RT2570_VERSION_D                4
  46
  47 /*
  48  * Signal information.
  49  */
  50 #define MAX_RX_SSI                      -1
  51 #define MAX_RX_NOISE                    -110
  52 #define DEFAULT_RSSI_OFFSET             120
  53
  54 /*
  55  * Register layout information.
  56  */
  57 #define CSR_REG_BASE                    0x0400
  58 #define CSR_REG_SIZE                    0x0100
  59 #define EEPROM_BASE                     0x0000
  60 #define EEPROM_SIZE                     0x006a
  61 #define BBP_SIZE                        0x0060
  62
  63 /*
  64  * Control/Status Registers(CSR).
  65  * Some values are set in TU, whereas 1 TU == 1024 us.
  66  */
  67
  68 /*
  69  * MAC_CSR0: ASIC revision number.
  70  */
  71 #define MAC_CSR0                        0x0400
  72
  73 /*
  74  * MAC_CSR1: System control.
  75  */
  76 #define MAC_CSR1                        0x0402
  77
  78 /*
  79  * MAC_CSR2: STA MAC register 0.
  80  */
  81 #define MAC_CSR2                        0x0404
  82 #define MAC_CSR2_BYTE0                  FIELD16(0x00ff)
  83 #define MAC_CSR2_BYTE1                  FIELD16(0xff00)
  84
  85 /*
  86  * MAC_CSR3: STA MAC register 1.
  87  */
  88 #define MAC_CSR3                        0x0406
  89 #define MAC_CSR3_BYTE2                  FIELD16(0x00ff)
  90 #define MAC_CSR3_BYTE3                  FIELD16(0xff00)
  91
  92 /*
  93  * MAC_CSR4: STA MAC register 2.
  94  */
  95 #define MAC_CSR4                        0X0408
  96 #define MAC_CSR4_BYTE4                  FIELD16(0x00ff)
  97 #define MAC_CSR4_BYTE5                  FIELD16(0xff00)
  98
  99 /*
 100  * MAC_CSR5: BSSID register 0.
 101  */
 102 #define MAC_CSR5                        0x040a
 103 #define MAC_CSR5_BYTE0                  FIELD16(0x00ff)
 104 #define MAC_CSR5_BYTE1                  FIELD16(0xff00)
 105
 106 /*
 107  * MAC_CSR6: BSSID register 1.
 108  */
 109 #define MAC_CSR6                        0x040c
 110 #define MAC_CSR6_BYTE2                  FIELD16(0x00ff)
 111 #define MAC_CSR6_BYTE3                  FIELD16(0xff00)
 112
 113 /*
 114  * MAC_CSR7: BSSID register 2.
 115  */
 116 #define MAC_CSR7                        0x040e
 117 #define MAC_CSR7_BYTE4                  FIELD16(0x00ff)
 118 #define MAC_CSR7_BYTE5                  FIELD16(0xff00)
 119
 120 /*
 121  * MAC_CSR8: Max frame length.
 122  */
 123 #define MAC_CSR8                        0x0410
 124 #define MAC_CSR8_MAX_FRAME_UNIT         FIELD16(0x0fff)
 125
 126 /*
 127  * Misc MAC_CSR registers.
 128  * MAC_CSR9: Timer control.
 129  * MAC_CSR10: Slot time.
 130  * MAC_CSR11: IFS.
 131  * MAC_CSR12: EIFS.
 132  * MAC_CSR13: Power mode0.
 133  * MAC_CSR14: Power mode1.
 134  * MAC_CSR15: Power saving transition0
 135  * MAC_CSR16: Power saving transition1
 136  */
 137 #define MAC_CSR9                        0x0412
 138 #define MAC_CSR10                       0x0414
 139 #define MAC_CSR11                       0x0416
 140 #define MAC_CSR12                       0x0418
 141 #define MAC_CSR13                       0x041a
 142 #define MAC_CSR14                       0x041c
 143 #define MAC_CSR15                       0x041e
 144 #define MAC_CSR16                       0x0420
 145
 146 /*
 147  * MAC_CSR17: Manual power control / status register.
 148  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 149  * SET_STATE: Set state. Write 1 to trigger, self cleared.
 150  * BBP_DESIRE_STATE: BBP desired state.
 151  * RF_DESIRE_STATE: RF desired state.
 152  * BBP_CURRENT_STATE: BBP current state.
 153  * RF_CURRENT_STATE: RF current state.
 154  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 155  */
 156 #define MAC_CSR17                       0x0422
 157 #define MAC_CSR17_SET_STATE             FIELD16(0x0001)
 158 #define MAC_CSR17_BBP_DESIRE_STATE      FIELD16(0x0006)
 159 #define MAC_CSR17_RF_DESIRE_STATE       FIELD16(0x0018)
 160 #define MAC_CSR17_BBP_CURR_STATE        FIELD16(0x0060)
 161 #define MAC_CSR17_RF_CURR_STATE         FIELD16(0x0180)
 162 #define MAC_CSR17_PUT_TO_SLEEP          FIELD16(0x0200)
 163
 164 /*
 165  * MAC_CSR18: Wakeup timer register.
 166  * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
 167  * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
 168  * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
 169  */
 170 #define MAC_CSR18                       0x0424
 171 #define MAC_CSR18_DELAY_AFTER_BEACON    FIELD16(0x00ff)
 172 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
 173 #define MAC_CSR18_AUTO_WAKE             FIELD16(0x8000)
 174
 175 /*
 176  * MAC_CSR19: GPIO control register.
 177  */
 178 #define MAC_CSR19                       0x0426
 179
 180 /*
 181  * MAC_CSR20: LED control register.
 182  * ACTIVITY: 0: idle, 1: active.
 183  * LINK: 0: linkoff, 1: linkup.
 184  * ACTIVITY_POLARITY: 0: active low, 1: active high.
 185  */
 186 #define MAC_CSR20                       0x0428
 187 #define MAC_CSR20_ACTIVITY              FIELD16(0x0001)
 188 #define MAC_CSR20_LINK                  FIELD16(0x0002)
 189 #define MAC_CSR20_ACTIVITY_POLARITY     FIELD16(0x0004)
 190
 191 /*
 192  * MAC_CSR21: LED control register.
 193  * ON_PERIOD: On period, default 70ms.
 194  * OFF_PERIOD: Off period, default 30ms.
 195  */
 196 #define MAC_CSR21                       0x042a
 197 #define MAC_CSR21_ON_PERIOD             FIELD16(0x00ff)
 198 #define MAC_CSR21_OFF_PERIOD            FIELD16(0xff00)
 199
 200 /*
 201  * Collision window control register.
 202  */
 203 #define MAC_CSR22                       0x042c
 204
 205 /*
 206  * Transmit related CSRs.
 207  * Some values are set in TU, whereas 1 TU == 1024 us.
 208  */
 209
 210 /*
 211  * TXRX_CSR0: Security control register.
 212  */
 213 #define TXRX_CSR0                       0x0440
 214 #define TXRX_CSR0_ALGORITHM             FIELD16(0x0007)
 215 #define TXRX_CSR0_IV_OFFSET             FIELD16(0x01f8)
 216 #define TXRX_CSR0_KEY_ID                FIELD16(0x1e00)
 217
 218 /*
 219  * TXRX_CSR1: TX configuration.
 220  * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
 221  * TSF_OFFSET: TSF offset in MAC header.
 222  * AUTO_SEQUENCE: Let ASIC control frame sequence number.
 223  */
 224 #define TXRX_CSR1                       0x0442
 225 #define TXRX_CSR1_ACK_TIMEOUT           FIELD16(0x00ff)
 226 #define TXRX_CSR1_TSF_OFFSET            FIELD16(0x7f00)
 227 #define TXRX_CSR1_AUTO_SEQUENCE         FIELD16(0x8000)
 228
 229 /*
 230  * TXRX_CSR2: RX control.
 231  * DISABLE_RX: Disable rx engine.
 232  * DROP_CRC: Drop crc error.
 233  * DROP_PHYSICAL: Drop physical error.
 234  * DROP_CONTROL: Drop control frame.
 235  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 236  * DROP_TODS: Drop frame tods bit is true.
 237  * DROP_VERSION_ERROR: Drop version error frame.
 238  * DROP_MCAST: Drop multicast frames.
 239  * DROP_BCAST: Drop broadcast frames.
 240  */
 241 #define TXRX_CSR2                       0x0444
 242 #define TXRX_CSR2_DISABLE_RX            FIELD16(0x0001)
 243 #define TXRX_CSR2_DROP_CRC              FIELD16(0x0002)
 244 #define TXRX_CSR2_DROP_PHYSICAL         FIELD16(0x0004)
 245 #define TXRX_CSR2_DROP_CONTROL          FIELD16(0x0008)
 246 #define TXRX_CSR2_DROP_NOT_TO_ME        FIELD16(0x0010)
 247 #define TXRX_CSR2_DROP_TODS             FIELD16(0x0020)
 248 #define TXRX_CSR2_DROP_VERSION_ERROR    FIELD16(0x0040)
 249 #define TXRX_CSR2_DROP_MCAST            FIELD16(0x0200)
 250 #define TXRX_CSR2_DROP_BCAST            FIELD16(0x0400)
 251
 252 /*
 253  * RX BBP ID registers
 254  * TXRX_CSR3: CCK RX BBP ID.
 255  * TXRX_CSR4: OFDM RX BBP ID.
 256  */
 257 #define TXRX_CSR3                       0x0446
 258 #define TXRX_CSR4                       0x0448
 259
 260 /*
 261  * TX BBP ID registers
 262  * TXRX_CSR5: CCK TX BBP ID0.
 263  * TXRX_CSR5: CCK TX BBP ID1.
 264  * TXRX_CSR5: OFDM TX BBP ID0.
 265  * TXRX_CSR5: OFDM TX BBP ID1.
 266  */
 267 #define TXRX_CSR5                       0x044a
 268 #define TXRX_CSR6                       0x044c
 269 #define TXRX_CSR7                       0x044e
 270 #define TXRX_CSR8                       0x0450
 271
 272 /*
 273  * TXRX_CSR9: TX ACK time-out.
 274  */
 275 #define TXRX_CSR9                       0x0452
 276
 277 /*
 278  * TXRX_CSR10: Auto responder control.
 279  */
 280 #define TXRX_CSR10                      0x0454
 281 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
 282
 283 /*
 284  * TXRX_CSR11: Auto responder basic rate.
 285  */
 286 #define TXRX_CSR11                      0x0456
 287
 288 /*
 289  * ACK/CTS time registers.
 290  */
 291 #define TXRX_CSR12                      0x0458
 292 #define TXRX_CSR13                      0x045a
 293 #define TXRX_CSR14                      0x045c
 294 #define TXRX_CSR15                      0x045e
 295 #define TXRX_CSR16                      0x0460
 296 #define TXRX_CSR17                      0x0462
 297
 298 /*
 299  * TXRX_CSR18: Synchronization control register.
 300  */
 301 #define TXRX_CSR18                      0x0464
 302 #define TXRX_CSR18_OFFSET               FIELD16(0x000f)
 303 #define TXRX_CSR18_INTERVAL             FIELD16(0xfff0)
 304
 305 /*
 306  * TXRX_CSR19: Synchronization control register.
 307  * TSF_COUNT: Enable TSF auto counting.
 308  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 309  * TBCN: Enable Tbcn with reload value.
 310  * BEACON_GEN: Enable beacon generator.
 311  */
 312 #define TXRX_CSR19                      0x0466
 313 #define TXRX_CSR19_TSF_COUNT            FIELD16(0x0001)
 314 #define TXRX_CSR19_TSF_SYNC             FIELD16(0x0006)
 315 #define TXRX_CSR19_TBCN                 FIELD16(0x0008)
 316 #define TXRX_CSR19_BEACON_GEN           FIELD16(0x0010)
 317
 318 /*
 319  * TXRX_CSR20: Tx BEACON offset time control register.
 320  * OFFSET: In units of usec.
 321  * BCN_EXPECT_WINDOW: Default: 2^CWmin
 322  */
 323 #define TXRX_CSR20                      0x0468
 324 #define TXRX_CSR20_OFFSET               FIELD16(0x1fff)
 325 #define TXRX_CSR20_BCN_EXPECT_WINDOW    FIELD16(0xe000)
 326
 327 /*
 328  * TXRX_CSR21
 329  */
 330 #define TXRX_CSR21                      0x046a
 331
 332 /*
 333  * Encryption related CSRs.
 334  *
 335  */
 336
 337 /*
 338  * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
 339  */
 340 #define SEC_CSR0                        0x0480
 341 #define SEC_CSR1                        0x0482
 342 #define SEC_CSR2                        0x0484
 343 #define SEC_CSR3                        0x0486
 344 #define SEC_CSR4                        0x0488
 345 #define SEC_CSR5                        0x048a
 346 #define SEC_CSR6                        0x048c
 347 #define SEC_CSR7                        0x048e
 348
 349 /*
 350  * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
 351  */
 352 #define SEC_CSR8                        0x0490
 353 #define SEC_CSR9                        0x0492
 354 #define SEC_CSR10                       0x0494
 355 #define SEC_CSR11                       0x0496
 356 #define SEC_CSR12                       0x0498
 357 #define SEC_CSR13                       0x049a
 358 #define SEC_CSR14                       0x049c
 359 #define SEC_CSR15                       0x049e
 360
 361 /*
 362  * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
 363  */
 364 #define SEC_CSR16                       0x04a0
 365 #define SEC_CSR17                       0x04a2
 366 #define SEC_CSR18                       0X04A4
 367 #define SEC_CSR19                       0x04a6
 368 #define SEC_CSR20                       0x04a8
 369 #define SEC_CSR21                       0x04aa
 370 #define SEC_CSR22                       0x04ac
 371 #define SEC_CSR23                       0x04ae
 372
 373 /*
 374  * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
 375  */
 376 #define SEC_CSR24                       0x04b0
 377 #define SEC_CSR25                       0x04b2
 378 #define SEC_CSR26                       0x04b4
 379 #define SEC_CSR27                       0x04b6
 380 #define SEC_CSR28                       0x04b8
 381 #define SEC_CSR29                       0x04ba
 382 #define SEC_CSR30                       0x04bc
 383 #define SEC_CSR31                       0x04be
 384
 385 /*
 386  * PHY control registers.
 387  */
 388
 389 /*
 390  * PHY_CSR0: RF switching timing control.
 391  */
 392 #define PHY_CSR0                        0x04c0
 393
 394 /*
 395  * PHY_CSR1: TX PA configuration.
 396  */
 397 #define PHY_CSR1                        0x04c2
 398
 399 /*
 400  * MAC configuration registers.
 401  * PHY_CSR2: TX MAC configuration.
 402  * PHY_CSR3: RX MAC configuration.
 403  */
 404 #define PHY_CSR2                        0x04c4
 405 #define PHY_CSR3                        0x04c6
 406
 407 /*
 408  * PHY_CSR4: Interface configuration.
 409  */
 410 #define PHY_CSR4                        0x04c8
 411
 412 /*
 413  * BBP pre-TX registers.
 414  * PHY_CSR5: BBP pre-TX CCK.
 415  */
 416 #define PHY_CSR5                        0x04ca
 417 #define PHY_CSR5_CCK                    FIELD16(0x0003)
 418 #define PHY_CSR5_CCK_FLIP               FIELD16(0x0004)
 419
 420 /*
 421  * BBP pre-TX registers.
 422  * PHY_CSR6: BBP pre-TX OFDM.
 423  */
 424 #define PHY_CSR6                        0x04cc
 425 #define PHY_CSR6_OFDM                   FIELD16(0x0003)
 426 #define PHY_CSR6_OFDM_FLIP              FIELD16(0x0004)
 427
 428 /*
 429  * PHY_CSR7: BBP access register 0.
 430  * BBP_DATA: BBP data.
 431  * BBP_REG_ID: BBP register ID.
 432  * BBP_READ_CONTROL: 0: write, 1: read.
 433  */
 434 #define PHY_CSR7                        0x04ce
 435 #define PHY_CSR7_DATA                   FIELD16(0x00ff)
 436 #define PHY_CSR7_REG_ID                 FIELD16(0x7f00)
 437 #define PHY_CSR7_READ_CONTROL           FIELD16(0x8000)
 438
 439 /*
 440  * PHY_CSR8: BBP access register 1.
 441  * BBP_BUSY: ASIC is busy execute BBP programming.
 442  */
 443 #define PHY_CSR8                        0x04d0
 444 #define PHY_CSR8_BUSY                   FIELD16(0x0001)
 445
 446 /*
 447  * PHY_CSR9: RF access register.
 448  * RF_VALUE: Register value + id to program into rf/if.
 449  */
 450 #define PHY_CSR9                        0x04d2
 451 #define PHY_CSR9_RF_VALUE               FIELD16(0xffff)
 452
 453 /*
 454  * PHY_CSR10: RF access register.
 455  * RF_VALUE: Register value + id to program into rf/if.
 456  * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 457  * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
 458  * RF_PLL_LD: Rf pll_ld status.
 459  * RF_BUSY: 1: asic is busy execute rf programming.
 460  */
 461 #define PHY_CSR10                       0x04d4
 462 #define PHY_CSR10_RF_VALUE              FIELD16(0x00ff)
 463 #define PHY_CSR10_RF_NUMBER_OF_BITS     FIELD16(0x1f00)
 464 #define PHY_CSR10_RF_IF_SELECT          FIELD16(0x2000)
 465 #define PHY_CSR10_RF_PLL_LD             FIELD16(0x4000)
 466 #define PHY_CSR10_RF_BUSY               FIELD16(0x8000)
 467
 468 /*
 469  * STA_CSR0: FCS error count.
 470  * FCS_ERROR: FCS error count, cleared when read.
 471  */
 472 #define STA_CSR0                        0x04e0
 473 #define STA_CSR0_FCS_ERROR              FIELD16(0xffff)
 474
 475 /*
 476  * Statistic Register.
 477  * STA_CSR1: PLCP error.
 478  * STA_CSR2: LONG error.
 479  * STA_CSR3: CCA false alarm.
 480  * STA_CSR4: RX FIFO overflow.
 481  * STA_CSR5: Beacon sent counter.
 482  */
 483 #define STA_CSR1                        0x04e2
 484 #define STA_CSR2                        0x04e4
 485 #define STA_CSR3                        0x04e6
 486 #define STA_CSR4                        0x04e8
 487 #define STA_CSR5                        0x04ea
 488 #define STA_CSR6                        0x04ec
 489 #define STA_CSR7                        0x04ee
 490 #define STA_CSR8                        0x04f0
 491 #define STA_CSR9                        0x04f2
 492 #define STA_CSR10                       0x04f4
 493
 494 /*
 495  * RF registers.
 496  */
 497 #define RF1_TUNER                       FIELD32(0x00020000)
 498 #define RF3_TUNER                       FIELD32(0x00000100)
 499 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 500
 501 /*
 502  * EEPROM contents.
 503  */
 504
 505 /*
 506  * HW MAC address.
 507  */
 508 #define EEPROM_MAC_ADDR_0               0x0002
 509 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 510 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 511 #define EEPROM_MAC_ADDR1                0x0003
 512 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 513 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 514 #define EEPROM_MAC_ADDR_2               0x0004
 515 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 516 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 517
 518 /*
 519  * EEPROM antenna.
 520  * ANTENNA_NUM: Number of antenna's.
 521  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 522  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 523  * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
 524  * DYN_TXAGC: Dynamic TX AGC control.
 525  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 526  * RF_TYPE: Rf_type of this adapter.
 527  */
 528 #define EEPROM_ANTENNA                  0x000b
 529 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 530 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 531 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 532 #define EEPROM_ANTENNA_LED_MODE         FIELD16(0x01c0)
 533 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 534 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 535 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 536
 537 /*
 538  * EEPROM NIC config.
 539  * CARDBUS_ACCEL: 0: enable, 1: disable.
 540  * DYN_BBP_TUNE: 0: enable, 1: disable.
 541  * CCK_TX_POWER: CCK TX power compensation.
 542  */
 543 #define EEPROM_NIC                      0x000c
 544 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0001)
 545 #define EEPROM_NIC_DYN_BBP_TUNE         FIELD16(0x0002)
 546 #define EEPROM_NIC_CCK_TX_POWER         FIELD16(0x000c)
 547
 548 /*
 549  * EEPROM geography.
 550  * GEO: Default geography setting for device.
 551  */
 552 #define EEPROM_GEOGRAPHY                0x000d
 553 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0x0f00)
 554
 555 /*
 556  * EEPROM BBP.
 557  */
 558 #define EEPROM_BBP_START                0x000e
 559 #define EEPROM_BBP_SIZE                 16
 560 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 561 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 562
 563 /*
 564  * EEPROM TXPOWER
 565  */
 566 #define EEPROM_TXPOWER_START            0x001e
 567 #define EEPROM_TXPOWER_SIZE             7
 568 #define EEPROM_TXPOWER_1                FIELD16(0x00ff)
 569 #define EEPROM_TXPOWER_2                FIELD16(0xff00)
 570
 571 /*
 572  * EEPROM Tuning threshold
 573  */
 574 #define EEPROM_BBPTUNE                  0x0030
 575 #define EEPROM_BBPTUNE_THRESHOLD        FIELD16(0x00ff)
 576
 577 /*
 578  * EEPROM BBP R24 Tuning.
 579  */
 580 #define EEPROM_BBPTUNE_R24              0x0031
 581 #define EEPROM_BBPTUNE_R24_LOW          FIELD16(0x00ff)
 582 #define EEPROM_BBPTUNE_R24_HIGH         FIELD16(0xff00)
 583
 584 /*
 585  * EEPROM BBP R25 Tuning.
 586  */
 587 #define EEPROM_BBPTUNE_R25              0x0032
 588 #define EEPROM_BBPTUNE_R25_LOW          FIELD16(0x00ff)
 589 #define EEPROM_BBPTUNE_R25_HIGH         FIELD16(0xff00)
 590
 591 /*
 592  * EEPROM BBP R24 Tuning.
 593  */
 594 #define EEPROM_BBPTUNE_R61              0x0033
 595 #define EEPROM_BBPTUNE_R61_LOW          FIELD16(0x00ff)
 596 #define EEPROM_BBPTUNE_R61_HIGH         FIELD16(0xff00)
 597
 598 /*
 599  * EEPROM BBP VGC Tuning.
 600  */
 601 #define EEPROM_BBPTUNE_VGC              0x0034
 602 #define EEPROM_BBPTUNE_VGCUPPER         FIELD16(0x00ff)
 603
 604 /*
 605  * EEPROM BBP R17 Tuning.
 606  */
 607 #define EEPROM_BBPTUNE_R17              0x0035
 608 #define EEPROM_BBPTUNE_R17_LOW          FIELD16(0x00ff)
 609 #define EEPROM_BBPTUNE_R17_HIGH         FIELD16(0xff00)
 610
 611 /*
 612  * RSSI <-> dBm offset calibration
 613  */
 614 #define EEPROM_CALIBRATE_OFFSET         0x0036
 615 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
 616
 617 /*
 618  * BBP content.
 619  * The wordsize of the BBP is 8 bits.
 620  */
 621
 622 /*
 623  * BBP_R2: TX antenna control
 624  */
 625 #define BBP_R2_TX_ANTENNA               FIELD8(0x03)
 626 #define BBP_R2_TX_IQ_FLIP               FIELD8(0x04)
 627
 628 /*
 629  * BBP_R14: RX antenna control
 630  */
 631 #define BBP_R14_RX_ANTENNA              FIELD8(0x03)
 632 #define BBP_R14_RX_IQ_FLIP              FIELD8(0x04)
 633
 634 /*
 635  * DMA descriptor defines.
 636  */
 637 #define TXD_DESC_SIZE                   ( 5 * sizeof(struct data_desc) )
 638 #define RXD_DESC_SIZE                   ( 4 * sizeof(struct data_desc) )
 639
 640 /*
 641  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 642  */
 643
 644 /*
 645  * Word0
 646  */
 647 #define TXD_W0_PACKET_ID                FIELD32(0x0000000f)
 648 #define TXD_W0_RETRY_LIMIT              FIELD32(0x000000f0)
 649 #define TXD_W0_MORE_FRAG                FIELD32(0x00000100)
 650 #define TXD_W0_ACK                      FIELD32(0x00000200)
 651 #define TXD_W0_TIMESTAMP                FIELD32(0x00000400)
 652 #define TXD_W0_OFDM                     FIELD32(0x00000800)
 653 #define TXD_W0_NEW_SEQ                  FIELD32(0x00001000)
 654 #define TXD_W0_IFS                      FIELD32(0x00006000)
 655 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 656 #define TXD_W0_CIPHER                   FIELD32(0x20000000)
 657 #define TXD_W0_KEY_ID                   FIELD32(0xc0000000)
 658
 659 /*
 660  * Word1
 661  */
 662 #define TXD_W1_IV_OFFSET                FIELD32(0x0000003f)
 663 #define TXD_W1_AIFS                     FIELD32(0x000000c0)
 664 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 665 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 666
 667 /*
 668  * Word2: PLCP information
 669  */
 670 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 671 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 672 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 673 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 674
 675 /*
 676  * Word3
 677  */
 678 #define TXD_W3_IV                       FIELD32(0xffffffff)
 679
 680 /*
 681  * Word4
 682  */
 683 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 684
 685 /*
 686  * RX descriptor format for RX Ring.
 687  */
 688
 689 /*
 690  * Word0
 691  */
 692 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000002)
 693 #define RXD_W0_MULTICAST                FIELD32(0x00000004)
 694 #define RXD_W0_BROADCAST                FIELD32(0x00000008)
 695 #define RXD_W0_MY_BSS                   FIELD32(0x00000010)
 696 #define RXD_W0_CRC                      FIELD32(0x00000020)
 697 #define RXD_W0_OFDM                     FIELD32(0x00000040)
 698 #define RXD_W0_PHYSICAL_ERROR           FIELD32(0x00000080)
 699 #define RXD_W0_CIPHER                   FIELD32(0x00000100)
 700 #define RXD_W0_CI_ERROR                 FIELD32(0x00000200)
 701 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 702
 703 /*
 704  * Word1
 705  */
 706 #define RXD_W1_RSSI                     FIELD32(0x000000ff)
 707 #define RXD_W1_SIGNAL                   FIELD32(0x0000ff00)
 708
 709 /*
 710  * Word2
 711  */
 712 #define RXD_W2_IV                       FIELD32(0xffffffff)
 713
 714 /*
 715  * Word3
 716  */
 717 #define RXD_W3_EIV                      FIELD32(0xffffffff)
 718
 719 /*
 720  * Macro's for converting txpower from EEPROM to dscape value
 721  * and from dscape value to register value.
 722  */
 723 #define MIN_TXPOWER     0
 724 #define MAX_TXPOWER     31
 725 #define DEFAULT_TXPOWER 24
 726
 727 #define TXPOWER_FROM_DEV(__txpower)             \
 728 ({                                              \
 729         ((__txpower) > MAX_TXPOWER) ?           \
 730                 DEFAULT_TXPOWER : (__txpower);  \
 731 })
 732
 733 #define TXPOWER_TO_DEV(__txpower)                       \
 734 ({                                                      \
 735         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
 736         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
 737         (__txpower));                                   \
 738 })
 739
 740 #endif /* RT2500USB_H */