package/ifxmips-dsl-api/src/ifxmips_atm_danube.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_danube.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include <asm/ifx/ifx_types.h>
  49 #include <asm/ifx/ifx_regs.h>
  50 #include <asm/ifx/common_routines.h>
  51 #include <asm/ifx/ifx_pmu.h>
  52 #include "ifxmips_atm_core.h"
  53 #include "ifxmips_atm_fw_danube.h"
  54
  55
  56
  57 /*
  58  * ####################################
  59  *              Definition
  60  * ####################################
  61  */
  62
  63 /*
  64  *  EMA Settings
  65  */
  66 #define EMA_CMD_BUF_LEN      0x0040
  67 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  68 #define EMA_DATA_BUF_LEN     0x0100
  69 #define EMA_DATA_BASE_ADDR   (0x00001900 << 2)
  70 #define EMA_WRITE_BURST      0x2
  71 #define EMA_READ_BURST       0x2
  72
  73
  74
  75 /*
  76  * ####################################
  77  *             Declaration
  78  * ####################################
  79  */
  80
  81 /*
  82  *  Hardware Init/Uninit Functions
  83  */
  84 static inline void init_pmu(void);
  85 static inline void uninit_pmu(void);
  86 static inline void init_ema(void);
  87 static inline void init_mailbox(void);
  88 static inline void init_atm_tc(void);
  89 static inline void clear_share_buffer(void);
  90
  91
  92
  93 /*
  94  * ####################################
  95  *            Local Variable
  96  * ####################################
  97  */
  98
  99
 100
 101 /*
 102  * ####################################
 103  *            Local Function
 104  * ####################################
 105  */
 106
 107 static inline void init_pmu(void)
 108 {
 109     //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
 110     PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 111     PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 112     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 113     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 114     PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 115     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 116     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
 117 }
 118
 119 static inline void uninit_pmu(void)
 120 {
 121     PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 122     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 123     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 124     PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 125     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 126     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 127     PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
 128 }
 129
 130 static inline void init_ema(void)
 131 {
 132     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 133     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 134     IFX_REG_W32(0x000000FF, EMA_IER);
 135     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 136 }
 137
 138 static inline void init_mailbox(void)
 139 {
 140     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 141     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 142     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 143     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 144 }
 145
 146 static inline void init_atm_tc(void)
 147 {
 148     //  for ReTX expansion in future
 149     //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); //  pnum = 6
 150     //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); //  pnum = 6
 151 }
 152
 153 static inline void clear_share_buffer(void)
 154 {
 155     volatile u32 *p = SB_RAM0_ADDR(0);
 156     unsigned int i;
 157
 158     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 159         IFX_REG_W32(0, p++);
 160 }
 161
 162 /*
 163  *  Description:
 164  *    Download PPE firmware binary code.
 165  *  Input:
 166  *    src       --- u32 *, binary code buffer
 167  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 168  *  Output:
 169  *    int       --- IFX_SUCCESS:    Success
 170  *                  else:           Error Code
 171  */
 172 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 173 {
 174     volatile u32 *dest;
 175
 176     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 177         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 178         return IFX_ERROR;
 179
 180     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 181         IFX_REG_W32(0x00, CDM_CFG);
 182     else
 183         IFX_REG_W32(0x02, CDM_CFG);
 184
 185     /*  copy code   */
 186     dest = CDM_CODE_MEMORY(0, 0);
 187     while ( code_dword_len-- > 0 )
 188         IFX_REG_W32(*code_src++, dest++);
 189
 190     /*  copy data   */
 191     dest = CDM_DATA_MEMORY(0, 0);
 192     while ( data_dword_len-- > 0 )
 193         IFX_REG_W32(*data_src++, dest++);
 194
 195     return IFX_SUCCESS;
 196 }
 197
 198
 199
 200 /*
 201  * ####################################
 202  *           Global Function
 203  * ####################################
 204  */
 205
 206 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
 207 {
 208     ASSERT(major != NULL, "pointer is NULL");
 209     ASSERT(minor != NULL, "pointer is NULL");
 210
 211     *major = ATM_FW_VER_MAJOR;
 212     *minor = ATM_FW_VER_MINOR;
 213 }
 214
 215 void ifx_atm_init_chip(void)
 216 {
 217     init_pmu();
 218
 219     init_ema();
 220
 221     init_mailbox();
 222
 223     init_atm_tc();
 224
 225     clear_share_buffer();
 226 }
 227
 228 void ifx_atm_uninit_chip(void)
 229 {
 230     uninit_pmu();
 231 }
 232
 233 /*
 234  *  Description:
 235  *    Initialize and start up PP32.
 236  *  Input:
 237  *    none
 238  *  Output:
 239  *    int  --- IFX_SUCCESS: Success
 240  *             else:        Error Code
 241  */
 242 int ifx_pp32_start(int pp32)
 243 {
 244     int ret;
 245
 246     /*  download firmware   */
 247     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 248     if ( ret != IFX_SUCCESS )
 249         return ret;
 250
 251     /*  run PP32    */
 252     IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
 253
 254     /*  idle for a while to let PP32 init itself    */
 255     udelay(10);
 256
 257     return IFX_SUCCESS;
 258 }
 259
 260 /*
 261  *  Description:
 262  *    Halt PP32.
 263  *  Input:
 264  *    none
 265  *  Output:
 266  *    none
 267  */
 268 void ifx_pp32_stop(int pp32)
 269 {
 270     /*  halt PP32   */
 271     IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
 272 }