target/linux/brcm63xx/patches-2.6.27/004_add_pci_support.patch

   1 From 2a7fa2dbbf68650644f807a50cc2d84ca30835c1 Mon Sep 17 00:00:00 2001
   2 From: Maxime Bizon <mbizon@freebox.fr>
   3 Date: Sun, 21 Sep 2008 04:47:13 +0200
   4 Subject: [PATCH] [MIPS] BCM63XX: Add PCI support.
   5
   6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
   7 ---
   8  arch/mips/bcm63xx/Kconfig                       |    2 +
   9  arch/mips/bcm63xx/setup.c                       |    2 +
  10  arch/mips/pci/Makefile                          |    2 +
  11  arch/mips/pci/fixup-bcm63xx.c                   |   21 +++
  12  arch/mips/pci/ops-bcm63xx.c                     |  179 +++++++++++++++++++++++
  13  arch/mips/pci/pci-bcm63xx.c                     |  178 ++++++++++++++++++++++
  14  arch/mips/pci/pci-bcm63xx.h                     |   27 ++++
  15  include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h |    6 +
  16  8 files changed, 417 insertions(+), 0 deletions(-)
  17  create mode 100644 arch/mips/pci/fixup-bcm63xx.c
  18  create mode 100644 arch/mips/pci/ops-bcm63xx.c
  19  create mode 100644 arch/mips/pci/pci-bcm63xx.c
  20  create mode 100644 arch/mips/pci/pci-bcm63xx.h
  21  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
  22
  23 --- a/arch/mips/bcm63xx/Kconfig
  24 +++ b/arch/mips/bcm63xx/Kconfig
  25 @@ -3,7 +3,9 @@ menu "CPU support"
  26
  27  config BCM63XX_CPU_6348
  28         bool "support 6348 CPU"
  29 +       select HW_HAS_PCI
  30
  31  config BCM63XX_CPU_6358
  32         bool "support 6358 CPU"
  33 +       select HW_HAS_PCI
  34  endmenu
  35 --- a/arch/mips/bcm63xx/setup.c
  36 +++ b/arch/mips/bcm63xx/setup.c
  37 @@ -105,4 +105,6 @@ void __init plat_mem_setup(void)
  38         pm_power_off = bcm63xx_machine_halt;
  39
  40         set_io_port_base(0);
  41 +       ioport_resource.start = 0;
  42 +       ioport_resource.end = ~0;
  43  }
  44 --- a/arch/mips/pci/Makefile
  45 +++ b/arch/mips/pci/Makefile
  46 @@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX)      += ops-vr41xx.o
  47  obj-$(CONFIG_MARKEINS)         += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
  48  obj-$(CONFIG_PCI_TX4927)       += ops-tx4927.o
  49  obj-$(CONFIG_BCM47XX)          += pci-bcm47xx.o
  50 +obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
  51 +                                       ops-bcm63xx.o
  52
  53  #
  54  # These are still pretty much in the old state, watch, go blind.
  55 --- /dev/null
  56 +++ b/arch/mips/pci/fixup-bcm63xx.c
  57 @@ -0,0 +1,21 @@
  58 +/*
  59 + * This file is subject to the terms and conditions of the GNU General Public
  60 + * License.  See the file "COPYING" in the main directory of this archive
  61 + * for more details.
  62 + *
  63 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  64 + */
  65 +
  66 +#include <linux/types.h>
  67 +#include <linux/pci.h>
  68 +#include <bcm63xx_cpu.h>
  69 +
  70 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  71 +{
  72 +       return bcm63xx_get_irq_number(IRQ_PCI);
  73 +}
  74 +
  75 +int pcibios_plat_dev_init(struct pci_dev *dev)
  76 +{
  77 +       return 0;
  78 +}
  79 --- /dev/null
  80 +++ b/arch/mips/pci/ops-bcm63xx.c
  81 @@ -0,0 +1,179 @@
  82 +/*
  83 + * This file is subject to the terms and conditions of the GNU General Public
  84 + * License.  See the file "COPYING" in the main directory of this archive
  85 + * for more details.
  86 + *
  87 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  88 + */
  89 +
  90 +#include <linux/types.h>
  91 +#include <linux/pci.h>
  92 +#include <linux/kernel.h>
  93 +#include <linux/init.h>
  94 +#include <linux/delay.h>
  95 +#include <linux/io.h>
  96 +
  97 +#include "pci-bcm63xx.h"
  98 +
  99 +/*
 100 + * swizzle 32bits data to return only the needed part
 101 + */
 102 +static int postprocess_read(u32 data, int where, unsigned int size)
 103 +{
 104 +       u32 ret;
 105 +
 106 +       ret = 0;
 107 +       switch (size) {
 108 +       case 1:
 109 +               ret = (data >> ((where & 3) << 3)) & 0xff;
 110 +               break;
 111 +       case 2:
 112 +               ret = (data >> ((where & 3) << 3)) & 0xffff;
 113 +               break;
 114 +       case 4:
 115 +               ret = data;
 116 +               break;
 117 +       }
 118 +       return ret;
 119 +}
 120 +
 121 +static int preprocess_write(u32 orig_data, u32 val, int where,
 122 +                           unsigned int size)
 123 +{
 124 +       u32 ret;
 125 +
 126 +       ret = 0;
 127 +       switch (size) {
 128 +       case 1:
 129 +               ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 130 +                       (val << ((where & 3) << 3));
 131 +               break;
 132 +       case 2:
 133 +               ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 134 +                       (val << ((where & 3) << 3));
 135 +               break;
 136 +       case 4:
 137 +               ret = val;
 138 +               break;
 139 +       }
 140 +       return ret;
 141 +}
 142 +
 143 +/*
 144 + * setup hardware for a configuration cycle with given parameters
 145 + */
 146 +static int bcm63xx_setup_cfg_access(int type, unsigned int busn,
 147 +                                   unsigned int devfn, int where)
 148 +{
 149 +       unsigned int slot, func, reg;
 150 +       u32 val;
 151 +
 152 +       slot = PCI_SLOT(devfn);
 153 +       func = PCI_FUNC(devfn);
 154 +       reg = where >> 2;
 155 +
 156 +       /* sanity check */
 157 +       if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
 158 +               return 1;
 159 +
 160 +       if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
 161 +               return 1;
 162 +
 163 +       if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
 164 +               return 1;
 165 +
 166 +       /* ok, setup config access */
 167 +       val = (reg << MPI_L2PCFG_REG_SHIFT);
 168 +       val |= (func << MPI_L2PCFG_FUNC_SHIFT);
 169 +       val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
 170 +       val |= MPI_L2PCFG_CFG_USEREG_MASK;
 171 +       val |= MPI_L2PCFG_CFG_SEL_MASK;
 172 +       /* type 0 cycle for local bus, type 1 cycle for anything else */
 173 +       if (type != 0) {
 174 +               /* FIXME: how to specify bus ??? */
 175 +               val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
 176 +       }
 177 +       bcm_mpi_writel(val, MPI_L2PCFG_REG);
 178 +
 179 +       return 0;
 180 +}
 181 +
 182 +static int bcm63xx_do_cfg_read(int type, unsigned int busn,
 183 +                               unsigned int devfn, int where, int size,
 184 +                               u32 *val)
 185 +{
 186 +       u32 data;
 187 +
 188 +       /* two phase cycle, first we write address, then read data at
 189 +        * another location, caller already has a spinlock so no need
 190 +        * to add one here  */
 191 +       if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
 192 +               return PCIBIOS_DEVICE_NOT_FOUND;
 193 +       iob();
 194 +       data = le32_to_cpu(__raw_readl(pci_iospace_start));
 195 +       /* restore IO space normal behaviour */
 196 +       bcm_mpi_writel(0, MPI_L2PCFG_REG);
 197 +
 198 +       *val = postprocess_read(data, where, size);
 199 +
 200 +       return PCIBIOS_SUCCESSFUL;
 201 +}
 202 +
 203 +static int bcm63xx_do_cfg_write(int type, unsigned int busn,
 204 +                                unsigned int devfn, int where, int size,
 205 +                                u32 val)
 206 +{
 207 +       u32 data;
 208 +
 209 +       /* two phase cycle, first we write address, then write data to
 210 +        * another location, caller already has a spinlock so no need
 211 +        * to add one here  */
 212 +       if (bcm63xx_setup_cfg_access(type, busn, devfn, where))
 213 +               return PCIBIOS_DEVICE_NOT_FOUND;
 214 +       iob();
 215 +
 216 +       data = le32_to_cpu(__raw_readl(pci_iospace_start));
 217 +       data = preprocess_write(data, val, where, size);
 218 +
 219 +       __raw_writel(cpu_to_le32(data), pci_iospace_start);
 220 +       wmb();
 221 +       /* no way to know the access is done, we have to wait */
 222 +       udelay(500);
 223 +       /* restore IO space normal behaviour */
 224 +       bcm_mpi_writel(0, MPI_L2PCFG_REG);
 225 +
 226 +       return PCIBIOS_SUCCESSFUL;
 227 +}
 228 +
 229 +static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn,
 230 +                            int where, int size, u32 *val)
 231 +{
 232 +       int type;
 233 +
 234 +       type = bus->parent ? 1 : 0;
 235 +
 236 +       if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 237 +               return PCIBIOS_DEVICE_NOT_FOUND;
 238 +
 239 +       return bcm63xx_do_cfg_read(type, bus->number, devfn,
 240 +                                   where, size, val);
 241 +}
 242 +
 243 +static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
 244 +                             int where, int size, u32 val)
 245 +{
 246 +       int type;
 247 +
 248 +       type = bus->parent ? 1 : 0;
 249 +
 250 +       if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 251 +               return PCIBIOS_DEVICE_NOT_FOUND;
 252 +
 253 +       return bcm63xx_do_cfg_write(type, bus->number, devfn,
 254 +                                    where, size, val);
 255 +}
 256 +
 257 +struct pci_ops bcm63xx_pci_ops = {
 258 +       .read   = bcm63xx_pci_read,
 259 +       .write  = bcm63xx_pci_write
 260 +};
 261 --- /dev/null
 262 +++ b/arch/mips/pci/pci-bcm63xx.c
 263 @@ -0,0 +1,178 @@
 264 +/*
 265 + * This file is subject to the terms and conditions of the GNU General Public
 266 + * License.  See the file "COPYING" in the main directory of this archive
 267 + * for more details.
 268 + *
 269 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 270 + */
 271 +
 272 +#include <linux/types.h>
 273 +#include <linux/pci.h>
 274 +#include <linux/kernel.h>
 275 +#include <linux/init.h>
 276 +#include <asm/bootinfo.h>
 277 +
 278 +#include "pci-bcm63xx.h"
 279 +
 280 +/* allow PCI to be disabled at runtime depending on board nvram
 281 + * configuration */
 282 +int bcm63xx_pci_enabled = 0;
 283 +
 284 +static struct resource bcm_pci_mem_resource = {
 285 +       .name   = "bcm63xx PCI memory space",
 286 +       .start  = BCM_PCI_MEM_BASE_PA,
 287 +       .end    = BCM_PCI_MEM_END_PA,
 288 +       .flags  = IORESOURCE_MEM
 289 +};
 290 +
 291 +static struct resource bcm_pci_io_resource = {
 292 +       .name   = "bcm63xx PCI IO space",
 293 +       .start  = BCM_PCI_IO_BASE_PA,
 294 +       .end    = BCM_PCI_IO_END_PA,
 295 +       .flags  = IORESOURCE_IO
 296 +};
 297 +
 298 +struct pci_controller bcm63xx_controller = {
 299 +       .pci_ops        = &bcm63xx_pci_ops,
 300 +       .io_resource    = &bcm_pci_io_resource,
 301 +       .mem_resource   = &bcm_pci_mem_resource,
 302 +};
 303 +
 304 +static u32 bcm63xx_int_cfg_readl(u32 reg)
 305 +{
 306 +       u32 tmp;
 307 +
 308 +       tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 309 +       tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 310 +       bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
 311 +       iob();
 312 +       return bcm_mpi_readl(MPI_PCICFGDATA_REG);
 313 +}
 314 +
 315 +static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
 316 +{
 317 +       u32 tmp;
 318 +
 319 +       tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 320 +       tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
 321 +       bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
 322 +       bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
 323 +}
 324 +
 325 +void __iomem *pci_iospace_start;
 326 +
 327 +static int __init bcm63xx_pci_init(void)
 328 +{
 329 +       unsigned int mem_size;
 330 +       u32 val;
 331 +
 332 +       if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
 333 +               return -ENODEV;
 334 +
 335 +       if (!bcm63xx_pci_enabled)
 336 +               return -ENODEV;
 337 +
 338 +       /*
 339 +        * configuration  access are  done through  IO space,  remap 4
 340 +        * first bytes to access it from CPU.
 341 +        *
 342 +        * this means that  no io access from CPU  should happen while
 343 +        * we do a configuration cycle,  but there's no way we can add
 344 +        * a spinlock for each io access, so this is currently kind of
 345 +        * broken on SMP.
 346 +        */
 347 +       pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4);
 348 +       if (!pci_iospace_start)
 349 +               return -ENOMEM;
 350 +
 351 +       /* setup local bus to PCI access (PCI memory) */
 352 +       val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK;
 353 +       bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG);
 354 +       bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG);
 355 +       bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG);
 356 +
 357 +       /* set Cardbus IDSEL (type 0 cfg access on primary bus for
 358 +        * this IDSEL will be done on Cardbus instead) */
 359 +       val = bcm_pcmcia_readl(PCMCIA_C1_REG);
 360 +       val &= ~PCMCIA_C1_CBIDSEL_MASK;
 361 +       val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 362 +       bcm_pcmcia_writel(val, PCMCIA_C1_REG);
 363 +
 364 +       /* disable second access windows */
 365 +       bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 366 +
 367 +       /* setup local bus  to PCI access (IO memory),  we have only 1
 368 +        * IO window  for both PCI  and cardbus, but it  cannot handle
 369 +        * both  at the  same time,  assume standard  PCI for  now, if
 370 +        * cardbus card has  IO zone, PCI fixup will  change window to
 371 +        * cardbus */
 372 +       val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
 373 +       bcm_mpi_writel(val, MPI_L2PIOBASE_REG);
 374 +       bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG);
 375 +       bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG);
 376 +
 377 +       /* enable PCI related GPIO pins */
 378 +       bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG);
 379 +
 380 +       /* setup PCI to local bus access, used by PCI device to target
 381 +        * local RAM while bus mastering */
 382 +       bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 383 +       if (BCMCPU_IS_6358())
 384 +               val = MPI_SP0_REMAP_ENABLE_MASK;
 385 +       else
 386 +               val = 0;
 387 +       bcm_mpi_writel(val, MPI_SP0_REMAP_REG);
 388 +
 389 +       bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4);
 390 +       bcm_mpi_writel(0, MPI_SP1_REMAP_REG);
 391 +
 392 +       mem_size = bcm63xx_get_memory_size();
 393 +
 394 +       /* 6348 before rev b0 exposes only 16 MB of RAM memory through
 395 +        * PCI, throw a warning if we have more memory */
 396 +       if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) {
 397 +               if (mem_size > (16 * 1024 * 1024))
 398 +                       printk(KERN_WARNING "bcm63xx: this CPU "
 399 +                              "revision cannot handle more than 16MB "
 400 +                              "of RAM for PCI bus mastering\n");
 401 +       } else {
 402 +               /* setup sp0 range to local RAM size */
 403 +               bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG);
 404 +               bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
 405 +       }
 406 +
 407 +       /* change  host bridge  retry  counter to  infinite number  of
 408 +        * retry,  needed for  some broadcom  wifi cards  with Silicon
 409 +        * Backplane bus where access to srom seems very slow  */
 410 +       val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
 411 +       val &= ~REG_TIMER_RETRY_MASK;
 412 +       bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 413 +
 414 +       /* enable memory decoder and bus mastering */
 415 +       val = bcm63xx_int_cfg_readl(PCI_COMMAND);
 416 +       val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 417 +       bcm63xx_int_cfg_writel(val, PCI_COMMAND);
 418 +
 419 +       /* enable read prefetching & disable byte swapping for bus
 420 +        * mastering transfers */
 421 +       val = bcm_mpi_readl(MPI_PCIMODESEL_REG);
 422 +       val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 423 +       val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 424 +       val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 425 +       val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 426 +       bcm_mpi_writel(val, MPI_PCIMODESEL_REG);
 427 +
 428 +       /* enable pci interrupt */
 429 +       val = bcm_mpi_readl(MPI_LOCINT_REG);
 430 +       val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 431 +       bcm_mpi_writel(val, MPI_LOCINT_REG);
 432 +
 433 +       register_pci_controller(&bcm63xx_controller);
 434 +
 435 +       /* mark memory space used for IO mapping as reserved */
 436 +       request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
 437 +                          "bcm63xx PCI IO space");
 438 +       return 0;
 439 +}
 440 +
 441 +arch_initcall(bcm63xx_pci_init);
 442 --- /dev/null
 443 +++ b/arch/mips/pci/pci-bcm63xx.h
 444 @@ -0,0 +1,27 @@
 445 +#ifndef PCI_BCM63XX_H_
 446 +#define PCI_BCM63XX_H_
 447 +
 448 +#include <bcm63xx_cpu.h>
 449 +#include <bcm63xx_io.h>
 450 +#include <bcm63xx_regs.h>
 451 +#include <bcm63xx_dev_pci.h>
 452 +
 453 +/*
 454 + * Cardbus shares  the PCI bus, but has  no IDSEL, so a  special id is
 455 + * reserved for it.  If you have a standard PCI device at this id, you
 456 + * need to change the following definition.
 457 + */
 458 +#define CARDBUS_PCI_IDSEL      0x8
 459 +
 460 +/*
 461 + * defined in ops-bcm63xx.c
 462 + */
 463 +extern struct pci_ops bcm63xx_pci_ops;
 464 +extern struct pci_ops bcm63xx_cb_ops;
 465 +
 466 +/*
 467 + * defined in pci-bcm63xx.c
 468 + */
 469 +extern void __iomem *pci_iospace_start;
 470 +
 471 +#endif /* ! PCI_BCM63XX_H_ */
 472 --- /dev/null
 473 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_dev_pci.h
 474 @@ -0,0 +1,6 @@
 475 +#ifndef BCM63XX_DEV_PCI_H_
 476 +#define BCM63XX_DEV_PCI_H_
 477 +
 478 +extern int bcm63xx_pci_enabled;
 479 +
 480 +#endif /* BCM63XX_DEV_PCI_H_ */