ath9k: increase rx buffers for improved performance with 3x3 chipsets
[openwrt.git] / package / mac80211 / patches / 542-ath9k_fix_half_quarter_sifs.patch
1 --- a/drivers/net/wireless/ath/ath9k/hw.c
2 +++ b/drivers/net/wireless/ath/ath9k/hw.c
3 @@ -1007,31 +1007,35 @@ void ath9k_hw_init_global_settings(struc
4 if (IS_CHAN_HALF_RATE(chan)) {
5 eifs = 175;
6
7 - if (!AR_SREV_9300_20_OR_LATER(ah))
8 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
9 rx_lat = 10;
10 - else
11 + sifstime = 8;
12 + } else {
13 rx_lat *= 2;
14 + sifstime = 32;
15 + }
16
17 tx_lat *= 2;
18 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
19 tx_lat += 11;
20
21 slottime = 13;
22 - sifstime = 32;
23 } else if (IS_CHAN_QUARTER_RATE(chan)) {
24 eifs = 340;
25
26 - if (!AR_SREV_9300_20_OR_LATER(ah))
27 + if (!AR_SREV_9300_20_OR_LATER(ah)) {
28 rx_lat = 20;
29 - else
30 + sifstime = 8;
31 + } else {
32 rx_lat = (rx_lat * 4) - 1;
33 + sifstime = 64;
34 + }
35
36 tx_lat *= 4;
37 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
38 tx_lat += 22;
39
40 slottime = 21;
41 - sifstime = 64;
42 } else {
43 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
44 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
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