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[openwrt.git] / target / linux / rdc-2.6 / patches / 002-r6040_ethernet.patch
1 diff -urN linux-2.6.17/drivers/net/Kconfig linux-2.6.17.new/drivers/net/Kconfig
2 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
3 +++ linux-2.6.17.new/drivers/net/Kconfig 2006-09-25 13:14:27.000000000 +0200
4 @@ -1358,6 +1358,19 @@
5 <file:Documentation/networking/net-modules.txt>. The module will be
6 called apricot.
7
8 +config R6040
9 + tristate "RDC Fast-Ethernet support (EXPERIMENTAL)"
10 + depends on NET_PCI && EXPERIMENTAL
11 + select MII
12 + help
13 + If you have a network (Ethernet) controller of this type, say Y and
14 + read the Ethernet-HOWTO, available from
15 + <http://www.tldp.org/docs.html#howto>.
16 +
17 + To compile this driver as a module, choose M here and read
18 + <file:Documentation/networking/net-modules.txt>. The module will be
19 + called r6040.
20 +
21 config B44
22 tristate "Broadcom 4400 ethernet support (EXPERIMENTAL)"
23 depends on NET_PCI && PCI && EXPERIMENTAL
24 diff -urN linux-2.6.17/drivers/net/Makefile linux-2.6.17.new/drivers/net/Makefile
25 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
26 +++ linux-2.6.17.new/drivers/net/Makefile 2006-09-25 13:14:45.000000000 +0200
27 @@ -106,6 +106,7 @@
28 obj-$(CONFIG_NE3210) += ne3210.o 8390.o
29 obj-$(CONFIG_NET_SB1250_MAC) += sb1250-mac.o
30 obj-$(CONFIG_B44) += b44.o
31 +obj-$(CONFIG_R6040) += r6040.o
32 obj-$(CONFIG_FORCEDETH) += forcedeth.o
33 obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o
34
35 diff -urN linux-2.6.17/drivers/net/r6040.c linux-2.6.17.new/drivers/net/r6040.c
36 --- linux-2.6.17/drivers/net/r6040.c 1970-01-01 01:00:00.000000000 +0100
37 +++ linux-2.6.17.new/drivers/net/r6040.c 2006-09-25 13:12:41.000000000 +0200
38 @@ -0,0 +1,980 @@
39 +/* rdc.c: A RDC FastEthernet driver for linux. */
40 +/*
41 + Re-written 2004 by Sten Wang.
42 +
43 + Copyright 1994-2000 by Donald Becker.
44 + Copyright 1993 United States Government as represented by the
45 + Director, National Security Agency. This software may be used and
46 + distributed according to the terms of the GNU General Public License,
47 + incorporated herein by reference.
48 +
49 + This driver is for RDC FastEthernet MAC series.
50 + For kernel version after 2.4.22
51 +
52 + Modification List
53 + ---------- ------------------------------------------------
54 + 12-22-2004 Sten Init MAC MBCR register=0x012A
55 + PHY_CAP = 0x01E1
56 +*/
57 +
58 +#define FORICPLUS /* Supports ICPlus IP175C switch chip */
59 +#define BOOSTRDC /* Accelerate Ethernet performance */
60 +
61 +#define DRV_NAME "rdc"
62 +#define DRV_VERSION "0.6"
63 +#define DRV_RELDATE "9July2004"
64 +
65 +/* PHY CHIP Address */
66 +#define PHY1_ADDR 1 /* For MAC1 */
67 +#define PHY2_ADDR 2 /* For MAC2 */
68 +#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
69 +#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
70 +
71 +/* Time in jiffies before concluding the transmitter is hung. */
72 +#define TX_TIMEOUT (400 * HZ / 1000)
73 +#define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
74 +
75 +/* RDC MAC ID */
76 +#define RDC_MAC_ID 0x6040
77 +
78 +/* RDC MAC I/O Size */
79 +#define R6040_IO_SIZE 256
80 +
81 +/* RDC Chip PCI Command */
82 +#define R6040_PCI_CMD 0x0005 /* IO, Master */
83 +
84 +/* MAX RDC MAC */
85 +#define MAX_MAC 2
86 +
87 +/* MAC setting */
88 +#ifdef BOOSTRDC
89 +#define TX_DCNT 32 /* TX descriptor count */
90 +#define RX_DCNT 32 /* RX descriptor count */
91 +#else
92 +#define TX_DCNT 0x8 /* TX descriptor count */
93 +#define RX_DCNT 0x8 /* RX descriptor count */
94 +#endif
95 +#define MAX_BUF_SIZE 0x600
96 +#define ALLOC_DESC_SIZE ((TX_DCNT+RX_DCNT)*sizeof(struct rdc_descriptor)+0x10)
97 +#define MBCR_DEFAULT 0x012A /* MAC Control Register */
98 +
99 +/* Debug enable or not */
100 +#define RDC_DEBUG 0
101 +
102 +#if RDC_DEBUG > 1
103 +#define RDC_DBUG(msg, value) printk("%s %x\n", msg, value);
104 +#else
105 +#define RDC_DBUG(msg, value)
106 +#endif
107 +
108 +
109 +#include <linux/module.h>
110 +#include <linux/kernel.h>
111 +#include <linux/string.h>
112 +#include <linux/timer.h>
113 +#include <linux/errno.h>
114 +#include <linux/ioport.h>
115 +#include <linux/slab.h>
116 +#include <linux/interrupt.h>
117 +#include <linux/pci.h>
118 +#include <linux/netdevice.h>
119 +#include <linux/etherdevice.h>
120 +#include <linux/skbuff.h>
121 +#include <linux/init.h>
122 +#include <linux/delay.h> /* for udelay() */
123 +#include <linux/mii.h>
124 +#include <linux/ethtool.h>
125 +#include <linux/crc32.h>
126 +#include <linux/spinlock.h>
127 +
128 +#include <asm/processor.h>
129 +#include <asm/bitops.h>
130 +#include <asm/io.h>
131 +#include <asm/irq.h>
132 +#include <asm/uaccess.h>
133 +
134 +MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>");
135 +MODULE_DESCRIPTION("RDC R6040 PCI FastEthernet Driver");
136 +MODULE_LICENSE("GPL");
137 +
138 +//MODULE_PARM(adr_table, "2-4i");
139 +MODULE_PARM_DESC(adr_table, "MAC Address (assigned)");
140 +
141 +struct rdc_descriptor {
142 + u16 status, len; /* 0-3 */
143 + u32 buf; /* 4-7 */
144 + u32 ndesc; /* 8-B */
145 + u32 rev1; /* C-F */
146 + char *vbufp; /* 10-13 */
147 + struct rdc_descriptor *vndescp; /* 14-17 */
148 + struct sk_buff *skb_ptr; /* 18-1B */
149 + u32 rev2; /* 1C-1F */
150 +} __attribute__(( aligned(32) ));
151 +
152 +struct rdc_private {
153 + struct net_device_stats stats;
154 + spinlock_t lock;
155 + struct timer_list timer;
156 + struct pci_dev *pdev;
157 +
158 + struct rdc_descriptor *rx_insert_ptr;
159 + struct rdc_descriptor *rx_remove_ptr;
160 + struct rdc_descriptor *tx_insert_ptr;
161 + struct rdc_descriptor *tx_remove_ptr;
162 + u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
163 + u16 mcr0, mcr1;
164 + dma_addr_t desc_dma;
165 + char *desc_pool;
166 +};
167 +
168 +struct rdc_chip_info {
169 + const char *name;
170 + u16 pci_flags;
171 + int io_size;
172 + int drv_flags;
173 +};
174 +
175 +static int __devinitdata printed_version;
176 +static char version[] __devinitdata =
177 + KERN_INFO DRV_NAME ": RDC R6040 net driver, version "
178 + DRV_VERSION " (" DRV_RELDATE ")\n";
179 +
180 +static struct rdc_chip_info rdc_chip_info[] __devinitdata =
181 +{
182 + { "RDC R6040 Knight", R6040_PCI_CMD, R6040_IO_SIZE, 0}
183 +};
184 +
185 +static int phy_table[] = { 0x1, 0x2};
186 +static u8 adr_table[2][8] = {{0x00, 0x00, 0x60, 0x00, 0x00, 0x01}, {0x00, 0x00, 0x60, 0x00, 0x00, 0x02}};
187 +
188 +static int rdc_open(struct net_device *dev);
189 +static int rdc_start_xmit(struct sk_buff *skb, struct net_device *dev);
190 +static irqreturn_t rdc_interrupt(int irq, void *dev_id);
191 +static struct net_device_stats *rdc_get_stats(struct net_device *dev);
192 +static int rdc_close(struct net_device *dev);
193 +static void set_multicast_list(struct net_device *dev);
194 +static struct ethtool_ops netdev_ethtool_ops;
195 +static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
196 +static void rdc_down(struct net_device *dev);
197 +static void rdc_up(struct net_device *dev);
198 +static void rdc_tx_timeout (struct net_device *dev);
199 +static void rdc_timer(unsigned long);
200 +
201 +static int phy_mode_chk(struct net_device *dev);
202 +static int phy_read(int ioaddr, int phy_adr, int reg_idx);
203 +static void phy_write(int ioaddr, int phy_adr, int reg_idx, int dat);
204 +
205 +#ifdef BOOSTRDC
206 +#define rx_buf_alloc(lp) \
207 + do { \
208 + struct rdc_descriptor *descptr; \
209 + descptr = lp->rx_insert_ptr; \
210 + while(lp->rx_free_desc < RX_DCNT){ \
211 + descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE); \
212 + if (!descptr->skb_ptr) break; \
213 + descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, descptr->skb_ptr->tail, MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); \
214 + descptr->status = 0x8000; \
215 + descptr = descptr->vndescp; \
216 + lp->rx_free_desc++; \
217 + } \
218 + lp->rx_insert_ptr = descptr; \
219 + } while(0)
220 +
221 +#else
222 +static void rx_buf_alloc(struct rdc_private *lp);
223 +#endif
224 +
225 +#ifdef FORICPLUS
226 +static void process_ioctl(struct net_device*, unsigned long* );
227 +#endif
228 +
229 +static int __devinit rdc_init_one (struct pci_dev *pdev,
230 + const struct pci_device_id *ent)
231 +{
232 + struct net_device *dev;
233 + struct rdc_private *lp;
234 + int ioaddr, io_size, err;
235 + static int card_idx = -1;
236 + int chip_id = (int)ent->driver_data;
237 +
238 + RDC_DBUG("rdc_init_one()", 0);
239 +
240 + if (printed_version++)
241 + printk(version);
242 +
243 + if ((err = pci_enable_device (pdev)))
244 + return err;
245 +
246 + /* this should always be supported */
247 + if (pci_set_dma_mask(pdev, 0xffffffff)) {
248 + printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses not supported by the card!?\n");
249 + return -ENODEV;
250 + }
251 +
252 + /* IO Size check */
253 + io_size = rdc_chip_info[chip_id].io_size;
254 + if (pci_resource_len (pdev, 0) < io_size) {
255 + return -ENODEV;
256 + }
257 +
258 + ioaddr = pci_resource_start (pdev, 0); /* IO map base address */
259 + pci_set_master(pdev);
260 +
261 + dev = alloc_etherdev(sizeof(struct rdc_private));
262 + if (dev == NULL)
263 + return -ENOMEM;
264 + SET_MODULE_OWNER(dev);
265 +
266 + if (pci_request_regions(pdev, DRV_NAME)) {
267 + printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
268 + err = -ENODEV;
269 + goto err_out_disable;
270 + }
271 +
272 + /* Init system & device */
273 + lp = dev->priv;
274 + dev->base_addr = ioaddr;
275 + dev->irq = pdev->irq;
276 +
277 + spin_lock_init(&lp->lock);
278 + pci_set_drvdata(pdev, dev);
279 +
280 + /* Set MAC address */
281 + card_idx++;
282 + memcpy(dev->dev_addr, (u8 *)&adr_table[card_idx][0], 6);
283 +
284 + /* Link new device into rdc_root_dev */
285 + lp->pdev = pdev;
286 +
287 + /* Init RDC private data */
288 + lp->mcr0 = 0x1002;
289 + lp->phy_addr = phy_table[card_idx];
290 +
291 + /* The RDC-specific entries in the device structure. */
292 + dev->open = &rdc_open;
293 + dev->hard_start_xmit = &rdc_start_xmit;
294 + dev->stop = &rdc_close;
295 + dev->get_stats = &rdc_get_stats;
296 + dev->set_multicast_list = &set_multicast_list;
297 + dev->do_ioctl = &netdev_ioctl;
298 + dev->ethtool_ops = &netdev_ethtool_ops;
299 + dev->tx_timeout = &rdc_tx_timeout;
300 + dev->watchdog_timeo = TX_TIMEOUT;
301 +
302 + /* Register net device. After this dev->name assign */
303 + if ((err = register_netdev(dev))) {
304 + printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
305 + goto err_out_res;
306 + }
307 +
308 + netif_carrier_on(dev);
309 + return 0;
310 +
311 +err_out_res:
312 + pci_release_regions(pdev);
313 +err_out_disable:
314 + pci_disable_device(pdev);
315 + pci_set_drvdata(pdev, NULL);
316 + kfree(dev);
317 +
318 + return err;
319 +}
320 +
321 +static void __devexit rdc_remove_one (struct pci_dev *pdev)
322 +{
323 + struct net_device *dev = pci_get_drvdata(pdev);
324 +
325 + unregister_netdev(dev);
326 + pci_release_regions(pdev);
327 + kfree(dev);
328 + pci_disable_device(pdev);
329 + pci_set_drvdata(pdev, NULL);
330 +}
331 +
332 +static int
333 +rdc_open(struct net_device *dev)
334 +{
335 + struct rdc_private *lp = dev->priv;
336 + int i;
337 +
338 + RDC_DBUG("rdc_open()", 0);
339 +
340 + /* Request IRQ and Register interrupt handler */
341 + i = request_irq(dev->irq, &rdc_interrupt, SA_SHIRQ, dev->name, dev);
342 + if (i) return i;
343 +
344 + /* Allocate Descriptor memory */
345 + lp->desc_pool = pci_alloc_consistent(lp->pdev, ALLOC_DESC_SIZE, &lp->desc_dma);
346 + if (!lp->desc_pool) return -ENOMEM;
347 +
348 + rdc_up(dev);
349 +
350 + netif_start_queue(dev);
351 +
352 +#ifndef FORICPLUS
353 + /* set and active a timer process */
354 + init_timer(&lp->timer);
355 + lp->timer.expires = TIMER_WUT;
356 + lp->timer.data = (unsigned long)dev;
357 + lp->timer.function = &rdc_timer;
358 + add_timer(&lp->timer);
359 +#endif
360 +
361 + return 0;
362 +}
363 +
364 +static void
365 +rdc_tx_timeout (struct net_device *dev)
366 +{
367 + struct rdc_private *lp = dev->priv;
368 + //int ioaddr = dev->base_addr;
369 + //struct rdc_descriptor *descptr = lp->tx_remove_ptr;
370 +
371 + RDC_DBUG("rdc_tx_timeout()", 0);
372 +
373 + /* Transmitter timeout, serious problems. */
374 + /* Sten: Nothing need to do so far. */
375 + printk(KERN_ERR DRV_NAME ": Big Trobule, transmit timeout/n");
376 + lp->stats.tx_errors++;
377 + netif_stop_queue(dev);
378 +
379 +//printk("<RDC> XMT timedout: CR0 %x, CR40 %x, CR3C %x, CR2C %x, CR30 %x, CR34 %x, CR38 %x\n", inw(ioaddr), inw(ioaddr+0x40), inw(ioaddr+0x3c), inw(ioaddr+0x2c), inw(ioaddr+0x30), inw(ioaddr+0x34), inw(ioaddr+0x38));
380 +
381 +//printk("<RDC> XMT_TO: %08lx:%04x %04x %08lx %08lx %08lx %08lx\n", descptr, descptr->status, descptr->len, descptr->buf, descptr->skb_ptr, descptr->ndesc, descptr->vndescp);
382 +}
383 +
384 +
385 +static int
386 +rdc_start_xmit(struct sk_buff *skb, struct net_device *dev)
387 +{
388 + struct rdc_private *lp = dev->priv;
389 + struct rdc_descriptor *descptr;
390 + int ioaddr = dev->base_addr;
391 + unsigned long flags;
392 +
393 + RDC_DBUG("rdc_start_xmit()", 0);
394 +
395 + if (skb == NULL) /* NULL skb directly return */
396 + return 0;
397 + if (skb->len >= MAX_BUF_SIZE) { /* Packet too long, drop it */
398 + dev_kfree_skb(skb);
399 + return 0;
400 + }
401 +
402 + /* Critical Section */
403 + spin_lock_irqsave(&lp->lock, flags);
404 +
405 + /* TX resource check */
406 + if (!lp->tx_free_desc) {
407 + spin_unlock_irqrestore(&lp->lock, flags);
408 + printk(KERN_ERR DRV_NAME ": NO TX DESC ");
409 + return 1;
410 + }
411 +
412 + /* Statistic Counter */
413 + lp->stats.tx_packets++;
414 + lp->stats.tx_bytes += skb->len;
415 +
416 + /* Set TX descriptor & Transmit it */
417 + lp->tx_free_desc--;
418 + descptr = lp->tx_insert_ptr;
419 + if (skb->len < 0x3c) descptr->len = 0x3c;
420 + else descptr->len = skb->len;
421 + descptr->skb_ptr = skb;
422 + descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
423 + descptr->status = 0x8000;
424 + outw(0x01, ioaddr + 0x14);
425 + lp->tx_insert_ptr = descptr->vndescp;
426 +
427 +#if RDC_DEBUG
428 + printk("Xmit(): %08lx:%04x %04x %08lx %08lx %08lx %08lx\n", descptr, descptr->status, descptr->len, descptr->buf, descptr->skb_ptr, descptr->ndesc, descptr->vndescp);
429 +#endif
430 +
431 + /* If no tx resource, stop */
432 + if (!lp->tx_free_desc)
433 + netif_stop_queue(dev);
434 +
435 + dev->trans_start = jiffies;
436 + spin_unlock_irqrestore(&lp->lock, flags);
437 + return 0;
438 +}
439 +
440 +/* The RDC interrupt handler. */
441 +static irqreturn_t
442 +rdc_interrupt(int irq, void *dev_id)
443 +{
444 + struct net_device *dev = dev_id;
445 + struct rdc_private *lp;
446 + struct rdc_descriptor *descptr;
447 + struct sk_buff *skb_ptr;
448 + int ioaddr, status;
449 + unsigned long flags;
450 + int handled = 0;
451 +
452 + RDC_DBUG("rdc_interrupt()", 0);
453 + if (dev == NULL) {
454 + printk (KERN_ERR DRV_NAME ": INT() unknown device.\n");
455 + return IRQ_RETVAL(handled);
456 + }
457 +
458 + lp = (struct rdc_private *)dev->priv;
459 + spin_lock_irqsave(&lp->lock, flags);
460 +
461 + /* Check MAC Interrupt status */
462 + ioaddr = dev->base_addr;
463 + outw(0x0, ioaddr + 0x40); /* Mask Off RDC MAC interrupt */
464 + status = inw(ioaddr + 0x3c); /* Read INTR status and clear */
465 +
466 + /* TX interrupt request */
467 + if (status & 0x10) {
468 + handled = 1;
469 + descptr = lp->tx_remove_ptr;
470 + while(lp->tx_free_desc < TX_DCNT) {
471 + if (descptr->status & 0x8000) break; /* Not complte */
472 + skb_ptr = descptr->skb_ptr;
473 + pci_unmap_single(lp->pdev, descptr->buf, skb_ptr->len, PCI_DMA_TODEVICE);
474 + dev_kfree_skb_irq(skb_ptr); /* Free buffer */
475 + descptr->skb_ptr = 0;
476 + descptr = descptr->vndescp; /* To next descriptor */
477 + lp->tx_free_desc++;
478 + }
479 + lp->tx_remove_ptr = descptr;
480 + if (lp->tx_free_desc) netif_wake_queue(dev);
481 + }
482 +
483 + /* RX interrupt request */
484 + if (status & 0x01) {
485 + handled = 1;
486 + descptr = lp->rx_remove_ptr;
487 + while(lp->rx_free_desc) {
488 + if (descptr->status & 0x8000) break; /* No Rx packet */
489 + skb_ptr = descptr->skb_ptr;
490 + descptr->skb_ptr = 0;
491 + skb_ptr->dev = dev;
492 + skb_put(skb_ptr, descptr->len - 4);
493 + pci_unmap_single(lp->pdev, descptr->buf, MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
494 + skb_ptr->protocol = eth_type_trans(skb_ptr, dev);
495 + netif_rx(skb_ptr); /* Send to upper layer */
496 + lp->stats.rx_packets++;
497 + lp->stats.rx_bytes += descptr->len;
498 + descptr = descptr->vndescp; /* To next descriptor */
499 + lp->rx_free_desc--;
500 + }
501 + lp->rx_remove_ptr = descptr;
502 + }
503 +
504 + /* Allocate new RX buffer */
505 + if (lp->rx_free_desc < RX_DCNT) rx_buf_alloc(lp);
506 +
507 + outw(0x0011, ioaddr + 0x40); /* TX/RX interrupt enable */
508 + spin_unlock_irqrestore(&lp->lock, flags);
509 +
510 + return IRQ_RETVAL(handled);
511 +}
512 +
513 +
514 +static struct net_device_stats *
515 +rdc_get_stats(struct net_device *dev)
516 +{
517 + struct rdc_private *lp = dev->priv;
518 +
519 + RDC_DBUG("rdc_get_stats()", 0);
520 + return &lp->stats;
521 +}
522 +
523 +/*
524 + * Set or clear the multicast filter for this adaptor.
525 + */
526 +static void
527 +set_multicast_list(struct net_device *dev)
528 +{
529 + struct rdc_private *lp = dev->priv;
530 + struct dev_mc_list *mcptr;
531 + int ioaddr = dev->base_addr;
532 + u16 *adrp, i;
533 + unsigned long flags;
534 +
535 + RDC_DBUG("set_multicast_list()", 0);
536 +
537 + /* MAC Address */
538 + ioaddr += 0x68;
539 + adrp = (u16 *) dev->dev_addr;
540 + outw(adrp[0], ioaddr); ioaddr += 2;
541 + outw(adrp[1], ioaddr); ioaddr += 2;
542 + outw(adrp[2], ioaddr); ioaddr += 2;
543 +
544 +#if RDC_DEBUG
545 + printk("MAC ADDR: %04x %04x %04x\n", adrp[0], adrp[1], adrp[2]);
546 +#endif
547 +
548 + /* Promiscous Mode */
549 + spin_lock_irqsave(lp->lock, flags);
550 + i = inw(ioaddr) & ~0x0120; /* Clear AMCP & PROM */
551 + if (dev->flags & IFF_PROMISC) i |= 0x0020;
552 + if (dev->mc_count > 4) i |= 0x0100; /* Too many multicast address */
553 + outw(i, ioaddr);
554 + spin_unlock_irqrestore(lp->lock, flags);
555 +
556 + /* Multicast Address */
557 + if (dev->mc_count > 4) /* Wait to do: Hash Table for multicast */
558 + return;
559 +
560 + /* Multicast Address 1~4 case */
561 + for (i = 0, mcptr = dev->mc_list; (i<dev->mc_count) && (i<4); i++) {
562 + adrp = (u16 *)mcptr->dmi_addr;
563 + outw(adrp[0], ioaddr); ioaddr += 2;
564 + outw(adrp[1], ioaddr); ioaddr += 2;
565 + outw(adrp[2], ioaddr); ioaddr += 2;
566 + mcptr = mcptr->next;
567 +#if RDC_DEBUG
568 + printk("M_ADDR: %04x %04x %04x\n", adrp[0], adrp[1], adrp[2]);
569 +#endif
570 + }
571 + for (i = dev->mc_count; i < 4; i++) {
572 + outw(0xffff, ioaddr); ioaddr += 2;
573 + outw(0xffff, ioaddr); ioaddr += 2;
574 + outw(0xffff, ioaddr); ioaddr += 2;
575 + }
576 +}
577 +
578 +static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
579 +{
580 + struct rdc_private *rp = dev->priv;
581 +
582 + strcpy (info->driver, DRV_NAME);
583 + strcpy (info->version, DRV_VERSION);
584 + strcpy (info->bus_info, pci_name(rp->pdev));
585 +}
586 +
587 +static struct ethtool_ops netdev_ethtool_ops = {
588 + .get_drvinfo = netdev_get_drvinfo,
589 +};
590 +
591 +static int
592 +rdc_close(struct net_device *dev)
593 +{
594 + struct rdc_private *lp = dev->priv;
595 +
596 + RDC_DBUG("rdc_close()", 0);
597 +
598 + /* deleted timer */
599 + del_timer_sync(&lp->timer);
600 +
601 + spin_lock_irq(&lp->lock);
602 +
603 + netif_stop_queue(dev);
604 +
605 + rdc_down(dev);
606 +
607 + spin_unlock_irq(&lp->lock);
608 +
609 + return 0;
610 +}
611 +
612 +/**
613 + */
614 +static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
615 +{
616 + RDC_DBUG("netdev_ioctl()", 0);
617 +
618 +#ifdef FORICPLUS
619 + switch(cmd)
620 + {
621 + case SIOCDEVPRIVATE:
622 +
623 + //printk(KERN_INFO"Ethernet IOCTL: cmd SIOCDEVPRIVATE\n");
624 + {
625 + unsigned long *data;
626 + unsigned long args[4];
627 +
628 + data = (unsigned long *)rq->ifr_data;
629 + if (copy_from_user(args, data, 4*sizeof(unsigned long)))
630 + return -EFAULT;
631 +
632 + process_ioctl(dev, args);
633 + }
634 + break;
635 +
636 + default:
637 + break;
638 + }
639 +#endif
640 + return 0;
641 +}
642 +
643 +/**
644 + Stop RDC MAC and Free the allocated resource
645 + */
646 +static void rdc_down(struct net_device *dev)
647 +{
648 + struct rdc_private *lp = dev->priv;
649 + int i;
650 + int ioaddr = dev->base_addr;
651 +
652 + RDC_DBUG("rdc_down()", 0);
653 +
654 + /* Stop MAC */
655 + outw(0x0000, ioaddr + 0x40); /* Mask Off Interrupt */
656 + outw(0x0001, ioaddr + 0x04); /* Reset RDC MAC */
657 + i = 0;
658 + do{}while((i++ < 2048) && (inw(ioaddr + 0x04) & 0x1));
659 +
660 + free_irq(dev->irq, dev);
661 +
662 + /* Free RX buffer */
663 + for (i = 0; i < RX_DCNT; i++) {
664 + if (lp->rx_insert_ptr->skb_ptr) {
665 + pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf, MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
666 + dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
667 + lp->rx_insert_ptr->skb_ptr = 0;
668 + }
669 + lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
670 + }
671 +
672 + /* Free TX buffer */
673 + for (i = 0; i < TX_DCNT; i++) {
674 + if (lp->tx_insert_ptr->skb_ptr) {
675 + pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf, MAX_BUF_SIZE, PCI_DMA_TODEVICE);
676 + dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
677 + lp->rx_insert_ptr->skb_ptr = 0;
678 + }
679 + lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
680 + }
681 +
682 + /* Free Descriptor memory */
683 + pci_free_consistent(lp->pdev, ALLOC_DESC_SIZE, lp->desc_pool, lp->desc_dma);
684 +}
685 +
686 +/* Init RDC MAC */
687 +static void rdc_up(struct net_device *dev)
688 +{
689 + struct rdc_private *lp = dev->priv;
690 + struct rdc_descriptor *descptr;
691 + int i;
692 + int ioaddr = dev->base_addr;
693 + u32 tmp_addr;
694 + dma_addr_t desc_dma, start_dma;
695 +
696 + RDC_DBUG("rdc_up()", 0);
697 +
698 + /* Initilize */
699 + lp->tx_free_desc = TX_DCNT;
700 + lp->rx_free_desc = 0;
701 +
702 + /* Init descriptor */
703 + memset(lp->desc_pool, 0, ALLOC_DESC_SIZE); /* Let all descriptor = 0 */
704 + lp->tx_insert_ptr = (struct rdc_descriptor *)lp->desc_pool;
705 + lp->tx_remove_ptr = lp->tx_insert_ptr;
706 + lp->rx_insert_ptr = (struct rdc_descriptor *)lp->tx_insert_ptr+TX_DCNT;
707 + lp->rx_remove_ptr = lp->rx_insert_ptr;
708 +
709 + /* Init TX descriptor */
710 + descptr = lp->tx_insert_ptr;
711 + desc_dma = lp->desc_dma;
712 + start_dma = desc_dma;
713 + for (i = 0; i < TX_DCNT; i++) {
714 + descptr->ndesc = cpu_to_le32(desc_dma + sizeof(struct rdc_descriptor));
715 + descptr->vndescp = (descptr + 1);
716 + descptr = (descptr + 1);
717 + desc_dma += sizeof(struct rdc_descriptor);
718 + }
719 + (descptr - 1)->ndesc = cpu_to_le32(start_dma);
720 + (descptr - 1)->vndescp = lp->tx_insert_ptr;
721 +
722 + /* Init RX descriptor */
723 + start_dma = desc_dma;
724 + descptr = lp->rx_insert_ptr;
725 + for (i = 0; i < RX_DCNT; i++) {
726 + descptr->ndesc = cpu_to_le32(desc_dma + sizeof(struct rdc_descriptor));
727 + descptr->vndescp = (descptr + 1);
728 + descptr = (descptr + 1);
729 + desc_dma += sizeof(struct rdc_descriptor);
730 + }
731 + (descptr - 1)->ndesc = cpu_to_le32(start_dma);
732 + (descptr - 1)->vndescp = lp->rx_insert_ptr;
733 +
734 + /* Allocate buffer for RX descriptor */
735 + rx_buf_alloc(lp);
736 +
737 +#if RDC_DEBUG
738 +descptr = lp->tx_insert_ptr;
739 +for (i = 0; i < TX_DCNT; i++) {
740 + printk("%08lx:%04x %04x %08lx %08lx %08lx %08lx\n", descptr, descptr->status, descptr->len, descptr->buf, descptr->skb_ptr, descptr->ndesc, descptr->vndescp);
741 + descptr = descptr->vndescp;
742 +}
743 +descptr = lp->rx_insert_ptr;
744 +for (i = 0; i < RX_DCNT; i++) {
745 + printk("%08lx:%04x %04x %08lx %08lx %08lx %08lx\n", descptr, descptr->status, descptr->len, descptr->buf, descptr->skb_ptr, descptr->ndesc, descptr->vndescp);
746 + descptr = descptr->vndescp;
747 +}
748 +#endif
749 +
750 + /* MAC operation register */
751 + outw(0x01, ioaddr); /* Reset MAC */
752 + outw(2 , ioaddr+0xAC);
753 + outw(0 , ioaddr+0xAC);
754 + udelay(5000);
755 +
756 + /* TX and RX descriptor start Register */
757 + tmp_addr = cpu_to_le32(lp->tx_insert_ptr);
758 + //timc
759 + tmp_addr = virt_to_bus((volatile void *)tmp_addr);
760 + outw((u16) tmp_addr, ioaddr+0x2c);
761 + outw(tmp_addr >> 16, ioaddr+0x30);
762 + tmp_addr = cpu_to_le32(lp->rx_insert_ptr);
763 + //timc
764 + tmp_addr = virt_to_bus((volatile void *)tmp_addr);
765 + outw((u16) tmp_addr, ioaddr+0x34);
766 + outw(tmp_addr >> 16, ioaddr+0x38);
767 +
768 + /* Buffer Size Register */
769 + outw(MAX_BUF_SIZE, ioaddr+0x18);
770 +
771 +#ifdef FORICPLUS
772 +
773 + if(phy_read(ioaddr, 0, 2) == 0x0243) // ICPlus IP175C Signature
774 + {
775 + phy_write(ioaddr, 29,31, 0x175C); //Enable registers
776 + }
777 + lp->phy_mode = 0x8000;
778 +
779 +#else
780 + /* PHY Mode Check */
781 + phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
782 + phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
783 +
784 + if (PHY_MODE == 0x3100)
785 + lp->phy_mode = phy_mode_chk(dev);
786 + else lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
787 +#endif
788 + /* MAC Bus Control Register */
789 + outw(MBCR_DEFAULT, ioaddr+0x8);
790 +
791 + /* MAC TX/RX Enable */
792 + lp->mcr0 |= lp->phy_mode;
793 +
794 + // Dante
795 + // BIT15 | BIT12 | BIT5 | BIT1
796 + lp->mcr0 |= 0x0020;
797 + //Xavier, only set promiscuous mode with eth1 (LAN i/f)
798 + //This is a very bad hard code...
799 + //if(ioaddr == 0xe900)lp->mcr0 |= 0x0020;
800 +
801 + outw(lp->mcr0, ioaddr);
802 +
803 +#ifdef BOOSTRDC
804 + /* set interrupt waiting time and packet numbers */
805 + outw(0x0802, ioaddr + 0x0C);
806 + outw(0x0802, ioaddr + 0x10);
807 +
808 +#ifdef FORICPLUS
809 + /* upgrade performance (by RDC guys) */
810 + phy_write(ioaddr,30,17,(phy_read(ioaddr,30,17)|0x4000)); //bit 14=1
811 + phy_write(ioaddr,30,17,~((~phy_read(ioaddr,30,17))|0x2000)); //bit 13=0
812 + phy_write(ioaddr,0,19,0x0000);
813 + phy_write(ioaddr,0,30,0x01F0);
814 +#endif
815 +#endif
816 +
817 + /* Interrupt Mask Register */
818 + outw(0x0011, ioaddr + 0x40);
819 +}
820 +
821 +/*
822 + A periodic timer routine
823 + Polling PHY Chip Link Status
824 +*/
825 +static void rdc_timer(unsigned long data)
826 +{
827 + struct net_device *dev=(struct net_device *)data;
828 + struct rdc_private *lp = dev->priv;
829 + u16 ioaddr = dev->base_addr, phy_mode;
830 +
831 + RDC_DBUG("rdc_timer()", 0);
832 +
833 + /* Polling PHY Chip Status */
834 + if (PHY_MODE == 0x3100)
835 + phy_mode = phy_mode_chk(dev);
836 + else phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
837 +
838 + if (phy_mode != lp->phy_mode) {
839 + lp->phy_mode = phy_mode;
840 + lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
841 + outw(lp->mcr0, ioaddr);
842 + printk("<RDC> Link Change %x \n", inw(ioaddr));
843 + }
844 +
845 + /* Debug */
846 +// printk("<RDC> Timer: CR0 %x CR40 %x CR3C %x\n", inw(ioaddr), inw(ioaddr+0x40), inw(ioaddr+0x3c));
847 +
848 + /* Timer active again */
849 + lp->timer.expires = TIMER_WUT;
850 + add_timer(&lp->timer);
851 +}
852 +
853 +#ifndef BOOSTRDC
854 +/* Allocate skb buffer for rx descriptor */
855 +static void rx_buf_alloc(struct rdc_private *lp)
856 +{
857 + struct rdc_descriptor *descptr;
858 +
859 + RDC_DBUG("rx_buf_alloc()", 0);
860 + descptr = lp->rx_insert_ptr;
861 + while(lp->rx_free_desc < RX_DCNT){
862 + descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE);
863 + if (!descptr->skb_ptr) break;
864 + descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, descptr->skb_ptr->tail, MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
865 + descptr->status = 0x8000;
866 + descptr = descptr->vndescp;
867 + lp->rx_free_desc++;
868 + }
869 + lp->rx_insert_ptr = descptr;
870 +}
871 +#endif
872 +
873 +/* Status of PHY CHIP */
874 +static int phy_mode_chk(struct net_device *dev)
875 +{
876 +
877 + struct rdc_private *lp = dev->priv;
878 + int ioaddr = dev->base_addr, phy_dat;
879 +
880 + RDC_DBUG("phy_mode_chk()", 0);
881 +
882 + /* PHY Link Status Check */
883 + phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
884 + if (!(phy_dat & 0x4)) return 0x8000; /* Link Failed, full duplex */
885 +
886 + /* PHY Chip Auto-Negotiation Status */
887 + phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
888 + if (phy_dat & 0x0020) {
889 + /* Auto Negotiation Mode */
890 + phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
891 + phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
892 + if (phy_dat & 0x140) phy_dat = 0x8000;
893 + else phy_dat = 0;
894 + } else {
895 + /* Force Mode */
896 + phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
897 + if (phy_dat & 0x100) phy_dat = 0x8000;
898 + else phy_dat = 0x0000;
899 + }
900 +
901 + return phy_dat;
902 +
903 +};
904 +
905 +/* Read a word data from PHY Chip */
906 +static int phy_read(int ioaddr, int phy_addr, int reg_idx)
907 +{
908 + int i = 0;
909 +
910 + RDC_DBUG("phy_read()", 0);
911 + outw(0x2000 + reg_idx + (phy_addr << 8), ioaddr + 0x20);
912 + do{}while( (i++ < 2048) && (inw(ioaddr + 0x20) & 0x2000) );
913 +
914 + return inw(ioaddr + 0x24);
915 +}
916 +
917 +/* Write a word data from PHY Chip */
918 +static void phy_write(int ioaddr, int phy_addr, int reg_idx, int dat)
919 +{
920 + int i = 0;
921 +
922 + RDC_DBUG("phy_write()", 0);
923 + outw(dat, ioaddr + 0x28);
924 + outw(0x4000 + reg_idx + (phy_addr << 8), ioaddr + 0x20);
925 + do{}while( (i++ < 2048) && (inw(ioaddr + 0x20) & 0x4000) );
926 +}
927 +
928 +enum {
929 + RDC_6040 = 0
930 +};
931 +
932 +static struct pci_device_id rdc_pci_tbl[] = {
933 + {0x17F3, 0x6040, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_6040},
934 + //{0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_6040},
935 + {0,} /* terminate list */
936 +};
937 +MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
938 +
939 +static struct pci_driver rdc_driver = {
940 + .name = "r6040",
941 + .id_table = rdc_pci_tbl,
942 + .probe = rdc_init_one,
943 + .remove = __devexit_p(rdc_remove_one),
944 +};
945 +
946 +
947 +static int __init rdc_init (void)
948 +{
949 + RDC_DBUG("rdc_init()", 0);
950 +
951 + printk(version);
952 + printed_version = 1;
953 +
954 + return pci_module_init (&rdc_driver);
955 +}
956 +
957 +
958 +static void __exit rdc_cleanup (void)
959 +{
960 + RDC_DBUG("rdc_cleanup()", 0);
961 + pci_unregister_driver (&rdc_driver);
962 +}
963 +
964 +module_init(rdc_init);
965 +module_exit(rdc_cleanup);
966 +
967 +
968 +/*
969 + * Local variables:
970 + * compile-command: "gcc -DMODULE -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -c rdc.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
971 + * c-indent-level: 4
972 + * c-basic-offset: 4
973 + * tab-width: 4
974 + * End:
975 + */
976 +
977 +#ifdef FORICPLUS
978 +#define DMZ_GPIO 1
979 +#define RDC3210_CFGREG_ADDR 0x0CF8
980 +#define RDC3210_CFGREG_DATA 0x0CFC
981 +static void process_ioctl(struct net_device *dev, unsigned long* args)
982 +{
983 + int ioaddr = dev->base_addr;
984 +
985 + /* port priority */
986 + if(args[0]&(1<<31))phy_write(ioaddr,29,19,(phy_read(ioaddr,29,19)|0x2000)); /* port 0 */
987 + if(args[0]&(1<<29))phy_write(ioaddr,29,19,(phy_read(ioaddr,29,19)|0x0020)); /* port 1 */
988 + if(args[0]&(1<<27))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x2000)); /* port 2 */
989 + if(args[0]&(1<<25))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x0020)); /* port 3 */
990 +
991 + /* DMZ LED */
992 +
993 + {
994 + unsigned int val;
995 +
996 + val = 0x80000000 | (7 << 11) | ((0x48));
997 + outl(val, RDC3210_CFGREG_ADDR);
998 + udelay(10);
999 + val = inl(RDC3210_CFGREG_DATA);
1000 +
1001 + val |= (0x1 << DMZ_GPIO);
1002 + outl(val, RDC3210_CFGREG_DATA);
1003 + udelay(10);
1004 +
1005 + val = 0x80000000 | (7 << 11) | ((0x4C));
1006 + outl(val, RDC3210_CFGREG_ADDR);
1007 + udelay(10);
1008 + val = inl(RDC3210_CFGREG_DATA);
1009 + if(args[0]&(1<<23)) /* DMZ enabled */
1010 + val &= ~(0x1 << DMZ_GPIO); /* low activated */
1011 + else val |= (0x1 << DMZ_GPIO);
1012 + outl(val, RDC3210_CFGREG_DATA);
1013 + udelay(10);
1014 + }
1015 +
1016 +
1017 +}
1018 +#endif /* FORICPLUS */
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