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add preliminary Netgear WNR854T support
[openwrt.git] / target / linux / avr32 / patches / 100-git_sync.patch
1 --- /dev/null
2 +++ b/arch/avr32/boards/atngw100/Kconfig
3 @@ -0,0 +1,12 @@
4 +# NGW100 customization
5 +
6 +config BOARD_ATNGW100_I2C_GPIO
7 + bool "Use GPIO for i2c instead of built-in TWI module"
8 + help
9 + The driver for the built-in TWI module has been plagued by
10 + various problems, while the i2c-gpio driver is based on the
11 + trusty old i2c-algo-bit bitbanging engine, making it work
12 + on pretty much any setup.
13 +
14 + Choose 'Y' here if you're having i2c-related problems and
15 + want to rule out the i2c bus driver.
16 --- a/arch/avr32/boards/atngw100/setup.c
17 +++ b/arch/avr32/boards/atngw100/setup.c
18 @@ -25,6 +25,13 @@
19 #include <asm/arch/init.h>
20 #include <asm/arch/portmux.h>
21
22 +/* Oscillator frequencies. These are board-specific */
23 +unsigned long at32_board_osc_rates[3] = {
24 + [0] = 32768, /* 32.768 kHz on RTC osc */
25 + [1] = 20000000, /* 20 MHz on osc0 */
26 + [2] = 12000000, /* 12 MHz on osc1 */
27 +};
28 +
29 /* Initialized by bootloader-specific startup code. */
30 struct tag *bootloader_tags __initdata;
31
32 @@ -37,11 +44,16 @@
33 static struct spi_board_info spi0_board_info[] __initdata = {
34 {
35 .modalias = "mtd_dataflash",
36 - .max_speed_hz = 10000000,
37 + .max_speed_hz = 8000000,
38 .chip_select = 0,
39 },
40 };
41
42 +static struct mci_platform_data __initdata mci0_data = {
43 + .detect_pin = GPIO_PIN_PC(25),
44 + .wp_pin = GPIO_PIN_PE(0),
45 +};
46 +
47 /*
48 * The next two functions should go away as the boot loader is
49 * supposed to initialize the macb address registers with a valid
50 @@ -124,6 +136,7 @@
51 }
52 };
53
54 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
55 static struct i2c_gpio_platform_data i2c_gpio_data = {
56 .sda_pin = GPIO_PIN_PA(6),
57 .scl_pin = GPIO_PIN_PA(7),
58 @@ -139,6 +152,7 @@
59 .platform_data = &i2c_gpio_data,
60 },
61 };
62 +#endif
63
64 static int __init atngw100_init(void)
65 {
66 @@ -157,6 +171,7 @@
67 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
68
69 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
70 + at32_add_device_mci(0, &mci0_data);
71 at32_add_device_usba(0, NULL);
72
73 for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
74 @@ -165,11 +180,15 @@
75 }
76 platform_device_register(&ngw_gpio_leds);
77
78 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
79 at32_select_gpio(i2c_gpio_data.sda_pin,
80 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
81 at32_select_gpio(i2c_gpio_data.scl_pin,
82 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
83 platform_device_register(&i2c_gpio_device);
84 +#else
85 + at32_add_device_twi(0, NULL, 0);
86 +#endif
87
88 return 0;
89 }
90 --- a/arch/avr32/boards/atstk1000/atstk1002.c
91 +++ b/arch/avr32/boards/atstk1000/atstk1002.c
92 @@ -1,7 +1,7 @@
93 /*
94 - * ATSTK1002 daughterboard-specific init code
95 + * ATSTK1002/ATSTK1006 daughterboard-specific init code
96 *
97 - * Copyright (C) 2005-2006 Atmel Corporation
98 + * Copyright (C) 2005-2007 Atmel Corporation
99 *
100 * This program is free software; you can redistribute it and/or modify
101 * it under the terms of the GNU General Public License version 2 as
102 @@ -28,6 +28,80 @@
103
104 #include "atstk1000.h"
105
106 +/* Oscillator frequencies. These are board specific */
107 +unsigned long at32_board_osc_rates[3] = {
108 + [0] = 32768, /* 32.768 kHz on RTC osc */
109 + [1] = 20000000, /* 20 MHz on osc0 */
110 + [2] = 12000000, /* 12 MHz on osc1 */
111 +};
112 +
113 +/*
114 + * The ATSTK1006 daughterboard is very similar to the ATSTK1002. Both
115 + * have the AT32AP7000 chip on board; the difference is that the
116 + * STK1006 has 128 MB SDRAM (the STK1002 uses the 8 MB SDRAM chip on
117 + * the STK1000 motherboard) and 256 MB NAND flash (the STK1002 has
118 + * none.)
119 + *
120 + * The RAM difference is handled by the boot loader, so the only
121 + * difference we end up handling here is the NAND flash.
122 + */
123 +#ifdef CONFIG_BOARD_ATSTK1006
124 +#include <linux/mtd/partitions.h>
125 +#include <asm/arch/smc.h>
126 +
127 +static struct smc_timing nand_timing __initdata = {
128 + .ncs_read_setup = 0,
129 + .nrd_setup = 10,
130 + .ncs_write_setup = 0,
131 + .nwe_setup = 10,
132 +
133 + .ncs_read_pulse = 30,
134 + .nrd_pulse = 15,
135 + .ncs_write_pulse = 30,
136 + .nwe_pulse = 15,
137 +
138 + .read_cycle = 30,
139 + .write_cycle = 30,
140 +
141 + .ncs_read_recover = 0,
142 + .nrd_recover = 15,
143 + .ncs_write_recover = 0,
144 + /* WE# high -> RE# low min 60 ns */
145 + .nwe_recover = 50,
146 +};
147 +
148 +static struct smc_config nand_config __initdata = {
149 + .bus_width = 1,
150 + .nrd_controlled = 1,
151 + .nwe_controlled = 1,
152 + .nwait_mode = 0,
153 + .byte_write = 0,
154 + .tdf_cycles = 2,
155 + .tdf_mode = 0,
156 +};
157 +
158 +static struct mtd_partition nand_partitions[] = {
159 + {
160 + .name = "main",
161 + .offset = 0x00000000,
162 + .size = MTDPART_SIZ_FULL,
163 + },
164 +};
165 +
166 +static struct mtd_partition *nand_part_info(int size, int *num_partitions)
167 +{
168 + *num_partitions = ARRAY_SIZE(nand_partitions);
169 + return nand_partitions;
170 +}
171 +
172 +static struct atmel_nand_data atstk1006_nand_data __initdata = {
173 + .cle = 21,
174 + .ale = 22,
175 + .rdy_pin = GPIO_PIN_PB(30),
176 + .enable_pin = GPIO_PIN_PB(29),
177 + .partition_info = nand_part_info,
178 +};
179 +#endif
180
181 struct eth_addr {
182 u8 addr[6];
183 @@ -83,6 +157,19 @@
184 } };
185 #endif
186
187 +static struct cf_platform_data __initdata cf0_data = {
188 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
189 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
190 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
191 +#else
192 + .detect_pin = GPIO_PIN_NONE,
193 + .reset_pin = GPIO_PIN_NONE,
194 +#endif
195 + .vcc_pin = GPIO_PIN_NONE,
196 + .ready_pin = GPIO_PIN_PB(27),
197 + .cs = 4,
198 +};
199 +
200 /*
201 * The next two functions should go away as the boot loader is
202 * supposed to initialize the macb address registers with a valid
203 @@ -212,6 +299,12 @@
204
205 at32_add_system_devices();
206
207 +#ifdef CONFIG_BOARD_ATSTK1006
208 + smc_set_timing(&nand_config, &nand_timing);
209 + smc_set_configuration(3, &nand_config);
210 + at32_add_device_nand(0, &atstk1006_nand_data);
211 +#endif
212 +
213 #ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
214 at32_add_device_usart(1);
215 #else
216 @@ -228,16 +321,30 @@
217 #ifdef CONFIG_BOARD_ATSTK100X_SPI1
218 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
219 #endif
220 + at32_add_device_twi(0, NULL, 0);
221 +#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
222 + at32_add_device_mci(0, NULL);
223 +#endif
224 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
225 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
226 #else
227 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
228 - fbmem_start, fbmem_size);
229 + fbmem_start, fbmem_size, 0);
230 #endif
231 at32_add_device_usba(0, NULL);
232 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
233 + at32_add_device_ac97c(0);
234 +#else
235 + at32_add_device_abdac(0);
236 +#endif
237 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
238 at32_add_device_ssc(0, ATMEL_SSC_TX);
239 #endif
240 + at32_add_device_cf(0, 2, &cf0_data);
241 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
242 + at32_add_device_psif(0);
243 + at32_add_device_psif(1);
244 +#endif
245
246 atstk1000_setup_j2_leds();
247 atstk1002_setup_extdac();
248 --- a/arch/avr32/boards/atstk1000/atstk1003.c
249 +++ b/arch/avr32/boards/atstk1000/atstk1003.c
250 @@ -27,6 +27,13 @@
251
252 #include "atstk1000.h"
253
254 +/* Oscillator frequencies. These are board specific */
255 +unsigned long at32_board_osc_rates[3] = {
256 + [0] = 32768, /* 32.768 kHz on RTC osc */
257 + [1] = 20000000, /* 20 MHz on osc0 */
258 + [2] = 12000000, /* 12 MHz on osc1 */
259 +};
260 +
261 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
262 static struct at73c213_board_info at73c213_data = {
263 .ssc_id = 0,
264 @@ -59,6 +66,19 @@
265 } };
266 #endif
267
268 +static struct cf_platform_data __initdata cf0_data = {
269 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
270 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
271 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
272 +#else
273 + .detect_pin = GPIO_PIN_NONE,
274 + .reset_pin = GPIO_PIN_NONE,
275 +#endif
276 + .vcc_pin = GPIO_PIN_NONE,
277 + .ready_pin = GPIO_PIN_PB(27),
278 + .cs = 4,
279 +};
280 +
281 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
282 static void __init atstk1003_setup_extdac(void)
283 {
284 @@ -147,12 +167,22 @@
285 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
286 #endif
287 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
288 - at32_add_device_mci(0);
289 + at32_add_device_mci(0, NULL);
290 #endif
291 at32_add_device_usba(0, NULL);
292 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
293 + at32_add_device_ac97c(0);
294 +#else
295 + at32_add_device_abdac(0);
296 +#endif
297 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
298 at32_add_device_ssc(0, ATMEL_SSC_TX);
299 #endif
300 + at32_add_device_cf(0, 2, &cf0_data);
301 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
302 + at32_add_device_psif(0);
303 + at32_add_device_psif(1);
304 +#endif
305
306 atstk1000_setup_j2_leds();
307 atstk1003_setup_extdac();
308 --- a/arch/avr32/boards/atstk1000/atstk1004.c
309 +++ b/arch/avr32/boards/atstk1000/atstk1004.c
310 @@ -29,6 +29,13 @@
311
312 #include "atstk1000.h"
313
314 +/* Oscillator frequencies. These are board specific */
315 +unsigned long at32_board_osc_rates[3] = {
316 + [0] = 32768, /* 32.768 kHz on RTC osc */
317 + [1] = 20000000, /* 20 MHz on osc0 */
318 + [2] = 12000000, /* 12 MHz on osc1 */
319 +};
320 +
321 #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
322 static struct at73c213_board_info at73c213_data = {
323 .ssc_id = 0,
324 @@ -130,14 +137,23 @@
325 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
326 #endif
327 #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
328 - at32_add_device_mci(0);
329 + at32_add_device_mci(0, NULL);
330 #endif
331 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
332 - fbmem_start, fbmem_size);
333 + fbmem_start, fbmem_size, 0);
334 at32_add_device_usba(0, NULL);
335 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
336 + at32_add_device_ac97c(0);
337 +#else
338 + at32_add_device_abdac(0);
339 +#endif
340 #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
341 at32_add_device_ssc(0, ATMEL_SSC_TX);
342 #endif
343 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
344 + at32_add_device_psif(0);
345 + at32_add_device_psif(1);
346 +#endif
347
348 atstk1000_setup_j2_leds();
349 atstk1004_setup_extdac();
350 --- a/arch/avr32/boards/atstk1000/Kconfig
351 +++ b/arch/avr32/boards/atstk1000/Kconfig
352 @@ -18,6 +18,10 @@
353 bool "ATSTK1004"
354 select CPU_AT32AP7002
355
356 +config BOARD_ATSTK1006
357 + bool "ATSTK1006"
358 + select CPU_AT32AP7000
359 +
360 endchoice
361
362
363 @@ -102,4 +106,60 @@
364 depends on !BOARD_ATSTK100X_SW1_CUSTOM && !BOARD_ATSTK100X_SW3_CUSTOM
365 default y
366
367 +config BOARD_ATSTK100X_ENABLE_AC97
368 + bool "Use AC97C instead of ABDAC"
369 + help
370 + Select this if you want to use the built-in AC97 controller
371 + instead of the built-in Audio Bitstream DAC. These share
372 + the same I/O pins on the AP7000, so both can't be enabled
373 + at the same time.
374 +
375 + Note that the STK1000 kit doesn't ship with an AC97 codec on
376 + board, so say N unless you've got an expansion board with an
377 + AC97 codec on it that you want to use.
378 +
379 +config BOARD_ATSTK1000_CF_HACKS
380 + bool "ATSTK1000 CompactFlash hacks"
381 + depends on !BOARD_ATSTK100X_SW4_CUSTOM
382 + help
383 + Select this if you have re-routed the CompactFlash RESET and
384 + CD signals to GPIOs on your STK1000. This is necessary for
385 + reset and card detection to work properly, although some CF
386 + cards may be able to cope without reset.
387 +
388 +config BOARD_ATSTK1000_CF_RESET_PIN
389 + hex "CompactFlash RESET pin"
390 + default 0x30
391 + depends on BOARD_ATSTK1000_CF_HACKS
392 + help
393 + Select which GPIO pin to use for the CompactFlash RESET
394 + signal. This is specified as a hexadecimal number and should
395 + be defined as 0x20 * gpio_port + pin.
396 +
397 + The default is 0x30, which is pin 16 on PIOB, aka GPIO14.
398 +
399 +config BOARD_ATSTK1000_CF_DETECT_PIN
400 + hex "CompactFlash DETECT pin"
401 + default 0x3e
402 + depends on BOARD_ATSTK1000_CF_HACKS
403 + help
404 + Select which GPIO pin to use for the CompactFlash CD
405 + signal. This is specified as a hexadecimal number and should
406 + be defined as 0x20 * gpio_port + pin.
407 +
408 + The default is 0x3e, which is pin 30 on PIOB, aka GPIO15.
409 +
410 +config BOARD_ATSTK100X_ENABLE_PSIF
411 + bool "Enable PSIF peripheral (PS/2 support)"
412 + default n
413 + help
414 + Select this if you want to use the PSIF peripheral to hook up PS/2
415 + devices to your STK1000. This will require a hardware modification to
416 + work correctly, since PS/2 devices require 5 volt power and signals,
417 + while the STK1000 only provides 3.3 volt.
418 +
419 + Say N if you have not modified the hardware to boost the voltage, say
420 + Y if you have level convertion hardware or a PS/2 device capable of
421 + operating on 3.3 volt.
422 +
423 endif # stk 1000
424 --- a/arch/avr32/boards/atstk1000/Makefile
425 +++ b/arch/avr32/boards/atstk1000/Makefile
426 @@ -2,3 +2,4 @@
427 obj-$(CONFIG_BOARD_ATSTK1002) += atstk1002.o
428 obj-$(CONFIG_BOARD_ATSTK1003) += atstk1003.o
429 obj-$(CONFIG_BOARD_ATSTK1004) += atstk1004.o
430 +obj-$(CONFIG_BOARD_ATSTK1006) += atstk1002.o
431 --- a/arch/avr32/configs/atngw100_defconfig
432 +++ b/arch/avr32/configs/atngw100_defconfig
433 @@ -1,7 +1,7 @@
434 #
435 # Automatically generated make config: don't edit
436 -# Linux kernel version: 2.6.24-rc7
437 -# Wed Jan 9 23:20:41 2008
438 +# Linux kernel version: 2.6.25.4
439 +# Wed Jun 11 15:23:36 2008
440 #
441 CONFIG_AVR32=y
442 CONFIG_GENERIC_GPIO=y
443 @@ -13,10 +13,10 @@
444 CONFIG_GENERIC_IRQ_PROBE=y
445 CONFIG_RWSEM_GENERIC_SPINLOCK=y
446 CONFIG_GENERIC_TIME=y
447 +CONFIG_GENERIC_CLOCKEVENTS=y
448 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
449 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
450 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
451 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
452 CONFIG_GENERIC_HWEIGHT=y
453 CONFIG_GENERIC_CALIBRATE_DELAY=y
454 CONFIG_GENERIC_BUG=y
455 @@ -37,17 +37,15 @@
456 CONFIG_BSD_PROCESS_ACCT=y
457 CONFIG_BSD_PROCESS_ACCT_V3=y
458 # CONFIG_TASKSTATS is not set
459 -# CONFIG_USER_NS is not set
460 -# CONFIG_PID_NS is not set
461 # CONFIG_AUDIT is not set
462 # CONFIG_IKCONFIG is not set
463 CONFIG_LOG_BUF_SHIFT=14
464 # CONFIG_CGROUPS is not set
465 -CONFIG_FAIR_GROUP_SCHED=y
466 -CONFIG_FAIR_USER_SCHED=y
467 -# CONFIG_FAIR_CGROUP_SCHED is not set
468 +# CONFIG_GROUP_SCHED is not set
469 CONFIG_SYSFS_DEPRECATED=y
470 +CONFIG_SYSFS_DEPRECATED_V2=y
471 # CONFIG_RELAY is not set
472 +# CONFIG_NAMESPACES is not set
473 CONFIG_BLK_DEV_INITRD=y
474 CONFIG_INITRAMFS_SOURCE=""
475 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
476 @@ -61,11 +59,13 @@
477 CONFIG_PRINTK=y
478 CONFIG_BUG=y
479 CONFIG_ELF_CORE=y
480 +# CONFIG_COMPAT_BRK is not set
481 # CONFIG_BASE_FULL is not set
482 CONFIG_FUTEX=y
483 CONFIG_ANON_INODES=y
484 CONFIG_EPOLL=y
485 CONFIG_SIGNALFD=y
486 +CONFIG_TIMERFD=y
487 CONFIG_EVENTFD=y
488 CONFIG_SHMEM=y
489 CONFIG_VM_EVENT_COUNTERS=y
490 @@ -73,6 +73,14 @@
491 # CONFIG_SLAB is not set
492 CONFIG_SLUB=y
493 # CONFIG_SLOB is not set
494 +CONFIG_PROFILING=y
495 +# CONFIG_MARKERS is not set
496 +CONFIG_OPROFILE=m
497 +CONFIG_HAVE_OPROFILE=y
498 +CONFIG_KPROBES=y
499 +CONFIG_HAVE_KPROBES=y
500 +# CONFIG_HAVE_KRETPROBES is not set
501 +CONFIG_PROC_PAGE_MONITOR=y
502 CONFIG_SLABINFO=y
503 CONFIG_RT_MUTEXES=y
504 # CONFIG_TINY_SHMEM is not set
505 @@ -101,10 +109,15 @@
506 CONFIG_DEFAULT_CFQ=y
507 # CONFIG_DEFAULT_NOOP is not set
508 CONFIG_DEFAULT_IOSCHED="cfq"
509 +CONFIG_CLASSIC_RCU=y
510
511 #
512 # System Type and features
513 #
514 +CONFIG_TICK_ONESHOT=y
515 +CONFIG_NO_HZ=y
516 +CONFIG_HIGH_RES_TIMERS=y
517 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
518 CONFIG_SUBARCH_AVR32B=y
519 CONFIG_MMU=y
520 CONFIG_PERFORMANCE_COUNTERS=y
521 @@ -113,6 +126,7 @@
522 CONFIG_CPU_AT32AP7000=y
523 # CONFIG_BOARD_ATSTK1000 is not set
524 CONFIG_BOARD_ATNGW100=y
525 +CONFIG_BOARD_ATNGW100_I2C_GPIO=y
526 CONFIG_LOADER_U_BOOT=y
527
528 #
529 @@ -121,6 +135,7 @@
530 # CONFIG_AP700X_32_BIT_SMC is not set
531 CONFIG_AP700X_16_BIT_SMC=y
532 # CONFIG_AP700X_8_BIT_SMC is not set
533 +CONFIG_GPIO_DEV=y
534 CONFIG_LOAD_ADDRESS=0x10000000
535 CONFIG_ENTRY_ADDRESS=0x90000000
536 CONFIG_PHYS_OFFSET=0x10000000
537 @@ -146,16 +161,26 @@
538 CONFIG_ZONE_DMA_FLAG=0
539 CONFIG_VIRT_TO_BUS=y
540 # CONFIG_OWNERSHIP_TRACE is not set
541 +CONFIG_NMI_DEBUGGING=y
542 +CONFIG_DW_DMAC=y
543 # CONFIG_HZ_100 is not set
544 CONFIG_HZ_250=y
545 # CONFIG_HZ_300 is not set
546 # CONFIG_HZ_1000 is not set
547 CONFIG_HZ=250
548 +# CONFIG_SCHED_HRTICK is not set
549 CONFIG_CMDLINE=""
550
551 #
552 # Power management options
553 #
554 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
555 +CONFIG_PM=y
556 +# CONFIG_PM_LEGACY is not set
557 +# CONFIG_PM_DEBUG is not set
558 +CONFIG_PM_SLEEP=y
559 +CONFIG_SUSPEND=y
560 +CONFIG_SUSPEND_FREEZER=y
561
562 #
563 # CPU Frequency scaling
564 @@ -164,9 +189,9 @@
565 CONFIG_CPU_FREQ_TABLE=y
566 # CONFIG_CPU_FREQ_DEBUG is not set
567 # CONFIG_CPU_FREQ_STAT is not set
568 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
569 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
570 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
571 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
572 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
573 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
574 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
575 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
576 @@ -202,6 +227,7 @@
577 CONFIG_XFRM_USER=y
578 # CONFIG_XFRM_SUB_POLICY is not set
579 # CONFIG_XFRM_MIGRATE is not set
580 +# CONFIG_XFRM_STATISTICS is not set
581 CONFIG_NET_KEY=y
582 # CONFIG_NET_KEY_MIGRATE is not set
583 CONFIG_INET=y
584 @@ -260,82 +286,33 @@
585 # CONFIG_NETWORK_SECMARK is not set
586 CONFIG_NETFILTER=y
587 # CONFIG_NETFILTER_DEBUG is not set
588 -CONFIG_BRIDGE_NETFILTER=y
589 +# CONFIG_NETFILTER_ADVANCED is not set
590
591 #
592 # Core Netfilter Configuration
593 #
594 -# CONFIG_NETFILTER_NETLINK is not set
595 -CONFIG_NF_CONNTRACK_ENABLED=m
596 +CONFIG_NETFILTER_NETLINK=m
597 +CONFIG_NETFILTER_NETLINK_LOG=m
598 CONFIG_NF_CONNTRACK=m
599 -CONFIG_NF_CT_ACCT=y
600 -CONFIG_NF_CONNTRACK_MARK=y
601 -# CONFIG_NF_CONNTRACK_EVENTS is not set
602 -CONFIG_NF_CT_PROTO_GRE=m
603 -# CONFIG_NF_CT_PROTO_SCTP is not set
604 -# CONFIG_NF_CT_PROTO_UDPLITE is not set
605 -CONFIG_NF_CONNTRACK_AMANDA=m
606 CONFIG_NF_CONNTRACK_FTP=m
607 -CONFIG_NF_CONNTRACK_H323=m
608 CONFIG_NF_CONNTRACK_IRC=m
609 -CONFIG_NF_CONNTRACK_NETBIOS_NS=m
610 -CONFIG_NF_CONNTRACK_PPTP=m
611 -CONFIG_NF_CONNTRACK_SANE=m
612 CONFIG_NF_CONNTRACK_SIP=m
613 -CONFIG_NF_CONNTRACK_TFTP=m
614 +CONFIG_NF_CT_NETLINK=m
615 CONFIG_NETFILTER_XTABLES=y
616 -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
617 -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
618 -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
619 CONFIG_NETFILTER_XT_TARGET_MARK=m
620 -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
621 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
622 -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
623 -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
624 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
625 -CONFIG_NETFILTER_XT_MATCH_COMMENT=m
626 -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
627 -# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
628 -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
629 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
630 -# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
631 -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
632 -CONFIG_NETFILTER_XT_MATCH_ESP=m
633 -CONFIG_NETFILTER_XT_MATCH_HELPER=m
634 -CONFIG_NETFILTER_XT_MATCH_LENGTH=m
635 -CONFIG_NETFILTER_XT_MATCH_LIMIT=m
636 -CONFIG_NETFILTER_XT_MATCH_MAC=m
637 CONFIG_NETFILTER_XT_MATCH_MARK=m
638 CONFIG_NETFILTER_XT_MATCH_POLICY=m
639 -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
640 -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
641 -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
642 -CONFIG_NETFILTER_XT_MATCH_QUOTA=m
643 -CONFIG_NETFILTER_XT_MATCH_REALM=m
644 -# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
645 CONFIG_NETFILTER_XT_MATCH_STATE=m
646 -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
647 -CONFIG_NETFILTER_XT_MATCH_STRING=m
648 -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
649 -# CONFIG_NETFILTER_XT_MATCH_TIME is not set
650 -# CONFIG_NETFILTER_XT_MATCH_U32 is not set
651 -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
652
653 #
654 # IP: Netfilter Configuration
655 #
656 CONFIG_NF_CONNTRACK_IPV4=m
657 CONFIG_NF_CONNTRACK_PROC_COMPAT=y
658 -# CONFIG_IP_NF_QUEUE is not set
659 CONFIG_IP_NF_IPTABLES=m
660 -CONFIG_IP_NF_MATCH_IPRANGE=m
661 -CONFIG_IP_NF_MATCH_TOS=m
662 -CONFIG_IP_NF_MATCH_RECENT=m
663 -CONFIG_IP_NF_MATCH_ECN=m
664 -CONFIG_IP_NF_MATCH_AH=m
665 -CONFIG_IP_NF_MATCH_TTL=m
666 -CONFIG_IP_NF_MATCH_OWNER=m
667 -CONFIG_IP_NF_MATCH_ADDRTYPE=m
668 CONFIG_IP_NF_FILTER=m
669 CONFIG_IP_NF_TARGET_REJECT=m
670 CONFIG_IP_NF_TARGET_LOG=m
671 @@ -343,54 +320,25 @@
672 CONFIG_NF_NAT=m
673 CONFIG_NF_NAT_NEEDED=y
674 CONFIG_IP_NF_TARGET_MASQUERADE=m
675 -CONFIG_IP_NF_TARGET_REDIRECT=m
676 -CONFIG_IP_NF_TARGET_NETMAP=m
677 -CONFIG_IP_NF_TARGET_SAME=m
678 -CONFIG_NF_NAT_SNMP_BASIC=m
679 -CONFIG_NF_NAT_PROTO_GRE=m
680 CONFIG_NF_NAT_FTP=m
681 CONFIG_NF_NAT_IRC=m
682 -CONFIG_NF_NAT_TFTP=m
683 -CONFIG_NF_NAT_AMANDA=m
684 -CONFIG_NF_NAT_PPTP=m
685 -CONFIG_NF_NAT_H323=m
686 +# CONFIG_NF_NAT_TFTP is not set
687 +# CONFIG_NF_NAT_AMANDA is not set
688 +# CONFIG_NF_NAT_PPTP is not set
689 +# CONFIG_NF_NAT_H323 is not set
690 CONFIG_NF_NAT_SIP=m
691 CONFIG_IP_NF_MANGLE=m
692 -CONFIG_IP_NF_TARGET_TOS=m
693 -CONFIG_IP_NF_TARGET_ECN=m
694 -CONFIG_IP_NF_TARGET_TTL=m
695 -CONFIG_IP_NF_TARGET_CLUSTERIP=m
696 -CONFIG_IP_NF_RAW=m
697 -CONFIG_IP_NF_ARPTABLES=m
698 -CONFIG_IP_NF_ARPFILTER=m
699 -CONFIG_IP_NF_ARP_MANGLE=m
700
701 #
702 -# IPv6: Netfilter Configuration (EXPERIMENTAL)
703 +# IPv6: Netfilter Configuration
704 #
705 CONFIG_NF_CONNTRACK_IPV6=m
706 -CONFIG_IP6_NF_QUEUE=m
707 CONFIG_IP6_NF_IPTABLES=m
708 -CONFIG_IP6_NF_MATCH_RT=m
709 -CONFIG_IP6_NF_MATCH_OPTS=m
710 -CONFIG_IP6_NF_MATCH_FRAG=m
711 -CONFIG_IP6_NF_MATCH_HL=m
712 -CONFIG_IP6_NF_MATCH_OWNER=m
713 CONFIG_IP6_NF_MATCH_IPV6HEADER=m
714 -CONFIG_IP6_NF_MATCH_AH=m
715 -CONFIG_IP6_NF_MATCH_MH=m
716 -CONFIG_IP6_NF_MATCH_EUI64=m
717 CONFIG_IP6_NF_FILTER=m
718 CONFIG_IP6_NF_TARGET_LOG=m
719 CONFIG_IP6_NF_TARGET_REJECT=m
720 CONFIG_IP6_NF_MANGLE=m
721 -CONFIG_IP6_NF_TARGET_HL=m
722 -CONFIG_IP6_NF_RAW=m
723 -
724 -#
725 -# Bridge: Netfilter Configuration
726 -#
727 -# CONFIG_BRIDGE_NF_EBTABLES is not set
728 # CONFIG_IP_DCCP is not set
729 # CONFIG_IP_SCTP is not set
730 # CONFIG_TIPC is not set
731 @@ -407,7 +355,6 @@
732 # CONFIG_ECONET is not set
733 # CONFIG_WAN_ROUTER is not set
734 # CONFIG_NET_SCHED is not set
735 -CONFIG_NET_CLS_ROUTE=y
736
737 #
738 # Network testing
739 @@ -415,6 +362,7 @@
740 # CONFIG_NET_PKTGEN is not set
741 # CONFIG_NET_TCPPROBE is not set
742 # CONFIG_HAMRADIO is not set
743 +# CONFIG_CAN is not set
744 # CONFIG_IRDA is not set
745 # CONFIG_BT is not set
746 # CONFIG_AF_RXRPC is not set
747 @@ -531,11 +479,18 @@
748 CONFIG_BLK_DEV_RAM=m
749 CONFIG_BLK_DEV_RAM_COUNT=16
750 CONFIG_BLK_DEV_RAM_SIZE=4096
751 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
752 +# CONFIG_BLK_DEV_XIP is not set
753 # CONFIG_CDROM_PKTCDVD is not set
754 # CONFIG_ATA_OVER_ETH is not set
755 -# CONFIG_MISC_DEVICES is not set
756 -# CONFIG_IDE is not set
757 +CONFIG_MISC_DEVICES=y
758 +# CONFIG_ATMEL_PWM is not set
759 +CONFIG_ATMEL_TCLIB=y
760 +CONFIG_ATMEL_TCB_CLKSRC=y
761 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
762 +# CONFIG_EEPROM_93CX6 is not set
763 +# CONFIG_ATMEL_SSC is not set
764 +# CONFIG_ENCLOSURE_SERVICES is not set
765 +# CONFIG_HAVE_IDE is not set
766
767 #
768 # SCSI device support
769 @@ -568,11 +523,13 @@
770 # CONFIG_SMSC_PHY is not set
771 # CONFIG_BROADCOM_PHY is not set
772 # CONFIG_ICPLUS_PHY is not set
773 +# CONFIG_REALTEK_PHY is not set
774 # CONFIG_FIXED_PHY is not set
775 # CONFIG_MDIO_BITBANG is not set
776 CONFIG_NET_ETHERNET=y
777 # CONFIG_MII is not set
778 CONFIG_MACB=y
779 +# CONFIG_ENC28J60 is not set
780 # CONFIG_IBM_NEW_EMAC_ZMII is not set
781 # CONFIG_IBM_NEW_EMAC_RGMII is not set
782 # CONFIG_IBM_NEW_EMAC_TAH is not set
783 @@ -599,7 +556,6 @@
784 # CONFIG_PPPOL2TP is not set
785 # CONFIG_SLIP is not set
786 CONFIG_SLHC=m
787 -# CONFIG_SHAPER is not set
788 # CONFIG_NETCONSOLE is not set
789 # CONFIG_NETPOLL is not set
790 # CONFIG_NET_POLL_CONTROLLER is not set
791 @@ -633,6 +589,7 @@
792 #
793 CONFIG_SERIAL_ATMEL=y
794 CONFIG_SERIAL_ATMEL_CONSOLE=y
795 +CONFIG_SERIAL_ATMEL_PDC=y
796 # CONFIG_SERIAL_ATMEL_TTYAT is not set
797 CONFIG_SERIAL_CORE=y
798 CONFIG_SERIAL_CORE_CONSOLE=y
799 @@ -640,8 +597,6 @@
800 # CONFIG_LEGACY_PTYS is not set
801 # CONFIG_IPMI_HANDLER is not set
802 # CONFIG_HW_RANDOM is not set
803 -# CONFIG_RTC is not set
804 -# CONFIG_GEN_RTC is not set
805 # CONFIG_R3964 is not set
806 # CONFIG_RAW_DRIVER is not set
807 # CONFIG_TCG_TPM is not set
808 @@ -659,6 +614,7 @@
809 #
810 # I2C Hardware Bus support
811 #
812 +CONFIG_I2C_ATMELTWI=m
813 CONFIG_I2C_GPIO=m
814 # CONFIG_I2C_OCORES is not set
815 # CONFIG_I2C_PARPORT_LIGHT is not set
816 @@ -669,13 +625,12 @@
817 #
818 # Miscellaneous I2C Chip support
819 #
820 -# CONFIG_SENSORS_DS1337 is not set
821 -# CONFIG_SENSORS_DS1374 is not set
822 # CONFIG_DS1682 is not set
823 # CONFIG_SENSORS_EEPROM is not set
824 # CONFIG_SENSORS_PCF8574 is not set
825 -# CONFIG_SENSORS_PCA9539 is not set
826 +# CONFIG_PCF8575 is not set
827 # CONFIG_SENSORS_PCF8591 is not set
828 +# CONFIG_TPS65010 is not set
829 # CONFIG_SENSORS_MAX6875 is not set
830 # CONFIG_SENSORS_TSL2550 is not set
831 # CONFIG_I2C_DEBUG_CORE is not set
832 @@ -702,9 +657,27 @@
833 # CONFIG_SPI_AT25 is not set
834 CONFIG_SPI_SPIDEV=m
835 # CONFIG_SPI_TLE62X0 is not set
836 +CONFIG_HAVE_GPIO_LIB=y
837 +
838 +#
839 +# GPIO Support
840 +#
841 +# CONFIG_DEBUG_GPIO is not set
842 +
843 +#
844 +# I2C GPIO expanders:
845 +#
846 +# CONFIG_GPIO_PCA953X is not set
847 +# CONFIG_GPIO_PCF857X is not set
848 +
849 +#
850 +# SPI GPIO expanders:
851 +#
852 +# CONFIG_GPIO_MCP23S08 is not set
853 # CONFIG_W1 is not set
854 # CONFIG_POWER_SUPPLY is not set
855 # CONFIG_HWMON is not set
856 +# CONFIG_THERMAL is not set
857 CONFIG_WATCHDOG=y
858 # CONFIG_WATCHDOG_NOWAYOUT is not set
859
860 @@ -757,10 +730,6 @@
861 #
862 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
863 #
864 -
865 -#
866 -# USB Gadget Support
867 -#
868 CONFIG_USB_GADGET=y
869 # CONFIG_USB_GADGET_DEBUG is not set
870 # CONFIG_USB_GADGET_DEBUG_FILES is not set
871 @@ -787,21 +756,24 @@
872 # CONFIG_USB_FILE_STORAGE_TEST is not set
873 CONFIG_USB_G_SERIAL=m
874 # CONFIG_USB_MIDI_GADGET is not set
875 -CONFIG_MMC=m
876 +# CONFIG_USB_G_PRINTER is not set
877 +CONFIG_MMC=y
878 # CONFIG_MMC_DEBUG is not set
879 # CONFIG_MMC_UNSAFE_RESUME is not set
880
881 #
882 # MMC/SD Card Drivers
883 #
884 -CONFIG_MMC_BLOCK=m
885 +CONFIG_MMC_BLOCK=y
886 CONFIG_MMC_BLOCK_BOUNCE=y
887 # CONFIG_SDIO_UART is not set
888
889 #
890 # MMC/SD Host Controller Drivers
891 #
892 +CONFIG_MMC_ATMELMCI=y
893 CONFIG_MMC_SPI=m
894 +# CONFIG_MEMSTICK is not set
895 CONFIG_NEW_LEDS=y
896 CONFIG_LEDS_CLASS=y
897
898 @@ -844,19 +816,22 @@
899 # CONFIG_RTC_DRV_PCF8563 is not set
900 # CONFIG_RTC_DRV_PCF8583 is not set
901 # CONFIG_RTC_DRV_M41T80 is not set
902 +# CONFIG_RTC_DRV_S35390A is not set
903
904 #
905 # SPI RTC drivers
906 #
907 -# CONFIG_RTC_DRV_RS5C348 is not set
908 # CONFIG_RTC_DRV_MAX6902 is not set
909 +# CONFIG_RTC_DRV_R9701 is not set
910 +# CONFIG_RTC_DRV_RS5C348 is not set
911
912 #
913 # Platform RTC drivers
914 #
915 +# CONFIG_RTC_DRV_DS1511 is not set
916 # CONFIG_RTC_DRV_DS1553 is not set
917 -# CONFIG_RTC_DRV_STK17TA8 is not set
918 # CONFIG_RTC_DRV_DS1742 is not set
919 +# CONFIG_RTC_DRV_STK17TA8 is not set
920 # CONFIG_RTC_DRV_M48T86 is not set
921 # CONFIG_RTC_DRV_M48T59 is not set
922 # CONFIG_RTC_DRV_V3020 is not set
923 @@ -874,25 +849,23 @@
924 #
925 # File systems
926 #
927 -CONFIG_EXT2_FS=m
928 +CONFIG_EXT2_FS=y
929 # CONFIG_EXT2_FS_XATTR is not set
930 # CONFIG_EXT2_FS_XIP is not set
931 -CONFIG_EXT3_FS=m
932 +CONFIG_EXT3_FS=y
933 # CONFIG_EXT3_FS_XATTR is not set
934 # CONFIG_EXT4DEV_FS is not set
935 -CONFIG_JBD=m
936 +CONFIG_JBD=y
937 # CONFIG_REISERFS_FS is not set
938 # CONFIG_JFS_FS is not set
939 # CONFIG_FS_POSIX_ACL is not set
940 # CONFIG_XFS_FS is not set
941 # CONFIG_GFS2_FS is not set
942 # CONFIG_OCFS2_FS is not set
943 -# CONFIG_MINIX_FS is not set
944 -# CONFIG_ROMFS_FS is not set
945 +# CONFIG_DNOTIFY is not set
946 CONFIG_INOTIFY=y
947 CONFIG_INOTIFY_USER=y
948 # CONFIG_QUOTA is not set
949 -# CONFIG_DNOTIFY is not set
950 # CONFIG_AUTOFS_FS is not set
951 # CONFIG_AUTOFS4_FS is not set
952 CONFIG_FUSE_FS=m
953 @@ -923,7 +896,7 @@
954 CONFIG_TMPFS=y
955 # CONFIG_TMPFS_POSIX_ACL is not set
956 # CONFIG_HUGETLB_PAGE is not set
957 -CONFIG_CONFIGFS_FS=m
958 +CONFIG_CONFIGFS_FS=y
959
960 #
961 # Miscellaneous filesystems
962 @@ -948,8 +921,10 @@
963 # CONFIG_JFFS2_RUBIN is not set
964 # CONFIG_CRAMFS is not set
965 # CONFIG_VXFS_FS is not set
966 +# CONFIG_MINIX_FS is not set
967 # CONFIG_HPFS_FS is not set
968 # CONFIG_QNX4FS_FS is not set
969 +# CONFIG_ROMFS_FS is not set
970 # CONFIG_SYSV_FS is not set
971 # CONFIG_UFS_FS is not set
972 CONFIG_NETWORK_FILESYSTEMS=y
973 @@ -1030,11 +1005,6 @@
974 # CONFIG_NLS_KOI8_U is not set
975 CONFIG_NLS_UTF8=m
976 # CONFIG_DLM is not set
977 -CONFIG_INSTRUMENTATION=y
978 -CONFIG_PROFILING=y
979 -CONFIG_OPROFILE=m
980 -CONFIG_KPROBES=y
981 -# CONFIG_MARKERS is not set
982
983 #
984 # Kernel hacking
985 @@ -1053,6 +1023,7 @@
986 # CONFIG_SCHEDSTATS is not set
987 # CONFIG_TIMER_STATS is not set
988 # CONFIG_SLUB_DEBUG_ON is not set
989 +# CONFIG_SLUB_STATS is not set
990 # CONFIG_DEBUG_RT_MUTEXES is not set
991 # CONFIG_RT_MUTEX_TESTER is not set
992 # CONFIG_DEBUG_SPINLOCK is not set
993 @@ -1069,9 +1040,10 @@
994 # CONFIG_DEBUG_LIST is not set
995 # CONFIG_DEBUG_SG is not set
996 CONFIG_FRAME_POINTER=y
997 -# CONFIG_FORCED_INLINING is not set
998 # CONFIG_BOOT_PRINTK_DELAY is not set
999 # CONFIG_RCU_TORTURE_TEST is not set
1000 +# CONFIG_KPROBES_SANITY_TEST is not set
1001 +# CONFIG_BACKTRACE_SELF_TEST is not set
1002 # CONFIG_LKDTM is not set
1003 # CONFIG_FAULT_INJECTION is not set
1004 # CONFIG_SAMPLES is not set
1005 @@ -1084,7 +1056,9 @@
1006 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
1007 CONFIG_CRYPTO=y
1008 CONFIG_CRYPTO_ALGAPI=y
1009 +CONFIG_CRYPTO_AEAD=y
1010 CONFIG_CRYPTO_BLKCIPHER=y
1011 +# CONFIG_CRYPTO_SEQIV is not set
1012 CONFIG_CRYPTO_HASH=y
1013 CONFIG_CRYPTO_MANAGER=y
1014 CONFIG_CRYPTO_HMAC=y
1015 @@ -1103,6 +1077,9 @@
1016 CONFIG_CRYPTO_PCBC=m
1017 # CONFIG_CRYPTO_LRW is not set
1018 # CONFIG_CRYPTO_XTS is not set
1019 +# CONFIG_CRYPTO_CTR is not set
1020 +# CONFIG_CRYPTO_GCM is not set
1021 +# CONFIG_CRYPTO_CCM is not set
1022 # CONFIG_CRYPTO_CRYPTD is not set
1023 CONFIG_CRYPTO_DES=y
1024 # CONFIG_CRYPTO_FCRYPT is not set
1025 @@ -1117,12 +1094,14 @@
1026 # CONFIG_CRYPTO_KHAZAD is not set
1027 # CONFIG_CRYPTO_ANUBIS is not set
1028 # CONFIG_CRYPTO_SEED is not set
1029 +# CONFIG_CRYPTO_SALSA20 is not set
1030 CONFIG_CRYPTO_DEFLATE=y
1031 # CONFIG_CRYPTO_MICHAEL_MIC is not set
1032 # CONFIG_CRYPTO_CRC32C is not set
1033 # CONFIG_CRYPTO_CAMELLIA is not set
1034 # CONFIG_CRYPTO_TEST is not set
1035 -# CONFIG_CRYPTO_AUTHENC is not set
1036 +CONFIG_CRYPTO_AUTHENC=y
1037 +# CONFIG_CRYPTO_LZO is not set
1038 CONFIG_CRYPTO_HW=y
1039
1040 #
1041 @@ -1137,10 +1116,7 @@
1042 # CONFIG_LIBCRC32C is not set
1043 CONFIG_ZLIB_INFLATE=y
1044 CONFIG_ZLIB_DEFLATE=y
1045 -CONFIG_TEXTSEARCH=y
1046 -CONFIG_TEXTSEARCH_KMP=m
1047 -CONFIG_TEXTSEARCH_BM=m
1048 -CONFIG_TEXTSEARCH_FSM=m
1049 +CONFIG_GENERIC_ALLOCATOR=y
1050 CONFIG_PLIST=y
1051 CONFIG_HAS_IOMEM=y
1052 CONFIG_HAS_IOPORT=y
1053 --- a/arch/avr32/configs/atstk1002_defconfig
1054 +++ b/arch/avr32/configs/atstk1002_defconfig
1055 @@ -1,7 +1,7 @@
1056 #
1057 # Automatically generated make config: don't edit
1058 -# Linux kernel version: 2.6.24-rc7
1059 -# Wed Jan 9 23:07:43 2008
1060 +# Linux kernel version: 2.6.25.4
1061 +# Wed Jun 11 15:29:18 2008
1062 #
1063 CONFIG_AVR32=y
1064 CONFIG_GENERIC_GPIO=y
1065 @@ -13,10 +13,10 @@
1066 CONFIG_GENERIC_IRQ_PROBE=y
1067 CONFIG_RWSEM_GENERIC_SPINLOCK=y
1068 CONFIG_GENERIC_TIME=y
1069 +CONFIG_GENERIC_CLOCKEVENTS=y
1070 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1071 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
1072 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
1073 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
1074 CONFIG_GENERIC_HWEIGHT=y
1075 CONFIG_GENERIC_CALIBRATE_DELAY=y
1076 CONFIG_GENERIC_BUG=y
1077 @@ -36,15 +36,15 @@
1078 CONFIG_POSIX_MQUEUE=y
1079 # CONFIG_BSD_PROCESS_ACCT is not set
1080 # CONFIG_TASKSTATS is not set
1081 -# CONFIG_USER_NS is not set
1082 -# CONFIG_PID_NS is not set
1083 # CONFIG_AUDIT is not set
1084 # CONFIG_IKCONFIG is not set
1085 CONFIG_LOG_BUF_SHIFT=14
1086 # CONFIG_CGROUPS is not set
1087 -# CONFIG_FAIR_GROUP_SCHED is not set
1088 +# CONFIG_GROUP_SCHED is not set
1089 CONFIG_SYSFS_DEPRECATED=y
1090 +CONFIG_SYSFS_DEPRECATED_V2=y
1091 CONFIG_RELAY=y
1092 +# CONFIG_NAMESPACES is not set
1093 CONFIG_BLK_DEV_INITRD=y
1094 CONFIG_INITRAMFS_SOURCE=""
1095 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1096 @@ -58,11 +58,13 @@
1097 CONFIG_PRINTK=y
1098 CONFIG_BUG=y
1099 CONFIG_ELF_CORE=y
1100 +# CONFIG_COMPAT_BRK is not set
1101 # CONFIG_BASE_FULL is not set
1102 CONFIG_FUTEX=y
1103 CONFIG_ANON_INODES=y
1104 CONFIG_EPOLL=y
1105 CONFIG_SIGNALFD=y
1106 +CONFIG_TIMERFD=y
1107 CONFIG_EVENTFD=y
1108 CONFIG_SHMEM=y
1109 CONFIG_VM_EVENT_COUNTERS=y
1110 @@ -70,6 +72,14 @@
1111 # CONFIG_SLAB is not set
1112 CONFIG_SLUB=y
1113 # CONFIG_SLOB is not set
1114 +CONFIG_PROFILING=y
1115 +# CONFIG_MARKERS is not set
1116 +CONFIG_OPROFILE=m
1117 +CONFIG_HAVE_OPROFILE=y
1118 +CONFIG_KPROBES=y
1119 +CONFIG_HAVE_KPROBES=y
1120 +# CONFIG_HAVE_KRETPROBES is not set
1121 +CONFIG_PROC_PAGE_MONITOR=y
1122 CONFIG_SLABINFO=y
1123 CONFIG_RT_MUTEXES=y
1124 # CONFIG_TINY_SHMEM is not set
1125 @@ -98,10 +108,15 @@
1126 CONFIG_DEFAULT_CFQ=y
1127 # CONFIG_DEFAULT_NOOP is not set
1128 CONFIG_DEFAULT_IOSCHED="cfq"
1129 +CONFIG_CLASSIC_RCU=y
1130
1131 #
1132 # System Type and features
1133 #
1134 +CONFIG_TICK_ONESHOT=y
1135 +CONFIG_NO_HZ=y
1136 +CONFIG_HIGH_RES_TIMERS=y
1137 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1138 CONFIG_SUBARCH_AVR32B=y
1139 CONFIG_MMU=y
1140 CONFIG_PERFORMANCE_COUNTERS=y
1141 @@ -113,12 +128,16 @@
1142 CONFIG_BOARD_ATSTK1002=y
1143 # CONFIG_BOARD_ATSTK1003 is not set
1144 # CONFIG_BOARD_ATSTK1004 is not set
1145 +# CONFIG_BOARD_ATSTK1006 is not set
1146 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
1147 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
1148 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
1149 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
1150 # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
1151 CONFIG_BOARD_ATSTK1000_EXTDAC=y
1152 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
1153 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
1154 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
1155 CONFIG_LOADER_U_BOOT=y
1156
1157 #
1158 @@ -127,6 +146,7 @@
1159 # CONFIG_AP700X_32_BIT_SMC is not set
1160 CONFIG_AP700X_16_BIT_SMC=y
1161 # CONFIG_AP700X_8_BIT_SMC is not set
1162 +CONFIG_GPIO_DEV=y
1163 CONFIG_LOAD_ADDRESS=0x10000000
1164 CONFIG_ENTRY_ADDRESS=0x90000000
1165 CONFIG_PHYS_OFFSET=0x10000000
1166 @@ -152,16 +172,26 @@
1167 CONFIG_ZONE_DMA_FLAG=0
1168 CONFIG_VIRT_TO_BUS=y
1169 # CONFIG_OWNERSHIP_TRACE is not set
1170 +CONFIG_NMI_DEBUGGING=y
1171 +CONFIG_DW_DMAC=y
1172 # CONFIG_HZ_100 is not set
1173 CONFIG_HZ_250=y
1174 # CONFIG_HZ_300 is not set
1175 # CONFIG_HZ_1000 is not set
1176 CONFIG_HZ=250
1177 +# CONFIG_SCHED_HRTICK is not set
1178 CONFIG_CMDLINE=""
1179
1180 #
1181 # Power management options
1182 #
1183 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1184 +CONFIG_PM=y
1185 +# CONFIG_PM_LEGACY is not set
1186 +# CONFIG_PM_DEBUG is not set
1187 +CONFIG_PM_SLEEP=y
1188 +CONFIG_SUSPEND=y
1189 +CONFIG_SUSPEND_FREEZER=y
1190
1191 #
1192 # CPU Frequency scaling
1193 @@ -170,9 +200,9 @@
1194 CONFIG_CPU_FREQ_TABLE=y
1195 # CONFIG_CPU_FREQ_DEBUG is not set
1196 # CONFIG_CPU_FREQ_STAT is not set
1197 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
1198 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
1199 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
1200 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
1201 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
1202 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
1203 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1204 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
1205 @@ -208,6 +238,7 @@
1206 CONFIG_XFRM_USER=m
1207 # CONFIG_XFRM_SUB_POLICY is not set
1208 # CONFIG_XFRM_MIGRATE is not set
1209 +# CONFIG_XFRM_STATISTICS is not set
1210 CONFIG_NET_KEY=m
1211 # CONFIG_NET_KEY_MIGRATE is not set
1212 CONFIG_INET=y
1213 @@ -279,6 +310,7 @@
1214 # CONFIG_NET_PKTGEN is not set
1215 # CONFIG_NET_TCPPROBE is not set
1216 # CONFIG_HAMRADIO is not set
1217 +# CONFIG_CAN is not set
1218 # CONFIG_IRDA is not set
1219 # CONFIG_BT is not set
1220 # CONFIG_AF_RXRPC is not set
1221 @@ -395,13 +427,18 @@
1222 CONFIG_BLK_DEV_RAM=m
1223 CONFIG_BLK_DEV_RAM_COUNT=16
1224 CONFIG_BLK_DEV_RAM_SIZE=4096
1225 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1226 +# CONFIG_BLK_DEV_XIP is not set
1227 # CONFIG_CDROM_PKTCDVD is not set
1228 # CONFIG_ATA_OVER_ETH is not set
1229 CONFIG_MISC_DEVICES=y
1230 +CONFIG_ATMEL_PWM=m
1231 +CONFIG_ATMEL_TCLIB=y
1232 +CONFIG_ATMEL_TCB_CLKSRC=y
1233 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
1234 # CONFIG_EEPROM_93CX6 is not set
1235 CONFIG_ATMEL_SSC=m
1236 -# CONFIG_IDE is not set
1237 +# CONFIG_ENCLOSURE_SERVICES is not set
1238 +# CONFIG_HAVE_IDE is not set
1239
1240 #
1241 # SCSI device support
1242 @@ -444,6 +481,7 @@
1243 # CONFIG_SCSI_LOWLEVEL is not set
1244 CONFIG_ATA=m
1245 # CONFIG_ATA_NONSTANDARD is not set
1246 +# CONFIG_SATA_MV is not set
1247 CONFIG_PATA_AT32=m
1248 # CONFIG_PATA_PLATFORM is not set
1249 # CONFIG_MD is not set
1250 @@ -469,11 +507,13 @@
1251 # CONFIG_SMSC_PHY is not set
1252 # CONFIG_BROADCOM_PHY is not set
1253 # CONFIG_ICPLUS_PHY is not set
1254 +# CONFIG_REALTEK_PHY is not set
1255 # CONFIG_FIXED_PHY is not set
1256 # CONFIG_MDIO_BITBANG is not set
1257 CONFIG_NET_ETHERNET=y
1258 # CONFIG_MII is not set
1259 CONFIG_MACB=y
1260 +# CONFIG_ENC28J60 is not set
1261 # CONFIG_IBM_NEW_EMAC_ZMII is not set
1262 # CONFIG_IBM_NEW_EMAC_RGMII is not set
1263 # CONFIG_IBM_NEW_EMAC_TAH is not set
1264 @@ -500,7 +540,6 @@
1265 # CONFIG_PPPOL2TP is not set
1266 # CONFIG_SLIP is not set
1267 CONFIG_SLHC=m
1268 -# CONFIG_SHAPER is not set
1269 # CONFIG_NETCONSOLE is not set
1270 # CONFIG_NETPOLL is not set
1271 # CONFIG_NET_POLL_CONTROLLER is not set
1272 @@ -568,6 +607,7 @@
1273 #
1274 CONFIG_SERIAL_ATMEL=y
1275 CONFIG_SERIAL_ATMEL_CONSOLE=y
1276 +CONFIG_SERIAL_ATMEL_PDC=y
1277 # CONFIG_SERIAL_ATMEL_TTYAT is not set
1278 CONFIG_SERIAL_CORE=y
1279 CONFIG_SERIAL_CORE_CONSOLE=y
1280 @@ -575,8 +615,6 @@
1281 # CONFIG_LEGACY_PTYS is not set
1282 # CONFIG_IPMI_HANDLER is not set
1283 # CONFIG_HW_RANDOM is not set
1284 -# CONFIG_RTC is not set
1285 -# CONFIG_GEN_RTC is not set
1286 # CONFIG_R3964 is not set
1287 # CONFIG_RAW_DRIVER is not set
1288 # CONFIG_TCG_TPM is not set
1289 @@ -594,6 +632,7 @@
1290 #
1291 # I2C Hardware Bus support
1292 #
1293 +CONFIG_I2C_ATMELTWI=m
1294 CONFIG_I2C_GPIO=m
1295 # CONFIG_I2C_OCORES is not set
1296 # CONFIG_I2C_PARPORT_LIGHT is not set
1297 @@ -604,13 +643,12 @@
1298 #
1299 # Miscellaneous I2C Chip support
1300 #
1301 -# CONFIG_SENSORS_DS1337 is not set
1302 -# CONFIG_SENSORS_DS1374 is not set
1303 # CONFIG_DS1682 is not set
1304 # CONFIG_SENSORS_EEPROM is not set
1305 # CONFIG_SENSORS_PCF8574 is not set
1306 -# CONFIG_SENSORS_PCA9539 is not set
1307 +# CONFIG_PCF8575 is not set
1308 # CONFIG_SENSORS_PCF8591 is not set
1309 +# CONFIG_TPS65010 is not set
1310 # CONFIG_SENSORS_MAX6875 is not set
1311 # CONFIG_SENSORS_TSL2550 is not set
1312 # CONFIG_I2C_DEBUG_CORE is not set
1313 @@ -637,9 +675,27 @@
1314 # CONFIG_SPI_AT25 is not set
1315 CONFIG_SPI_SPIDEV=m
1316 # CONFIG_SPI_TLE62X0 is not set
1317 +CONFIG_HAVE_GPIO_LIB=y
1318 +
1319 +#
1320 +# GPIO Support
1321 +#
1322 +# CONFIG_DEBUG_GPIO is not set
1323 +
1324 +#
1325 +# I2C GPIO expanders:
1326 +#
1327 +# CONFIG_GPIO_PCA953X is not set
1328 +# CONFIG_GPIO_PCF857X is not set
1329 +
1330 +#
1331 +# SPI GPIO expanders:
1332 +#
1333 +# CONFIG_GPIO_MCP23S08 is not set
1334 # CONFIG_W1 is not set
1335 # CONFIG_POWER_SUPPLY is not set
1336 # CONFIG_HWMON is not set
1337 +# CONFIG_THERMAL is not set
1338 CONFIG_WATCHDOG=y
1339 # CONFIG_WATCHDOG_NOWAYOUT is not set
1340
1341 @@ -732,12 +788,18 @@
1342 #
1343 # Generic devices
1344 #
1345 +CONFIG_SND_AC97_CODEC=m
1346 # CONFIG_SND_DUMMY is not set
1347 # CONFIG_SND_MTPAV is not set
1348 # CONFIG_SND_SERIAL_U16550 is not set
1349 # CONFIG_SND_MPU401 is not set
1350
1351 #
1352 +# AVR32 devices
1353 +#
1354 +CONFIG_SND_ATMEL_AC97=m
1355 +
1356 +#
1357 # SPI devices
1358 #
1359 CONFIG_SND_AT73C213=m
1360 @@ -753,9 +815,14 @@
1361 #
1362
1363 #
1364 +# ALSA SoC audio for Freescale SOCs
1365 +#
1366 +
1367 +#
1368 # Open Sound System
1369 #
1370 # CONFIG_SOUND_PRIME is not set
1371 +CONFIG_AC97_BUS=m
1372 # CONFIG_HID_SUPPORT is not set
1373 CONFIG_USB_SUPPORT=y
1374 # CONFIG_USB_ARCH_HAS_HCD is not set
1375 @@ -765,10 +832,6 @@
1376 #
1377 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1378 #
1379 -
1380 -#
1381 -# USB Gadget Support
1382 -#
1383 CONFIG_USB_GADGET=y
1384 # CONFIG_USB_GADGET_DEBUG is not set
1385 # CONFIG_USB_GADGET_DEBUG_FILES is not set
1386 @@ -796,27 +859,31 @@
1387 # CONFIG_USB_FILE_STORAGE_TEST is not set
1388 CONFIG_USB_G_SERIAL=m
1389 # CONFIG_USB_MIDI_GADGET is not set
1390 -CONFIG_MMC=m
1391 +# CONFIG_USB_G_PRINTER is not set
1392 +CONFIG_MMC=y
1393 # CONFIG_MMC_DEBUG is not set
1394 # CONFIG_MMC_UNSAFE_RESUME is not set
1395
1396 #
1397 # MMC/SD Card Drivers
1398 #
1399 -CONFIG_MMC_BLOCK=m
1400 +CONFIG_MMC_BLOCK=y
1401 CONFIG_MMC_BLOCK_BOUNCE=y
1402 # CONFIG_SDIO_UART is not set
1403
1404 #
1405 # MMC/SD Host Controller Drivers
1406 #
1407 +CONFIG_MMC_ATMELMCI=y
1408 CONFIG_MMC_SPI=m
1409 +# CONFIG_MEMSTICK is not set
1410 CONFIG_NEW_LEDS=y
1411 CONFIG_LEDS_CLASS=m
1412
1413 #
1414 # LED drivers
1415 #
1416 +CONFIG_LEDS_ATMEL_PWM=m
1417 CONFIG_LEDS_GPIO=m
1418
1419 #
1420 @@ -853,19 +920,22 @@
1421 # CONFIG_RTC_DRV_PCF8563 is not set
1422 # CONFIG_RTC_DRV_PCF8583 is not set
1423 # CONFIG_RTC_DRV_M41T80 is not set
1424 +# CONFIG_RTC_DRV_S35390A is not set
1425
1426 #
1427 # SPI RTC drivers
1428 #
1429 -# CONFIG_RTC_DRV_RS5C348 is not set
1430 # CONFIG_RTC_DRV_MAX6902 is not set
1431 +# CONFIG_RTC_DRV_R9701 is not set
1432 +# CONFIG_RTC_DRV_RS5C348 is not set
1433
1434 #
1435 # Platform RTC drivers
1436 #
1437 +# CONFIG_RTC_DRV_DS1511 is not set
1438 # CONFIG_RTC_DRV_DS1553 is not set
1439 -# CONFIG_RTC_DRV_STK17TA8 is not set
1440 # CONFIG_RTC_DRV_DS1742 is not set
1441 +# CONFIG_RTC_DRV_STK17TA8 is not set
1442 # CONFIG_RTC_DRV_M48T86 is not set
1443 # CONFIG_RTC_DRV_M48T59 is not set
1444 # CONFIG_RTC_DRV_V3020 is not set
1445 @@ -883,13 +953,13 @@
1446 #
1447 # File systems
1448 #
1449 -CONFIG_EXT2_FS=m
1450 +CONFIG_EXT2_FS=y
1451 # CONFIG_EXT2_FS_XATTR is not set
1452 # CONFIG_EXT2_FS_XIP is not set
1453 -CONFIG_EXT3_FS=m
1454 +CONFIG_EXT3_FS=y
1455 # CONFIG_EXT3_FS_XATTR is not set
1456 # CONFIG_EXT4DEV_FS is not set
1457 -CONFIG_JBD=m
1458 +CONFIG_JBD=y
1459 # CONFIG_JBD_DEBUG is not set
1460 # CONFIG_REISERFS_FS is not set
1461 # CONFIG_JFS_FS is not set
1462 @@ -897,12 +967,10 @@
1463 # CONFIG_XFS_FS is not set
1464 # CONFIG_GFS2_FS is not set
1465 # CONFIG_OCFS2_FS is not set
1466 -CONFIG_MINIX_FS=m
1467 -# CONFIG_ROMFS_FS is not set
1468 +# CONFIG_DNOTIFY is not set
1469 CONFIG_INOTIFY=y
1470 CONFIG_INOTIFY_USER=y
1471 # CONFIG_QUOTA is not set
1472 -# CONFIG_DNOTIFY is not set
1473 # CONFIG_AUTOFS_FS is not set
1474 # CONFIG_AUTOFS4_FS is not set
1475 CONFIG_FUSE_FS=m
1476 @@ -933,7 +1001,7 @@
1477 CONFIG_TMPFS=y
1478 # CONFIG_TMPFS_POSIX_ACL is not set
1479 # CONFIG_HUGETLB_PAGE is not set
1480 -# CONFIG_CONFIGFS_FS is not set
1481 +CONFIG_CONFIGFS_FS=y
1482
1483 #
1484 # Miscellaneous filesystems
1485 @@ -957,8 +1025,10 @@
1486 # CONFIG_JFFS2_RUBIN is not set
1487 # CONFIG_CRAMFS is not set
1488 # CONFIG_VXFS_FS is not set
1489 +CONFIG_MINIX_FS=m
1490 # CONFIG_HPFS_FS is not set
1491 # CONFIG_QNX4FS_FS is not set
1492 +# CONFIG_ROMFS_FS is not set
1493 # CONFIG_SYSV_FS is not set
1494 # CONFIG_UFS_FS is not set
1495 CONFIG_NETWORK_FILESYSTEMS=y
1496 @@ -1028,11 +1098,6 @@
1497 # CONFIG_NLS_KOI8_U is not set
1498 CONFIG_NLS_UTF8=m
1499 # CONFIG_DLM is not set
1500 -CONFIG_INSTRUMENTATION=y
1501 -CONFIG_PROFILING=y
1502 -CONFIG_OPROFILE=m
1503 -CONFIG_KPROBES=y
1504 -# CONFIG_MARKERS is not set
1505
1506 #
1507 # Kernel hacking
1508 @@ -1051,6 +1116,7 @@
1509 # CONFIG_SCHEDSTATS is not set
1510 # CONFIG_TIMER_STATS is not set
1511 # CONFIG_SLUB_DEBUG_ON is not set
1512 +# CONFIG_SLUB_STATS is not set
1513 # CONFIG_DEBUG_RT_MUTEXES is not set
1514 # CONFIG_RT_MUTEX_TESTER is not set
1515 # CONFIG_DEBUG_SPINLOCK is not set
1516 @@ -1067,9 +1133,10 @@
1517 # CONFIG_DEBUG_LIST is not set
1518 # CONFIG_DEBUG_SG is not set
1519 CONFIG_FRAME_POINTER=y
1520 -CONFIG_FORCED_INLINING=y
1521 # CONFIG_BOOT_PRINTK_DELAY is not set
1522 # CONFIG_RCU_TORTURE_TEST is not set
1523 +# CONFIG_KPROBES_SANITY_TEST is not set
1524 +# CONFIG_BACKTRACE_SELF_TEST is not set
1525 # CONFIG_LKDTM is not set
1526 # CONFIG_FAULT_INJECTION is not set
1527 # CONFIG_SAMPLES is not set
1528 @@ -1082,7 +1149,9 @@
1529 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
1530 CONFIG_CRYPTO=y
1531 CONFIG_CRYPTO_ALGAPI=m
1532 +CONFIG_CRYPTO_AEAD=m
1533 CONFIG_CRYPTO_BLKCIPHER=m
1534 +# CONFIG_CRYPTO_SEQIV is not set
1535 CONFIG_CRYPTO_HASH=m
1536 CONFIG_CRYPTO_MANAGER=m
1537 CONFIG_CRYPTO_HMAC=m
1538 @@ -1101,6 +1170,9 @@
1539 # CONFIG_CRYPTO_PCBC is not set
1540 # CONFIG_CRYPTO_LRW is not set
1541 # CONFIG_CRYPTO_XTS is not set
1542 +# CONFIG_CRYPTO_CTR is not set
1543 +# CONFIG_CRYPTO_GCM is not set
1544 +# CONFIG_CRYPTO_CCM is not set
1545 # CONFIG_CRYPTO_CRYPTD is not set
1546 CONFIG_CRYPTO_DES=m
1547 # CONFIG_CRYPTO_FCRYPT is not set
1548 @@ -1115,12 +1187,14 @@
1549 # CONFIG_CRYPTO_KHAZAD is not set
1550 # CONFIG_CRYPTO_ANUBIS is not set
1551 # CONFIG_CRYPTO_SEED is not set
1552 +# CONFIG_CRYPTO_SALSA20 is not set
1553 CONFIG_CRYPTO_DEFLATE=m
1554 # CONFIG_CRYPTO_MICHAEL_MIC is not set
1555 # CONFIG_CRYPTO_CRC32C is not set
1556 # CONFIG_CRYPTO_CAMELLIA is not set
1557 # CONFIG_CRYPTO_TEST is not set
1558 -# CONFIG_CRYPTO_AUTHENC is not set
1559 +CONFIG_CRYPTO_AUTHENC=m
1560 +# CONFIG_CRYPTO_LZO is not set
1561 # CONFIG_CRYPTO_HW is not set
1562
1563 #
1564 @@ -1135,6 +1209,7 @@
1565 # CONFIG_LIBCRC32C is not set
1566 CONFIG_ZLIB_INFLATE=y
1567 CONFIG_ZLIB_DEFLATE=y
1568 +CONFIG_GENERIC_ALLOCATOR=y
1569 CONFIG_PLIST=y
1570 CONFIG_HAS_IOMEM=y
1571 CONFIG_HAS_IOPORT=y
1572 --- a/arch/avr32/configs/atstk1003_defconfig
1573 +++ b/arch/avr32/configs/atstk1003_defconfig
1574 @@ -1,7 +1,7 @@
1575 #
1576 # Automatically generated make config: don't edit
1577 -# Linux kernel version: 2.6.24-rc7
1578 -# Wed Jan 9 22:54:34 2008
1579 +# Linux kernel version: 2.6.25.4
1580 +# Wed Jun 11 15:33:36 2008
1581 #
1582 CONFIG_AVR32=y
1583 CONFIG_GENERIC_GPIO=y
1584 @@ -13,10 +13,10 @@
1585 CONFIG_GENERIC_IRQ_PROBE=y
1586 CONFIG_RWSEM_GENERIC_SPINLOCK=y
1587 CONFIG_GENERIC_TIME=y
1588 +CONFIG_GENERIC_CLOCKEVENTS=y
1589 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1590 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
1591 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
1592 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
1593 CONFIG_GENERIC_HWEIGHT=y
1594 CONFIG_GENERIC_CALIBRATE_DELAY=y
1595 CONFIG_GENERIC_BUG=y
1596 @@ -39,17 +39,15 @@
1597 CONFIG_TASKSTATS=y
1598 CONFIG_TASK_DELAY_ACCT=y
1599 # CONFIG_TASK_XACCT is not set
1600 -# CONFIG_USER_NS is not set
1601 -# CONFIG_PID_NS is not set
1602 CONFIG_AUDIT=y
1603 # CONFIG_IKCONFIG is not set
1604 CONFIG_LOG_BUF_SHIFT=14
1605 # CONFIG_CGROUPS is not set
1606 -CONFIG_FAIR_GROUP_SCHED=y
1607 -CONFIG_FAIR_USER_SCHED=y
1608 -# CONFIG_FAIR_CGROUP_SCHED is not set
1609 +# CONFIG_GROUP_SCHED is not set
1610 CONFIG_SYSFS_DEPRECATED=y
1611 +CONFIG_SYSFS_DEPRECATED_V2=y
1612 CONFIG_RELAY=y
1613 +# CONFIG_NAMESPACES is not set
1614 CONFIG_BLK_DEV_INITRD=y
1615 CONFIG_INITRAMFS_SOURCE=""
1616 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
1617 @@ -63,11 +61,13 @@
1618 CONFIG_PRINTK=y
1619 CONFIG_BUG=y
1620 CONFIG_ELF_CORE=y
1621 +# CONFIG_COMPAT_BRK is not set
1622 # CONFIG_BASE_FULL is not set
1623 CONFIG_FUTEX=y
1624 CONFIG_ANON_INODES=y
1625 CONFIG_EPOLL=y
1626 CONFIG_SIGNALFD=y
1627 +CONFIG_TIMERFD=y
1628 CONFIG_EVENTFD=y
1629 CONFIG_SHMEM=y
1630 CONFIG_VM_EVENT_COUNTERS=y
1631 @@ -75,6 +75,14 @@
1632 # CONFIG_SLAB is not set
1633 CONFIG_SLUB=y
1634 # CONFIG_SLOB is not set
1635 +CONFIG_PROFILING=y
1636 +# CONFIG_MARKERS is not set
1637 +CONFIG_OPROFILE=m
1638 +CONFIG_HAVE_OPROFILE=y
1639 +CONFIG_KPROBES=y
1640 +CONFIG_HAVE_KPROBES=y
1641 +# CONFIG_HAVE_KRETPROBES is not set
1642 +CONFIG_PROC_PAGE_MONITOR=y
1643 CONFIG_SLABINFO=y
1644 CONFIG_RT_MUTEXES=y
1645 # CONFIG_TINY_SHMEM is not set
1646 @@ -103,10 +111,15 @@
1647 CONFIG_DEFAULT_CFQ=y
1648 # CONFIG_DEFAULT_NOOP is not set
1649 CONFIG_DEFAULT_IOSCHED="cfq"
1650 +CONFIG_CLASSIC_RCU=y
1651
1652 #
1653 # System Type and features
1654 #
1655 +CONFIG_TICK_ONESHOT=y
1656 +CONFIG_NO_HZ=y
1657 +CONFIG_HIGH_RES_TIMERS=y
1658 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1659 CONFIG_SUBARCH_AVR32B=y
1660 CONFIG_MMU=y
1661 CONFIG_PERFORMANCE_COUNTERS=y
1662 @@ -118,12 +131,16 @@
1663 # CONFIG_BOARD_ATSTK1002 is not set
1664 CONFIG_BOARD_ATSTK1003=y
1665 # CONFIG_BOARD_ATSTK1004 is not set
1666 +# CONFIG_BOARD_ATSTK1006 is not set
1667 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
1668 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
1669 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
1670 # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
1671 # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
1672 CONFIG_BOARD_ATSTK1000_EXTDAC=y
1673 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
1674 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
1675 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
1676 CONFIG_LOADER_U_BOOT=y
1677
1678 #
1679 @@ -132,6 +149,7 @@
1680 # CONFIG_AP700X_32_BIT_SMC is not set
1681 CONFIG_AP700X_16_BIT_SMC=y
1682 # CONFIG_AP700X_8_BIT_SMC is not set
1683 +CONFIG_GPIO_DEV=y
1684 CONFIG_LOAD_ADDRESS=0x10000000
1685 CONFIG_ENTRY_ADDRESS=0x90000000
1686 CONFIG_PHYS_OFFSET=0x10000000
1687 @@ -157,16 +175,26 @@
1688 CONFIG_ZONE_DMA_FLAG=0
1689 CONFIG_VIRT_TO_BUS=y
1690 # CONFIG_OWNERSHIP_TRACE is not set
1691 +CONFIG_NMI_DEBUGGING=y
1692 +CONFIG_DW_DMAC=y
1693 # CONFIG_HZ_100 is not set
1694 CONFIG_HZ_250=y
1695 # CONFIG_HZ_300 is not set
1696 # CONFIG_HZ_1000 is not set
1697 CONFIG_HZ=250
1698 +# CONFIG_SCHED_HRTICK is not set
1699 CONFIG_CMDLINE=""
1700
1701 #
1702 # Power management options
1703 #
1704 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
1705 +CONFIG_PM=y
1706 +# CONFIG_PM_LEGACY is not set
1707 +# CONFIG_PM_DEBUG is not set
1708 +CONFIG_PM_SLEEP=y
1709 +CONFIG_SUSPEND=y
1710 +CONFIG_SUSPEND_FREEZER=y
1711
1712 #
1713 # CPU Frequency scaling
1714 @@ -175,9 +203,9 @@
1715 CONFIG_CPU_FREQ_TABLE=y
1716 # CONFIG_CPU_FREQ_DEBUG is not set
1717 # CONFIG_CPU_FREQ_STAT is not set
1718 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
1719 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
1720 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
1721 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
1722 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
1723 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
1724 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1725 # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
1726 @@ -260,6 +288,7 @@
1727 # CONFIG_NET_PKTGEN is not set
1728 # CONFIG_NET_TCPPROBE is not set
1729 # CONFIG_HAMRADIO is not set
1730 +# CONFIG_CAN is not set
1731 # CONFIG_IRDA is not set
1732 # CONFIG_BT is not set
1733 # CONFIG_AF_RXRPC is not set
1734 @@ -376,13 +405,18 @@
1735 CONFIG_BLK_DEV_RAM=m
1736 CONFIG_BLK_DEV_RAM_COUNT=16
1737 CONFIG_BLK_DEV_RAM_SIZE=4096
1738 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1739 +# CONFIG_BLK_DEV_XIP is not set
1740 # CONFIG_CDROM_PKTCDVD is not set
1741 # CONFIG_ATA_OVER_ETH is not set
1742 CONFIG_MISC_DEVICES=y
1743 +CONFIG_ATMEL_PWM=m
1744 +CONFIG_ATMEL_TCLIB=y
1745 +CONFIG_ATMEL_TCB_CLKSRC=y
1746 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
1747 # CONFIG_EEPROM_93CX6 is not set
1748 CONFIG_ATMEL_SSC=m
1749 -# CONFIG_IDE is not set
1750 +# CONFIG_ENCLOSURE_SERVICES is not set
1751 +# CONFIG_HAVE_IDE is not set
1752
1753 #
1754 # SCSI device support
1755 @@ -427,6 +461,7 @@
1756 # CONFIG_SCSI_DEBUG is not set
1757 CONFIG_ATA=m
1758 # CONFIG_ATA_NONSTANDARD is not set
1759 +# CONFIG_SATA_MV is not set
1760 CONFIG_PATA_AT32=m
1761 # CONFIG_PATA_PLATFORM is not set
1762 # CONFIG_MD is not set
1763 @@ -460,7 +495,6 @@
1764 # CONFIG_PPPOL2TP is not set
1765 # CONFIG_SLIP is not set
1766 CONFIG_SLHC=m
1767 -# CONFIG_SHAPER is not set
1768 # CONFIG_NETCONSOLE is not set
1769 # CONFIG_NETPOLL is not set
1770 # CONFIG_NET_POLL_CONTROLLER is not set
1771 @@ -528,6 +562,7 @@
1772 #
1773 CONFIG_SERIAL_ATMEL=y
1774 CONFIG_SERIAL_ATMEL_CONSOLE=y
1775 +CONFIG_SERIAL_ATMEL_PDC=y
1776 # CONFIG_SERIAL_ATMEL_TTYAT is not set
1777 CONFIG_SERIAL_CORE=y
1778 CONFIG_SERIAL_CORE_CONSOLE=y
1779 @@ -535,8 +570,6 @@
1780 # CONFIG_LEGACY_PTYS is not set
1781 # CONFIG_IPMI_HANDLER is not set
1782 # CONFIG_HW_RANDOM is not set
1783 -# CONFIG_RTC is not set
1784 -# CONFIG_GEN_RTC is not set
1785 # CONFIG_R3964 is not set
1786 # CONFIG_RAW_DRIVER is not set
1787 # CONFIG_TCG_TPM is not set
1788 @@ -554,6 +587,7 @@
1789 #
1790 # I2C Hardware Bus support
1791 #
1792 +CONFIG_I2C_ATMELTWI=m
1793 CONFIG_I2C_GPIO=m
1794 # CONFIG_I2C_OCORES is not set
1795 # CONFIG_I2C_PARPORT_LIGHT is not set
1796 @@ -564,13 +598,12 @@
1797 #
1798 # Miscellaneous I2C Chip support
1799 #
1800 -# CONFIG_SENSORS_DS1337 is not set
1801 -# CONFIG_SENSORS_DS1374 is not set
1802 # CONFIG_DS1682 is not set
1803 # CONFIG_SENSORS_EEPROM is not set
1804 # CONFIG_SENSORS_PCF8574 is not set
1805 -# CONFIG_SENSORS_PCA9539 is not set
1806 +# CONFIG_PCF8575 is not set
1807 # CONFIG_SENSORS_PCF8591 is not set
1808 +# CONFIG_TPS65010 is not set
1809 # CONFIG_SENSORS_MAX6875 is not set
1810 # CONFIG_SENSORS_TSL2550 is not set
1811 # CONFIG_I2C_DEBUG_CORE is not set
1812 @@ -597,9 +630,27 @@
1813 # CONFIG_SPI_AT25 is not set
1814 CONFIG_SPI_SPIDEV=m
1815 # CONFIG_SPI_TLE62X0 is not set
1816 +CONFIG_HAVE_GPIO_LIB=y
1817 +
1818 +#
1819 +# GPIO Support
1820 +#
1821 +# CONFIG_DEBUG_GPIO is not set
1822 +
1823 +#
1824 +# I2C GPIO expanders:
1825 +#
1826 +# CONFIG_GPIO_PCA953X is not set
1827 +# CONFIG_GPIO_PCF857X is not set
1828 +
1829 +#
1830 +# SPI GPIO expanders:
1831 +#
1832 +# CONFIG_GPIO_MCP23S08 is not set
1833 # CONFIG_W1 is not set
1834 # CONFIG_POWER_SUPPLY is not set
1835 # CONFIG_HWMON is not set
1836 +# CONFIG_THERMAL is not set
1837 CONFIG_WATCHDOG=y
1838 # CONFIG_WATCHDOG_NOWAYOUT is not set
1839
1840 @@ -665,12 +716,18 @@
1841 #
1842 # Generic devices
1843 #
1844 +CONFIG_SND_AC97_CODEC=m
1845 # CONFIG_SND_DUMMY is not set
1846 # CONFIG_SND_MTPAV is not set
1847 # CONFIG_SND_SERIAL_U16550 is not set
1848 # CONFIG_SND_MPU401 is not set
1849
1850 #
1851 +# AVR32 devices
1852 +#
1853 +CONFIG_SND_ATMEL_AC97=m
1854 +
1855 +#
1856 # SPI devices
1857 #
1858 CONFIG_SND_AT73C213=m
1859 @@ -686,9 +743,14 @@
1860 #
1861
1862 #
1863 +# ALSA SoC audio for Freescale SOCs
1864 +#
1865 +
1866 +#
1867 # Open Sound System
1868 #
1869 # CONFIG_SOUND_PRIME is not set
1870 +CONFIG_AC97_BUS=m
1871 # CONFIG_HID_SUPPORT is not set
1872 CONFIG_USB_SUPPORT=y
1873 # CONFIG_USB_ARCH_HAS_HCD is not set
1874 @@ -698,10 +760,6 @@
1875 #
1876 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1877 #
1878 -
1879 -#
1880 -# USB Gadget Support
1881 -#
1882 CONFIG_USB_GADGET=y
1883 # CONFIG_USB_GADGET_DEBUG is not set
1884 # CONFIG_USB_GADGET_DEBUG_FILES is not set
1885 @@ -729,27 +787,31 @@
1886 # CONFIG_USB_FILE_STORAGE_TEST is not set
1887 CONFIG_USB_G_SERIAL=m
1888 # CONFIG_USB_MIDI_GADGET is not set
1889 -CONFIG_MMC=m
1890 +# CONFIG_USB_G_PRINTER is not set
1891 +CONFIG_MMC=y
1892 # CONFIG_MMC_DEBUG is not set
1893 # CONFIG_MMC_UNSAFE_RESUME is not set
1894
1895 #
1896 # MMC/SD Card Drivers
1897 #
1898 -CONFIG_MMC_BLOCK=m
1899 +CONFIG_MMC_BLOCK=y
1900 # CONFIG_MMC_BLOCK_BOUNCE is not set
1901 # CONFIG_SDIO_UART is not set
1902
1903 #
1904 # MMC/SD Host Controller Drivers
1905 #
1906 +CONFIG_MMC_ATMELMCI=y
1907 CONFIG_MMC_SPI=m
1908 +# CONFIG_MEMSTICK is not set
1909 CONFIG_NEW_LEDS=y
1910 CONFIG_LEDS_CLASS=y
1911
1912 #
1913 # LED drivers
1914 #
1915 +CONFIG_LEDS_ATMEL_PWM=m
1916 CONFIG_LEDS_GPIO=y
1917
1918 #
1919 @@ -786,19 +848,22 @@
1920 # CONFIG_RTC_DRV_PCF8563 is not set
1921 # CONFIG_RTC_DRV_PCF8583 is not set
1922 # CONFIG_RTC_DRV_M41T80 is not set
1923 +# CONFIG_RTC_DRV_S35390A is not set
1924
1925 #
1926 # SPI RTC drivers
1927 #
1928 -# CONFIG_RTC_DRV_RS5C348 is not set
1929 # CONFIG_RTC_DRV_MAX6902 is not set
1930 +# CONFIG_RTC_DRV_R9701 is not set
1931 +# CONFIG_RTC_DRV_RS5C348 is not set
1932
1933 #
1934 # Platform RTC drivers
1935 #
1936 +# CONFIG_RTC_DRV_DS1511 is not set
1937 # CONFIG_RTC_DRV_DS1553 is not set
1938 -# CONFIG_RTC_DRV_STK17TA8 is not set
1939 # CONFIG_RTC_DRV_DS1742 is not set
1940 +# CONFIG_RTC_DRV_STK17TA8 is not set
1941 # CONFIG_RTC_DRV_M48T86 is not set
1942 # CONFIG_RTC_DRV_M48T59 is not set
1943 # CONFIG_RTC_DRV_V3020 is not set
1944 @@ -816,13 +881,13 @@
1945 #
1946 # File systems
1947 #
1948 -CONFIG_EXT2_FS=m
1949 +CONFIG_EXT2_FS=y
1950 # CONFIG_EXT2_FS_XATTR is not set
1951 # CONFIG_EXT2_FS_XIP is not set
1952 -CONFIG_EXT3_FS=m
1953 +CONFIG_EXT3_FS=y
1954 # CONFIG_EXT3_FS_XATTR is not set
1955 # CONFIG_EXT4DEV_FS is not set
1956 -CONFIG_JBD=m
1957 +CONFIG_JBD=y
1958 # CONFIG_JBD_DEBUG is not set
1959 # CONFIG_REISERFS_FS is not set
1960 # CONFIG_JFS_FS is not set
1961 @@ -830,12 +895,10 @@
1962 # CONFIG_XFS_FS is not set
1963 # CONFIG_GFS2_FS is not set
1964 # CONFIG_OCFS2_FS is not set
1965 -# CONFIG_MINIX_FS is not set
1966 -# CONFIG_ROMFS_FS is not set
1967 +# CONFIG_DNOTIFY is not set
1968 CONFIG_INOTIFY=y
1969 CONFIG_INOTIFY_USER=y
1970 # CONFIG_QUOTA is not set
1971 -# CONFIG_DNOTIFY is not set
1972 # CONFIG_AUTOFS_FS is not set
1973 # CONFIG_AUTOFS4_FS is not set
1974 CONFIG_FUSE_FS=m
1975 @@ -866,7 +929,7 @@
1976 CONFIG_TMPFS=y
1977 # CONFIG_TMPFS_POSIX_ACL is not set
1978 # CONFIG_HUGETLB_PAGE is not set
1979 -CONFIG_CONFIGFS_FS=m
1980 +CONFIG_CONFIGFS_FS=y
1981
1982 #
1983 # Miscellaneous filesystems
1984 @@ -891,8 +954,10 @@
1985 # CONFIG_JFFS2_RUBIN is not set
1986 # CONFIG_CRAMFS is not set
1987 # CONFIG_VXFS_FS is not set
1988 +# CONFIG_MINIX_FS is not set
1989 # CONFIG_HPFS_FS is not set
1990 # CONFIG_QNX4FS_FS is not set
1991 +# CONFIG_ROMFS_FS is not set
1992 # CONFIG_SYSV_FS is not set
1993 # CONFIG_UFS_FS is not set
1994 # CONFIG_NETWORK_FILESYSTEMS is not set
1995 @@ -943,11 +1008,6 @@
1996 # CONFIG_NLS_KOI8_U is not set
1997 CONFIG_NLS_UTF8=m
1998 # CONFIG_DLM is not set
1999 -CONFIG_INSTRUMENTATION=y
2000 -CONFIG_PROFILING=y
2001 -CONFIG_OPROFILE=m
2002 -CONFIG_KPROBES=y
2003 -# CONFIG_MARKERS is not set
2004
2005 #
2006 # Kernel hacking
2007 @@ -965,6 +1025,7 @@
2008 CONFIG_SCHED_DEBUG=y
2009 # CONFIG_SCHEDSTATS is not set
2010 # CONFIG_TIMER_STATS is not set
2011 +# CONFIG_SLUB_STATS is not set
2012 # CONFIG_DEBUG_RT_MUTEXES is not set
2013 # CONFIG_RT_MUTEX_TESTER is not set
2014 # CONFIG_DEBUG_SPINLOCK is not set
2015 @@ -981,9 +1042,10 @@
2016 # CONFIG_DEBUG_LIST is not set
2017 # CONFIG_DEBUG_SG is not set
2018 CONFIG_FRAME_POINTER=y
2019 -CONFIG_FORCED_INLINING=y
2020 # CONFIG_BOOT_PRINTK_DELAY is not set
2021 # CONFIG_RCU_TORTURE_TEST is not set
2022 +# CONFIG_KPROBES_SANITY_TEST is not set
2023 +# CONFIG_BACKTRACE_SELF_TEST is not set
2024 # CONFIG_LKDTM is not set
2025 # CONFIG_FAULT_INJECTION is not set
2026 # CONFIG_SAMPLES is not set
2027 @@ -1009,6 +1071,7 @@
2028 CONFIG_AUDIT_GENERIC=y
2029 CONFIG_ZLIB_INFLATE=y
2030 CONFIG_ZLIB_DEFLATE=y
2031 +CONFIG_GENERIC_ALLOCATOR=y
2032 CONFIG_PLIST=y
2033 CONFIG_HAS_IOMEM=y
2034 CONFIG_HAS_IOPORT=y
2035 --- a/arch/avr32/configs/atstk1004_defconfig
2036 +++ b/arch/avr32/configs/atstk1004_defconfig
2037 @@ -1,7 +1,7 @@
2038 #
2039 # Automatically generated make config: don't edit
2040 -# Linux kernel version: 2.6.24-rc7
2041 -# Wed Jan 9 23:04:20 2008
2042 +# Linux kernel version: 2.6.25.4
2043 +# Wed Jun 11 15:37:49 2008
2044 #
2045 CONFIG_AVR32=y
2046 CONFIG_GENERIC_GPIO=y
2047 @@ -13,10 +13,10 @@
2048 CONFIG_GENERIC_IRQ_PROBE=y
2049 CONFIG_RWSEM_GENERIC_SPINLOCK=y
2050 CONFIG_GENERIC_TIME=y
2051 +CONFIG_GENERIC_CLOCKEVENTS=y
2052 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2053 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
2054 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
2055 -CONFIG_ARCH_SUPPORTS_OPROFILE=y
2056 CONFIG_GENERIC_HWEIGHT=y
2057 CONFIG_GENERIC_CALIBRATE_DELAY=y
2058 CONFIG_GENERIC_BUG=y
2059 @@ -34,15 +34,15 @@
2060 # CONFIG_POSIX_MQUEUE is not set
2061 # CONFIG_BSD_PROCESS_ACCT is not set
2062 # CONFIG_TASKSTATS is not set
2063 -# CONFIG_USER_NS is not set
2064 -# CONFIG_PID_NS is not set
2065 # CONFIG_AUDIT is not set
2066 # CONFIG_IKCONFIG is not set
2067 CONFIG_LOG_BUF_SHIFT=14
2068 # CONFIG_CGROUPS is not set
2069 -# CONFIG_FAIR_GROUP_SCHED is not set
2070 +# CONFIG_GROUP_SCHED is not set
2071 CONFIG_SYSFS_DEPRECATED=y
2072 +CONFIG_SYSFS_DEPRECATED_V2=y
2073 # CONFIG_RELAY is not set
2074 +# CONFIG_NAMESPACES is not set
2075 # CONFIG_BLK_DEV_INITRD is not set
2076 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2077 CONFIG_SYSCTL=y
2078 @@ -54,24 +54,37 @@
2079 CONFIG_PRINTK=y
2080 CONFIG_BUG=y
2081 CONFIG_ELF_CORE=y
2082 +# CONFIG_COMPAT_BRK is not set
2083 # CONFIG_BASE_FULL is not set
2084 # CONFIG_FUTEX is not set
2085 # CONFIG_EPOLL is not set
2086 # CONFIG_SIGNALFD is not set
2087 +# CONFIG_TIMERFD is not set
2088 # CONFIG_EVENTFD is not set
2089 CONFIG_SHMEM=y
2090 CONFIG_VM_EVENT_COUNTERS=y
2091 # CONFIG_SLAB is not set
2092 # CONFIG_SLUB is not set
2093 CONFIG_SLOB=y
2094 +# CONFIG_PROFILING is not set
2095 +# CONFIG_MARKERS is not set
2096 +CONFIG_HAVE_OPROFILE=y
2097 +CONFIG_HAVE_KPROBES=y
2098 +# CONFIG_HAVE_KRETPROBES is not set
2099 +# CONFIG_PROC_PAGE_MONITOR is not set
2100 # CONFIG_TINY_SHMEM is not set
2101 CONFIG_BASE_SMALL=1
2102 # CONFIG_MODULES is not set
2103 # CONFIG_BLOCK is not set
2104 +CONFIG_CLASSIC_RCU=y
2105
2106 #
2107 # System Type and features
2108 #
2109 +# CONFIG_TICK_ONESHOT is not set
2110 +# CONFIG_NO_HZ is not set
2111 +# CONFIG_HIGH_RES_TIMERS is not set
2112 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2113 CONFIG_SUBARCH_AVR32B=y
2114 CONFIG_MMU=y
2115 CONFIG_PERFORMANCE_COUNTERS=y
2116 @@ -83,10 +96,14 @@
2117 # CONFIG_BOARD_ATSTK1002 is not set
2118 # CONFIG_BOARD_ATSTK1003 is not set
2119 CONFIG_BOARD_ATSTK1004=y
2120 +# CONFIG_BOARD_ATSTK1006 is not set
2121 # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
2122 # CONFIG_BOARD_ATSTK100X_SPI1 is not set
2123 # CONFIG_BOARD_ATSTK1000_J2_LED is not set
2124 CONFIG_BOARD_ATSTK1000_EXTDAC=y
2125 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
2126 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
2127 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
2128 CONFIG_LOADER_U_BOOT=y
2129
2130 #
2131 @@ -95,6 +112,7 @@
2132 # CONFIG_AP700X_32_BIT_SMC is not set
2133 CONFIG_AP700X_16_BIT_SMC=y
2134 # CONFIG_AP700X_8_BIT_SMC is not set
2135 +# CONFIG_GPIO_DEV is not set
2136 CONFIG_LOAD_ADDRESS=0x10000000
2137 CONFIG_ENTRY_ADDRESS=0x90000000
2138 CONFIG_PHYS_OFFSET=0x10000000
2139 @@ -120,34 +138,26 @@
2140 CONFIG_ZONE_DMA_FLAG=0
2141 CONFIG_VIRT_TO_BUS=y
2142 # CONFIG_OWNERSHIP_TRACE is not set
2143 +# CONFIG_NMI_DEBUGGING is not set
2144 +CONFIG_DW_DMAC=y
2145 # CONFIG_HZ_100 is not set
2146 CONFIG_HZ_250=y
2147 # CONFIG_HZ_300 is not set
2148 # CONFIG_HZ_1000 is not set
2149 CONFIG_HZ=250
2150 +# CONFIG_SCHED_HRTICK is not set
2151 CONFIG_CMDLINE=""
2152
2153 #
2154 # Power management options
2155 #
2156 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2157 +# CONFIG_PM is not set
2158
2159 #
2160 # CPU Frequency scaling
2161 #
2162 -CONFIG_CPU_FREQ=y
2163 -CONFIG_CPU_FREQ_TABLE=y
2164 -# CONFIG_CPU_FREQ_DEBUG is not set
2165 -# CONFIG_CPU_FREQ_STAT is not set
2166 -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
2167 -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
2168 -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
2169 -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
2170 -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2171 -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
2172 -CONFIG_CPU_FREQ_GOV_USERSPACE=y
2173 -CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2174 -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
2175 -CONFIG_CPU_FREQ_AT32AP=y
2176 +# CONFIG_CPU_FREQ is not set
2177
2178 #
2179 # Bus options
2180 @@ -222,6 +232,7 @@
2181 #
2182 # CONFIG_NET_PKTGEN is not set
2183 # CONFIG_HAMRADIO is not set
2184 +# CONFIG_CAN is not set
2185 # CONFIG_IRDA is not set
2186 # CONFIG_BT is not set
2187 # CONFIG_AF_RXRPC is not set
2188 @@ -321,6 +332,7 @@
2189 # CONFIG_MTD_UBI is not set
2190 # CONFIG_PARPORT is not set
2191 # CONFIG_MISC_DEVICES is not set
2192 +# CONFIG_HAVE_IDE is not set
2193
2194 #
2195 # SCSI device support
2196 @@ -358,6 +370,7 @@
2197 #
2198 CONFIG_SERIAL_ATMEL=y
2199 CONFIG_SERIAL_ATMEL_CONSOLE=y
2200 +# CONFIG_SERIAL_ATMEL_PDC is not set
2201 # CONFIG_SERIAL_ATMEL_TTYAT is not set
2202 CONFIG_SERIAL_CORE=y
2203 CONFIG_SERIAL_CORE_CONSOLE=y
2204 @@ -365,8 +378,6 @@
2205 # CONFIG_LEGACY_PTYS is not set
2206 # CONFIG_IPMI_HANDLER is not set
2207 # CONFIG_HW_RANDOM is not set
2208 -# CONFIG_RTC is not set
2209 -# CONFIG_GEN_RTC is not set
2210 # CONFIG_R3964 is not set
2211 # CONFIG_TCG_TPM is not set
2212 # CONFIG_I2C is not set
2213 @@ -389,9 +400,24 @@
2214 # CONFIG_SPI_AT25 is not set
2215 # CONFIG_SPI_SPIDEV is not set
2216 # CONFIG_SPI_TLE62X0 is not set
2217 +CONFIG_HAVE_GPIO_LIB=y
2218 +
2219 +#
2220 +# GPIO Support
2221 +#
2222 +
2223 +#
2224 +# I2C GPIO expanders:
2225 +#
2226 +
2227 +#
2228 +# SPI GPIO expanders:
2229 +#
2230 +# CONFIG_GPIO_MCP23S08 is not set
2231 # CONFIG_W1 is not set
2232 # CONFIG_POWER_SUPPLY is not set
2233 # CONFIG_HWMON is not set
2234 +# CONFIG_THERMAL is not set
2235 CONFIG_WATCHDOG=y
2236 # CONFIG_WATCHDOG_NOWAYOUT is not set
2237
2238 @@ -471,10 +497,6 @@
2239 #
2240 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
2241 #
2242 -
2243 -#
2244 -# USB Gadget Support
2245 -#
2246 CONFIG_USB_GADGET=y
2247 # CONFIG_USB_GADGET_DEBUG_FILES is not set
2248 CONFIG_USB_GADGET_SELECTED=y
2249 @@ -499,7 +521,9 @@
2250 # CONFIG_USB_FILE_STORAGE is not set
2251 # CONFIG_USB_G_SERIAL is not set
2252 # CONFIG_USB_MIDI_GADGET is not set
2253 +# CONFIG_USB_G_PRINTER is not set
2254 # CONFIG_MMC is not set
2255 +# CONFIG_MEMSTICK is not set
2256 # CONFIG_NEW_LEDS is not set
2257 CONFIG_RTC_LIB=y
2258 CONFIG_RTC_CLASS=y
2259 @@ -519,15 +543,17 @@
2260 #
2261 # SPI RTC drivers
2262 #
2263 -# CONFIG_RTC_DRV_RS5C348 is not set
2264 # CONFIG_RTC_DRV_MAX6902 is not set
2265 +# CONFIG_RTC_DRV_R9701 is not set
2266 +# CONFIG_RTC_DRV_RS5C348 is not set
2267
2268 #
2269 # Platform RTC drivers
2270 #
2271 +# CONFIG_RTC_DRV_DS1511 is not set
2272 # CONFIG_RTC_DRV_DS1553 is not set
2273 -# CONFIG_RTC_DRV_STK17TA8 is not set
2274 # CONFIG_RTC_DRV_DS1742 is not set
2275 +# CONFIG_RTC_DRV_STK17TA8 is not set
2276 # CONFIG_RTC_DRV_M48T86 is not set
2277 # CONFIG_RTC_DRV_M48T59 is not set
2278 # CONFIG_RTC_DRV_V3020 is not set
2279 @@ -545,9 +571,9 @@
2280 #
2281 # File systems
2282 #
2283 +# CONFIG_DNOTIFY is not set
2284 # CONFIG_INOTIFY is not set
2285 # CONFIG_QUOTA is not set
2286 -# CONFIG_DNOTIFY is not set
2287 # CONFIG_AUTOFS_FS is not set
2288 # CONFIG_AUTOFS4_FS is not set
2289 # CONFIG_FUSE_FS is not set
2290 @@ -580,7 +606,6 @@
2291 # CONFIG_NETWORK_FILESYSTEMS is not set
2292 # CONFIG_NLS is not set
2293 # CONFIG_DLM is not set
2294 -# CONFIG_INSTRUMENTATION is not set
2295
2296 #
2297 # Kernel hacking
2298 @@ -616,6 +641,7 @@
2299 # CONFIG_LIBCRC32C is not set
2300 CONFIG_ZLIB_INFLATE=y
2301 CONFIG_ZLIB_DEFLATE=y
2302 +CONFIG_GENERIC_ALLOCATOR=y
2303 CONFIG_HAS_IOMEM=y
2304 CONFIG_HAS_IOPORT=y
2305 CONFIG_HAS_DMA=y
2306 --- /dev/null
2307 +++ b/arch/avr32/configs/atstk1006_defconfig
2308 @@ -0,0 +1,1235 @@
2309 +#
2310 +# Automatically generated make config: don't edit
2311 +# Linux kernel version: 2.6.25.4
2312 +# Wed Jun 11 15:40:45 2008
2313 +#
2314 +CONFIG_AVR32=y
2315 +CONFIG_GENERIC_GPIO=y
2316 +CONFIG_GENERIC_HARDIRQS=y
2317 +CONFIG_STACKTRACE_SUPPORT=y
2318 +CONFIG_LOCKDEP_SUPPORT=y
2319 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2320 +CONFIG_HARDIRQS_SW_RESEND=y
2321 +CONFIG_GENERIC_IRQ_PROBE=y
2322 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2323 +CONFIG_GENERIC_TIME=y
2324 +CONFIG_GENERIC_CLOCKEVENTS=y
2325 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2326 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2327 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2328 +CONFIG_GENERIC_HWEIGHT=y
2329 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2330 +CONFIG_GENERIC_BUG=y
2331 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2332 +
2333 +#
2334 +# General setup
2335 +#
2336 +CONFIG_EXPERIMENTAL=y
2337 +CONFIG_BROKEN_ON_SMP=y
2338 +CONFIG_INIT_ENV_ARG_LIMIT=32
2339 +CONFIG_LOCALVERSION=""
2340 +# CONFIG_LOCALVERSION_AUTO is not set
2341 +CONFIG_SWAP=y
2342 +CONFIG_SYSVIPC=y
2343 +CONFIG_SYSVIPC_SYSCTL=y
2344 +CONFIG_POSIX_MQUEUE=y
2345 +# CONFIG_BSD_PROCESS_ACCT is not set
2346 +# CONFIG_TASKSTATS is not set
2347 +# CONFIG_AUDIT is not set
2348 +# CONFIG_IKCONFIG is not set
2349 +CONFIG_LOG_BUF_SHIFT=14
2350 +# CONFIG_CGROUPS is not set
2351 +# CONFIG_GROUP_SCHED is not set
2352 +CONFIG_SYSFS_DEPRECATED=y
2353 +CONFIG_SYSFS_DEPRECATED_V2=y
2354 +CONFIG_RELAY=y
2355 +# CONFIG_NAMESPACES is not set
2356 +CONFIG_BLK_DEV_INITRD=y
2357 +CONFIG_INITRAMFS_SOURCE=""
2358 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
2359 +CONFIG_SYSCTL=y
2360 +CONFIG_EMBEDDED=y
2361 +# CONFIG_SYSCTL_SYSCALL is not set
2362 +CONFIG_KALLSYMS=y
2363 +# CONFIG_KALLSYMS_ALL is not set
2364 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2365 +CONFIG_HOTPLUG=y
2366 +CONFIG_PRINTK=y
2367 +CONFIG_BUG=y
2368 +CONFIG_ELF_CORE=y
2369 +# CONFIG_COMPAT_BRK is not set
2370 +# CONFIG_BASE_FULL is not set
2371 +CONFIG_FUTEX=y
2372 +CONFIG_ANON_INODES=y
2373 +CONFIG_EPOLL=y
2374 +CONFIG_SIGNALFD=y
2375 +CONFIG_TIMERFD=y
2376 +CONFIG_EVENTFD=y
2377 +CONFIG_SHMEM=y
2378 +CONFIG_VM_EVENT_COUNTERS=y
2379 +CONFIG_SLUB_DEBUG=y
2380 +# CONFIG_SLAB is not set
2381 +CONFIG_SLUB=y
2382 +# CONFIG_SLOB is not set
2383 +CONFIG_PROFILING=y
2384 +# CONFIG_MARKERS is not set
2385 +CONFIG_OPROFILE=m
2386 +CONFIG_HAVE_OPROFILE=y
2387 +CONFIG_KPROBES=y
2388 +CONFIG_HAVE_KPROBES=y
2389 +# CONFIG_HAVE_KRETPROBES is not set
2390 +CONFIG_PROC_PAGE_MONITOR=y
2391 +CONFIG_SLABINFO=y
2392 +CONFIG_RT_MUTEXES=y
2393 +# CONFIG_TINY_SHMEM is not set
2394 +CONFIG_BASE_SMALL=1
2395 +CONFIG_MODULES=y
2396 +CONFIG_MODULE_UNLOAD=y
2397 +# CONFIG_MODULE_FORCE_UNLOAD is not set
2398 +# CONFIG_MODVERSIONS is not set
2399 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2400 +# CONFIG_KMOD is not set
2401 +CONFIG_BLOCK=y
2402 +# CONFIG_LBD is not set
2403 +# CONFIG_BLK_DEV_IO_TRACE is not set
2404 +# CONFIG_LSF is not set
2405 +# CONFIG_BLK_DEV_BSG is not set
2406 +
2407 +#
2408 +# IO Schedulers
2409 +#
2410 +CONFIG_IOSCHED_NOOP=y
2411 +# CONFIG_IOSCHED_AS is not set
2412 +# CONFIG_IOSCHED_DEADLINE is not set
2413 +CONFIG_IOSCHED_CFQ=y
2414 +# CONFIG_DEFAULT_AS is not set
2415 +# CONFIG_DEFAULT_DEADLINE is not set
2416 +CONFIG_DEFAULT_CFQ=y
2417 +# CONFIG_DEFAULT_NOOP is not set
2418 +CONFIG_DEFAULT_IOSCHED="cfq"
2419 +CONFIG_CLASSIC_RCU=y
2420 +
2421 +#
2422 +# System Type and features
2423 +#
2424 +CONFIG_TICK_ONESHOT=y
2425 +CONFIG_NO_HZ=y
2426 +CONFIG_HIGH_RES_TIMERS=y
2427 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2428 +CONFIG_SUBARCH_AVR32B=y
2429 +CONFIG_MMU=y
2430 +CONFIG_PERFORMANCE_COUNTERS=y
2431 +CONFIG_PLATFORM_AT32AP=y
2432 +CONFIG_CPU_AT32AP700X=y
2433 +CONFIG_CPU_AT32AP7000=y
2434 +CONFIG_BOARD_ATSTK1000=y
2435 +# CONFIG_BOARD_ATNGW100 is not set
2436 +# CONFIG_BOARD_ATSTK1002 is not set
2437 +# CONFIG_BOARD_ATSTK1003 is not set
2438 +# CONFIG_BOARD_ATSTK1004 is not set
2439 +CONFIG_BOARD_ATSTK1006=y
2440 +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
2441 +# CONFIG_BOARD_ATSTK100X_SPI1 is not set
2442 +# CONFIG_BOARD_ATSTK1000_J2_LED is not set
2443 +# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
2444 +# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
2445 +CONFIG_BOARD_ATSTK1000_EXTDAC=y
2446 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
2447 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
2448 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
2449 +CONFIG_LOADER_U_BOOT=y
2450 +
2451 +#
2452 +# Atmel AVR32 AP options
2453 +#
2454 +# CONFIG_AP700X_32_BIT_SMC is not set
2455 +CONFIG_AP700X_16_BIT_SMC=y
2456 +# CONFIG_AP700X_8_BIT_SMC is not set
2457 +CONFIG_GPIO_DEV=y
2458 +CONFIG_LOAD_ADDRESS=0x10000000
2459 +CONFIG_ENTRY_ADDRESS=0x90000000
2460 +CONFIG_PHYS_OFFSET=0x10000000
2461 +CONFIG_PREEMPT_NONE=y
2462 +# CONFIG_PREEMPT_VOLUNTARY is not set
2463 +# CONFIG_PREEMPT is not set
2464 +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
2465 +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
2466 +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
2467 +CONFIG_ARCH_FLATMEM_ENABLE=y
2468 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
2469 +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
2470 +CONFIG_SELECT_MEMORY_MODEL=y
2471 +CONFIG_FLATMEM_MANUAL=y
2472 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2473 +# CONFIG_SPARSEMEM_MANUAL is not set
2474 +CONFIG_FLATMEM=y
2475 +CONFIG_FLAT_NODE_MEM_MAP=y
2476 +# CONFIG_SPARSEMEM_STATIC is not set
2477 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
2478 +CONFIG_SPLIT_PTLOCK_CPUS=4
2479 +# CONFIG_RESOURCES_64BIT is not set
2480 +CONFIG_ZONE_DMA_FLAG=0
2481 +CONFIG_VIRT_TO_BUS=y
2482 +# CONFIG_OWNERSHIP_TRACE is not set
2483 +CONFIG_NMI_DEBUGGING=y
2484 +CONFIG_DW_DMAC=y
2485 +# CONFIG_HZ_100 is not set
2486 +CONFIG_HZ_250=y
2487 +# CONFIG_HZ_300 is not set
2488 +# CONFIG_HZ_1000 is not set
2489 +CONFIG_HZ=250
2490 +# CONFIG_SCHED_HRTICK is not set
2491 +CONFIG_CMDLINE=""
2492 +
2493 +#
2494 +# Power management options
2495 +#
2496 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
2497 +CONFIG_PM=y
2498 +# CONFIG_PM_LEGACY is not set
2499 +# CONFIG_PM_DEBUG is not set
2500 +CONFIG_PM_SLEEP=y
2501 +CONFIG_SUSPEND=y
2502 +CONFIG_SUSPEND_FREEZER=y
2503 +
2504 +#
2505 +# CPU Frequency scaling
2506 +#
2507 +CONFIG_CPU_FREQ=y
2508 +CONFIG_CPU_FREQ_TABLE=y
2509 +# CONFIG_CPU_FREQ_DEBUG is not set
2510 +# CONFIG_CPU_FREQ_STAT is not set
2511 +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
2512 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
2513 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
2514 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
2515 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2516 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
2517 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
2518 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2519 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
2520 +CONFIG_CPU_FREQ_AT32AP=y
2521 +
2522 +#
2523 +# Bus options
2524 +#
2525 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2526 +# CONFIG_PCCARD is not set
2527 +
2528 +#
2529 +# Executable file formats
2530 +#
2531 +CONFIG_BINFMT_ELF=y
2532 +# CONFIG_BINFMT_MISC is not set
2533 +
2534 +#
2535 +# Networking
2536 +#
2537 +CONFIG_NET=y
2538 +
2539 +#
2540 +# Networking options
2541 +#
2542 +CONFIG_PACKET=y
2543 +CONFIG_PACKET_MMAP=y
2544 +CONFIG_UNIX=y
2545 +CONFIG_XFRM=y
2546 +CONFIG_XFRM_USER=m
2547 +# CONFIG_XFRM_SUB_POLICY is not set
2548 +# CONFIG_XFRM_MIGRATE is not set
2549 +# CONFIG_XFRM_STATISTICS is not set
2550 +CONFIG_NET_KEY=m
2551 +# CONFIG_NET_KEY_MIGRATE is not set
2552 +CONFIG_INET=y
2553 +# CONFIG_IP_MULTICAST is not set
2554 +# CONFIG_IP_ADVANCED_ROUTER is not set
2555 +CONFIG_IP_FIB_HASH=y
2556 +CONFIG_IP_PNP=y
2557 +CONFIG_IP_PNP_DHCP=y
2558 +# CONFIG_IP_PNP_BOOTP is not set
2559 +# CONFIG_IP_PNP_RARP is not set
2560 +CONFIG_NET_IPIP=m
2561 +CONFIG_NET_IPGRE=m
2562 +# CONFIG_ARPD is not set
2563 +# CONFIG_SYN_COOKIES is not set
2564 +CONFIG_INET_AH=m
2565 +CONFIG_INET_ESP=m
2566 +# CONFIG_INET_IPCOMP is not set
2567 +# CONFIG_INET_XFRM_TUNNEL is not set
2568 +CONFIG_INET_TUNNEL=m
2569 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
2570 +CONFIG_INET_XFRM_MODE_TUNNEL=m
2571 +CONFIG_INET_XFRM_MODE_BEET=m
2572 +# CONFIG_INET_LRO is not set
2573 +CONFIG_INET_DIAG=y
2574 +CONFIG_INET_TCP_DIAG=y
2575 +# CONFIG_TCP_CONG_ADVANCED is not set
2576 +CONFIG_TCP_CONG_CUBIC=y
2577 +CONFIG_DEFAULT_TCP_CONG="cubic"
2578 +# CONFIG_TCP_MD5SIG is not set
2579 +CONFIG_IPV6=m
2580 +# CONFIG_IPV6_PRIVACY is not set
2581 +# CONFIG_IPV6_ROUTER_PREF is not set
2582 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
2583 +CONFIG_INET6_AH=m
2584 +CONFIG_INET6_ESP=m
2585 +CONFIG_INET6_IPCOMP=m
2586 +# CONFIG_IPV6_MIP6 is not set
2587 +CONFIG_INET6_XFRM_TUNNEL=m
2588 +CONFIG_INET6_TUNNEL=m
2589 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
2590 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
2591 +CONFIG_INET6_XFRM_MODE_BEET=m
2592 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
2593 +CONFIG_IPV6_SIT=m
2594 +CONFIG_IPV6_TUNNEL=m
2595 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
2596 +# CONFIG_NETWORK_SECMARK is not set
2597 +# CONFIG_NETFILTER is not set
2598 +# CONFIG_IP_DCCP is not set
2599 +# CONFIG_IP_SCTP is not set
2600 +# CONFIG_TIPC is not set
2601 +# CONFIG_ATM is not set
2602 +CONFIG_BRIDGE=m
2603 +# CONFIG_VLAN_8021Q is not set
2604 +# CONFIG_DECNET is not set
2605 +CONFIG_LLC=m
2606 +# CONFIG_LLC2 is not set
2607 +# CONFIG_IPX is not set
2608 +# CONFIG_ATALK is not set
2609 +# CONFIG_X25 is not set
2610 +# CONFIG_LAPB is not set
2611 +# CONFIG_ECONET is not set
2612 +# CONFIG_WAN_ROUTER is not set
2613 +# CONFIG_NET_SCHED is not set
2614 +
2615 +#
2616 +# Network testing
2617 +#
2618 +# CONFIG_NET_PKTGEN is not set
2619 +# CONFIG_NET_TCPPROBE is not set
2620 +# CONFIG_HAMRADIO is not set
2621 +# CONFIG_CAN is not set
2622 +# CONFIG_IRDA is not set
2623 +# CONFIG_BT is not set
2624 +# CONFIG_AF_RXRPC is not set
2625 +
2626 +#
2627 +# Wireless
2628 +#
2629 +# CONFIG_CFG80211 is not set
2630 +# CONFIG_WIRELESS_EXT is not set
2631 +# CONFIG_MAC80211 is not set
2632 +# CONFIG_IEEE80211 is not set
2633 +# CONFIG_RFKILL is not set
2634 +# CONFIG_NET_9P is not set
2635 +
2636 +#
2637 +# Device Drivers
2638 +#
2639 +
2640 +#
2641 +# Generic Driver Options
2642 +#
2643 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2644 +CONFIG_STANDALONE=y
2645 +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
2646 +# CONFIG_FW_LOADER is not set
2647 +# CONFIG_DEBUG_DRIVER is not set
2648 +# CONFIG_DEBUG_DEVRES is not set
2649 +# CONFIG_SYS_HYPERVISOR is not set
2650 +# CONFIG_CONNECTOR is not set
2651 +CONFIG_MTD=y
2652 +# CONFIG_MTD_DEBUG is not set
2653 +# CONFIG_MTD_CONCAT is not set
2654 +CONFIG_MTD_PARTITIONS=y
2655 +# CONFIG_MTD_REDBOOT_PARTS is not set
2656 +CONFIG_MTD_CMDLINE_PARTS=y
2657 +
2658 +#
2659 +# User Modules And Translation Layers
2660 +#
2661 +CONFIG_MTD_CHAR=y
2662 +CONFIG_MTD_BLKDEVS=y
2663 +CONFIG_MTD_BLOCK=y
2664 +# CONFIG_FTL is not set
2665 +# CONFIG_NFTL is not set
2666 +# CONFIG_INFTL is not set
2667 +# CONFIG_RFD_FTL is not set
2668 +# CONFIG_SSFDC is not set
2669 +# CONFIG_MTD_OOPS is not set
2670 +
2671 +#
2672 +# RAM/ROM/Flash chip drivers
2673 +#
2674 +CONFIG_MTD_CFI=y
2675 +# CONFIG_MTD_JEDECPROBE is not set
2676 +CONFIG_MTD_GEN_PROBE=y
2677 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2678 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
2679 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
2680 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
2681 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2682 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2683 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2684 +CONFIG_MTD_CFI_I1=y
2685 +CONFIG_MTD_CFI_I2=y
2686 +# CONFIG_MTD_CFI_I4 is not set
2687 +# CONFIG_MTD_CFI_I8 is not set
2688 +# CONFIG_MTD_CFI_INTELEXT is not set
2689 +CONFIG_MTD_CFI_AMDSTD=y
2690 +# CONFIG_MTD_CFI_STAA is not set
2691 +CONFIG_MTD_CFI_UTIL=y
2692 +# CONFIG_MTD_RAM is not set
2693 +# CONFIG_MTD_ROM is not set
2694 +# CONFIG_MTD_ABSENT is not set
2695 +
2696 +#
2697 +# Mapping drivers for chip access
2698 +#
2699 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2700 +CONFIG_MTD_PHYSMAP=y
2701 +CONFIG_MTD_PHYSMAP_START=0x8000000
2702 +CONFIG_MTD_PHYSMAP_LEN=0x0
2703 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
2704 +# CONFIG_MTD_PLATRAM is not set
2705 +
2706 +#
2707 +# Self-contained MTD device drivers
2708 +#
2709 +CONFIG_MTD_DATAFLASH=m
2710 +CONFIG_MTD_M25P80=m
2711 +# CONFIG_MTD_SLRAM is not set
2712 +# CONFIG_MTD_PHRAM is not set
2713 +# CONFIG_MTD_MTDRAM is not set
2714 +# CONFIG_MTD_BLOCK2MTD is not set
2715 +
2716 +#
2717 +# Disk-On-Chip Device Drivers
2718 +#
2719 +# CONFIG_MTD_DOC2000 is not set
2720 +# CONFIG_MTD_DOC2001 is not set
2721 +# CONFIG_MTD_DOC2001PLUS is not set
2722 +CONFIG_MTD_NAND=y
2723 +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
2724 +# CONFIG_MTD_NAND_ECC_SMC is not set
2725 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
2726 +CONFIG_MTD_NAND_IDS=y
2727 +# CONFIG_MTD_NAND_DISKONCHIP is not set
2728 +CONFIG_MTD_NAND_ATMEL=y
2729 +CONFIG_MTD_NAND_ATMEL_ECC_HW=y
2730 +# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
2731 +# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
2732 +# CONFIG_MTD_NAND_NANDSIM is not set
2733 +# CONFIG_MTD_NAND_PLATFORM is not set
2734 +# CONFIG_MTD_ONENAND is not set
2735 +
2736 +#
2737 +# UBI - Unsorted block images
2738 +#
2739 +CONFIG_MTD_UBI=m
2740 +CONFIG_MTD_UBI_WL_THRESHOLD=4096
2741 +CONFIG_MTD_UBI_BEB_RESERVE=1
2742 +CONFIG_MTD_UBI_GLUEBI=y
2743 +
2744 +#
2745 +# UBI debugging options
2746 +#
2747 +# CONFIG_MTD_UBI_DEBUG is not set
2748 +# CONFIG_PARPORT is not set
2749 +CONFIG_BLK_DEV=y
2750 +# CONFIG_BLK_DEV_COW_COMMON is not set
2751 +CONFIG_BLK_DEV_LOOP=m
2752 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
2753 +CONFIG_BLK_DEV_NBD=m
2754 +CONFIG_BLK_DEV_RAM=m
2755 +CONFIG_BLK_DEV_RAM_COUNT=16
2756 +CONFIG_BLK_DEV_RAM_SIZE=4096
2757 +# CONFIG_BLK_DEV_XIP is not set
2758 +# CONFIG_CDROM_PKTCDVD is not set
2759 +# CONFIG_ATA_OVER_ETH is not set
2760 +CONFIG_MISC_DEVICES=y
2761 +CONFIG_ATMEL_PWM=m
2762 +CONFIG_ATMEL_TCLIB=y
2763 +CONFIG_ATMEL_TCB_CLKSRC=y
2764 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
2765 +# CONFIG_EEPROM_93CX6 is not set
2766 +CONFIG_ATMEL_SSC=m
2767 +# CONFIG_ENCLOSURE_SERVICES is not set
2768 +# CONFIG_HAVE_IDE is not set
2769 +
2770 +#
2771 +# SCSI device support
2772 +#
2773 +# CONFIG_RAID_ATTRS is not set
2774 +CONFIG_SCSI=m
2775 +CONFIG_SCSI_DMA=y
2776 +# CONFIG_SCSI_TGT is not set
2777 +# CONFIG_SCSI_NETLINK is not set
2778 +# CONFIG_SCSI_PROC_FS is not set
2779 +
2780 +#
2781 +# SCSI support type (disk, tape, CD-ROM)
2782 +#
2783 +CONFIG_BLK_DEV_SD=m
2784 +# CONFIG_CHR_DEV_ST is not set
2785 +# CONFIG_CHR_DEV_OSST is not set
2786 +CONFIG_BLK_DEV_SR=m
2787 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2788 +# CONFIG_CHR_DEV_SG is not set
2789 +# CONFIG_CHR_DEV_SCH is not set
2790 +
2791 +#
2792 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2793 +#
2794 +# CONFIG_SCSI_MULTI_LUN is not set
2795 +# CONFIG_SCSI_CONSTANTS is not set
2796 +# CONFIG_SCSI_LOGGING is not set
2797 +# CONFIG_SCSI_SCAN_ASYNC is not set
2798 +CONFIG_SCSI_WAIT_SCAN=m
2799 +
2800 +#
2801 +# SCSI Transports
2802 +#
2803 +# CONFIG_SCSI_SPI_ATTRS is not set
2804 +# CONFIG_SCSI_FC_ATTRS is not set
2805 +# CONFIG_SCSI_ISCSI_ATTRS is not set
2806 +# CONFIG_SCSI_SAS_LIBSAS is not set
2807 +# CONFIG_SCSI_SRP_ATTRS is not set
2808 +# CONFIG_SCSI_LOWLEVEL is not set
2809 +CONFIG_ATA=m
2810 +# CONFIG_ATA_NONSTANDARD is not set
2811 +# CONFIG_SATA_MV is not set
2812 +CONFIG_PATA_AT32=m
2813 +# CONFIG_PATA_PLATFORM is not set
2814 +# CONFIG_MD is not set
2815 +CONFIG_NETDEVICES=y
2816 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
2817 +# CONFIG_DUMMY is not set
2818 +# CONFIG_BONDING is not set
2819 +# CONFIG_MACVLAN is not set
2820 +# CONFIG_EQUALIZER is not set
2821 +CONFIG_TUN=m
2822 +# CONFIG_VETH is not set
2823 +CONFIG_PHYLIB=y
2824 +
2825 +#
2826 +# MII PHY device drivers
2827 +#
2828 +# CONFIG_MARVELL_PHY is not set
2829 +# CONFIG_DAVICOM_PHY is not set
2830 +# CONFIG_QSEMI_PHY is not set
2831 +# CONFIG_LXT_PHY is not set
2832 +# CONFIG_CICADA_PHY is not set
2833 +# CONFIG_VITESSE_PHY is not set
2834 +# CONFIG_SMSC_PHY is not set
2835 +# CONFIG_BROADCOM_PHY is not set
2836 +# CONFIG_ICPLUS_PHY is not set
2837 +# CONFIG_REALTEK_PHY is not set
2838 +# CONFIG_FIXED_PHY is not set
2839 +# CONFIG_MDIO_BITBANG is not set
2840 +CONFIG_NET_ETHERNET=y
2841 +# CONFIG_MII is not set
2842 +CONFIG_MACB=y
2843 +# CONFIG_ENC28J60 is not set
2844 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
2845 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
2846 +# CONFIG_IBM_NEW_EMAC_TAH is not set
2847 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2848 +# CONFIG_B44 is not set
2849 +# CONFIG_NETDEV_1000 is not set
2850 +# CONFIG_NETDEV_10000 is not set
2851 +
2852 +#
2853 +# Wireless LAN
2854 +#
2855 +# CONFIG_WLAN_PRE80211 is not set
2856 +# CONFIG_WLAN_80211 is not set
2857 +# CONFIG_WAN is not set
2858 +CONFIG_PPP=m
2859 +# CONFIG_PPP_MULTILINK is not set
2860 +# CONFIG_PPP_FILTER is not set
2861 +CONFIG_PPP_ASYNC=m
2862 +# CONFIG_PPP_SYNC_TTY is not set
2863 +CONFIG_PPP_DEFLATE=m
2864 +CONFIG_PPP_BSDCOMP=m
2865 +# CONFIG_PPP_MPPE is not set
2866 +# CONFIG_PPPOE is not set
2867 +# CONFIG_PPPOL2TP is not set
2868 +# CONFIG_SLIP is not set
2869 +CONFIG_SLHC=m
2870 +# CONFIG_NETCONSOLE is not set
2871 +# CONFIG_NETPOLL is not set
2872 +# CONFIG_NET_POLL_CONTROLLER is not set
2873 +# CONFIG_ISDN is not set
2874 +# CONFIG_PHONE is not set
2875 +
2876 +#
2877 +# Input device support
2878 +#
2879 +CONFIG_INPUT=m
2880 +# CONFIG_INPUT_FF_MEMLESS is not set
2881 +CONFIG_INPUT_POLLDEV=m
2882 +
2883 +#
2884 +# Userland interfaces
2885 +#
2886 +CONFIG_INPUT_MOUSEDEV=m
2887 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
2888 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2889 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2890 +# CONFIG_INPUT_JOYDEV is not set
2891 +CONFIG_INPUT_EVDEV=m
2892 +# CONFIG_INPUT_EVBUG is not set
2893 +
2894 +#
2895 +# Input Device Drivers
2896 +#
2897 +CONFIG_INPUT_KEYBOARD=y
2898 +# CONFIG_KEYBOARD_ATKBD is not set
2899 +# CONFIG_KEYBOARD_SUNKBD is not set
2900 +# CONFIG_KEYBOARD_LKKBD is not set
2901 +# CONFIG_KEYBOARD_XTKBD is not set
2902 +# CONFIG_KEYBOARD_NEWTON is not set
2903 +# CONFIG_KEYBOARD_STOWAWAY is not set
2904 +CONFIG_KEYBOARD_GPIO=m
2905 +CONFIG_INPUT_MOUSE=y
2906 +# CONFIG_MOUSE_PS2 is not set
2907 +# CONFIG_MOUSE_SERIAL is not set
2908 +# CONFIG_MOUSE_VSXXXAA is not set
2909 +CONFIG_MOUSE_GPIO=m
2910 +# CONFIG_INPUT_JOYSTICK is not set
2911 +# CONFIG_INPUT_TABLET is not set
2912 +# CONFIG_INPUT_TOUCHSCREEN is not set
2913 +# CONFIG_INPUT_MISC is not set
2914 +
2915 +#
2916 +# Hardware I/O ports
2917 +#
2918 +# CONFIG_SERIO is not set
2919 +# CONFIG_GAMEPORT is not set
2920 +
2921 +#
2922 +# Character devices
2923 +#
2924 +# CONFIG_VT is not set
2925 +# CONFIG_SERIAL_NONSTANDARD is not set
2926 +
2927 +#
2928 +# Serial drivers
2929 +#
2930 +# CONFIG_SERIAL_8250 is not set
2931 +
2932 +#
2933 +# Non-8250 serial port support
2934 +#
2935 +CONFIG_SERIAL_ATMEL=y
2936 +CONFIG_SERIAL_ATMEL_CONSOLE=y
2937 +CONFIG_SERIAL_ATMEL_PDC=y
2938 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
2939 +CONFIG_SERIAL_CORE=y
2940 +CONFIG_SERIAL_CORE_CONSOLE=y
2941 +CONFIG_UNIX98_PTYS=y
2942 +# CONFIG_LEGACY_PTYS is not set
2943 +# CONFIG_IPMI_HANDLER is not set
2944 +# CONFIG_HW_RANDOM is not set
2945 +# CONFIG_R3964 is not set
2946 +# CONFIG_RAW_DRIVER is not set
2947 +# CONFIG_TCG_TPM is not set
2948 +CONFIG_I2C=m
2949 +CONFIG_I2C_BOARDINFO=y
2950 +CONFIG_I2C_CHARDEV=m
2951 +
2952 +#
2953 +# I2C Algorithms
2954 +#
2955 +CONFIG_I2C_ALGOBIT=m
2956 +# CONFIG_I2C_ALGOPCF is not set
2957 +# CONFIG_I2C_ALGOPCA is not set
2958 +
2959 +#
2960 +# I2C Hardware Bus support
2961 +#
2962 +CONFIG_I2C_ATMELTWI=m
2963 +CONFIG_I2C_GPIO=m
2964 +# CONFIG_I2C_OCORES is not set
2965 +# CONFIG_I2C_PARPORT_LIGHT is not set
2966 +# CONFIG_I2C_SIMTEC is not set
2967 +# CONFIG_I2C_TAOS_EVM is not set
2968 +# CONFIG_I2C_STUB is not set
2969 +
2970 +#
2971 +# Miscellaneous I2C Chip support
2972 +#
2973 +# CONFIG_DS1682 is not set
2974 +# CONFIG_SENSORS_EEPROM is not set
2975 +# CONFIG_SENSORS_PCF8574 is not set
2976 +# CONFIG_PCF8575 is not set
2977 +# CONFIG_SENSORS_PCF8591 is not set
2978 +# CONFIG_TPS65010 is not set
2979 +# CONFIG_SENSORS_MAX6875 is not set
2980 +# CONFIG_SENSORS_TSL2550 is not set
2981 +# CONFIG_I2C_DEBUG_CORE is not set
2982 +# CONFIG_I2C_DEBUG_ALGO is not set
2983 +# CONFIG_I2C_DEBUG_BUS is not set
2984 +# CONFIG_I2C_DEBUG_CHIP is not set
2985 +
2986 +#
2987 +# SPI support
2988 +#
2989 +CONFIG_SPI=y
2990 +# CONFIG_SPI_DEBUG is not set
2991 +CONFIG_SPI_MASTER=y
2992 +
2993 +#
2994 +# SPI Master Controller Drivers
2995 +#
2996 +CONFIG_SPI_ATMEL=y
2997 +# CONFIG_SPI_BITBANG is not set
2998 +
2999 +#
3000 +# SPI Protocol Masters
3001 +#
3002 +# CONFIG_SPI_AT25 is not set
3003 +CONFIG_SPI_SPIDEV=m
3004 +# CONFIG_SPI_TLE62X0 is not set
3005 +CONFIG_HAVE_GPIO_LIB=y
3006 +
3007 +#
3008 +# GPIO Support
3009 +#
3010 +# CONFIG_DEBUG_GPIO is not set
3011 +
3012 +#
3013 +# I2C GPIO expanders:
3014 +#
3015 +# CONFIG_GPIO_PCA953X is not set
3016 +# CONFIG_GPIO_PCF857X is not set
3017 +
3018 +#
3019 +# SPI GPIO expanders:
3020 +#
3021 +# CONFIG_GPIO_MCP23S08 is not set
3022 +# CONFIG_W1 is not set
3023 +# CONFIG_POWER_SUPPLY is not set
3024 +# CONFIG_HWMON is not set
3025 +# CONFIG_THERMAL is not set
3026 +CONFIG_WATCHDOG=y
3027 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3028 +
3029 +#
3030 +# Watchdog Device Drivers
3031 +#
3032 +# CONFIG_SOFT_WATCHDOG is not set
3033 +CONFIG_AT32AP700X_WDT=y
3034 +
3035 +#
3036 +# Sonics Silicon Backplane
3037 +#
3038 +CONFIG_SSB_POSSIBLE=y
3039 +# CONFIG_SSB is not set
3040 +
3041 +#
3042 +# Multifunction device drivers
3043 +#
3044 +# CONFIG_MFD_SM501 is not set
3045 +
3046 +#
3047 +# Multimedia devices
3048 +#
3049 +# CONFIG_VIDEO_DEV is not set
3050 +# CONFIG_DVB_CORE is not set
3051 +# CONFIG_DAB is not set
3052 +
3053 +#
3054 +# Graphics support
3055 +#
3056 +# CONFIG_VGASTATE is not set
3057 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
3058 +CONFIG_FB=y
3059 +# CONFIG_FIRMWARE_EDID is not set
3060 +# CONFIG_FB_DDC is not set
3061 +CONFIG_FB_CFB_FILLRECT=y
3062 +CONFIG_FB_CFB_COPYAREA=y
3063 +CONFIG_FB_CFB_IMAGEBLIT=y
3064 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
3065 +# CONFIG_FB_SYS_FILLRECT is not set
3066 +# CONFIG_FB_SYS_COPYAREA is not set
3067 +# CONFIG_FB_SYS_IMAGEBLIT is not set
3068 +# CONFIG_FB_SYS_FOPS is not set
3069 +CONFIG_FB_DEFERRED_IO=y
3070 +# CONFIG_FB_SVGALIB is not set
3071 +# CONFIG_FB_MACMODES is not set
3072 +# CONFIG_FB_BACKLIGHT is not set
3073 +# CONFIG_FB_MODE_HELPERS is not set
3074 +# CONFIG_FB_TILEBLITTING is not set
3075 +
3076 +#
3077 +# Frame buffer hardware drivers
3078 +#
3079 +# CONFIG_FB_S1D13XXX is not set
3080 +CONFIG_FB_ATMEL=y
3081 +# CONFIG_FB_VIRTUAL is not set
3082 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
3083 +CONFIG_LCD_CLASS_DEVICE=y
3084 +CONFIG_LCD_LTV350QV=y
3085 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
3086 +
3087 +#
3088 +# Display device support
3089 +#
3090 +# CONFIG_DISPLAY_SUPPORT is not set
3091 +# CONFIG_LOGO is not set
3092 +
3093 +#
3094 +# Sound
3095 +#
3096 +CONFIG_SOUND=m
3097 +
3098 +#
3099 +# Advanced Linux Sound Architecture
3100 +#
3101 +CONFIG_SND=m
3102 +CONFIG_SND_TIMER=m
3103 +CONFIG_SND_PCM=m
3104 +# CONFIG_SND_SEQUENCER is not set
3105 +CONFIG_SND_OSSEMUL=y
3106 +CONFIG_SND_MIXER_OSS=m
3107 +CONFIG_SND_PCM_OSS=m
3108 +CONFIG_SND_PCM_OSS_PLUGINS=y
3109 +# CONFIG_SND_DYNAMIC_MINORS is not set
3110 +# CONFIG_SND_SUPPORT_OLD_API is not set
3111 +# CONFIG_SND_VERBOSE_PROCFS is not set
3112 +# CONFIG_SND_VERBOSE_PRINTK is not set
3113 +# CONFIG_SND_DEBUG is not set
3114 +
3115 +#
3116 +# Generic devices
3117 +#
3118 +CONFIG_SND_AC97_CODEC=m
3119 +# CONFIG_SND_DUMMY is not set
3120 +# CONFIG_SND_MTPAV is not set
3121 +# CONFIG_SND_SERIAL_U16550 is not set
3122 +# CONFIG_SND_MPU401 is not set
3123 +
3124 +#
3125 +# AVR32 devices
3126 +#
3127 +CONFIG_SND_ATMEL_AC97=m
3128 +
3129 +#
3130 +# SPI devices
3131 +#
3132 +CONFIG_SND_AT73C213=m
3133 +CONFIG_SND_AT73C213_TARGET_BITRATE=48000
3134 +
3135 +#
3136 +# System on Chip audio support
3137 +#
3138 +# CONFIG_SND_SOC is not set
3139 +
3140 +#
3141 +# SoC Audio support for SuperH
3142 +#
3143 +
3144 +#
3145 +# ALSA SoC audio for Freescale SOCs
3146 +#
3147 +
3148 +#
3149 +# Open Sound System
3150 +#
3151 +# CONFIG_SOUND_PRIME is not set
3152 +CONFIG_AC97_BUS=m
3153 +# CONFIG_HID_SUPPORT is not set
3154 +CONFIG_USB_SUPPORT=y
3155 +# CONFIG_USB_ARCH_HAS_HCD is not set
3156 +# CONFIG_USB_ARCH_HAS_OHCI is not set
3157 +# CONFIG_USB_ARCH_HAS_EHCI is not set
3158 +
3159 +#
3160 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3161 +#
3162 +CONFIG_USB_GADGET=y
3163 +# CONFIG_USB_GADGET_DEBUG is not set
3164 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3165 +# CONFIG_USB_GADGET_DEBUG_FS is not set
3166 +CONFIG_USB_GADGET_SELECTED=y
3167 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3168 +CONFIG_USB_GADGET_ATMEL_USBA=y
3169 +CONFIG_USB_ATMEL_USBA=y
3170 +# CONFIG_USB_GADGET_FSL_USB2 is not set
3171 +# CONFIG_USB_GADGET_NET2280 is not set
3172 +# CONFIG_USB_GADGET_PXA2XX is not set
3173 +# CONFIG_USB_GADGET_M66592 is not set
3174 +# CONFIG_USB_GADGET_GOKU is not set
3175 +# CONFIG_USB_GADGET_LH7A40X is not set
3176 +# CONFIG_USB_GADGET_OMAP is not set
3177 +# CONFIG_USB_GADGET_S3C2410 is not set
3178 +# CONFIG_USB_GADGET_AT91 is not set
3179 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3180 +CONFIG_USB_GADGET_DUALSPEED=y
3181 +CONFIG_USB_ZERO=m
3182 +CONFIG_USB_ETH=m
3183 +CONFIG_USB_ETH_RNDIS=y
3184 +CONFIG_USB_GADGETFS=m
3185 +CONFIG_USB_FILE_STORAGE=m
3186 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3187 +CONFIG_USB_G_SERIAL=m
3188 +# CONFIG_USB_MIDI_GADGET is not set
3189 +# CONFIG_USB_G_PRINTER is not set
3190 +CONFIG_MMC=y
3191 +# CONFIG_MMC_DEBUG is not set
3192 +# CONFIG_MMC_UNSAFE_RESUME is not set
3193 +
3194 +#
3195 +# MMC/SD Card Drivers
3196 +#
3197 +CONFIG_MMC_BLOCK=y
3198 +CONFIG_MMC_BLOCK_BOUNCE=y
3199 +# CONFIG_SDIO_UART is not set
3200 +
3201 +#
3202 +# MMC/SD Host Controller Drivers
3203 +#
3204 +CONFIG_MMC_ATMELMCI=y
3205 +CONFIG_MMC_SPI=m
3206 +# CONFIG_MEMSTICK is not set
3207 +CONFIG_NEW_LEDS=y
3208 +CONFIG_LEDS_CLASS=m
3209 +
3210 +#
3211 +# LED drivers
3212 +#
3213 +CONFIG_LEDS_ATMEL_PWM=m
3214 +CONFIG_LEDS_GPIO=m
3215 +
3216 +#
3217 +# LED Triggers
3218 +#
3219 +CONFIG_LEDS_TRIGGERS=y
3220 +CONFIG_LEDS_TRIGGER_TIMER=m
3221 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
3222 +CONFIG_RTC_LIB=y
3223 +CONFIG_RTC_CLASS=y
3224 +CONFIG_RTC_HCTOSYS=y
3225 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3226 +# CONFIG_RTC_DEBUG is not set
3227 +
3228 +#
3229 +# RTC interfaces
3230 +#
3231 +CONFIG_RTC_INTF_SYSFS=y
3232 +CONFIG_RTC_INTF_PROC=y
3233 +CONFIG_RTC_INTF_DEV=y
3234 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3235 +# CONFIG_RTC_DRV_TEST is not set
3236 +
3237 +#
3238 +# I2C RTC drivers
3239 +#
3240 +# CONFIG_RTC_DRV_DS1307 is not set
3241 +# CONFIG_RTC_DRV_DS1374 is not set
3242 +# CONFIG_RTC_DRV_DS1672 is not set
3243 +# CONFIG_RTC_DRV_MAX6900 is not set
3244 +# CONFIG_RTC_DRV_RS5C372 is not set
3245 +# CONFIG_RTC_DRV_ISL1208 is not set
3246 +# CONFIG_RTC_DRV_X1205 is not set
3247 +# CONFIG_RTC_DRV_PCF8563 is not set
3248 +# CONFIG_RTC_DRV_PCF8583 is not set
3249 +# CONFIG_RTC_DRV_M41T80 is not set
3250 +# CONFIG_RTC_DRV_S35390A is not set
3251 +
3252 +#
3253 +# SPI RTC drivers
3254 +#
3255 +# CONFIG_RTC_DRV_MAX6902 is not set
3256 +# CONFIG_RTC_DRV_R9701 is not set
3257 +# CONFIG_RTC_DRV_RS5C348 is not set
3258 +
3259 +#
3260 +# Platform RTC drivers
3261 +#
3262 +# CONFIG_RTC_DRV_DS1511 is not set
3263 +# CONFIG_RTC_DRV_DS1553 is not set
3264 +# CONFIG_RTC_DRV_DS1742 is not set
3265 +# CONFIG_RTC_DRV_STK17TA8 is not set
3266 +# CONFIG_RTC_DRV_M48T86 is not set
3267 +# CONFIG_RTC_DRV_M48T59 is not set
3268 +# CONFIG_RTC_DRV_V3020 is not set
3269 +
3270 +#
3271 +# on-CPU RTC drivers
3272 +#
3273 +CONFIG_RTC_DRV_AT32AP700X=y
3274 +
3275 +#
3276 +# Userspace I/O
3277 +#
3278 +# CONFIG_UIO is not set
3279 +
3280 +#
3281 +# File systems
3282 +#
3283 +CONFIG_EXT2_FS=y
3284 +# CONFIG_EXT2_FS_XATTR is not set
3285 +# CONFIG_EXT2_FS_XIP is not set
3286 +CONFIG_EXT3_FS=y
3287 +# CONFIG_EXT3_FS_XATTR is not set
3288 +# CONFIG_EXT4DEV_FS is not set
3289 +CONFIG_JBD=y
3290 +# CONFIG_JBD_DEBUG is not set
3291 +# CONFIG_REISERFS_FS is not set
3292 +# CONFIG_JFS_FS is not set
3293 +# CONFIG_FS_POSIX_ACL is not set
3294 +# CONFIG_XFS_FS is not set
3295 +# CONFIG_GFS2_FS is not set
3296 +# CONFIG_OCFS2_FS is not set
3297 +# CONFIG_DNOTIFY is not set
3298 +CONFIG_INOTIFY=y
3299 +CONFIG_INOTIFY_USER=y
3300 +# CONFIG_QUOTA is not set
3301 +# CONFIG_AUTOFS_FS is not set
3302 +# CONFIG_AUTOFS4_FS is not set
3303 +CONFIG_FUSE_FS=m
3304 +
3305 +#
3306 +# CD-ROM/DVD Filesystems
3307 +#
3308 +# CONFIG_ISO9660_FS is not set
3309 +# CONFIG_UDF_FS is not set
3310 +
3311 +#
3312 +# DOS/FAT/NT Filesystems
3313 +#
3314 +CONFIG_FAT_FS=m
3315 +CONFIG_MSDOS_FS=m
3316 +CONFIG_VFAT_FS=m
3317 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3318 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3319 +# CONFIG_NTFS_FS is not set
3320 +
3321 +#
3322 +# Pseudo filesystems
3323 +#
3324 +CONFIG_PROC_FS=y
3325 +CONFIG_PROC_KCORE=y
3326 +CONFIG_PROC_SYSCTL=y
3327 +CONFIG_SYSFS=y
3328 +CONFIG_TMPFS=y
3329 +# CONFIG_TMPFS_POSIX_ACL is not set
3330 +# CONFIG_HUGETLB_PAGE is not set
3331 +CONFIG_CONFIGFS_FS=y
3332 +
3333 +#
3334 +# Miscellaneous filesystems
3335 +#
3336 +# CONFIG_ADFS_FS is not set
3337 +# CONFIG_AFFS_FS is not set
3338 +# CONFIG_HFS_FS is not set
3339 +# CONFIG_HFSPLUS_FS is not set
3340 +# CONFIG_BEFS_FS is not set
3341 +# CONFIG_BFS_FS is not set
3342 +# CONFIG_EFS_FS is not set
3343 +CONFIG_JFFS2_FS=y
3344 +CONFIG_JFFS2_FS_DEBUG=0
3345 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set
3346 +# CONFIG_JFFS2_SUMMARY is not set
3347 +# CONFIG_JFFS2_FS_XATTR is not set
3348 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3349 +CONFIG_JFFS2_ZLIB=y
3350 +# CONFIG_JFFS2_LZO is not set
3351 +CONFIG_JFFS2_RTIME=y
3352 +# CONFIG_JFFS2_RUBIN is not set
3353 +# CONFIG_CRAMFS is not set
3354 +# CONFIG_VXFS_FS is not set
3355 +CONFIG_MINIX_FS=m
3356 +# CONFIG_HPFS_FS is not set
3357 +# CONFIG_QNX4FS_FS is not set
3358 +# CONFIG_ROMFS_FS is not set
3359 +# CONFIG_SYSV_FS is not set
3360 +# CONFIG_UFS_FS is not set
3361 +CONFIG_NETWORK_FILESYSTEMS=y
3362 +CONFIG_NFS_FS=y
3363 +CONFIG_NFS_V3=y
3364 +# CONFIG_NFS_V3_ACL is not set
3365 +# CONFIG_NFS_V4 is not set
3366 +# CONFIG_NFS_DIRECTIO is not set
3367 +# CONFIG_NFSD is not set
3368 +CONFIG_ROOT_NFS=y
3369 +CONFIG_LOCKD=y
3370 +CONFIG_LOCKD_V4=y
3371 +CONFIG_NFS_COMMON=y
3372 +CONFIG_SUNRPC=y
3373 +# CONFIG_SUNRPC_BIND34 is not set
3374 +# CONFIG_RPCSEC_GSS_KRB5 is not set
3375 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
3376 +# CONFIG_SMB_FS is not set
3377 +# CONFIG_CIFS is not set
3378 +# CONFIG_NCP_FS is not set
3379 +# CONFIG_CODA_FS is not set
3380 +# CONFIG_AFS_FS is not set
3381 +
3382 +#
3383 +# Partition Types
3384 +#
3385 +# CONFIG_PARTITION_ADVANCED is not set
3386 +CONFIG_MSDOS_PARTITION=y
3387 +CONFIG_NLS=m
3388 +CONFIG_NLS_DEFAULT="iso8859-1"
3389 +CONFIG_NLS_CODEPAGE_437=m
3390 +# CONFIG_NLS_CODEPAGE_737 is not set
3391 +# CONFIG_NLS_CODEPAGE_775 is not set
3392 +# CONFIG_NLS_CODEPAGE_850 is not set
3393 +# CONFIG_NLS_CODEPAGE_852 is not set
3394 +# CONFIG_NLS_CODEPAGE_855 is not set
3395 +# CONFIG_NLS_CODEPAGE_857 is not set
3396 +# CONFIG_NLS_CODEPAGE_860 is not set
3397 +# CONFIG_NLS_CODEPAGE_861 is not set
3398 +# CONFIG_NLS_CODEPAGE_862 is not set
3399 +# CONFIG_NLS_CODEPAGE_863 is not set
3400 +# CONFIG_NLS_CODEPAGE_864 is not set
3401 +# CONFIG_NLS_CODEPAGE_865 is not set
3402 +# CONFIG_NLS_CODEPAGE_866 is not set
3403 +# CONFIG_NLS_CODEPAGE_869 is not set
3404 +# CONFIG_NLS_CODEPAGE_936 is not set
3405 +# CONFIG_NLS_CODEPAGE_950 is not set
3406 +# CONFIG_NLS_CODEPAGE_932 is not set
3407 +# CONFIG_NLS_CODEPAGE_949 is not set
3408 +# CONFIG_NLS_CODEPAGE_874 is not set
3409 +# CONFIG_NLS_ISO8859_8 is not set
3410 +# CONFIG_NLS_CODEPAGE_1250 is not set
3411 +# CONFIG_NLS_CODEPAGE_1251 is not set
3412 +# CONFIG_NLS_ASCII is not set
3413 +CONFIG_NLS_ISO8859_1=m
3414 +# CONFIG_NLS_ISO8859_2 is not set
3415 +# CONFIG_NLS_ISO8859_3 is not set
3416 +# CONFIG_NLS_ISO8859_4 is not set
3417 +# CONFIG_NLS_ISO8859_5 is not set
3418 +# CONFIG_NLS_ISO8859_6 is not set
3419 +# CONFIG_NLS_ISO8859_7 is not set
3420 +# CONFIG_NLS_ISO8859_9 is not set
3421 +# CONFIG_NLS_ISO8859_13 is not set
3422 +# CONFIG_NLS_ISO8859_14 is not set
3423 +# CONFIG_NLS_ISO8859_15 is not set
3424 +# CONFIG_NLS_KOI8_R is not set
3425 +# CONFIG_NLS_KOI8_U is not set
3426 +CONFIG_NLS_UTF8=m
3427 +# CONFIG_DLM is not set
3428 +
3429 +#
3430 +# Kernel hacking
3431 +#
3432 +# CONFIG_PRINTK_TIME is not set
3433 +CONFIG_ENABLE_WARN_DEPRECATED=y
3434 +CONFIG_ENABLE_MUST_CHECK=y
3435 +CONFIG_MAGIC_SYSRQ=y
3436 +# CONFIG_UNUSED_SYMBOLS is not set
3437 +CONFIG_DEBUG_FS=y
3438 +# CONFIG_HEADERS_CHECK is not set
3439 +CONFIG_DEBUG_KERNEL=y
3440 +# CONFIG_DEBUG_SHIRQ is not set
3441 +CONFIG_DETECT_SOFTLOCKUP=y
3442 +CONFIG_SCHED_DEBUG=y
3443 +# CONFIG_SCHEDSTATS is not set
3444 +# CONFIG_TIMER_STATS is not set
3445 +# CONFIG_SLUB_DEBUG_ON is not set
3446 +# CONFIG_SLUB_STATS is not set
3447 +# CONFIG_DEBUG_RT_MUTEXES is not set
3448 +# CONFIG_RT_MUTEX_TESTER is not set
3449 +# CONFIG_DEBUG_SPINLOCK is not set
3450 +# CONFIG_DEBUG_MUTEXES is not set
3451 +# CONFIG_DEBUG_LOCK_ALLOC is not set
3452 +# CONFIG_PROVE_LOCKING is not set
3453 +# CONFIG_LOCK_STAT is not set
3454 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
3455 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
3456 +# CONFIG_DEBUG_KOBJECT is not set
3457 +CONFIG_DEBUG_BUGVERBOSE=y
3458 +# CONFIG_DEBUG_INFO is not set
3459 +# CONFIG_DEBUG_VM is not set
3460 +# CONFIG_DEBUG_LIST is not set
3461 +# CONFIG_DEBUG_SG is not set
3462 +CONFIG_FRAME_POINTER=y
3463 +# CONFIG_BOOT_PRINTK_DELAY is not set
3464 +# CONFIG_RCU_TORTURE_TEST is not set
3465 +# CONFIG_KPROBES_SANITY_TEST is not set
3466 +# CONFIG_BACKTRACE_SELF_TEST is not set
3467 +# CONFIG_LKDTM is not set
3468 +# CONFIG_FAULT_INJECTION is not set
3469 +# CONFIG_SAMPLES is not set
3470 +
3471 +#
3472 +# Security options
3473 +#
3474 +# CONFIG_KEYS is not set
3475 +# CONFIG_SECURITY is not set
3476 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
3477 +CONFIG_CRYPTO=y
3478 +CONFIG_CRYPTO_ALGAPI=m
3479 +CONFIG_CRYPTO_AEAD=m
3480 +CONFIG_CRYPTO_BLKCIPHER=m
3481 +# CONFIG_CRYPTO_SEQIV is not set
3482 +CONFIG_CRYPTO_HASH=m
3483 +CONFIG_CRYPTO_MANAGER=m
3484 +CONFIG_CRYPTO_HMAC=m
3485 +# CONFIG_CRYPTO_XCBC is not set
3486 +# CONFIG_CRYPTO_NULL is not set
3487 +# CONFIG_CRYPTO_MD4 is not set
3488 +CONFIG_CRYPTO_MD5=m
3489 +CONFIG_CRYPTO_SHA1=m
3490 +# CONFIG_CRYPTO_SHA256 is not set
3491 +# CONFIG_CRYPTO_SHA512 is not set
3492 +# CONFIG_CRYPTO_WP512 is not set
3493 +# CONFIG_CRYPTO_TGR192 is not set
3494 +# CONFIG_CRYPTO_GF128MUL is not set
3495 +# CONFIG_CRYPTO_ECB is not set
3496 +CONFIG_CRYPTO_CBC=m
3497 +# CONFIG_CRYPTO_PCBC is not set
3498 +# CONFIG_CRYPTO_LRW is not set
3499 +# CONFIG_CRYPTO_XTS is not set
3500 +# CONFIG_CRYPTO_CTR is not set
3501 +# CONFIG_CRYPTO_GCM is not set
3502 +# CONFIG_CRYPTO_CCM is not set
3503 +# CONFIG_CRYPTO_CRYPTD is not set
3504 +CONFIG_CRYPTO_DES=m
3505 +# CONFIG_CRYPTO_FCRYPT is not set
3506 +# CONFIG_CRYPTO_BLOWFISH is not set
3507 +# CONFIG_CRYPTO_TWOFISH is not set
3508 +# CONFIG_CRYPTO_SERPENT is not set
3509 +# CONFIG_CRYPTO_AES is not set
3510 +# CONFIG_CRYPTO_CAST5 is not set
3511 +# CONFIG_CRYPTO_CAST6 is not set
3512 +# CONFIG_CRYPTO_TEA is not set
3513 +# CONFIG_CRYPTO_ARC4 is not set
3514 +# CONFIG_CRYPTO_KHAZAD is not set
3515 +# CONFIG_CRYPTO_ANUBIS is not set
3516 +# CONFIG_CRYPTO_SEED is not set
3517 +# CONFIG_CRYPTO_SALSA20 is not set
3518 +CONFIG_CRYPTO_DEFLATE=m
3519 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
3520 +# CONFIG_CRYPTO_CRC32C is not set
3521 +# CONFIG_CRYPTO_CAMELLIA is not set
3522 +# CONFIG_CRYPTO_TEST is not set
3523 +CONFIG_CRYPTO_AUTHENC=m
3524 +# CONFIG_CRYPTO_LZO is not set
3525 +# CONFIG_CRYPTO_HW is not set
3526 +
3527 +#
3528 +# Library routines
3529 +#
3530 +CONFIG_BITREVERSE=y
3531 +CONFIG_CRC_CCITT=m
3532 +# CONFIG_CRC16 is not set
3533 +CONFIG_CRC_ITU_T=m
3534 +CONFIG_CRC32=y
3535 +CONFIG_CRC7=m
3536 +# CONFIG_LIBCRC32C is not set
3537 +CONFIG_ZLIB_INFLATE=y
3538 +CONFIG_ZLIB_DEFLATE=y
3539 +CONFIG_GENERIC_ALLOCATOR=y
3540 +CONFIG_PLIST=y
3541 +CONFIG_HAS_IOMEM=y
3542 +CONFIG_HAS_IOPORT=y
3543 +CONFIG_HAS_DMA=y
3544 --- /dev/null
3545 +++ b/arch/avr32/drivers/dw-dmac.c
3546 @@ -0,0 +1,761 @@
3547 +/*
3548 + * Driver for the Synopsys DesignWare DMA Controller
3549 + *
3550 + * Copyright (C) 2005-2006 Atmel Corporation
3551 + *
3552 + * This program is free software; you can redistribute it and/or modify
3553 + * it under the terms of the GNU General Public License version 2 as
3554 + * published by the Free Software Foundation.
3555 + */
3556 +#include <linux/clk.h>
3557 +#include <linux/device.h>
3558 +#include <linux/dma-mapping.h>
3559 +#include <linux/dmapool.h>
3560 +#include <linux/init.h>
3561 +#include <linux/interrupt.h>
3562 +#include <linux/module.h>
3563 +#include <linux/platform_device.h>
3564 +
3565 +#include <asm/dma-controller.h>
3566 +#include <asm/io.h>
3567 +
3568 +#include "dw-dmac.h"
3569 +
3570 +#define DMAC_NR_CHANNELS 3
3571 +#define DMAC_MAX_BLOCKSIZE 4095
3572 +
3573 +enum {
3574 + CH_STATE_FREE = 0,
3575 + CH_STATE_ALLOCATED,
3576 + CH_STATE_BUSY,
3577 +};
3578 +
3579 +struct dw_dma_lli {
3580 + dma_addr_t sar;
3581 + dma_addr_t dar;
3582 + dma_addr_t llp;
3583 + u32 ctllo;
3584 + u32 ctlhi;
3585 + u32 sstat;
3586 + u32 dstat;
3587 +};
3588 +
3589 +struct dw_dma_block {
3590 + struct dw_dma_lli *lli_vaddr;
3591 + dma_addr_t lli_dma_addr;
3592 +};
3593 +
3594 +struct dw_dma_channel {
3595 + unsigned int state;
3596 + int is_cyclic;
3597 + struct dma_request_sg *req_sg;
3598 + struct dma_request_cyclic *req_cyclic;
3599 + unsigned int nr_blocks;
3600 + int direction;
3601 + struct dw_dma_block *block;
3602 +};
3603 +
3604 +struct dw_dma_controller {
3605 + spinlock_t lock;
3606 + void * __iomem regs;
3607 + struct dma_pool *lli_pool;
3608 + struct clk *hclk;
3609 + struct dma_controller dma;
3610 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
3611 +};
3612 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
3613 +
3614 +#define dmac_writel_hi(dmac, reg, value) \
3615 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
3616 +#define dmac_readl_hi(dmac, reg) \
3617 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
3618 +#define dmac_writel_lo(dmac, reg, value) \
3619 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
3620 +#define dmac_readl_lo(dmac, reg) \
3621 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
3622 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
3623 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
3624 + + DW_DMAC_CHAN_##reg + 4))
3625 +#define dmac_chan_readl_hi(dmac, chan, reg) \
3626 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
3627 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
3628 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
3629 +#define dmac_chan_readl_lo(dmac, chan, reg) \
3630 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
3631 +#define set_channel_bit(dmac, reg, chan) \
3632 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
3633 +#define clear_channel_bit(dmac, reg, chan) \
3634 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
3635 +
3636 +static int dmac_alloc_channel(struct dma_controller *_dmac)
3637 +{
3638 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3639 + struct dw_dma_channel *chan;
3640 + unsigned long flags;
3641 + int i;
3642 +
3643 + spin_lock_irqsave(&dmac->lock, flags);
3644 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
3645 + if (dmac->channel[i].state == CH_STATE_FREE)
3646 + break;
3647 +
3648 + if (i < DMAC_NR_CHANNELS) {
3649 + chan = &dmac->channel[i];
3650 + chan->state = CH_STATE_ALLOCATED;
3651 + } else {
3652 + i = -EBUSY;
3653 + }
3654 +
3655 + spin_unlock_irqrestore(&dmac->lock, flags);
3656 +
3657 + return i;
3658 +}
3659 +
3660 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
3661 +{
3662 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3663 +
3664 + BUG_ON(channel >= DMAC_NR_CHANNELS
3665 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
3666 +
3667 + dmac->channel[channel].state = CH_STATE_FREE;
3668 +}
3669 +
3670 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
3671 + unsigned int nr_blocks)
3672 +{
3673 + struct dw_dma_block *block;
3674 + void *p;
3675 + unsigned int i;
3676 +
3677 + block = kmalloc(nr_blocks * sizeof(*block),
3678 + GFP_KERNEL);
3679 + if (unlikely(!block))
3680 + return NULL;
3681 +
3682 + for (i = 0; i < nr_blocks; i++) {
3683 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
3684 + &block[i].lli_dma_addr);
3685 + block[i].lli_vaddr = p;
3686 + if (unlikely(!p))
3687 + goto fail;
3688 + }
3689 +
3690 + return block;
3691 +
3692 +fail:
3693 + for (i = 0; i < nr_blocks; i++) {
3694 + if (!block[i].lli_vaddr)
3695 + break;
3696 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
3697 + block[i].lli_dma_addr);
3698 + }
3699 + kfree(block);
3700 + return NULL;
3701 +}
3702 +
3703 +static void cleanup_channel(struct dw_dma_controller *dmac,
3704 + struct dw_dma_channel *chan)
3705 +{
3706 + unsigned int i;
3707 +
3708 + if (chan->nr_blocks > 1) {
3709 + for (i = 0; i < chan->nr_blocks; i++)
3710 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
3711 + chan->block[i].lli_dma_addr);
3712 + kfree(chan->block);
3713 + }
3714 +
3715 + chan->state = CH_STATE_ALLOCATED;
3716 +}
3717 +
3718 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
3719 + struct dma_request_sg *req)
3720 +{
3721 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3722 + struct dw_dma_channel *chan;
3723 + unsigned long ctlhi, ctllo, cfghi, cfglo;
3724 + unsigned long block_size;
3725 + unsigned int nr_blocks;
3726 + int ret, i, direction;
3727 + unsigned long flags;
3728 +
3729 + spin_lock_irqsave(&dmac->lock, flags);
3730 +
3731 + ret = -EINVAL;
3732 + if (req->req.channel >= DMAC_NR_CHANNELS
3733 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
3734 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
3735 + spin_unlock_irqrestore(&dmac->lock, flags);
3736 + return -EINVAL;
3737 + }
3738 +
3739 + chan = &dmac->channel[req->req.channel];
3740 + chan->state = CH_STATE_BUSY;
3741 + chan->req_sg = req;
3742 + chan->is_cyclic = 0;
3743 +
3744 + /*
3745 + * We have marked the channel as busy, so no need to keep the
3746 + * lock as long as we only touch the channel-specific
3747 + * registers
3748 + */
3749 + spin_unlock_irqrestore(&dmac->lock, flags);
3750 +
3751 + /*
3752 + * There may be limitations in the driver and/or the DMA
3753 + * controller that prevents us from sending a whole
3754 + * scatterlist item in one go. Taking this into account,
3755 + * calculate the number of block transfers we need to set up.
3756 + *
3757 + * FIXME: Let the peripheral driver know about the maximum
3758 + * block size we support. We really don't want to use a
3759 + * different block size than what was suggested by the
3760 + * peripheral.
3761 + *
3762 + * Each block will get its own Linked List Item (LLI) below.
3763 + */
3764 + block_size = req->block_size;
3765 + nr_blocks = req->nr_blocks;
3766 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
3767 + block_size, nr_blocks, req->nr_sg);
3768 +
3769 + BUG_ON(nr_blocks == 0);
3770 + chan->nr_blocks = nr_blocks;
3771 +
3772 + ret = -EINVAL;
3773 + cfglo = cfghi = 0;
3774 + switch (req->direction) {
3775 + case DMA_DIR_MEM_TO_PERIPH:
3776 + direction = DMA_TO_DEVICE;
3777 + cfghi = req->periph_id << (43 - 32);
3778 + break;
3779 +
3780 + case DMA_DIR_PERIPH_TO_MEM:
3781 + direction = DMA_FROM_DEVICE;
3782 + cfghi = req->periph_id << (39 - 32);
3783 + break;
3784 + default:
3785 + goto out_unclaim_channel;
3786 + }
3787 +
3788 + chan->direction = direction;
3789 +
3790 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
3791 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
3792 +
3793 + ctlhi = block_size >> req->width;
3794 + ctllo = ((req->direction << 20)
3795 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
3796 + | (req->width << 4) | (req->width << 1)
3797 + | (1 << 0)); // interrupt enable
3798 +
3799 + if (nr_blocks == 1) {
3800 + /* Only one block: No need to use block chaining */
3801 + if (direction == DMA_TO_DEVICE) {
3802 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
3803 + req->sg->dma_address);
3804 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
3805 + req->data_reg);
3806 + ctllo |= 2 << 7; // no dst increment
3807 + } else {
3808 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
3809 + req->data_reg);
3810 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
3811 + req->sg->dma_address);
3812 + ctllo |= 2 << 9; // no src increment
3813 + }
3814 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
3815 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
3816 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
3817 + } else {
3818 + struct dw_dma_lli *lli, *lli_prev = NULL;
3819 + int j = 0, offset = 0;
3820 +
3821 + ret = -ENOMEM;
3822 + chan->block = allocate_blocks(dmac, nr_blocks);
3823 + if (!chan->block)
3824 + goto out_unclaim_channel;
3825 +
3826 + if (direction == DMA_TO_DEVICE)
3827 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
3828 + else
3829 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
3830 +
3831 + /*
3832 + * Map scatterlist items to blocks. One scatterlist
3833 + * item may need more than one block for the reasons
3834 + * mentioned above.
3835 + */
3836 + for (i = 0; i < nr_blocks; i++) {
3837 + lli = chan->block[i].lli_vaddr;
3838 + if (lli_prev) {
3839 + lli_prev->llp = chan->block[i].lli_dma_addr;
3840 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3841 + i - 1, chan->block[i - 1].lli_vaddr,
3842 + chan->block[i - 1].lli_dma_addr,
3843 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
3844 + lli_prev->ctllo, lli_prev->ctlhi);
3845 + }
3846 + lli->llp = 0;
3847 + lli->ctllo = ctllo;
3848 + lli->ctlhi = ctlhi;
3849 + if (direction == DMA_TO_DEVICE) {
3850 + lli->sar = req->sg[j].dma_address + offset;
3851 + lli->dar = req->data_reg;
3852 + } else {
3853 + lli->sar = req->data_reg;
3854 + lli->dar = req->sg[j].dma_address + offset;
3855 + }
3856 + lli_prev = lli;
3857 +
3858 + offset += block_size;
3859 + if (offset > req->sg[j].length) {
3860 + j++;
3861 + offset = 0;
3862 + }
3863 + }
3864 +
3865 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3866 + i - 1, chan->block[i - 1].lli_vaddr,
3867 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
3868 + lli_prev->dar, lli_prev->llp,
3869 + lli_prev->ctllo, lli_prev->ctlhi);
3870 +
3871 + /*
3872 + * SAR, DAR and CTL are initialized from the LLI. We
3873 + * only have to enable the LLI bits in CTL.
3874 + */
3875 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
3876 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
3877 + chan->block[0].lli_dma_addr);
3878 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
3879 + }
3880 +
3881 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
3882 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
3883 + if (req->req.block_complete)
3884 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
3885 + else
3886 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
3887 +
3888 + return 0;
3889 +
3890 +out_unclaim_channel:
3891 + chan->state = CH_STATE_ALLOCATED;
3892 + return ret;
3893 +}
3894 +
3895 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
3896 + struct dma_request_cyclic *req)
3897 +{
3898 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
3899 + struct dw_dma_channel *chan;
3900 + unsigned long ctlhi, ctllo, cfghi, cfglo;
3901 + unsigned long block_size;
3902 + int ret, i, direction;
3903 + unsigned long flags;
3904 +
3905 + spin_lock_irqsave(&dmac->lock, flags);
3906 +
3907 + block_size = (req->buffer_size/req->periods) >> req->width;
3908 +
3909 + ret = -EINVAL;
3910 + if (req->req.channel >= DMAC_NR_CHANNELS
3911 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
3912 + || (req->periods == 0)
3913 + || block_size > DMAC_MAX_BLOCKSIZE) {
3914 + spin_unlock_irqrestore(&dmac->lock, flags);
3915 + return -EINVAL;
3916 + }
3917 +
3918 + chan = &dmac->channel[req->req.channel];
3919 + chan->state = CH_STATE_BUSY;
3920 + chan->is_cyclic = 1;
3921 + chan->req_cyclic = req;
3922 +
3923 + /*
3924 + * We have marked the channel as busy, so no need to keep the
3925 + * lock as long as we only touch the channel-specific
3926 + * registers
3927 + */
3928 + spin_unlock_irqrestore(&dmac->lock, flags);
3929 +
3930 + /*
3931 + Setup
3932 + */
3933 + BUG_ON(req->buffer_size % req->periods);
3934 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
3935 +
3936 + chan->nr_blocks = req->periods;
3937 +
3938 + ret = -EINVAL;
3939 + cfglo = cfghi = 0;
3940 + switch (req->direction) {
3941 + case DMA_DIR_MEM_TO_PERIPH:
3942 + direction = DMA_TO_DEVICE;
3943 + cfghi = req->periph_id << (43 - 32);
3944 + break;
3945 +
3946 + case DMA_DIR_PERIPH_TO_MEM:
3947 + direction = DMA_FROM_DEVICE;
3948 + cfghi = req->periph_id << (39 - 32);
3949 + break;
3950 + default:
3951 + goto out_unclaim_channel;
3952 + }
3953 +
3954 + chan->direction = direction;
3955 +
3956 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
3957 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
3958 +
3959 + ctlhi = block_size;
3960 + ctllo = ((req->direction << 20)
3961 + | (req->width << 4) | (req->width << 1)
3962 + | (1 << 0)); // interrupt enable
3963 +
3964 + {
3965 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
3966 +
3967 + ret = -ENOMEM;
3968 + chan->block = allocate_blocks(dmac, req->periods);
3969 + if (!chan->block)
3970 + goto out_unclaim_channel;
3971 +
3972 + if (direction == DMA_TO_DEVICE)
3973 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
3974 + else
3975 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
3976 +
3977 + /*
3978 + * Set up a linked list items where each period gets
3979 + * an item. The linked list item for the last period
3980 + * points back to the star of the buffer making a
3981 + * cyclic buffer.
3982 + */
3983 + for (i = 0; i < req->periods; i++) {
3984 + lli = chan->block[i].lli_vaddr;
3985 + if (lli_prev) {
3986 + lli_prev->llp = chan->block[i].lli_dma_addr;
3987 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
3988 + i - 1, chan->block[i - 1].lli_vaddr,
3989 + chan->block[i - 1].lli_dma_addr,
3990 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
3991 + lli_prev->ctllo, lli_prev->ctlhi);*/
3992 + }
3993 + lli->llp = 0;
3994 + lli->ctllo = ctllo;
3995 + lli->ctlhi = ctlhi;
3996 + if (direction == DMA_TO_DEVICE) {
3997 + lli->sar = req->buffer_start + i*(block_size << req->width);
3998 + lli->dar = req->data_reg;
3999 + } else {
4000 + lli->sar = req->data_reg;
4001 + lli->dar = req->buffer_start + i*(block_size << req->width);
4002 + }
4003 + lli_prev = lli;
4004 + }
4005 + lli->llp = chan->block[0].lli_dma_addr;
4006 +
4007 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
4008 + i - 1, chan->block[i - 1].lli_vaddr,
4009 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
4010 + lli_prev->dar, lli_prev->llp,
4011 + lli_prev->ctllo, lli_prev->ctlhi); */
4012 +
4013 + /*
4014 + * SAR, DAR and CTL are initialized from the LLI. We
4015 + * only have to enable the LLI bits in CTL.
4016 + */
4017 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
4018 + chan->block[0].lli_dma_addr);
4019 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
4020 + }
4021 +
4022 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
4023 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
4024 + if (req->req.block_complete)
4025 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4026 + else
4027 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4028 +
4029 + return 0;
4030 +
4031 +out_unclaim_channel:
4032 + chan->state = CH_STATE_ALLOCATED;
4033 + return ret;
4034 +}
4035 +
4036 +static int dmac_start_request(struct dma_controller *_dmac,
4037 + unsigned int channel)
4038 +{
4039 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4040 +
4041 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4042 +
4043 + set_channel_bit(dmac, CH_EN, channel);
4044 +
4045 + return 0;
4046 +}
4047 +
4048 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
4049 + unsigned int channel)
4050 +{
4051 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4052 + struct dw_dma_channel *chan;
4053 + dma_addr_t current_pos;
4054 +
4055 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4056 +
4057 + chan = &dmac->channel[channel];
4058 +
4059 + switch (chan->direction) {
4060 + case DMA_TO_DEVICE:
4061 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
4062 + break;
4063 + case DMA_FROM_DEVICE:
4064 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
4065 + break;
4066 + default:
4067 + return 0;
4068 + }
4069 +
4070 +
4071 + if (!current_pos) {
4072 + if (chan->is_cyclic) {
4073 + current_pos = chan->req_cyclic->buffer_start;
4074 + } else {
4075 + current_pos = chan->req_sg->sg->dma_address;
4076 + }
4077 + }
4078 +
4079 + return current_pos;
4080 +}
4081 +
4082 +
4083 +static int dmac_stop_request(struct dma_controller *_dmac,
4084 + unsigned int channel)
4085 +{
4086 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4087 + struct dw_dma_channel *chan;
4088 +
4089 + BUG_ON(channel >= DMAC_NR_CHANNELS);
4090 +
4091 + chan = &dmac->channel[channel];
4092 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
4093 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
4094 + dmac_chan_readl_lo(dmac, channel, DAR),
4095 + dmac_chan_readl_lo(dmac, channel, LLP),
4096 + dmac_chan_readl_hi(dmac, channel, CTL),
4097 + dmac_chan_readl_lo(dmac, channel, CTL));
4098 +
4099 + if (chan->state == CH_STATE_BUSY) {
4100 + clear_channel_bit(dmac, CH_EN, channel);
4101 + cleanup_channel(dmac, &dmac->channel[channel]);
4102 + }
4103 +
4104 + return 0;
4105 +}
4106 +
4107 +
4108 +static void dmac_block_complete(struct dw_dma_controller *dmac)
4109 +{
4110 + struct dw_dma_channel *chan;
4111 + unsigned long status, chanid;
4112 +
4113 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
4114 +
4115 + while (status) {
4116 + struct dma_request *req;
4117 + chanid = __ffs(status);
4118 + chan = &dmac->channel[chanid];
4119 +
4120 + if (chan->is_cyclic) {
4121 + BUG_ON(!chan->req_cyclic
4122 + || !chan->req_cyclic->req.block_complete);
4123 + req = &chan->req_cyclic->req;
4124 + } else {
4125 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
4126 + req = &chan->req_sg->req;
4127 + }
4128 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
4129 + req->block_complete(req);
4130 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
4131 + }
4132 +}
4133 +
4134 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
4135 +{
4136 + struct dw_dma_channel *chan;
4137 + struct dma_request *req;
4138 + unsigned long status, chanid;
4139 +
4140 + status = dmac_readl_lo(dmac, STATUS_XFER);
4141 +
4142 + while (status) {
4143 + chanid = __ffs(status);
4144 + chan = &dmac->channel[chanid];
4145 +
4146 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
4147 +
4148 + req = &chan->req_sg->req;
4149 + BUG_ON(!req);
4150 + cleanup_channel(dmac, chan);
4151 + if (req->xfer_complete)
4152 + req->xfer_complete(req);
4153 +
4154 + status = dmac_readl_lo(dmac, STATUS_XFER);
4155 + }
4156 +}
4157 +
4158 +static void dmac_error(struct dw_dma_controller *dmac)
4159 +{
4160 + struct dw_dma_channel *chan;
4161 + unsigned long status, chanid;
4162 +
4163 + status = dmac_readl_lo(dmac, STATUS_ERROR);
4164 +
4165 + while (status) {
4166 + struct dma_request *req;
4167 +
4168 + chanid = __ffs(status);
4169 + chan = &dmac->channel[chanid];
4170 +
4171 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
4172 + clear_channel_bit(dmac, CH_EN, chanid);
4173 +
4174 + if (chan->is_cyclic) {
4175 + BUG_ON(!chan->req_cyclic);
4176 + req = &chan->req_cyclic->req;
4177 + } else {
4178 + BUG_ON(!chan->req_sg);
4179 + req = &chan->req_sg->req;
4180 + }
4181 +
4182 + cleanup_channel(dmac, chan);
4183 + if (req->error)
4184 + req->error(req);
4185 +
4186 + status = dmac_readl_lo(dmac, STATUS_XFER);
4187 + }
4188 +}
4189 +
4190 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
4191 +{
4192 + struct dw_dma_controller *dmac = dev_id;
4193 + unsigned long status;
4194 + int ret = IRQ_NONE;
4195 +
4196 + spin_lock(&dmac->lock);
4197 +
4198 + status = dmac_readl_lo(dmac, STATUS_INT);
4199 +
4200 + while (status) {
4201 + ret = IRQ_HANDLED;
4202 + if (status & 0x10)
4203 + dmac_error(dmac);
4204 + if (status & 0x02)
4205 + dmac_block_complete(dmac);
4206 + if (status & 0x01)
4207 + dmac_xfer_complete(dmac);
4208 +
4209 + status = dmac_readl_lo(dmac, STATUS_INT);
4210 + }
4211 +
4212 + spin_unlock(&dmac->lock);
4213 + return ret;
4214 +}
4215 +
4216 +static int __devinit dmac_probe(struct platform_device *pdev)
4217 +{
4218 + struct dw_dma_controller *dmac;
4219 + struct resource *regs;
4220 + int ret;
4221 +
4222 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4223 + if (!regs)
4224 + return -ENXIO;
4225 +
4226 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
4227 + if (!dmac)
4228 + return -ENOMEM;
4229 + memset(dmac, 0, sizeof(*dmac));
4230 +
4231 + dmac->hclk = clk_get(&pdev->dev, "hclk");
4232 + if (IS_ERR(dmac->hclk)) {
4233 + ret = PTR_ERR(dmac->hclk);
4234 + goto out_free_dmac;
4235 + }
4236 + clk_enable(dmac->hclk);
4237 +
4238 + ret = -ENOMEM;
4239 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
4240 + sizeof(struct dw_dma_lli), 4, 0);
4241 + if (!dmac->lli_pool)
4242 + goto out_disable_clk;
4243 +
4244 + spin_lock_init(&dmac->lock);
4245 + dmac->dma.dev = &pdev->dev;
4246 + dmac->dma.alloc_channel = dmac_alloc_channel;
4247 + dmac->dma.release_channel = dmac_release_channel;
4248 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
4249 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
4250 + dmac->dma.start_request = dmac_start_request;
4251 + dmac->dma.stop_request = dmac_stop_request;
4252 + dmac->dma.get_current_pos = dmac_get_current_pos;
4253 +
4254 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
4255 + if (!dmac->regs)
4256 + goto out_free_pool;
4257 +
4258 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
4259 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
4260 + if (ret)
4261 + goto out_unmap_regs;
4262 +
4263 + /* Enable the DMA controller */
4264 + dmac_writel_lo(dmac, CFG, 1);
4265 +
4266 + register_dma_controller(&dmac->dma);
4267 +
4268 + printk(KERN_INFO
4269 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
4270 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
4271 +
4272 + return 0;
4273 +
4274 +out_unmap_regs:
4275 + iounmap(dmac->regs);
4276 +out_free_pool:
4277 + dma_pool_destroy(dmac->lli_pool);
4278 +out_disable_clk:
4279 + clk_disable(dmac->hclk);
4280 + clk_put(dmac->hclk);
4281 +out_free_dmac:
4282 + kfree(dmac);
4283 + return ret;
4284 +}
4285 +
4286 +static struct platform_driver dmac_driver = {
4287 + .probe = dmac_probe,
4288 + .driver = {
4289 + .name = "dmaca",
4290 + },
4291 +};
4292 +
4293 +static int __init dmac_init(void)
4294 +{
4295 + return platform_driver_register(&dmac_driver);
4296 +}
4297 +subsys_initcall(dmac_init);
4298 +
4299 +static void __exit dmac_exit(void)
4300 +{
4301 + platform_driver_unregister(&dmac_driver);
4302 +}
4303 +module_exit(dmac_exit);
4304 +
4305 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
4306 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
4307 +MODULE_LICENSE("GPL");
4308 --- /dev/null
4309 +++ b/arch/avr32/drivers/dw-dmac.h
4310 @@ -0,0 +1,42 @@
4311 +/*
4312 + * Driver for the Synopsys DesignWare DMA Controller
4313 + *
4314 + * Copyright (C) 2005-2006 Atmel Corporation
4315 + *
4316 + * This program is free software; you can redistribute it and/or modify
4317 + * it under the terms of the GNU General Public License version 2 as
4318 + * published by the Free Software Foundation.
4319 + */
4320 +#ifndef __AVR32_DW_DMAC_H__
4321 +#define __AVR32_DW_DMAC_H__
4322 +
4323 +#define DW_DMAC_CFG 0x398
4324 +#define DW_DMAC_CH_EN 0x3a0
4325 +
4326 +#define DW_DMAC_STATUS_XFER 0x2e8
4327 +#define DW_DMAC_STATUS_BLOCK 0x2f0
4328 +#define DW_DMAC_STATUS_ERROR 0x308
4329 +
4330 +#define DW_DMAC_MASK_XFER 0x310
4331 +#define DW_DMAC_MASK_BLOCK 0x318
4332 +#define DW_DMAC_MASK_ERROR 0x330
4333 +
4334 +#define DW_DMAC_CLEAR_XFER 0x338
4335 +#define DW_DMAC_CLEAR_BLOCK 0x340
4336 +#define DW_DMAC_CLEAR_ERROR 0x358
4337 +
4338 +#define DW_DMAC_STATUS_INT 0x360
4339 +
4340 +#define DW_DMAC_CHAN_SAR 0x000
4341 +#define DW_DMAC_CHAN_DAR 0x008
4342 +#define DW_DMAC_CHAN_LLP 0x010
4343 +#define DW_DMAC_CHAN_CTL 0x018
4344 +#define DW_DMAC_CHAN_SSTAT 0x020
4345 +#define DW_DMAC_CHAN_DSTAT 0x028
4346 +#define DW_DMAC_CHAN_SSTATAR 0x030
4347 +#define DW_DMAC_CHAN_DSTATAR 0x038
4348 +#define DW_DMAC_CHAN_CFG 0x040
4349 +#define DW_DMAC_CHAN_SGR 0x048
4350 +#define DW_DMAC_CHAN_DSR 0x050
4351 +
4352 +#endif /* __AVR32_DW_DMAC_H__ */
4353 --- /dev/null
4354 +++ b/arch/avr32/drivers/Makefile
4355 @@ -0,0 +1 @@
4356 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
4357 --- a/arch/avr32/Kconfig
4358 +++ b/arch/avr32/Kconfig
4359 @@ -47,6 +47,9 @@
4360 config GENERIC_TIME
4361 def_bool y
4362
4363 +config GENERIC_CLOCKEVENTS
4364 + def_bool y
4365 +
4366 config RWSEM_XCHGADD_ALGORITHM
4367 def_bool n
4368
4369 @@ -70,6 +73,8 @@
4370
4371 menu "System Type and features"
4372
4373 +source "kernel/time/Kconfig"
4374 +
4375 config SUBARCH_AVR32B
4376 bool
4377 config MMU
4378 @@ -83,6 +88,7 @@
4379 select MMU
4380 select PERFORMANCE_COUNTERS
4381 select HAVE_GPIO_LIB
4382 + select GENERIC_ALLOCATOR
4383
4384 #
4385 # CPU types
4386 @@ -117,6 +123,9 @@
4387 if BOARD_ATSTK1000
4388 source "arch/avr32/boards/atstk1000/Kconfig"
4389 endif
4390 +if BOARD_ATNGW100
4391 +source "arch/avr32/boards/atngw100/Kconfig"
4392 +endif
4393
4394 choice
4395 prompt "Boot loader type"
4396 @@ -180,6 +189,10 @@
4397 be dumped to the console when a Non-Maskable Interrupt
4398 happens.
4399
4400 +config DW_DMAC
4401 + tristate "Synopsys DesignWare DMA Controller support"
4402 + default y if CPU_AT32AP7000
4403 +
4404 # FPU emulation goes here
4405
4406 source "kernel/Kconfig.hz"
4407 @@ -196,6 +209,11 @@
4408
4409 menu "Power management options"
4410
4411 +config ARCH_SUSPEND_POSSIBLE
4412 + def_bool y
4413 +
4414 +source "kernel/power/Kconfig"
4415 +
4416 menu "CPU Frequency scaling"
4417
4418 source "drivers/cpufreq/Kconfig"
4419 --- a/arch/avr32/kernel/avr32_ksyms.c
4420 +++ b/arch/avr32/kernel/avr32_ksyms.c
4421 @@ -29,7 +29,9 @@
4422 */
4423 EXPORT_SYMBOL(memset);
4424 EXPORT_SYMBOL(memcpy);
4425 +
4426 EXPORT_SYMBOL(clear_page);
4427 +EXPORT_SYMBOL(copy_page);
4428
4429 /*
4430 * Userspace access stuff.
4431 @@ -41,6 +43,8 @@
4432 EXPORT_SYMBOL(__strncpy_from_user);
4433 EXPORT_SYMBOL(clear_user);
4434 EXPORT_SYMBOL(__clear_user);
4435 +EXPORT_SYMBOL(strnlen_user);
4436 +
4437 EXPORT_SYMBOL(csum_partial);
4438 EXPORT_SYMBOL(csum_partial_copy_generic);
4439
4440 --- /dev/null
4441 +++ b/arch/avr32/kernel/dma-controller.c
4442 @@ -0,0 +1,34 @@
4443 +/*
4444 + * Preliminary DMA controller framework for AVR32
4445 + *
4446 + * Copyright (C) 2005-2006 Atmel Corporation
4447 + *
4448 + * This program is free software; you can redistribute it and/or modify
4449 + * it under the terms of the GNU General Public License version 2 as
4450 + * published by the Free Software Foundation.
4451 + */
4452 +#include <asm/dma-controller.h>
4453 +
4454 +static LIST_HEAD(controllers);
4455 +
4456 +int register_dma_controller(struct dma_controller *dmac)
4457 +{
4458 + static int next_id;
4459 +
4460 + dmac->id = next_id++;
4461 + list_add_tail(&dmac->list, &controllers);
4462 +
4463 + return 0;
4464 +}
4465 +EXPORT_SYMBOL(register_dma_controller);
4466 +
4467 +struct dma_controller *find_dma_controller(int id)
4468 +{
4469 + struct dma_controller *dmac;
4470 +
4471 + list_for_each_entry(dmac, &controllers, list)
4472 + if (dmac->id == id)
4473 + return dmac;
4474 + return NULL;
4475 +}
4476 +EXPORT_SYMBOL(find_dma_controller);
4477 --- a/arch/avr32/kernel/entry-avr32b.S
4478 +++ b/arch/avr32/kernel/entry-avr32b.S
4479 @@ -741,26 +741,6 @@
4480
4481 .section .irq.text,"ax",@progbits
4482
4483 -.global cpu_idle_sleep
4484 -cpu_idle_sleep:
4485 - mask_interrupts
4486 - get_thread_info r8
4487 - ld.w r9, r8[TI_flags]
4488 - bld r9, TIF_NEED_RESCHED
4489 - brcs cpu_idle_enable_int_and_exit
4490 - sbr r9, TIF_CPU_GOING_TO_SLEEP
4491 - st.w r8[TI_flags], r9
4492 - unmask_interrupts
4493 - sleep 0
4494 -cpu_idle_skip_sleep:
4495 - mask_interrupts
4496 - ld.w r9, r8[TI_flags]
4497 - cbr r9, TIF_CPU_GOING_TO_SLEEP
4498 - st.w r8[TI_flags], r9
4499 -cpu_idle_enable_int_and_exit:
4500 - unmask_interrupts
4501 - retal r12
4502 -
4503 .global irq_level0
4504 .global irq_level1
4505 .global irq_level2
4506 --- a/arch/avr32/kernel/Makefile
4507 +++ b/arch/avr32/kernel/Makefile
4508 @@ -9,6 +9,7 @@
4509 obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
4510 obj-y += signal.o sys_avr32.o process.o time.o
4511 obj-y += init_task.o switch_to.o cpu.o
4512 +obj-y += dma-controller.o
4513 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
4514 obj-$(CONFIG_KPROBES) += kprobes.o
4515 obj-$(CONFIG_STACKTRACE) += stacktrace.o
4516 --- a/arch/avr32/kernel/process.c
4517 +++ b/arch/avr32/kernel/process.c
4518 @@ -18,11 +18,11 @@
4519 #include <asm/sysreg.h>
4520 #include <asm/ocd.h>
4521
4522 +#include <asm/arch/pm.h>
4523 +
4524 void (*pm_power_off)(void) = NULL;
4525 EXPORT_SYMBOL(pm_power_off);
4526
4527 -extern void cpu_idle_sleep(void);
4528 -
4529 /*
4530 * This file handles the architecture-dependent parts of process handling..
4531 */
4532 @@ -54,6 +54,8 @@
4533
4534 void machine_power_off(void)
4535 {
4536 + if (pm_power_off)
4537 + pm_power_off();
4538 }
4539
4540 void machine_restart(char *cmd)
4541 --- a/arch/avr32/kernel/setup.c
4542 +++ b/arch/avr32/kernel/setup.c
4543 @@ -274,6 +274,8 @@
4544 printk(KERN_WARNING
4545 "Failed to allocate framebuffer memory\n");
4546 fbmem_size = 0;
4547 + } else {
4548 + memset(__va(fbmem_start), 0, fbmem_size);
4549 }
4550 }
4551
4552 --- a/arch/avr32/kernel/signal.c
4553 +++ b/arch/avr32/kernel/signal.c
4554 @@ -93,6 +93,9 @@
4555 if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
4556 goto badframe;
4557
4558 + if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
4559 + goto badframe;
4560 +
4561 pr_debug("Context restored: pc = %08lx, lr = %08lx, sp = %08lx\n",
4562 regs->pc, regs->lr, regs->sp);
4563
4564 --- a/arch/avr32/kernel/time.c
4565 +++ b/arch/avr32/kernel/time.c
4566 @@ -1,16 +1,12 @@
4567 /*
4568 * Copyright (C) 2004-2007 Atmel Corporation
4569 *
4570 - * Based on MIPS implementation arch/mips/kernel/time.c
4571 - * Copyright 2001 MontaVista Software Inc.
4572 - *
4573 * This program is free software; you can redistribute it and/or modify
4574 * it under the terms of the GNU General Public License version 2 as
4575 * published by the Free Software Foundation.
4576 */
4577 -
4578 #include <linux/clk.h>
4579 -#include <linux/clocksource.h>
4580 +#include <linux/clockchips.h>
4581 #include <linux/time.h>
4582 #include <linux/module.h>
4583 #include <linux/interrupt.h>
4584 @@ -27,207 +23,133 @@
4585 #include <asm/io.h>
4586 #include <asm/sections.h>
4587
4588 -/* how many counter cycles in a jiffy? */
4589 -static u32 cycles_per_jiffy;
4590 +#include <asm/arch/pm.h>
4591
4592 -/* the count value for the next timer interrupt */
4593 -static u32 expirelo;
4594
4595 -cycle_t __weak read_cycle_count(void)
4596 +static cycle_t read_cycle_count(void)
4597 {
4598 return (cycle_t)sysreg_read(COUNT);
4599 }
4600
4601 -struct clocksource __weak clocksource_avr32 = {
4602 - .name = "avr32",
4603 - .rating = 350,
4604 +/*
4605 + * The architectural cycle count registers are a fine clocksource unless
4606 + * the system idle loop use sleep states like "idle": the CPU cycles
4607 + * measured by COUNT (and COMPARE) don't happen during sleep states.
4608 + * Their duration also changes if cpufreq changes the CPU clock rate.
4609 + * So we rate the clocksource using COUNT as very low quality.
4610 + */
4611 +static struct clocksource counter = {
4612 + .name = "avr32_counter",
4613 + .rating = 50,
4614 .read = read_cycle_count,
4615 .mask = CLOCKSOURCE_MASK(32),
4616 .shift = 16,
4617 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
4618 };
4619
4620 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
4621 -
4622 -struct irqaction timer_irqaction = {
4623 - .handler = timer_interrupt,
4624 - .flags = IRQF_DISABLED,
4625 - .name = "timer",
4626 -};
4627 -
4628 -/*
4629 - * By default we provide the null RTC ops
4630 - */
4631 -static unsigned long null_rtc_get_time(void)
4632 +static irqreturn_t timer_interrupt(int irq, void *dev_id)
4633 {
4634 - return mktime(2007, 1, 1, 0, 0, 0);
4635 -}
4636 -
4637 -static int null_rtc_set_time(unsigned long sec)
4638 -{
4639 - return 0;
4640 -}
4641 + struct clock_event_device *evdev = dev_id;
4642
4643 -static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
4644 -static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
4645 -
4646 -static void avr32_timer_ack(void)
4647 -{
4648 - u32 count;
4649 -
4650 - /* Ack this timer interrupt and set the next one */
4651 - expirelo += cycles_per_jiffy;
4652 - /* setting COMPARE to 0 stops the COUNT-COMPARE */
4653 - if (expirelo == 0) {
4654 - sysreg_write(COMPARE, expirelo + 1);
4655 - } else {
4656 - sysreg_write(COMPARE, expirelo);
4657 - }
4658 + /*
4659 + * Disable the interrupt until the clockevent subsystem
4660 + * reprograms it.
4661 + */
4662 + sysreg_write(COMPARE, 0);
4663
4664 - /* Check to see if we have missed any timer interrupts */
4665 - count = sysreg_read(COUNT);
4666 - if ((count - expirelo) < 0x7fffffff) {
4667 - expirelo = count + cycles_per_jiffy;
4668 - sysreg_write(COMPARE, expirelo);
4669 - }
4670 + evdev->event_handler(evdev);
4671 + return IRQ_HANDLED;
4672 }
4673
4674 -int __weak avr32_hpt_init(void)
4675 -{
4676 - int ret;
4677 - unsigned long mult, shift, count_hz;
4678 -
4679 - count_hz = clk_get_rate(boot_cpu_data.clk);
4680 - shift = clocksource_avr32.shift;
4681 - mult = clocksource_hz2mult(count_hz, shift);
4682 - clocksource_avr32.mult = mult;
4683 -
4684 - {
4685 - u64 tmp;
4686 -
4687 - tmp = TICK_NSEC;
4688 - tmp <<= shift;
4689 - tmp += mult / 2;
4690 - do_div(tmp, mult);
4691 -
4692 - cycles_per_jiffy = tmp;
4693 - }
4694 +static struct irqaction timer_irqaction = {
4695 + .handler = timer_interrupt,
4696 + .flags = IRQF_TIMER | IRQF_DISABLED,
4697 + .name = "avr32_comparator",
4698 +};
4699
4700 - ret = setup_irq(0, &timer_irqaction);
4701 - if (ret) {
4702 - pr_debug("timer: could not request IRQ 0: %d\n", ret);
4703 - return -ENODEV;
4704 - }
4705 +static int comparator_next_event(unsigned long delta,
4706 + struct clock_event_device *evdev)
4707 +{
4708 + unsigned long flags;
4709
4710 - printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
4711 - "%lu.%03lu MHz\n",
4712 - ((count_hz + 500) / 1000) / 1000,
4713 - ((count_hz + 500) / 1000) % 1000);
4714 + raw_local_irq_save(flags);
4715
4716 - return 0;
4717 -}
4718 + /* The time to read COUNT then update COMPARE must be less
4719 + * than the min_delta_ns value for this clockevent source.
4720 + */
4721 + sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
4722
4723 -/*
4724 - * Taken from MIPS c0_hpt_timer_init().
4725 - *
4726 - * The reason COUNT is written twice is probably to make sure we don't get any
4727 - * timer interrupts while we are messing with the counter.
4728 - */
4729 -int __weak avr32_hpt_start(void)
4730 -{
4731 - u32 count = sysreg_read(COUNT);
4732 - expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
4733 - sysreg_write(COUNT, expirelo - cycles_per_jiffy);
4734 - sysreg_write(COMPARE, expirelo);
4735 - sysreg_write(COUNT, count);
4736 + raw_local_irq_restore(flags);
4737
4738 return 0;
4739 }
4740
4741 -/*
4742 - * local_timer_interrupt() does profiling and process accounting on a
4743 - * per-CPU basis.
4744 - *
4745 - * In UP mode, it is invoked from the (global) timer_interrupt.
4746 - */
4747 -void local_timer_interrupt(int irq, void *dev_id)
4748 +static void comparator_mode(enum clock_event_mode mode,
4749 + struct clock_event_device *evdev)
4750 {
4751 - if (current->pid)
4752 - profile_tick(CPU_PROFILING);
4753 - update_process_times(user_mode(get_irq_regs()));
4754 + switch (mode) {
4755 + case CLOCK_EVT_MODE_ONESHOT:
4756 + pr_debug("%s: start\n", evdev->name);
4757 + /* FALLTHROUGH */
4758 + case CLOCK_EVT_MODE_RESUME:
4759 + cpu_disable_idle_sleep();
4760 + break;
4761 + case CLOCK_EVT_MODE_UNUSED:
4762 + case CLOCK_EVT_MODE_SHUTDOWN:
4763 + sysreg_write(COMPARE, 0);
4764 + pr_debug("%s: stop\n", evdev->name);
4765 + cpu_enable_idle_sleep();
4766 + break;
4767 + default:
4768 + BUG();
4769 + }
4770 }
4771
4772 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
4773 -{
4774 - /* ack timer interrupt and try to set next interrupt */
4775 - avr32_timer_ack();
4776 -
4777 - /*
4778 - * Call the generic timer interrupt handler
4779 - */
4780 - write_seqlock(&xtime_lock);
4781 - do_timer(1);
4782 - write_sequnlock(&xtime_lock);
4783 -
4784 - /*
4785 - * In UP mode, we call local_timer_interrupt() to do profiling
4786 - * and process accounting.
4787 - *
4788 - * SMP is not supported yet.
4789 - */
4790 - local_timer_interrupt(irq, dev_id);
4791 -
4792 - return IRQ_HANDLED;
4793 -}
4794 +static struct clock_event_device comparator = {
4795 + .name = "avr32_comparator",
4796 + .features = CLOCK_EVT_FEAT_ONESHOT,
4797 + .shift = 16,
4798 + .rating = 50,
4799 + .cpumask = CPU_MASK_CPU0,
4800 + .set_next_event = comparator_next_event,
4801 + .set_mode = comparator_mode,
4802 +};
4803
4804 void __init time_init(void)
4805 {
4806 + unsigned long counter_hz;
4807 int ret;
4808
4809 - /*
4810 - * Make sure we don't get any COMPARE interrupts before we can
4811 - * handle them.
4812 - */
4813 - sysreg_write(COMPARE, 0);
4814 -
4815 - xtime.tv_sec = rtc_get_time();
4816 + xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
4817 xtime.tv_nsec = 0;
4818
4819 set_normalized_timespec(&wall_to_monotonic,
4820 -xtime.tv_sec, -xtime.tv_nsec);
4821
4822 - ret = avr32_hpt_init();
4823 - if (ret) {
4824 - pr_debug("timer: failed setup: %d\n", ret);
4825 - return;
4826 - }
4827 + /* figure rate for counter */
4828 + counter_hz = clk_get_rate(boot_cpu_data.clk);
4829 + counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
4830
4831 - ret = clocksource_register(&clocksource_avr32);
4832 + ret = clocksource_register(&counter);
4833 if (ret)
4834 pr_debug("timer: could not register clocksource: %d\n", ret);
4835
4836 - ret = avr32_hpt_start();
4837 - if (ret) {
4838 - pr_debug("timer: failed starting: %d\n", ret);
4839 - return;
4840 - }
4841 -}
4842 + /* setup COMPARE clockevent */
4843 + comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
4844 + comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
4845 + comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
4846
4847 -static struct sysdev_class timer_class = {
4848 - .name = "timer",
4849 -};
4850 + sysreg_write(COMPARE, 0);
4851 + timer_irqaction.dev_id = &comparator;
4852
4853 -static struct sys_device timer_device = {
4854 - .id = 0,
4855 - .cls = &timer_class,
4856 -};
4857 + ret = setup_irq(0, &timer_irqaction);
4858 + if (ret)
4859 + pr_debug("timer: could not request IRQ 0: %d\n", ret);
4860 + else {
4861 + clockevents_register_device(&comparator);
4862
4863 -static int __init init_timer_sysfs(void)
4864 -{
4865 - int err = sysdev_class_register(&timer_class);
4866 - if (!err)
4867 - err = sysdev_register(&timer_device);
4868 - return err;
4869 + pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
4870 + ((counter_hz + 500) / 1000) / 1000,
4871 + ((counter_hz + 500) / 1000) % 1000);
4872 + }
4873 }
4874 -
4875 -device_initcall(init_timer_sysfs);
4876 --- a/arch/avr32/lib/io-readsb.S
4877 +++ b/arch/avr32/lib/io-readsb.S
4878 @@ -41,7 +41,7 @@
4879 2: sub r10, -4
4880 reteq r12
4881
4882 -3: ld.uh r8, r12[0]
4883 +3: ld.ub r8, r12[0]
4884 sub r10, 1
4885 st.b r11++, r8
4886 brne 3b
4887 --- a/arch/avr32/mach-at32ap/at32ap700x.c
4888 +++ b/arch/avr32/mach-at32ap/at32ap700x.c
4889 @@ -6,11 +6,13 @@
4890 * published by the Free Software Foundation.
4891 */
4892 #include <linux/clk.h>
4893 +#include <linux/delay.h>
4894 #include <linux/fb.h>
4895 #include <linux/init.h>
4896 #include <linux/platform_device.h>
4897 #include <linux/dma-mapping.h>
4898 #include <linux/spi/spi.h>
4899 +#include <linux/usb/atmel_usba_udc.h>
4900
4901 #include <asm/io.h>
4902 #include <asm/irq.h>
4903 @@ -18,6 +20,7 @@
4904 #include <asm/arch/at32ap700x.h>
4905 #include <asm/arch/board.h>
4906 #include <asm/arch/portmux.h>
4907 +#include <asm/arch/sram.h>
4908
4909 #include <video/atmel_lcdc.h>
4910
4911 @@ -91,25 +94,18 @@
4912
4913 static DEFINE_SPINLOCK(pm_lock);
4914
4915 -unsigned long at32ap7000_osc_rates[3] = {
4916 - [0] = 32768,
4917 - /* FIXME: these are ATSTK1002-specific */
4918 - [1] = 20000000,
4919 - [2] = 12000000,
4920 -};
4921 +static struct clk osc0;
4922 +static struct clk osc1;
4923
4924 static unsigned long osc_get_rate(struct clk *clk)
4925 {
4926 - return at32ap7000_osc_rates[clk->index];
4927 + return at32_board_osc_rates[clk->index];
4928 }
4929
4930 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
4931 {
4932 unsigned long div, mul, rate;
4933
4934 - if (!(control & PM_BIT(PLLEN)))
4935 - return 0;
4936 -
4937 div = PM_BFEXT(PLLDIV, control) + 1;
4938 mul = PM_BFEXT(PLLMUL, control) + 1;
4939
4940 @@ -120,6 +116,71 @@
4941 return rate;
4942 }
4943
4944 +static long pll_set_rate(struct clk *clk, unsigned long rate,
4945 + u32 *pll_ctrl)
4946 +{
4947 + unsigned long mul;
4948 + unsigned long mul_best_fit = 0;
4949 + unsigned long div;
4950 + unsigned long div_min;
4951 + unsigned long div_max;
4952 + unsigned long div_best_fit = 0;
4953 + unsigned long base;
4954 + unsigned long pll_in;
4955 + unsigned long actual = 0;
4956 + unsigned long rate_error;
4957 + unsigned long rate_error_prev = ~0UL;
4958 + u32 ctrl;
4959 +
4960 + /* Rate must be between 80 MHz and 200 Mhz. */
4961 + if (rate < 80000000UL || rate > 200000000UL)
4962 + return -EINVAL;
4963 +
4964 + ctrl = PM_BF(PLLOPT, 4);
4965 + base = clk->parent->get_rate(clk->parent);
4966 +
4967 + /* PLL input frequency must be between 6 MHz and 32 MHz. */
4968 + div_min = DIV_ROUND_UP(base, 32000000UL);
4969 + div_max = base / 6000000UL;
4970 +
4971 + if (div_max < div_min)
4972 + return -EINVAL;
4973 +
4974 + for (div = div_min; div <= div_max; div++) {
4975 + pll_in = (base + div / 2) / div;
4976 + mul = (rate + pll_in / 2) / pll_in;
4977 +
4978 + if (mul == 0)
4979 + continue;
4980 +
4981 + actual = pll_in * mul;
4982 + rate_error = abs(actual - rate);
4983 +
4984 + if (rate_error < rate_error_prev) {
4985 + mul_best_fit = mul;
4986 + div_best_fit = div;
4987 + rate_error_prev = rate_error;
4988 + }
4989 +
4990 + if (rate_error == 0)
4991 + break;
4992 + }
4993 +
4994 + if (div_best_fit == 0)
4995 + return -EINVAL;
4996 +
4997 + ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
4998 + ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
4999 + ctrl |= PM_BF(PLLCOUNT, 16);
5000 +
5001 + if (clk->parent == &osc1)
5002 + ctrl |= PM_BIT(PLLOSC);
5003 +
5004 + *pll_ctrl = ctrl;
5005 +
5006 + return actual;
5007 +}
5008 +
5009 static unsigned long pll0_get_rate(struct clk *clk)
5010 {
5011 u32 control;
5012 @@ -129,6 +190,41 @@
5013 return pll_get_rate(clk, control);
5014 }
5015
5016 +static void pll1_mode(struct clk *clk, int enabled)
5017 +{
5018 + unsigned long timeout;
5019 + u32 status;
5020 + u32 ctrl;
5021 +
5022 + ctrl = pm_readl(PLL1);
5023 +
5024 + if (enabled) {
5025 + if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
5026 + pr_debug("clk %s: failed to enable, rate not set\n",
5027 + clk->name);
5028 + return;
5029 + }
5030 +
5031 + ctrl |= PM_BIT(PLLEN);
5032 + pm_writel(PLL1, ctrl);
5033 +
5034 + /* Wait for PLL lock. */
5035 + for (timeout = 10000; timeout; timeout--) {
5036 + status = pm_readl(ISR);
5037 + if (status & PM_BIT(LOCK1))
5038 + break;
5039 + udelay(10);
5040 + }
5041 +
5042 + if (!(status & PM_BIT(LOCK1)))
5043 + printk(KERN_ERR "clk %s: timeout waiting for lock\n",
5044 + clk->name);
5045 + } else {
5046 + ctrl &= ~PM_BIT(PLLEN);
5047 + pm_writel(PLL1, ctrl);
5048 + }
5049 +}
5050 +
5051 static unsigned long pll1_get_rate(struct clk *clk)
5052 {
5053 u32 control;
5054 @@ -138,6 +234,49 @@
5055 return pll_get_rate(clk, control);
5056 }
5057
5058 +static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
5059 +{
5060 + u32 ctrl = 0;
5061 + unsigned long actual_rate;
5062 +
5063 + actual_rate = pll_set_rate(clk, rate, &ctrl);
5064 +
5065 + if (apply) {
5066 + if (actual_rate != rate)
5067 + return -EINVAL;
5068 + if (clk->users > 0)
5069 + return -EBUSY;
5070 + pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
5071 + clk->name, rate, actual_rate);
5072 + pm_writel(PLL1, ctrl);
5073 + }
5074 +
5075 + return actual_rate;
5076 +}
5077 +
5078 +static int pll1_set_parent(struct clk *clk, struct clk *parent)
5079 +{
5080 + u32 ctrl;
5081 +
5082 + if (clk->users > 0)
5083 + return -EBUSY;
5084 +
5085 + ctrl = pm_readl(PLL1);
5086 + WARN_ON(ctrl & PM_BIT(PLLEN));
5087 +
5088 + if (parent == &osc0)
5089 + ctrl &= ~PM_BIT(PLLOSC);
5090 + else if (parent == &osc1)
5091 + ctrl |= PM_BIT(PLLOSC);
5092 + else
5093 + return -EINVAL;
5094 +
5095 + pm_writel(PLL1, ctrl);
5096 + clk->parent = parent;
5097 +
5098 + return 0;
5099 +}
5100 +
5101 /*
5102 * The AT32AP7000 has five primary clock sources: One 32kHz
5103 * oscillator, two crystal oscillators and two PLLs.
5104 @@ -166,7 +305,10 @@
5105 };
5106 static struct clk pll1 = {
5107 .name = "pll1",
5108 + .mode = pll1_mode,
5109 .get_rate = pll1_get_rate,
5110 + .set_rate = pll1_set_rate,
5111 + .set_parent = pll1_set_parent,
5112 .parent = &osc0,
5113 };
5114
5115 @@ -534,6 +676,14 @@
5116 .users = 1,
5117 .index = 3,
5118 };
5119 +static struct clk sdramc_clk = {
5120 + .name = "sdramc_clk",
5121 + .parent = &pbb_clk,
5122 + .mode = pbb_clk_mode,
5123 + .get_rate = pbb_clk_get_rate,
5124 + .users = 1,
5125 + .index = 14,
5126 +};
5127
5128 static struct resource smc0_resource[] = {
5129 PBMEM(0xfff03400),
5130 @@ -605,19 +755,32 @@
5131 }
5132
5133 /* --------------------------------------------------------------------
5134 - * System Timer/Counter (TC)
5135 + * Timer/Counter (TC)
5136 * -------------------------------------------------------------------- */
5137 -static struct resource at32_systc0_resource[] = {
5138 +
5139 +static struct resource at32_tcb0_resource[] = {
5140 PBMEM(0xfff00c00),
5141 IRQ(22),
5142 };
5143 -struct platform_device at32_systc0_device = {
5144 - .name = "systc",
5145 +static struct platform_device at32_tcb0_device = {
5146 + .name = "atmel_tcb",
5147 .id = 0,
5148 - .resource = at32_systc0_resource,
5149 - .num_resources = ARRAY_SIZE(at32_systc0_resource),
5150 + .resource = at32_tcb0_resource,
5151 + .num_resources = ARRAY_SIZE(at32_tcb0_resource),
5152 };
5153 -DEV_CLK(pclk, at32_systc0, pbb, 3);
5154 +DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
5155 +
5156 +static struct resource at32_tcb1_resource[] = {
5157 + PBMEM(0xfff01000),
5158 + IRQ(23),
5159 +};
5160 +static struct platform_device at32_tcb1_device = {
5161 + .name = "atmel_tcb",
5162 + .id = 1,
5163 + .resource = at32_tcb1_resource,
5164 + .num_resources = ARRAY_SIZE(at32_tcb1_resource),
5165 +};
5166 +DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
5167
5168 /* --------------------------------------------------------------------
5169 * PIO
5170 @@ -669,7 +832,8 @@
5171 platform_device_register(&pdc_device);
5172 platform_device_register(&dmaca0_device);
5173
5174 - platform_device_register(&at32_systc0_device);
5175 + platform_device_register(&at32_tcb0_device);
5176 + platform_device_register(&at32_tcb1_device);
5177
5178 platform_device_register(&pio0_device);
5179 platform_device_register(&pio1_device);
5180 @@ -679,6 +843,81 @@
5181 }
5182
5183 /* --------------------------------------------------------------------
5184 + * PSIF
5185 + * -------------------------------------------------------------------- */
5186 +static struct resource atmel_psif0_resource[] __initdata = {
5187 + {
5188 + .start = 0xffe03c00,
5189 + .end = 0xffe03cff,
5190 + .flags = IORESOURCE_MEM,
5191 + },
5192 + IRQ(18),
5193 +};
5194 +static struct clk atmel_psif0_pclk = {
5195 + .name = "pclk",
5196 + .parent = &pba_clk,
5197 + .mode = pba_clk_mode,
5198 + .get_rate = pba_clk_get_rate,
5199 + .index = 15,
5200 +};
5201 +
5202 +static struct resource atmel_psif1_resource[] __initdata = {
5203 + {
5204 + .start = 0xffe03d00,
5205 + .end = 0xffe03dff,
5206 + .flags = IORESOURCE_MEM,
5207 + },
5208 + IRQ(18),
5209 +};
5210 +static struct clk atmel_psif1_pclk = {
5211 + .name = "pclk",
5212 + .parent = &pba_clk,
5213 + .mode = pba_clk_mode,
5214 + .get_rate = pba_clk_get_rate,
5215 + .index = 15,
5216 +};
5217 +
5218 +struct platform_device *__init at32_add_device_psif(unsigned int id)
5219 +{
5220 + struct platform_device *pdev;
5221 +
5222 + if (!(id == 0 || id == 1))
5223 + return NULL;
5224 +
5225 + pdev = platform_device_alloc("atmel_psif", id);
5226 + if (!pdev)
5227 + return NULL;
5228 +
5229 + switch (id) {
5230 + case 0:
5231 + if (platform_device_add_resources(pdev, atmel_psif0_resource,
5232 + ARRAY_SIZE(atmel_psif0_resource)))
5233 + goto err_add_resources;
5234 + atmel_psif0_pclk.dev = &pdev->dev;
5235 + select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
5236 + select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
5237 + break;
5238 + case 1:
5239 + if (platform_device_add_resources(pdev, atmel_psif1_resource,
5240 + ARRAY_SIZE(atmel_psif1_resource)))
5241 + goto err_add_resources;
5242 + atmel_psif1_pclk.dev = &pdev->dev;
5243 + select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
5244 + select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
5245 + break;
5246 + default:
5247 + return NULL;
5248 + }
5249 +
5250 + platform_device_add(pdev);
5251 + return pdev;
5252 +
5253 +err_add_resources:
5254 + platform_device_put(pdev);
5255 + return NULL;
5256 +}
5257 +
5258 +/* --------------------------------------------------------------------
5259 * USART
5260 * -------------------------------------------------------------------- */
5261
5262 @@ -989,7 +1228,9 @@
5263 .index = 2,
5264 };
5265
5266 -struct platform_device *__init at32_add_device_twi(unsigned int id)
5267 +struct platform_device *__init at32_add_device_twi(unsigned int id,
5268 + struct i2c_board_info *b,
5269 + unsigned int n)
5270 {
5271 struct platform_device *pdev;
5272
5273 @@ -1009,6 +1250,9 @@
5274
5275 atmel_twi0_pclk.dev = &pdev->dev;
5276
5277 + if (b)
5278 + i2c_register_board_info(id, b, n);
5279 +
5280 platform_device_add(pdev);
5281 return pdev;
5282
5283 @@ -1032,7 +1276,8 @@
5284 .index = 9,
5285 };
5286
5287 -struct platform_device *__init at32_add_device_mci(unsigned int id)
5288 +struct platform_device *__init
5289 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
5290 {
5291 struct platform_device *pdev;
5292
5293 @@ -1041,11 +1286,15 @@
5294
5295 pdev = platform_device_alloc("atmel_mci", id);
5296 if (!pdev)
5297 - return NULL;
5298 + goto fail;
5299
5300 if (platform_device_add_resources(pdev, atmel_mci0_resource,
5301 ARRAY_SIZE(atmel_mci0_resource)))
5302 - goto err_add_resources;
5303 + goto fail;
5304 +
5305 + if (data && platform_device_add_data(pdev, data,
5306 + sizeof(struct mci_platform_data)))
5307 + goto fail;
5308
5309 select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
5310 select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
5311 @@ -1054,12 +1303,19 @@
5312 select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
5313 select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
5314
5315 + if (data) {
5316 + if (data->detect_pin != GPIO_PIN_NONE)
5317 + at32_select_gpio(data->detect_pin, 0);
5318 + if (data->wp_pin != GPIO_PIN_NONE)
5319 + at32_select_gpio(data->wp_pin, 0);
5320 + }
5321 +
5322 atmel_mci0_pclk.dev = &pdev->dev;
5323
5324 platform_device_add(pdev);
5325 return pdev;
5326
5327 -err_add_resources:
5328 +fail:
5329 platform_device_put(pdev);
5330 return NULL;
5331 }
5332 @@ -1097,7 +1353,8 @@
5333
5334 struct platform_device *__init
5335 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
5336 - unsigned long fbmem_start, unsigned long fbmem_len)
5337 + unsigned long fbmem_start, unsigned long fbmem_len,
5338 + unsigned int pin_config)
5339 {
5340 struct platform_device *pdev;
5341 struct atmel_lcdfb_info *info;
5342 @@ -1124,37 +1381,77 @@
5343 switch (id) {
5344 case 0:
5345 pdev = &atmel_lcdfb0_device;
5346 - select_peripheral(PC(19), PERIPH_A, 0); /* CC */
5347 - select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5348 - select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5349 - select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5350 - select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
5351 - select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
5352 - select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5353 - select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
5354 - select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
5355 - select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
5356 - select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
5357 - select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
5358 - select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5359 - select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5360 - select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5361 - select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
5362 - select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
5363 - select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
5364 - select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
5365 - select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
5366 - select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5367 - select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5368 - select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5369 - select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
5370 - select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
5371 - select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
5372 - select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
5373 - select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
5374 - select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
5375 - select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5376 - select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5377 +
5378 + switch (pin_config) {
5379 + case 0:
5380 + select_peripheral(PC(19), PERIPH_A, 0); /* CC */
5381 + select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5382 + select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5383 + select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5384 + select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
5385 + select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
5386 + select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5387 + select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
5388 + select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
5389 + select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
5390 + select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
5391 + select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
5392 + select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5393 + select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5394 + select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5395 + select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
5396 + select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
5397 + select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
5398 + select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
5399 + select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
5400 + select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5401 + select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5402 + select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5403 + select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
5404 + select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
5405 + select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
5406 + select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
5407 + select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
5408 + select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
5409 + select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5410 + select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5411 + break;
5412 + case 1:
5413 + select_peripheral(PE(0), PERIPH_B, 0); /* CC */
5414 + select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
5415 + select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
5416 + select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
5417 + select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
5418 + select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
5419 + select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
5420 + select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
5421 + select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
5422 + select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
5423 + select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
5424 + select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
5425 + select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
5426 + select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
5427 + select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
5428 + select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
5429 + select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
5430 + select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
5431 + select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
5432 + select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
5433 + select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
5434 + select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
5435 + select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
5436 + select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
5437 + select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
5438 + select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
5439 + select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
5440 + select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
5441 + select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
5442 + select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
5443 + select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
5444 + break;
5445 + default:
5446 + goto err_invalid_id;
5447 + }
5448
5449 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
5450 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
5451 @@ -1351,9 +1648,39 @@
5452 .index = 6,
5453 };
5454
5455 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
5456 + [idx] = { \
5457 + .name = nam, \
5458 + .index = idx, \
5459 + .fifo_size = maxpkt, \
5460 + .nr_banks = maxbk, \
5461 + .can_dma = dma, \
5462 + .can_isoc = isoc, \
5463 + }
5464 +
5465 +static struct usba_ep_data at32_usba_ep[] __initdata = {
5466 + EP("ep0", 0, 64, 1, 0, 0),
5467 + EP("ep1", 1, 512, 2, 1, 1),
5468 + EP("ep2", 2, 512, 2, 1, 1),
5469 + EP("ep3-int", 3, 64, 3, 1, 0),
5470 + EP("ep4-int", 4, 64, 3, 1, 0),
5471 + EP("ep5", 5, 1024, 3, 1, 1),
5472 + EP("ep6", 6, 1024, 3, 1, 1),
5473 +};
5474 +
5475 +#undef EP
5476 +
5477 struct platform_device *__init
5478 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
5479 {
5480 + /*
5481 + * pdata doesn't have room for any endpoints, so we need to
5482 + * append room for the ones we need right after it.
5483 + */
5484 + struct {
5485 + struct usba_platform_data pdata;
5486 + struct usba_ep_data ep[7];
5487 + } usba_data;
5488 struct platform_device *pdev;
5489
5490 if (id != 0)
5491 @@ -1367,13 +1694,20 @@
5492 ARRAY_SIZE(usba0_resource)))
5493 goto out_free_pdev;
5494
5495 - if (data) {
5496 - if (platform_device_add_data(pdev, data, sizeof(*data)))
5497 - goto out_free_pdev;
5498 + if (data)
5499 + usba_data.pdata.vbus_pin = data->vbus_pin;
5500 + else
5501 + usba_data.pdata.vbus_pin = -EINVAL;
5502
5503 - if (data->vbus_pin != GPIO_PIN_NONE)
5504 - at32_select_gpio(data->vbus_pin, 0);
5505 - }
5506 + data = &usba_data.pdata;
5507 + data->num_ep = ARRAY_SIZE(at32_usba_ep);
5508 + memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
5509 +
5510 + if (platform_device_add_data(pdev, data, sizeof(usba_data)))
5511 + goto out_free_pdev;
5512 +
5513 + if (data->vbus_pin >= 0)
5514 + at32_select_gpio(data->vbus_pin, 0);
5515
5516 usba0_pclk.dev = &pdev->dev;
5517 usba0_hclk.dev = &pdev->dev;
5518 @@ -1526,6 +1860,58 @@
5519 #endif
5520
5521 /* --------------------------------------------------------------------
5522 + * NAND Flash / SmartMedia
5523 + * -------------------------------------------------------------------- */
5524 +static struct resource smc_cs3_resource[] __initdata = {
5525 + {
5526 + .start = 0x0c000000,
5527 + .end = 0x0fffffff,
5528 + .flags = IORESOURCE_MEM,
5529 + }, {
5530 + .start = 0xfff03c00,
5531 + .end = 0xfff03fff,
5532 + .flags = IORESOURCE_MEM,
5533 + },
5534 +};
5535 +
5536 +struct platform_device *__init
5537 +at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
5538 +{
5539 + struct platform_device *pdev;
5540 +
5541 + if (id != 0 || !data)
5542 + return NULL;
5543 +
5544 + pdev = platform_device_alloc("atmel_nand", id);
5545 + if (!pdev)
5546 + goto fail;
5547 +
5548 + if (platform_device_add_resources(pdev, smc_cs3_resource,
5549 + ARRAY_SIZE(smc_cs3_resource)))
5550 + goto fail;
5551 +
5552 + if (platform_device_add_data(pdev, data,
5553 + sizeof(struct atmel_nand_data)))
5554 + goto fail;
5555 +
5556 + set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
5557 + if (data->enable_pin)
5558 + at32_select_gpio(data->enable_pin,
5559 + AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
5560 + if (data->rdy_pin)
5561 + at32_select_gpio(data->rdy_pin, 0);
5562 + if (data->det_pin)
5563 + at32_select_gpio(data->det_pin, 0);
5564 +
5565 + platform_device_add(pdev);
5566 + return pdev;
5567 +
5568 +fail:
5569 + platform_device_put(pdev);
5570 + return NULL;
5571 +}
5572 +
5573 +/* --------------------------------------------------------------------
5574 * AC97C
5575 * -------------------------------------------------------------------- */
5576 static struct resource atmel_ac97c0_resource[] __initdata = {
5577 @@ -1683,6 +2069,7 @@
5578 &hmatrix_clk,
5579 &ebi_clk,
5580 &hramc_clk,
5581 + &sdramc_clk,
5582 &smc0_pclk,
5583 &smc0_mck,
5584 &pdc_hclk,
5585 @@ -1694,7 +2081,10 @@
5586 &pio2_mck,
5587 &pio3_mck,
5588 &pio4_mck,
5589 - &at32_systc0_pclk,
5590 + &at32_tcb0_t0_clk,
5591 + &at32_tcb1_t0_clk,
5592 + &atmel_psif0_pclk,
5593 + &atmel_psif1_pclk,
5594 &atmel_usart0_usart,
5595 &atmel_usart1_usart,
5596 &atmel_usart2_usart,
5597 @@ -1730,16 +2120,7 @@
5598 };
5599 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
5600
5601 -void __init at32_portmux_init(void)
5602 -{
5603 - at32_init_pio(&pio0_device);
5604 - at32_init_pio(&pio1_device);
5605 - at32_init_pio(&pio2_device);
5606 - at32_init_pio(&pio3_device);
5607 - at32_init_pio(&pio4_device);
5608 -}
5609 -
5610 -void __init at32_clock_init(void)
5611 +void __init setup_platform(void)
5612 {
5613 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
5614 int i;
5615 @@ -1794,4 +2175,36 @@
5616 pm_writel(HSB_MASK, hsb_mask);
5617 pm_writel(PBA_MASK, pba_mask);
5618 pm_writel(PBB_MASK, pbb_mask);
5619 +
5620 + /* Initialize the port muxes */
5621 + at32_init_pio(&pio0_device);
5622 + at32_init_pio(&pio1_device);
5623 + at32_init_pio(&pio2_device);
5624 + at32_init_pio(&pio3_device);
5625 + at32_init_pio(&pio4_device);
5626 +}
5627 +
5628 +struct gen_pool *sram_pool;
5629 +
5630 +static int __init sram_init(void)
5631 +{
5632 + struct gen_pool *pool;
5633 +
5634 + /* 1KiB granularity */
5635 + pool = gen_pool_create(10, -1);
5636 + if (!pool)
5637 + goto fail;
5638 +
5639 + if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
5640 + goto err_pool_add;
5641 +
5642 + sram_pool = pool;
5643 + return 0;
5644 +
5645 +err_pool_add:
5646 + gen_pool_destroy(pool);
5647 +fail:
5648 + pr_err("Failed to create SRAM pool\n");
5649 + return -ENOMEM;
5650 }
5651 +core_initcall(sram_init);
5652 --- a/arch/avr32/mach-at32ap/at32ap.c
5653 +++ /dev/null
5654 @@ -1,56 +0,0 @@
5655 -/*
5656 - * Copyright (C) 2006 Atmel Corporation
5657 - *
5658 - * This program is free software; you can redistribute it and/or modify
5659 - * it under the terms of the GNU General Public License version 2 as
5660 - * published by the Free Software Foundation.
5661 - */
5662 -
5663 -#include <linux/clk.h>
5664 -#include <linux/err.h>
5665 -#include <linux/init.h>
5666 -#include <linux/platform_device.h>
5667 -
5668 -#include <asm/arch/init.h>
5669 -
5670 -void __init setup_platform(void)
5671 -{
5672 - at32_clock_init();
5673 - at32_portmux_init();
5674 -}
5675 -
5676 -static int __init pdc_probe(struct platform_device *pdev)
5677 -{
5678 - struct clk *pclk, *hclk;
5679 -
5680 - pclk = clk_get(&pdev->dev, "pclk");
5681 - if (IS_ERR(pclk)) {
5682 - dev_err(&pdev->dev, "no pclk defined\n");
5683 - return PTR_ERR(pclk);
5684 - }
5685 - hclk = clk_get(&pdev->dev, "hclk");
5686 - if (IS_ERR(hclk)) {
5687 - dev_err(&pdev->dev, "no hclk defined\n");
5688 - clk_put(pclk);
5689 - return PTR_ERR(hclk);
5690 - }
5691 -
5692 - clk_enable(pclk);
5693 - clk_enable(hclk);
5694 -
5695 - dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
5696 - return 0;
5697 -}
5698 -
5699 -static struct platform_driver pdc_driver = {
5700 - .probe = pdc_probe,
5701 - .driver = {
5702 - .name = "pdc",
5703 - },
5704 -};
5705 -
5706 -static int __init pdc_init(void)
5707 -{
5708 - return platform_driver_register(&pdc_driver);
5709 -}
5710 -arch_initcall(pdc_init);
5711 --- a/arch/avr32/mach-at32ap/cpufreq.c
5712 +++ b/arch/avr32/mach-at32ap/cpufreq.c
5713 @@ -108,5 +108,4 @@
5714 {
5715 return cpufreq_register_driver(&at32_driver);
5716 }
5717 -
5718 -arch_initcall(at32_cpufreq_init);
5719 +late_initcall(at32_cpufreq_init);
5720 --- /dev/null
5721 +++ b/arch/avr32/mach-at32ap/gpio-dev.c
5722 @@ -0,0 +1,573 @@
5723 +/*
5724 + * GPIO /dev and configfs interface
5725 + *
5726 + * Copyright (C) 2006-2007 Atmel Corporation
5727 + *
5728 + * This program is free software; you can redistribute it and/or modify
5729 + * it under the terms of the GNU General Public License version 2 as
5730 + * published by the Free Software Foundation.
5731 + */
5732 +#include <linux/kernel.h>
5733 +#include <linux/configfs.h>
5734 +#include <linux/cdev.h>
5735 +#include <linux/device.h>
5736 +#include <linux/fs.h>
5737 +#include <linux/interrupt.h>
5738 +#include <linux/module.h>
5739 +#include <linux/poll.h>
5740 +#include <linux/uaccess.h>
5741 +#include <linux/wait.h>
5742 +
5743 +#include <asm/gpio.h>
5744 +#include <asm/arch/portmux.h>
5745 +
5746 +#define GPIO_DEV_MAX 8
5747 +
5748 +static struct class *gpio_dev_class;
5749 +static dev_t gpio_devt;
5750 +
5751 +struct gpio_item {
5752 + spinlock_t lock;
5753 +
5754 + int enabled;
5755 + int initialized;
5756 + int port;
5757 + u32 pin_mask;
5758 + u32 oe_mask;
5759 +
5760 + /* Pin state last time we read it (for blocking reads) */
5761 + u32 pin_state;
5762 + int changed;
5763 +
5764 + wait_queue_head_t change_wq;
5765 + struct fasync_struct *async_queue;
5766 +
5767 + int id;
5768 + struct class_device *gpio_dev;
5769 + struct cdev char_dev;
5770 + struct config_item item;
5771 +};
5772 +
5773 +struct gpio_attribute {
5774 + struct configfs_attribute attr;
5775 + ssize_t (*show)(struct gpio_item *, char *);
5776 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
5777 +};
5778 +
5779 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
5780 +{
5781 + struct gpio_item *gpio = dev_id;
5782 + u32 old_state, new_state;
5783 +
5784 + old_state = gpio->pin_state;
5785 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
5786 + gpio->pin_state = new_state;
5787 +
5788 + if (new_state != old_state) {
5789 + gpio->changed = 1;
5790 + wake_up_interruptible(&gpio->change_wq);
5791 +
5792 + if (gpio->async_queue)
5793 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
5794 + }
5795 +
5796 + return IRQ_HANDLED;
5797 +}
5798 +
5799 +static int gpio_dev_open(struct inode *inode, struct file *file)
5800 +{
5801 + struct gpio_item *gpio = container_of(inode->i_cdev,
5802 + struct gpio_item,
5803 + char_dev);
5804 + unsigned int irq;
5805 + unsigned int i;
5806 + int ret;
5807 +
5808 + nonseekable_open(inode, file);
5809 + config_item_get(&gpio->item);
5810 + file->private_data = gpio;
5811 +
5812 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
5813 + gpio->pin_mask);
5814 + gpio->changed = 1;
5815 +
5816 + for (i = 0; i < 32; i++) {
5817 + if (gpio->pin_mask & (1 << i)) {
5818 + irq = gpio_to_irq(32 * gpio->port + i);
5819 + ret = request_irq(irq, gpio_dev_interrupt, 0,
5820 + "gpio-dev", gpio);
5821 + if (ret)
5822 + goto err_irq;
5823 + }
5824 + }
5825 +
5826 + return 0;
5827 +
5828 +err_irq:
5829 + while (i--) {
5830 + if (gpio->pin_mask & (1 << i)) {
5831 + irq = gpio_to_irq(32 * gpio->port + i);
5832 + free_irq(irq, gpio);
5833 + }
5834 + }
5835 +
5836 + config_item_put(&gpio->item);
5837 +
5838 + return ret;
5839 +}
5840 +
5841 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
5842 +{
5843 + struct gpio_item *gpio = file->private_data;
5844 +
5845 + return fasync_helper(fd, file, mode, &gpio->async_queue);
5846 +}
5847 +
5848 +static int gpio_dev_release(struct inode *inode, struct file *file)
5849 +{
5850 + struct gpio_item *gpio = file->private_data;
5851 + unsigned int irq;
5852 + unsigned int i;
5853 +
5854 + gpio_dev_fasync(-1, file, 0);
5855 +
5856 + for (i = 0; i < 32; i++) {
5857 + if (gpio->pin_mask & (1 << i)) {
5858 + irq = gpio_to_irq(32 * gpio->port + i);
5859 + free_irq(irq, gpio);
5860 + }
5861 + }
5862 +
5863 + config_item_put(&gpio->item);
5864 +
5865 + return 0;
5866 +}
5867 +
5868 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
5869 +{
5870 + struct gpio_item *gpio = file->private_data;
5871 + unsigned int mask = 0;
5872 +
5873 + poll_wait(file, &gpio->change_wq, wait);
5874 + if (gpio->changed)
5875 + mask |= POLLIN | POLLRDNORM;
5876 +
5877 + return mask;
5878 +}
5879 +
5880 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
5881 + size_t count, loff_t *offset)
5882 +{
5883 + struct gpio_item *gpio = file->private_data;
5884 + u32 value;
5885 +
5886 + spin_lock_irq(&gpio->lock);
5887 + while (!gpio->changed) {
5888 + spin_unlock_irq(&gpio->lock);
5889 +
5890 + if (file->f_flags & O_NONBLOCK)
5891 + return -EAGAIN;
5892 +
5893 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
5894 + return -ERESTARTSYS;
5895 +
5896 + spin_lock_irq(&gpio->lock);
5897 + }
5898 +
5899 + gpio->changed = 0;
5900 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
5901 +
5902 + spin_unlock_irq(&gpio->lock);
5903 +
5904 + count = min(count, (size_t)4);
5905 + if (copy_to_user(buf, &value, count))
5906 + return -EFAULT;
5907 +
5908 + return count;
5909 +}
5910 +
5911 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
5912 + size_t count, loff_t *offset)
5913 +{
5914 + struct gpio_item *gpio = file->private_data;
5915 + u32 value = 0;
5916 + u32 mask = ~0UL;
5917 +
5918 + count = min(count, (size_t)4);
5919 + if (copy_from_user(&value, buf, count))
5920 + return -EFAULT;
5921 +
5922 + /* Assuming big endian */
5923 + mask <<= (4 - count) * 8;
5924 + mask &= gpio->pin_mask;
5925 +
5926 + at32_gpio_set_value_multiple(gpio->port, value, mask);
5927 +
5928 + return count;
5929 +}
5930 +
5931 +static struct file_operations gpio_dev_fops = {
5932 + .owner = THIS_MODULE,
5933 + .llseek = no_llseek,
5934 + .open = gpio_dev_open,
5935 + .release = gpio_dev_release,
5936 + .fasync = gpio_dev_fasync,
5937 + .poll = gpio_dev_poll,
5938 + .read = gpio_dev_read,
5939 + .write = gpio_dev_write,
5940 +};
5941 +
5942 +static struct gpio_item *to_gpio_item(struct config_item *item)
5943 +{
5944 + return item ? container_of(item, struct gpio_item, item) : NULL;
5945 +}
5946 +
5947 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
5948 +{
5949 + return sprintf(page, "%d\n", gpio->port);
5950 +}
5951 +
5952 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
5953 + const char *page, size_t count)
5954 +{
5955 + unsigned long id;
5956 + char *p = (char *)page;
5957 + ssize_t ret = -EINVAL;
5958 +
5959 + id = simple_strtoul(p, &p, 0);
5960 + if (!p || (*p && (*p != '\n')))
5961 + return -EINVAL;
5962 +
5963 + /* Switching PIO is not allowed when live... */
5964 + spin_lock(&gpio->lock);
5965 + if (!gpio->enabled) {
5966 + ret = -ENXIO;
5967 + if (at32_gpio_port_is_valid(id)) {
5968 + gpio->port = id;
5969 + ret = count;
5970 + }
5971 + }
5972 + spin_unlock(&gpio->lock);
5973 +
5974 + return ret;
5975 +}
5976 +
5977 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
5978 +{
5979 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
5980 +}
5981 +
5982 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
5983 + const char *page, size_t count)
5984 +{
5985 + u32 new_mask;
5986 + char *p = (char *)page;
5987 + ssize_t ret = -EINVAL;
5988 +
5989 + new_mask = simple_strtoul(p, &p, 0);
5990 + if (!p || (*p && (*p != '\n')))
5991 + return -EINVAL;
5992 +
5993 + /* Can't update the pin mask while live. */
5994 + spin_lock(&gpio->lock);
5995 + if (!gpio->enabled) {
5996 + gpio->oe_mask &= new_mask;
5997 + gpio->pin_mask = new_mask;
5998 + ret = count;
5999 + }
6000 + spin_unlock(&gpio->lock);
6001 +
6002 + return ret;
6003 +}
6004 +
6005 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
6006 +{
6007 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
6008 +}
6009 +
6010 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
6011 + const char *page, size_t count)
6012 +{
6013 + u32 mask;
6014 + char *p = (char *)page;
6015 + ssize_t ret = -EINVAL;
6016 +
6017 + mask = simple_strtoul(p, &p, 0);
6018 + if (!p || (*p && (*p != '\n')))
6019 + return -EINVAL;
6020 +
6021 + spin_lock(&gpio->lock);
6022 + if (!gpio->enabled) {
6023 + gpio->oe_mask = mask & gpio->pin_mask;
6024 + ret = count;
6025 + }
6026 + spin_unlock(&gpio->lock);
6027 +
6028 + return ret;
6029 +}
6030 +
6031 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
6032 +{
6033 + return sprintf(page, "%d\n", gpio->enabled);
6034 +}
6035 +
6036 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
6037 + const char *page, size_t count)
6038 +{
6039 + char *p = (char *)page;
6040 + int enabled;
6041 + int ret;
6042 +
6043 + enabled = simple_strtoul(p, &p, 0);
6044 + if (!p || (*p && (*p != '\n')))
6045 + return -EINVAL;
6046 +
6047 + /* make it a boolean value */
6048 + enabled = !!enabled;
6049 +
6050 + if (gpio->enabled == enabled)
6051 + /* No change; do nothing. */
6052 + return count;
6053 +
6054 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
6055 +
6056 + if (!enabled) {
6057 + class_device_unregister(gpio->gpio_dev);
6058 + cdev_del(&gpio->char_dev);
6059 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6060 + gpio->initialized = 0;
6061 + } else {
6062 + if (gpio->port < 0 || !gpio->pin_mask)
6063 + return -ENODEV;
6064 + }
6065 +
6066 + /* Disallow any updates to gpio_id or pin_mask */
6067 + spin_lock(&gpio->lock);
6068 + gpio->enabled = enabled;
6069 + spin_unlock(&gpio->lock);
6070 +
6071 + if (!enabled)
6072 + return count;
6073 +
6074 + /* Now, try to allocate the pins */
6075 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
6076 + if (ret)
6077 + goto err_alloc_pins;
6078 +
6079 + gpio->initialized = 1;
6080 +
6081 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
6082 + gpio->char_dev.owner = THIS_MODULE;
6083 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
6084 + if (ret < 0)
6085 + goto err_cdev_add;
6086 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
6087 + MKDEV(MAJOR(gpio_devt), gpio->id),
6088 + NULL,
6089 + "gpio%d", gpio->id);
6090 + if (IS_ERR(gpio->gpio_dev)) {
6091 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
6092 + ret = PTR_ERR(gpio->gpio_dev);
6093 + goto err_class_dev;
6094 + }
6095 +
6096 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
6097 + gpio->id, gpio->port, gpio->pin_mask,
6098 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
6099 +
6100 + return 0;
6101 +
6102 +err_class_dev:
6103 + cdev_del(&gpio->char_dev);
6104 +err_cdev_add:
6105 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6106 + gpio->initialized = 0;
6107 +err_alloc_pins:
6108 + spin_lock(&gpio->lock);
6109 + gpio->enabled = 0;
6110 + spin_unlock(&gpio->lock);
6111 +
6112 + return ret;
6113 +}
6114 +
6115 +static struct gpio_attribute gpio_item_attr_gpio_id = {
6116 + .attr = {
6117 + .ca_owner = THIS_MODULE,
6118 + .ca_name = "gpio_id",
6119 + .ca_mode = S_IRUGO | S_IWUSR,
6120 + },
6121 + .show = gpio_show_gpio_id,
6122 + .store = gpio_store_gpio_id,
6123 +};
6124 +static struct gpio_attribute gpio_item_attr_pin_mask = {
6125 + .attr = {
6126 + .ca_owner = THIS_MODULE,
6127 + .ca_name = "pin_mask",
6128 + .ca_mode = S_IRUGO | S_IWUSR,
6129 + },
6130 + .show = gpio_show_pin_mask,
6131 + .store = gpio_store_pin_mask,
6132 +};
6133 +static struct gpio_attribute gpio_item_attr_oe_mask = {
6134 + .attr = {
6135 + .ca_owner = THIS_MODULE,
6136 + .ca_name = "oe_mask",
6137 + .ca_mode = S_IRUGO | S_IWUSR,
6138 + },
6139 + .show = gpio_show_oe_mask,
6140 + .store = gpio_store_oe_mask,
6141 +};
6142 +static struct gpio_attribute gpio_item_attr_enabled = {
6143 + .attr = {
6144 + .ca_owner = THIS_MODULE,
6145 + .ca_name = "enabled",
6146 + .ca_mode = S_IRUGO | S_IWUSR,
6147 + },
6148 + .show = gpio_show_enabled,
6149 + .store = gpio_store_enabled,
6150 +};
6151 +
6152 +static struct configfs_attribute *gpio_item_attrs[] = {
6153 + &gpio_item_attr_gpio_id.attr,
6154 + &gpio_item_attr_pin_mask.attr,
6155 + &gpio_item_attr_oe_mask.attr,
6156 + &gpio_item_attr_enabled.attr,
6157 + NULL,
6158 +};
6159 +
6160 +static ssize_t gpio_show_attr(struct config_item *item,
6161 + struct configfs_attribute *attr,
6162 + char *page)
6163 +{
6164 + struct gpio_item *gpio_item = to_gpio_item(item);
6165 + struct gpio_attribute *gpio_attr
6166 + = container_of(attr, struct gpio_attribute, attr);
6167 + ssize_t ret = 0;
6168 +
6169 + if (gpio_attr->show)
6170 + ret = gpio_attr->show(gpio_item, page);
6171 + return ret;
6172 +}
6173 +
6174 +static ssize_t gpio_store_attr(struct config_item *item,
6175 + struct configfs_attribute *attr,
6176 + const char *page, size_t count)
6177 +{
6178 + struct gpio_item *gpio_item = to_gpio_item(item);
6179 + struct gpio_attribute *gpio_attr
6180 + = container_of(attr, struct gpio_attribute, attr);
6181 + ssize_t ret = -EINVAL;
6182 +
6183 + if (gpio_attr->store)
6184 + ret = gpio_attr->store(gpio_item, page, count);
6185 + return ret;
6186 +}
6187 +
6188 +static void gpio_release(struct config_item *item)
6189 +{
6190 + kfree(to_gpio_item(item));
6191 +}
6192 +
6193 +static struct configfs_item_operations gpio_item_ops = {
6194 + .release = gpio_release,
6195 + .show_attribute = gpio_show_attr,
6196 + .store_attribute = gpio_store_attr,
6197 +};
6198 +
6199 +static struct config_item_type gpio_item_type = {
6200 + .ct_item_ops = &gpio_item_ops,
6201 + .ct_attrs = gpio_item_attrs,
6202 + .ct_owner = THIS_MODULE,
6203 +};
6204 +
6205 +static struct config_item *gpio_make_item(struct config_group *group,
6206 + const char *name)
6207 +{
6208 + static int next_id;
6209 + struct gpio_item *gpio;
6210 +
6211 + if (next_id >= GPIO_DEV_MAX)
6212 + return NULL;
6213 +
6214 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
6215 + if (!gpio)
6216 + return NULL;
6217 +
6218 + gpio->id = next_id++;
6219 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
6220 + spin_lock_init(&gpio->lock);
6221 + init_waitqueue_head(&gpio->change_wq);
6222 +
6223 + return &gpio->item;
6224 +}
6225 +
6226 +static void gpio_drop_item(struct config_group *group,
6227 + struct config_item *item)
6228 +{
6229 + struct gpio_item *gpio = to_gpio_item(item);
6230 +
6231 + spin_lock(&gpio->lock);
6232 + if (gpio->enabled) {
6233 + class_device_unregister(gpio->gpio_dev);
6234 + cdev_del(&gpio->char_dev);
6235 + }
6236 +
6237 + if (gpio->initialized) {
6238 + at32_deselect_pins(gpio->port, gpio->pin_mask);
6239 + gpio->initialized = 0;
6240 + gpio->enabled = 0;
6241 + }
6242 + spin_unlock(&gpio->lock);
6243 +}
6244 +
6245 +static struct configfs_group_operations gpio_group_ops = {
6246 + .make_item = gpio_make_item,
6247 + .drop_item = gpio_drop_item,
6248 +};
6249 +
6250 +static struct config_item_type gpio_group_type = {
6251 + .ct_group_ops = &gpio_group_ops,
6252 + .ct_owner = THIS_MODULE,
6253 +};
6254 +
6255 +static struct configfs_subsystem gpio_subsys = {
6256 + .su_group = {
6257 + .cg_item = {
6258 + .ci_namebuf = "gpio",
6259 + .ci_type = &gpio_group_type,
6260 + },
6261 + },
6262 +};
6263 +
6264 +static int __init gpio_dev_init(void)
6265 +{
6266 + int err;
6267 +
6268 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
6269 + if (IS_ERR(gpio_dev_class)) {
6270 + err = PTR_ERR(gpio_dev_class);
6271 + goto err_class_create;
6272 + }
6273 +
6274 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
6275 + if (err < 0)
6276 + goto err_alloc_chrdev;
6277 +
6278 + /* Configfs initialization */
6279 + config_group_init(&gpio_subsys.su_group);
6280 + mutex_init(&gpio_subsys.su_mutex);
6281 + err = configfs_register_subsystem(&gpio_subsys);
6282 + if (err)
6283 + goto err_register_subsys;
6284 +
6285 + return 0;
6286 +
6287 +err_register_subsys:
6288 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
6289 +err_alloc_chrdev:
6290 + class_destroy(gpio_dev_class);
6291 +err_class_create:
6292 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
6293 + return err;
6294 +}
6295 +late_initcall(gpio_dev_init);
6296 --- a/arch/avr32/mach-at32ap/hsmc.c
6297 +++ b/arch/avr32/mach-at32ap/hsmc.c
6298 @@ -278,4 +278,4 @@
6299 {
6300 return platform_driver_register(&hsmc_driver);
6301 }
6302 -arch_initcall(hsmc_init);
6303 +core_initcall(hsmc_init);
6304 --- a/arch/avr32/mach-at32ap/intc.c
6305 +++ b/arch/avr32/mach-at32ap/intc.c
6306 @@ -1,5 +1,5 @@
6307 /*
6308 - * Copyright (C) 2006 Atmel Corporation
6309 + * Copyright (C) 2006, 2008 Atmel Corporation
6310 *
6311 * This program is free software; you can redistribute it and/or modify
6312 * it under the terms of the GNU General Public License version 2 as
6313 @@ -12,15 +12,20 @@
6314 #include <linux/interrupt.h>
6315 #include <linux/irq.h>
6316 #include <linux/platform_device.h>
6317 +#include <linux/sysdev.h>
6318
6319 -#include <asm/intc.h>
6320 #include <asm/io.h>
6321
6322 #include "intc.h"
6323
6324 struct intc {
6325 - void __iomem *regs;
6326 - struct irq_chip chip;
6327 + void __iomem *regs;
6328 + struct irq_chip chip;
6329 + struct sys_device sysdev;
6330 +#ifdef CONFIG_PM
6331 + unsigned long suspend_ipr;
6332 + unsigned long saved_ipr[64];
6333 +#endif
6334 };
6335
6336 extern struct platform_device at32_intc0_device;
6337 @@ -137,6 +142,74 @@
6338 panic("Interrupt controller initialization failed!\n");
6339 }
6340
6341 +#ifdef CONFIG_PM
6342 +void intc_set_suspend_handler(unsigned long offset)
6343 +{
6344 + intc0.suspend_ipr = offset;
6345 +}
6346 +
6347 +static int intc_suspend(struct sys_device *sdev, pm_message_t state)
6348 +{
6349 + struct intc *intc = container_of(sdev, struct intc, sysdev);
6350 + int i;
6351 +
6352 + if (unlikely(!irqs_disabled())) {
6353 + pr_err("intc_suspend: called with interrupts enabled\n");
6354 + return -EINVAL;
6355 + }
6356 +
6357 + if (unlikely(!intc->suspend_ipr)) {
6358 + pr_err("intc_suspend: suspend_ipr not initialized\n");
6359 + return -EINVAL;
6360 + }
6361 +
6362 + for (i = 0; i < 64; i++) {
6363 + intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
6364 + intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
6365 + }
6366 +
6367 + return 0;
6368 +}
6369 +
6370 +static int intc_resume(struct sys_device *sdev)
6371 +{
6372 + struct intc *intc = container_of(sdev, struct intc, sysdev);
6373 + int i;
6374 +
6375 + WARN_ON(!irqs_disabled());
6376 +
6377 + for (i = 0; i < 64; i++)
6378 + intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
6379 +
6380 + return 0;
6381 +}
6382 +#else
6383 +#define intc_suspend NULL
6384 +#define intc_resume NULL
6385 +#endif
6386 +
6387 +static struct sysdev_class intc_class = {
6388 + .name = "intc",
6389 + .suspend = intc_suspend,
6390 + .resume = intc_resume,
6391 +};
6392 +
6393 +static int __init intc_init_sysdev(void)
6394 +{
6395 + int ret;
6396 +
6397 + ret = sysdev_class_register(&intc_class);
6398 + if (ret)
6399 + return ret;
6400 +
6401 + intc0.sysdev.id = 0;
6402 + intc0.sysdev.cls = &intc_class;
6403 + ret = sysdev_register(&intc0.sysdev);
6404 +
6405 + return ret;
6406 +}
6407 +device_initcall(intc_init_sysdev);
6408 +
6409 unsigned long intc_get_pending(unsigned int group)
6410 {
6411 return intc_readl(&intc0, INTREQ0 + 4 * group);
6412 --- a/arch/avr32/mach-at32ap/Kconfig
6413 +++ b/arch/avr32/mach-at32ap/Kconfig
6414 @@ -26,6 +26,13 @@
6415
6416 endchoice
6417
6418 +config GPIO_DEV
6419 + bool "GPIO /dev interface"
6420 + select CONFIGFS_FS
6421 + default n
6422 + help
6423 + Say `Y' to enable a /dev interface to the GPIO pins.
6424 +
6425 endmenu
6426
6427 endif # PLATFORM_AT32AP
6428 --- a/arch/avr32/mach-at32ap/Makefile
6429 +++ b/arch/avr32/mach-at32ap/Makefile
6430 @@ -1,4 +1,9 @@
6431 -obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
6432 -obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o
6433 -obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
6434 +obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
6435 +obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
6436 obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
6437 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
6438 +obj-$(CONFIG_PM) += pm.o
6439 +
6440 +ifeq ($(CONFIG_PM_DEBUG),y)
6441 +CFLAGS_pm.o += -DDEBUG
6442 +endif
6443 --- /dev/null
6444 +++ b/arch/avr32/mach-at32ap/pdc.c
6445 @@ -0,0 +1,48 @@
6446 +/*
6447 + * Copyright (C) 2006 Atmel Corporation
6448 + *
6449 + * This program is free software; you can redistribute it and/or modify
6450 + * it under the terms of the GNU General Public License version 2 as
6451 + * published by the Free Software Foundation.
6452 + */
6453 +
6454 +#include <linux/clk.h>
6455 +#include <linux/err.h>
6456 +#include <linux/init.h>
6457 +#include <linux/platform_device.h>
6458 +
6459 +static int __init pdc_probe(struct platform_device *pdev)
6460 +{
6461 + struct clk *pclk, *hclk;
6462 +
6463 + pclk = clk_get(&pdev->dev, "pclk");
6464 + if (IS_ERR(pclk)) {
6465 + dev_err(&pdev->dev, "no pclk defined\n");
6466 + return PTR_ERR(pclk);
6467 + }
6468 + hclk = clk_get(&pdev->dev, "hclk");
6469 + if (IS_ERR(hclk)) {
6470 + dev_err(&pdev->dev, "no hclk defined\n");
6471 + clk_put(pclk);
6472 + return PTR_ERR(hclk);
6473 + }
6474 +
6475 + clk_enable(pclk);
6476 + clk_enable(hclk);
6477 +
6478 + dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
6479 + return 0;
6480 +}
6481 +
6482 +static struct platform_driver pdc_driver = {
6483 + .probe = pdc_probe,
6484 + .driver = {
6485 + .name = "pdc",
6486 + },
6487 +};
6488 +
6489 +static int __init pdc_init(void)
6490 +{
6491 + return platform_driver_register(&pdc_driver);
6492 +}
6493 +arch_initcall(pdc_init);
6494 --- a/arch/avr32/mach-at32ap/pio.c
6495 +++ b/arch/avr32/mach-at32ap/pio.c
6496 @@ -157,6 +157,82 @@
6497 dump_stack();
6498 }
6499
6500 +#ifdef CONFIG_GPIO_DEV
6501 +
6502 +/* Gang allocators and accessors; used by the GPIO /dev driver */
6503 +int at32_gpio_port_is_valid(unsigned int port)
6504 +{
6505 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
6506 +}
6507 +
6508 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
6509 +{
6510 + struct pio_device *pio;
6511 + u32 old, new;
6512 +
6513 + pio = &pio_dev[port];
6514 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
6515 +
6516 + /* Try to allocate the pins */
6517 + do {
6518 + old = pio->pinmux_mask;
6519 + if (old & pins)
6520 + return -EBUSY;
6521 +
6522 + new = old | pins;
6523 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
6524 +
6525 + /* That went well, now configure the port */
6526 + pio_writel(pio, OER, oe_mask);
6527 + pio_writel(pio, PER, pins);
6528 +
6529 + return 0;
6530 +}
6531 +
6532 +void at32_deselect_pins(unsigned int port, u32 pins)
6533 +{
6534 + struct pio_device *pio;
6535 + u32 old, new;
6536 +
6537 + pio = &pio_dev[port];
6538 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6539 +
6540 + /* Return to a "safe" mux configuration */
6541 + pio_writel(pio, PUER, pins);
6542 + pio_writel(pio, ODR, pins);
6543 +
6544 + /* Deallocate the pins */
6545 + do {
6546 + old = pio->pinmux_mask;
6547 + new = old & ~pins;
6548 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
6549 +}
6550 +
6551 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
6552 +{
6553 + struct pio_device *pio;
6554 +
6555 + pio = &pio_dev[port];
6556 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6557 +
6558 + return pio_readl(pio, PDSR) & pins;
6559 +}
6560 +
6561 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
6562 +{
6563 + struct pio_device *pio;
6564 +
6565 + pio = &pio_dev[port];
6566 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
6567 +
6568 + /* No atomic updates for now... */
6569 + pio_writel(pio, CODR, ~value & mask);
6570 + pio_writel(pio, SODR, value & mask);
6571 +}
6572 +
6573 +#endif /* CONFIG_GPIO_DEV */
6574 +
6575 +
6576 /*--------------------------------------------------------------------------*/
6577
6578 /* GPIO API */
6579 @@ -318,6 +394,8 @@
6580 const char *label;
6581
6582 label = gpiochip_is_requested(chip, i);
6583 + if (!label && (imr & mask))
6584 + label = "[irq]";
6585 if (!label)
6586 continue;
6587
6588 --- /dev/null
6589 +++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
6590 @@ -0,0 +1,174 @@
6591 +/*
6592 + * Low-level Power Management code.
6593 + *
6594 + * Copyright (C) 2008 Atmel Corporation
6595 + *
6596 + * This program is free software; you can redistribute it and/or modify
6597 + * it under the terms of the GNU General Public License version 2 as
6598 + * published by the Free Software Foundation.
6599 + */
6600 +#include <asm/asm.h>
6601 +#include <asm/asm-offsets.h>
6602 +#include <asm/thread_info.h>
6603 +#include <asm/arch/pm.h>
6604 +
6605 +#include "pm.h"
6606 +#include "sdramc.h"
6607 +
6608 +/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
6609 +#define PM_BASE -0x100000
6610 +
6611 + .section .bss, "wa", @nobits
6612 + .global disable_idle_sleep
6613 + .type disable_idle_sleep, @object
6614 +disable_idle_sleep:
6615 + .int 4
6616 + .size disable_idle_sleep, . - disable_idle_sleep
6617 +
6618 + /* Keep this close to the irq handlers */
6619 + .section .irq.text, "ax", @progbits
6620 +
6621 + /*
6622 + * void cpu_enter_idle(void)
6623 + *
6624 + * Put the CPU into "idle" mode, in which it will consume
6625 + * significantly less power.
6626 + *
6627 + * If an interrupt comes along in the window between
6628 + * unmask_interrupts and the sleep instruction below, the
6629 + * interrupt code will adjust the return address so that we
6630 + * never execute the sleep instruction. This is required
6631 + * because the AP7000 doesn't unmask interrupts when entering
6632 + * sleep modes; later CPUs may not need this workaround.
6633 + */
6634 + .global cpu_enter_idle
6635 + .type cpu_enter_idle, @function
6636 +cpu_enter_idle:
6637 + mask_interrupts
6638 + get_thread_info r8
6639 + ld.w r9, r8[TI_flags]
6640 + bld r9, TIF_NEED_RESCHED
6641 + brcs .Lret_from_sleep
6642 + sbr r9, TIF_CPU_GOING_TO_SLEEP
6643 + st.w r8[TI_flags], r9
6644 + unmask_interrupts
6645 + sleep CPU_SLEEP_IDLE
6646 + .size cpu_idle_sleep, . - cpu_idle_sleep
6647 +
6648 + /*
6649 + * Common return path for PM functions that don't run from
6650 + * SRAM.
6651 + */
6652 + .global cpu_idle_skip_sleep
6653 + .type cpu_idle_skip_sleep, @function
6654 +cpu_idle_skip_sleep:
6655 + mask_interrupts
6656 + ld.w r9, r8[TI_flags]
6657 + cbr r9, TIF_CPU_GOING_TO_SLEEP
6658 + st.w r8[TI_flags], r9
6659 +.Lret_from_sleep:
6660 + unmask_interrupts
6661 + retal r12
6662 + .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
6663 +
6664 +#ifdef CONFIG_PM
6665 + .section .init.text, "ax", @progbits
6666 +
6667 + .global pm_exception
6668 + .type pm_exception, @function
6669 +pm_exception:
6670 + /*
6671 + * Exceptions are masked when we switch to this handler, so
6672 + * we'll only get "unrecoverable" exceptions (offset 0.)
6673 + */
6674 + sub r12, pc, . - .Lpanic_msg
6675 + lddpc pc, .Lpanic_addr
6676 +
6677 + .align 2
6678 +.Lpanic_addr:
6679 + .long panic
6680 +.Lpanic_msg:
6681 + .asciz "Unrecoverable exception during suspend\n"
6682 + .size pm_exception, . - pm_exception
6683 +
6684 + .global pm_irq0
6685 + .type pm_irq0, @function
6686 +pm_irq0:
6687 + /* Disable interrupts and return after the sleep instruction */
6688 + mfsr r9, SYSREG_RSR_INT0
6689 + mtsr SYSREG_RAR_INT0, r8
6690 + sbr r9, SYSREG_GM_OFFSET
6691 + mtsr SYSREG_RSR_INT0, r9
6692 + rete
6693 +
6694 + /*
6695 + * void cpu_enter_standby(unsigned long sdramc_base)
6696 + *
6697 + * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
6698 + * are suspended and interrupts are disabled. Interrupts
6699 + * marked as 'wakeup' event sources may still come along and
6700 + * get us out of here.
6701 + *
6702 + * The SDRAM will be put into self-refresh mode (which does
6703 + * not require a clock from the CPU), and the CPU will be put
6704 + * into "frozen" mode (HSB bus stopped). The SDRAM controller
6705 + * will automatically bring the SDRAM into normal mode on the
6706 + * first access, and the power manager will automatically
6707 + * start the HSB and CPU clocks upon a wakeup event.
6708 + *
6709 + * This code uses the same "skip sleep" technique as above.
6710 + * It is very important that we jump directly to
6711 + * cpu_after_sleep after the sleep instruction since that's
6712 + * where we'll end up if the interrupt handler decides that we
6713 + * need to skip the sleep instruction.
6714 + */
6715 + .global pm_standby
6716 + .type pm_standby, @function
6717 +pm_standby:
6718 + /*
6719 + * interrupts are already masked at this point, and EVBA
6720 + * points to pm_exception above.
6721 + */
6722 + ld.w r10, r12[SDRAMC_LPR]
6723 + sub r8, pc, . - 1f /* return address for irq handler */
6724 + mov r11, SDRAMC_LPR_LPCB_SELF_RFR
6725 + bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
6726 + sync 0 /* flush write buffer */
6727 + st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */
6728 + ld.w r11, r12[SDRAMC_LPR]
6729 + unmask_interrupts
6730 + sleep CPU_SLEEP_FROZEN
6731 +1: mask_interrupts
6732 + retal r12
6733 + .size pm_standby, . - pm_standby
6734 +
6735 + .global pm_suspend_to_ram
6736 + .type pm_suspend_to_ram, @function
6737 +pm_suspend_to_ram:
6738 + /*
6739 + * interrupts are already masked at this point, and EVBA
6740 + * points to pm_exception above.
6741 + */
6742 + mov r11, 0
6743 + cache r11[2], 8 /* clean all dcache lines */
6744 + sync 0 /* flush write buffer */
6745 + ld.w r10, r12[SDRAMC_LPR]
6746 + sub r8, pc, . - 1f /* return address for irq handler */
6747 + mov r11, SDRAMC_LPR_LPCB_SELF_RFR
6748 + bfins r10, r11, 0, 2 /* LPCB <- self refresh */
6749 + st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
6750 + ld.w r11, r12[SDRAMC_LPR]
6751 +
6752 + unmask_interrupts
6753 + sleep CPU_SLEEP_STOP
6754 +1: mask_interrupts
6755 +
6756 + retal r12
6757 + .size pm_suspend_to_ram, . - pm_suspend_to_ram
6758 +
6759 + .global pm_sram_end
6760 + .type pm_sram_end, @function
6761 +pm_sram_end:
6762 + .size pm_sram_end, 0
6763 +
6764 +#endif /* CONFIG_PM */
6765 --- /dev/null
6766 +++ b/arch/avr32/mach-at32ap/pm.c
6767 @@ -0,0 +1,245 @@
6768 +/*
6769 + * AVR32 AP Power Management
6770 + *
6771 + * Copyright (C) 2008 Atmel Corporation
6772 + *
6773 + * This program is free software; you can redistribute it and/or
6774 + * modify it under the terms of the GNU General Public License
6775 + * version 2 as published by the Free Software Foundation.
6776 + */
6777 +#include <linux/io.h>
6778 +#include <linux/suspend.h>
6779 +#include <linux/vmalloc.h>
6780 +
6781 +#include <asm/cacheflush.h>
6782 +#include <asm/sysreg.h>
6783 +
6784 +#include <asm/arch/pm.h>
6785 +#include <asm/arch/sram.h>
6786 +
6787 +/* FIXME: This is only valid for AP7000 */
6788 +#define SDRAMC_BASE 0xfff03800
6789 +
6790 +#include "sdramc.h"
6791 +
6792 +#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
6793 + | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
6794 +
6795 +
6796 +static unsigned long pm_sram_start;
6797 +static size_t pm_sram_size;
6798 +static struct vm_struct *pm_sram_area;
6799 +
6800 +static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
6801 +static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
6802 +
6803 +/*
6804 + * Must be called with interrupts disabled. Exceptions will be masked
6805 + * on return (i.e. all exceptions will be "unrecoverable".)
6806 + */
6807 +static void *avr32_pm_map_sram(void)
6808 +{
6809 + unsigned long vaddr;
6810 + unsigned long page_addr;
6811 + u32 tlbehi;
6812 + u32 mmucr;
6813 +
6814 + vaddr = (unsigned long)pm_sram_area->addr;
6815 + page_addr = pm_sram_start & PAGE_MASK;
6816 +
6817 + /*
6818 + * Mask exceptions and grab the first TLB entry. We won't be
6819 + * needing it while sleeping.
6820 + */
6821 + asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
6822 +
6823 + mmucr = sysreg_read(MMUCR);
6824 + tlbehi = sysreg_read(TLBEHI);
6825 + sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
6826 +
6827 + tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
6828 + tlbehi |= vaddr & PAGE_MASK;
6829 + tlbehi |= SYSREG_BIT(TLBEHI_V);
6830 +
6831 + sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
6832 + sysreg_write(TLBEHI, tlbehi);
6833 + __builtin_tlbw();
6834 +
6835 + return (void *)(vaddr + pm_sram_start - page_addr);
6836 +}
6837 +
6838 +/*
6839 + * Must be called with interrupts disabled. Exceptions will be
6840 + * unmasked on return.
6841 + */
6842 +static void avr32_pm_unmap_sram(void)
6843 +{
6844 + u32 mmucr;
6845 + u32 tlbehi;
6846 + u32 tlbarlo;
6847 +
6848 + /* Going to update TLB entry at index 0 */
6849 + mmucr = sysreg_read(MMUCR);
6850 + tlbehi = sysreg_read(TLBEHI);
6851 + sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
6852 +
6853 + /* Clear the "valid" bit */
6854 + tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
6855 + sysreg_write(TLBEHI, tlbehi);
6856 +
6857 + /* Mark it as "not accessed" */
6858 + tlbarlo = sysreg_read(TLBARLO);
6859 + sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
6860 +
6861 + /* Update the TLB */
6862 + __builtin_tlbw();
6863 +
6864 + /* Unmask exceptions */
6865 + asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
6866 +}
6867 +
6868 +static int avr32_pm_valid_state(suspend_state_t state)
6869 +{
6870 + switch (state) {
6871 + case PM_SUSPEND_ON:
6872 + case PM_SUSPEND_STANDBY:
6873 + case PM_SUSPEND_MEM:
6874 + return 1;
6875 +
6876 + default:
6877 + return 0;
6878 + }
6879 +}
6880 +
6881 +static int avr32_pm_enter(suspend_state_t state)
6882 +{
6883 + u32 lpr_saved;
6884 + u32 evba_saved;
6885 + void *sram;
6886 +
6887 + switch (state) {
6888 + case PM_SUSPEND_STANDBY:
6889 + sram = avr32_pm_map_sram();
6890 +
6891 + /* Switch to in-sram exception handlers */
6892 + evba_saved = sysreg_read(EVBA);
6893 + sysreg_write(EVBA, (unsigned long)sram);
6894 +
6895 + /*
6896 + * Save the LPR register so that we can re-enable
6897 + * SDRAM Low Power mode on resume.
6898 + */
6899 + lpr_saved = sdramc_readl(LPR);
6900 + pr_debug("%s: Entering standby...\n", __func__);
6901 + avr32_pm_enter_standby(SDRAMC_BASE);
6902 + sdramc_writel(LPR, lpr_saved);
6903 +
6904 + /* Switch back to regular exception handlers */
6905 + sysreg_write(EVBA, evba_saved);
6906 +
6907 + avr32_pm_unmap_sram();
6908 + break;
6909 +
6910 + case PM_SUSPEND_MEM:
6911 + sram = avr32_pm_map_sram();
6912 +
6913 + /* Switch to in-sram exception handlers */
6914 + evba_saved = sysreg_read(EVBA);
6915 + sysreg_write(EVBA, (unsigned long)sram);
6916 +
6917 + /*
6918 + * Save the LPR register so that we can re-enable
6919 + * SDRAM Low Power mode on resume.
6920 + */
6921 + lpr_saved = sdramc_readl(LPR);
6922 + pr_debug("%s: Entering suspend-to-ram...\n", __func__);
6923 + avr32_pm_enter_str(SDRAMC_BASE);
6924 + sdramc_writel(LPR, lpr_saved);
6925 +
6926 + /* Switch back to regular exception handlers */
6927 + sysreg_write(EVBA, evba_saved);
6928 +
6929 + avr32_pm_unmap_sram();
6930 + break;
6931 +
6932 + case PM_SUSPEND_ON:
6933 + pr_debug("%s: Entering idle...\n", __func__);
6934 + cpu_enter_idle();
6935 + break;
6936 +
6937 + default:
6938 + pr_debug("%s: Invalid suspend state %d\n", __func__, state);
6939 + goto out;
6940 + }
6941 +
6942 + pr_debug("%s: wakeup\n", __func__);
6943 +
6944 +out:
6945 + return 0;
6946 +}
6947 +
6948 +static struct platform_suspend_ops avr32_pm_ops = {
6949 + .valid = avr32_pm_valid_state,
6950 + .enter = avr32_pm_enter,
6951 +};
6952 +
6953 +static unsigned long avr32_pm_offset(void *symbol)
6954 +{
6955 + extern u8 pm_exception[];
6956 +
6957 + return (unsigned long)symbol - (unsigned long)pm_exception;
6958 +}
6959 +
6960 +static int __init avr32_pm_init(void)
6961 +{
6962 + extern u8 pm_exception[];
6963 + extern u8 pm_irq0[];
6964 + extern u8 pm_standby[];
6965 + extern u8 pm_suspend_to_ram[];
6966 + extern u8 pm_sram_end[];
6967 + void *dst;
6968 +
6969 + /*
6970 + * To keep things simple, we depend on not needing more than a
6971 + * single page.
6972 + */
6973 + pm_sram_size = avr32_pm_offset(pm_sram_end);
6974 + if (pm_sram_size > PAGE_SIZE)
6975 + goto err;
6976 +
6977 + pm_sram_start = sram_alloc(pm_sram_size);
6978 + if (!pm_sram_start)
6979 + goto err_alloc_sram;
6980 +
6981 + /* Grab a virtual area we can use later on. */
6982 + pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
6983 + if (!pm_sram_area)
6984 + goto err_vm_area;
6985 + pm_sram_area->phys_addr = pm_sram_start;
6986 +
6987 + local_irq_disable();
6988 + dst = avr32_pm_map_sram();
6989 + memcpy(dst, pm_exception, pm_sram_size);
6990 + flush_dcache_region(dst, pm_sram_size);
6991 + invalidate_icache_region(dst, pm_sram_size);
6992 + avr32_pm_unmap_sram();
6993 + local_irq_enable();
6994 +
6995 + avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
6996 + avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
6997 + intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
6998 +
6999 + suspend_set_ops(&avr32_pm_ops);
7000 +
7001 + printk("AVR32 AP Power Management enabled\n");
7002 +
7003 + return 0;
7004 +
7005 +err_vm_area:
7006 + sram_free(pm_sram_start, pm_sram_size);
7007 +err_alloc_sram:
7008 +err:
7009 + pr_err("AVR32 Power Management initialization failed\n");
7010 + return -ENOMEM;
7011 +}
7012 +arch_initcall(avr32_pm_init);
7013 --- /dev/null
7014 +++ b/arch/avr32/mach-at32ap/sdramc.h
7015 @@ -0,0 +1,76 @@
7016 +/*
7017 + * Register definitions for the AT32AP SDRAM Controller
7018 + *
7019 + * Copyright (C) 2008 Atmel Corporation
7020 + *
7021 + * This program is free software; you can redistribute it and/or
7022 + * modify it under the terms of the GNU General Public License
7023 + * version 2 as published by the Free Software Foundation.
7024 + */
7025 +
7026 +/* Register offsets */
7027 +#define SDRAMC_MR 0x0000
7028 +#define SDRAMC_TR 0x0004
7029 +#define SDRAMC_CR 0x0008
7030 +#define SDRAMC_HSR 0x000c
7031 +#define SDRAMC_LPR 0x0010
7032 +#define SDRAMC_IER 0x0014
7033 +#define SDRAMC_IDR 0x0018
7034 +#define SDRAMC_IMR 0x001c
7035 +#define SDRAMC_ISR 0x0020
7036 +#define SDRAMC_MDR 0x0024
7037 +
7038 +/* MR - Mode Register */
7039 +#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
7040 +#define SDRAMC_MR_MODE_NOP ( 1 << 0)
7041 +#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
7042 +#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
7043 +#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
7044 +#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
7045 +#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
7046 +
7047 +/* CR - Configuration Register */
7048 +#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
7049 +#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
7050 +#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
7051 +#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
7052 +#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
7053 +#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
7054 +#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
7055 +#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
7056 +#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
7057 +#define SDRAMC_CR_CAS(x) ((x) << 5)
7058 +#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
7059 +#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
7060 +#define SDRAMC_CR_TWR(x) ((x) << 8)
7061 +#define SDRAMC_CR_TRC(x) ((x) << 12)
7062 +#define SDRAMC_CR_TRP(x) ((x) << 16)
7063 +#define SDRAMC_CR_TRCD(x) ((x) << 20)
7064 +#define SDRAMC_CR_TRAS(x) ((x) << 24)
7065 +#define SDRAMC_CR_TXSR(x) ((x) << 28)
7066 +
7067 +/* HSR - High Speed Register */
7068 +#define SDRAMC_HSR_DA ( 1 << 0)
7069 +
7070 +/* LPR - Low Power Register */
7071 +#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
7072 +#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
7073 +#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
7074 +#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
7075 +#define SDRAMC_LPR_PASR(x) ((x) << 4)
7076 +#define SDRAMC_LPR_TCSR(x) ((x) << 8)
7077 +#define SDRAMC_LPR_DS(x) ((x) << 10)
7078 +#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
7079 +
7080 +/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
7081 +#define SDRAMC_ISR_RES ( 1 << 0)
7082 +
7083 +/* MDR - Memory Device Register */
7084 +#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
7085 +#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
7086 +
7087 +/* Register access macros */
7088 +#define sdramc_readl(reg) \
7089 + __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
7090 +#define sdramc_writel(reg, value) \
7091 + __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
7092 --- a/arch/avr32/mach-at32ap/time-tc.c
7093 +++ /dev/null
7094 @@ -1,218 +0,0 @@
7095 -/*
7096 - * Copyright (C) 2004-2007 Atmel Corporation
7097 - *
7098 - * Based on MIPS implementation arch/mips/kernel/time.c
7099 - * Copyright 2001 MontaVista Software Inc.
7100 - *
7101 - * This program is free software; you can redistribute it and/or modify
7102 - * it under the terms of the GNU General Public License version 2 as
7103 - * published by the Free Software Foundation.
7104 - */
7105 -
7106 -#include <linux/clk.h>
7107 -#include <linux/clocksource.h>
7108 -#include <linux/time.h>
7109 -#include <linux/module.h>
7110 -#include <linux/interrupt.h>
7111 -#include <linux/irq.h>
7112 -#include <linux/kernel_stat.h>
7113 -#include <linux/errno.h>
7114 -#include <linux/init.h>
7115 -#include <linux/profile.h>
7116 -#include <linux/sysdev.h>
7117 -#include <linux/err.h>
7118 -
7119 -#include <asm/div64.h>
7120 -#include <asm/sysreg.h>
7121 -#include <asm/io.h>
7122 -#include <asm/sections.h>
7123 -
7124 -#include <asm/arch/time.h>
7125 -
7126 -/* how many counter cycles in a jiffy? */
7127 -static u32 cycles_per_jiffy;
7128 -
7129 -/* the count value for the next timer interrupt */
7130 -static u32 expirelo;
7131 -
7132 -/* the I/O registers of the TC module */
7133 -static void __iomem *ioregs;
7134 -
7135 -cycle_t read_cycle_count(void)
7136 -{
7137 - return (cycle_t)timer_read(ioregs, 0, CV);
7138 -}
7139 -
7140 -struct clocksource clocksource_avr32 = {
7141 - .name = "avr32",
7142 - .rating = 342,
7143 - .read = read_cycle_count,
7144 - .mask = CLOCKSOURCE_MASK(16),
7145 - .shift = 16,
7146 - .flags = CLOCK_SOURCE_IS_CONTINUOUS,
7147 -};
7148 -
7149 -static void avr32_timer_ack(void)
7150 -{
7151 - u16 count = expirelo;
7152 -
7153 - /* Ack this timer interrupt and set the next one, use a u16
7154 - * variable so it will wrap around correctly */
7155 - count += cycles_per_jiffy;
7156 - expirelo = count;
7157 - timer_write(ioregs, 0, RC, expirelo);
7158 -
7159 - /* Check to see if we have missed any timer interrupts */
7160 - count = timer_read(ioregs, 0, CV);
7161 - if ((count - expirelo) < 0x7fff) {
7162 - expirelo = count + cycles_per_jiffy;
7163 - timer_write(ioregs, 0, RC, expirelo);
7164 - }
7165 -}
7166 -
7167 -u32 avr32_hpt_read(void)
7168 -{
7169 - return timer_read(ioregs, 0, CV);
7170 -}
7171 -
7172 -static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
7173 -{
7174 - unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
7175 - unsigned int divs[] = { 4, 8, 16, 32 };
7176 - int divs_size = ARRAY_SIZE(divs);
7177 - int i = 0;
7178 - unsigned long count_hz;
7179 - unsigned long shift;
7180 - unsigned long mult;
7181 - int clock_div = -1;
7182 - u64 tmp;
7183 -
7184 - shift = clocksource_avr32.shift;
7185 -
7186 - do {
7187 - count_hz = clk_get_rate(pclk) / divs[i];
7188 - mult = clocksource_hz2mult(count_hz, shift);
7189 - clocksource_avr32.mult = mult;
7190 -
7191 - tmp = TICK_NSEC;
7192 - tmp <<= shift;
7193 - tmp += mult / 2;
7194 - do_div(tmp, mult);
7195 -
7196 - cycles_per_jiffy = tmp;
7197 - } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
7198 -
7199 - clock_div = i + 1;
7200 -
7201 - if (clock_div > divs_size) {
7202 - pr_debug("timer: could not calculate clock divider\n");
7203 - return -EFAULT;
7204 - }
7205 -
7206 - /* Set the clock divider */
7207 - timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
7208 -
7209 - return 0;
7210 -}
7211 -
7212 -int avr32_hpt_init(unsigned int count)
7213 -{
7214 - struct resource *regs;
7215 - struct clk *pclk;
7216 - int irq = -1;
7217 - int ret = 0;
7218 -
7219 - ret = -ENXIO;
7220 -
7221 - irq = platform_get_irq(&at32_systc0_device, 0);
7222 - if (irq < 0) {
7223 - pr_debug("timer: could not get irq\n");
7224 - goto out_error;
7225 - }
7226 -
7227 - pclk = clk_get(&at32_systc0_device.dev, "pclk");
7228 - if (IS_ERR(pclk)) {
7229 - pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
7230 - goto out_error;
7231 - }
7232 - clk_enable(pclk);
7233 -
7234 - regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
7235 - if (!regs) {
7236 - pr_debug("timer: could not get resource\n");
7237 - goto out_error_clk;
7238 - }
7239 -
7240 - ioregs = ioremap(regs->start, regs->end - regs->start + 1);
7241 - if (!ioregs) {
7242 - pr_debug("timer: could not get ioregs\n");
7243 - goto out_error_clk;
7244 - }
7245 -
7246 - ret = avr32_timer_calc_div_and_set_jiffies(pclk);
7247 - if (ret)
7248 - goto out_error_io;
7249 -
7250 - ret = setup_irq(irq, &timer_irqaction);
7251 - if (ret) {
7252 - pr_debug("timer: could not request irq %d: %d\n",
7253 - irq, ret);
7254 - goto out_error_io;
7255 - }
7256 -
7257 - expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
7258 - * cycles_per_jiffy;
7259 -
7260 - /* Enable clock and interrupts on RC compare */
7261 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
7262 - timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
7263 - /* Set cycles to first interrupt */
7264 - timer_write(ioregs, 0, RC, expirelo);
7265 -
7266 - printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
7267 - ioregs, irq);
7268 -
7269 - return 0;
7270 -
7271 -out_error_io:
7272 - iounmap(ioregs);
7273 -out_error_clk:
7274 - clk_put(pclk);
7275 -out_error:
7276 - return ret;
7277 -}
7278 -
7279 -int avr32_hpt_start(void)
7280 -{
7281 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
7282 - return 0;
7283 -}
7284 -
7285 -irqreturn_t timer_interrupt(int irq, void *dev_id)
7286 -{
7287 - unsigned int sr = timer_read(ioregs, 0, SR);
7288 -
7289 - if (sr & TIMER_BIT(SR_CPCS)) {
7290 - /* ack timer interrupt and try to set next interrupt */
7291 - avr32_timer_ack();
7292 -
7293 - /*
7294 - * Call the generic timer interrupt handler
7295 - */
7296 - write_seqlock(&xtime_lock);
7297 - do_timer(1);
7298 - write_sequnlock(&xtime_lock);
7299 -
7300 - /*
7301 - * In UP mode, we call local_timer_interrupt() to do profiling
7302 - * and process accounting.
7303 - *
7304 - * SMP is not supported yet.
7305 - */
7306 - local_timer_interrupt(irq, dev_id);
7307 -
7308 - return IRQ_HANDLED;
7309 - }
7310 -
7311 - return IRQ_NONE;
7312 -}
7313 --- a/arch/avr32/Makefile
7314 +++ b/arch/avr32/Makefile
7315 @@ -32,6 +32,7 @@
7316 core-y += arch/avr32/kernel/
7317 core-y += arch/avr32/mm/
7318 drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
7319 +drivers-y += arch/avr32/drivers/
7320 libs-y += arch/avr32/lib/
7321
7322 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
7323 --- a/arch/avr32/mm/init.c
7324 +++ b/arch/avr32/mm/init.c
7325 @@ -11,6 +11,7 @@
7326 #include <linux/swap.h>
7327 #include <linux/init.h>
7328 #include <linux/mmzone.h>
7329 +#include <linux/module.h>
7330 #include <linux/bootmem.h>
7331 #include <linux/pagemap.h>
7332 #include <linux/nodemask.h>
7333 @@ -28,15 +29,13 @@
7334 pgd_t swapper_pg_dir[PTRS_PER_PGD];
7335
7336 struct page *empty_zero_page;
7337 +EXPORT_SYMBOL(empty_zero_page);
7338
7339 /*
7340 * Cache of MMU context last used.
7341 */
7342 unsigned long mmu_context_cache = NO_CONTEXT;
7343
7344 -#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
7345 -#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
7346 -
7347 void show_mem(void)
7348 {
7349 int total = 0, reserved = 0, cached = 0;
7350 --- a/arch/avr32/oprofile/op_model_avr32.c
7351 +++ b/arch/avr32/oprofile/op_model_avr32.c
7352 @@ -16,7 +16,6 @@
7353 #include <linux/sched.h>
7354 #include <linux/types.h>
7355
7356 -#include <asm/intc.h>
7357 #include <asm/sysreg.h>
7358 #include <asm/system.h>
7359
7360 --- a/drivers/char/Kconfig
7361 +++ b/drivers/char/Kconfig
7362 @@ -706,7 +706,7 @@
7363
7364 config RTC
7365 tristate "Enhanced Real Time Clock Support"
7366 - depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390
7367 + depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 && !AVR32
7368 ---help---
7369 If you say Y here and create a character special file /dev/rtc with
7370 major number 10 and minor number 135 using mknod ("man mknod"), you
7371 @@ -776,7 +776,7 @@
7372
7373 config GEN_RTC
7374 tristate "Generic /dev/rtc emulation"
7375 - depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH
7376 + depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32
7377 ---help---
7378 If you say Y here and create a character special file /dev/rtc with
7379 major number 10 and minor number 135 using mknod ("man mknod"), you
7380 --- a/drivers/char/keyboard.c
7381 +++ b/drivers/char/keyboard.c
7382 @@ -1033,7 +1033,8 @@
7383 #if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\
7384 defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
7385 defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
7386 - (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
7387 + (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) ||\
7388 + defined(CONFIG_AVR32)
7389
7390 #define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\
7391 ((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001))
7392 --- a/drivers/clocksource/Makefile
7393 +++ b/drivers/clocksource/Makefile
7394 @@ -1,3 +1,4 @@
7395 +obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
7396 obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
7397 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
7398 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
7399 --- /dev/null
7400 +++ b/drivers/clocksource/tcb_clksrc.c
7401 @@ -0,0 +1,302 @@
7402 +#include <linux/init.h>
7403 +#include <linux/clocksource.h>
7404 +#include <linux/clockchips.h>
7405 +#include <linux/interrupt.h>
7406 +#include <linux/irq.h>
7407 +
7408 +#include <linux/clk.h>
7409 +#include <linux/err.h>
7410 +#include <linux/ioport.h>
7411 +#include <linux/io.h>
7412 +#include <linux/platform_device.h>
7413 +#include <linux/atmel_tc.h>
7414 +
7415 +
7416 +/*
7417 + * We're configured to use a specific TC block, one that's not hooked
7418 + * up to external hardware, to provide a time solution:
7419 + *
7420 + * - Two channels combine to create a free-running 32 bit counter
7421 + * with a base rate of 5+ MHz, packaged as a clocksource (with
7422 + * resolution better than 200 nsec).
7423 + *
7424 + * - The third channel may be used to provide a 16-bit clockevent
7425 + * source, used in either periodic or oneshot mode. This runs
7426 + * at 32 KiHZ, and can handle delays of up to two seconds.
7427 + *
7428 + * A boot clocksource and clockevent source are also currently needed,
7429 + * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
7430 + * this code can be used when init_timers() is called, well before most
7431 + * devices are set up. (Some low end AT91 parts, which can run uClinux,
7432 + * have only the timers in one TC block... they currently don't support
7433 + * the tclib code, because of that initialization issue.)
7434 + *
7435 + * REVISIT behavior during system suspend states... we should disable
7436 + * all clocks and save the power. Easily done for clockevent devices,
7437 + * but clocksources won't necessarily get the needed notifications.
7438 + * For deeper system sleep states, this will be mandatory...
7439 + */
7440 +
7441 +static void __iomem *tcaddr;
7442 +
7443 +static cycle_t tc_get_cycles(void)
7444 +{
7445 + unsigned long flags;
7446 + u32 lower, upper;
7447 +
7448 + raw_local_irq_save(flags);
7449 + do {
7450 + upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
7451 + lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
7452 + } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
7453 +
7454 + raw_local_irq_restore(flags);
7455 + return (upper << 16) | lower;
7456 +}
7457 +
7458 +static struct clocksource clksrc = {
7459 + .name = "tcb_clksrc",
7460 + .rating = 200,
7461 + .read = tc_get_cycles,
7462 + .mask = CLOCKSOURCE_MASK(32),
7463 + .shift = 18,
7464 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
7465 +};
7466 +
7467 +#ifdef CONFIG_GENERIC_CLOCKEVENTS
7468 +
7469 +struct tc_clkevt_device {
7470 + struct clock_event_device clkevt;
7471 + struct clk *clk;
7472 + void __iomem *regs;
7473 +};
7474 +
7475 +static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
7476 +{
7477 + return container_of(clkevt, struct tc_clkevt_device, clkevt);
7478 +}
7479 +
7480 +/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
7481 + * because using one of the divided clocks would usually mean the
7482 + * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
7483 + *
7484 + * A divided clock could be good for high resolution timers, since
7485 + * 30.5 usec resolution can seem "low".
7486 + */
7487 +static u32 timer_clock;
7488 +
7489 +static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
7490 +{
7491 + struct tc_clkevt_device *tcd = to_tc_clkevt(d);
7492 + void __iomem *regs = tcd->regs;
7493 +
7494 + if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
7495 + || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
7496 + __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
7497 + __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
7498 + clk_disable(tcd->clk);
7499 + }
7500 +
7501 + switch (m) {
7502 +
7503 + /* By not making the gentime core emulate periodic mode on top
7504 + * of oneshot, we get lower overhead and improved accuracy.
7505 + */
7506 + case CLOCK_EVT_MODE_PERIODIC:
7507 + clk_enable(tcd->clk);
7508 +
7509 + /* slow clock, count up to RC, then irq and restart */
7510 + __raw_writel(timer_clock
7511 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
7512 + regs + ATMEL_TC_REG(2, CMR));
7513 + __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
7514 +
7515 + /* Enable clock and interrupts on RC compare */
7516 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
7517 +
7518 + /* go go gadget! */
7519 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
7520 + regs + ATMEL_TC_REG(2, CCR));
7521 + break;
7522 +
7523 + case CLOCK_EVT_MODE_ONESHOT:
7524 + clk_enable(tcd->clk);
7525 +
7526 + /* slow clock, count up to RC, then irq and stop */
7527 + __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
7528 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
7529 + regs + ATMEL_TC_REG(2, CMR));
7530 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
7531 +
7532 + /* set_next_event() configures and starts the timer */
7533 + break;
7534 +
7535 + default:
7536 + break;
7537 + }
7538 +}
7539 +
7540 +static int tc_next_event(unsigned long delta, struct clock_event_device *d)
7541 +{
7542 + __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
7543 +
7544 + /* go go gadget! */
7545 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
7546 + tcaddr + ATMEL_TC_REG(2, CCR));
7547 + return 0;
7548 +}
7549 +
7550 +static struct tc_clkevt_device clkevt = {
7551 + .clkevt = {
7552 + .name = "tc_clkevt",
7553 + .features = CLOCK_EVT_FEAT_PERIODIC
7554 + | CLOCK_EVT_FEAT_ONESHOT,
7555 + .shift = 32,
7556 + /* Should be lower than at91rm9200's system timer */
7557 + .rating = 125,
7558 + .cpumask = CPU_MASK_CPU0,
7559 + .set_next_event = tc_next_event,
7560 + .set_mode = tc_mode,
7561 + },
7562 +};
7563 +
7564 +static irqreturn_t ch2_irq(int irq, void *handle)
7565 +{
7566 + struct tc_clkevt_device *dev = handle;
7567 + unsigned int sr;
7568 +
7569 + sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
7570 + if (sr & ATMEL_TC_CPCS) {
7571 + dev->clkevt.event_handler(&dev->clkevt);
7572 + return IRQ_HANDLED;
7573 + }
7574 +
7575 + return IRQ_NONE;
7576 +}
7577 +
7578 +static struct irqaction tc_irqaction = {
7579 + .name = "tc_clkevt",
7580 + .flags = IRQF_TIMER | IRQF_DISABLED,
7581 + .handler = ch2_irq,
7582 +};
7583 +
7584 +static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
7585 +{
7586 + struct clk *t2_clk = tc->clk[2];
7587 + int irq = tc->irq[2];
7588 +
7589 + clkevt.regs = tc->regs;
7590 + clkevt.clk = t2_clk;
7591 + tc_irqaction.dev_id = &clkevt;
7592 +
7593 + timer_clock = clk32k_divisor_idx;
7594 +
7595 + clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
7596 + clkevt.clkevt.max_delta_ns
7597 + = clockevent_delta2ns(0xffff, &clkevt.clkevt);
7598 + clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
7599 +
7600 + setup_irq(irq, &tc_irqaction);
7601 +
7602 + clockevents_register_device(&clkevt.clkevt);
7603 +}
7604 +
7605 +#else /* !CONFIG_GENERIC_CLOCKEVENTS */
7606 +
7607 +static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
7608 +{
7609 + /* NOTHING */
7610 +}
7611 +
7612 +#endif
7613 +
7614 +static int __init tcb_clksrc_init(void)
7615 +{
7616 + static char bootinfo[] __initdata
7617 + = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
7618 +
7619 + struct platform_device *pdev;
7620 + struct atmel_tc *tc;
7621 + struct clk *t0_clk;
7622 + u32 rate, divided_rate = 0;
7623 + int best_divisor_idx = -1;
7624 + int clk32k_divisor_idx = -1;
7625 + int i;
7626 +
7627 + tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
7628 + if (!tc) {
7629 + pr_debug("can't alloc TC for clocksource\n");
7630 + return -ENODEV;
7631 + }
7632 + tcaddr = tc->regs;
7633 + pdev = tc->pdev;
7634 +
7635 + t0_clk = tc->clk[0];
7636 + clk_enable(t0_clk);
7637 +
7638 + /* How fast will we be counting? Pick something over 5 MHz. */
7639 + rate = (u32) clk_get_rate(t0_clk);
7640 + for (i = 0; i < 5; i++) {
7641 + unsigned divisor = atmel_tc_divisors[i];
7642 + unsigned tmp;
7643 +
7644 + /* remember 32 KiHz clock for later */
7645 + if (!divisor) {
7646 + clk32k_divisor_idx = i;
7647 + continue;
7648 + }
7649 +
7650 + tmp = rate / divisor;
7651 + pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
7652 + if (best_divisor_idx > 0) {
7653 + if (tmp < 5 * 1000 * 1000)
7654 + continue;
7655 + }
7656 + divided_rate = tmp;
7657 + best_divisor_idx = i;
7658 + }
7659 +
7660 + clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
7661 +
7662 + printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
7663 + divided_rate / 1000000,
7664 + ((divided_rate + 500000) % 1000000) / 1000);
7665 +
7666 + /* tclib will give us three clocks no matter what the
7667 + * underlying platform supports.
7668 + */
7669 + clk_enable(tc->clk[1]);
7670 +
7671 + /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
7672 + __raw_writel(best_divisor_idx /* likely divide-by-8 */
7673 + | ATMEL_TC_WAVE
7674 + | ATMEL_TC_WAVESEL_UP /* free-run */
7675 + | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
7676 + | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
7677 + tcaddr + ATMEL_TC_REG(0, CMR));
7678 + __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
7679 + __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
7680 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
7681 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
7682 +
7683 + /* channel 1: waveform mode, input TIOA0 */
7684 + __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
7685 + | ATMEL_TC_WAVE
7686 + | ATMEL_TC_WAVESEL_UP, /* free-run */
7687 + tcaddr + ATMEL_TC_REG(1, CMR));
7688 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
7689 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
7690 +
7691 + /* chain channel 0 to channel 1, then reset all the timers */
7692 + __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
7693 + __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
7694 +
7695 + /* and away we go! */
7696 + clocksource_register(&clksrc);
7697 +
7698 + /* channel 2: periodic and oneshot timer support */
7699 + setup_clkevents(tc, clk32k_divisor_idx);
7700 +
7701 + return 0;
7702 +}
7703 +arch_initcall(tcb_clksrc_init);
7704 --- /dev/null
7705 +++ b/drivers/i2c/busses/i2c-atmeltwi.c
7706 @@ -0,0 +1,436 @@
7707 +/*
7708 + * i2c Support for Atmel's Two-Wire Interface (TWI)
7709 + *
7710 + * Based on the work of Copyright (C) 2004 Rick Bronson
7711 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
7712 + * Ported to AVR32 and heavily modified by Espen Krangnes
7713 + * <ekrangnes at atmel.com>
7714 + *
7715 + * Copyright (C) 2006 Atmel Corporation
7716 + *
7717 + * Borrowed heavily from the original work by:
7718 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
7719 + *
7720 + * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
7721 + * bugs removed, interrupt routine markedly rewritten
7722 + *
7723 + * This program is free software; you can redistribute it and/or modify
7724 + * it under the terms of the GNU General Public License as published by
7725 + * the Free Software Foundation; either version 2 of the License, or
7726 + * (at your option) any later version.
7727 + */
7728 +#undef VERBOSE_DEBUG
7729 +
7730 +#include <linux/module.h>
7731 +#include <linux/slab.h>
7732 +#include <linux/i2c.h>
7733 +#include <linux/init.h>
7734 +#include <linux/clk.h>
7735 +#include <linux/err.h>
7736 +#include <linux/interrupt.h>
7737 +#include <linux/platform_device.h>
7738 +#include <linux/completion.h>
7739 +#include <linux/io.h>
7740 +
7741 +#include "i2c-atmeltwi.h"
7742 +
7743 +static unsigned int baudrate = 100 * 1000;
7744 +module_param(baudrate, uint, S_IRUGO);
7745 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
7746 +
7747 +
7748 +struct atmel_twi {
7749 + void __iomem *regs;
7750 + struct i2c_adapter adapter;
7751 + struct clk *pclk;
7752 + struct completion comp;
7753 + u32 mask;
7754 + u8 *buf;
7755 + u16 len;
7756 + u16 acks_left;
7757 + int status;
7758 + unsigned int irq;
7759 +
7760 +};
7761 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
7762 +
7763 +/*
7764 + * (Re)Initialize the TWI hardware registers.
7765 + */
7766 +static int twi_hwinit(struct atmel_twi *twi)
7767 +{
7768 + unsigned long cdiv, ckdiv = 0;
7769 +
7770 + /* REVISIT: wait till SCL is high before resetting; otherwise,
7771 + * some versions will wedge forever.
7772 + */
7773 +
7774 + twi_writel(twi, IDR, ~0UL);
7775 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
7776 + twi_readl(twi, SR);
7777 +
7778 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
7779 +
7780 + while (cdiv > 255) {
7781 + ckdiv++;
7782 + cdiv = cdiv >> 1;
7783 + }
7784 +
7785 + /* REVISIT: there are various errata to consider re CDIV and CHDIV
7786 + * here, at least on at91 parts.
7787 + */
7788 +
7789 + if (ckdiv > 7)
7790 + return -EINVAL;
7791 + else
7792 + twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
7793 + | TWI_BF(CHDIV, cdiv)
7794 + | TWI_BF(CLDIV, cdiv));
7795 + return 0;
7796 +}
7797 +
7798 +/*
7799 + * Waits for the i2c status register to set the specified bitmask
7800 + * Returns 0 if timed out ... ~100ms is much longer than the SMBus
7801 + * limit, but I2C has no limit at all.
7802 + */
7803 +static int twi_complete(struct atmel_twi *twi, u32 mask)
7804 +{
7805 + int timeout = msecs_to_jiffies(100);
7806 +
7807 + mask |= TWI_BIT(TXCOMP);
7808 + twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
7809 + init_completion(&twi->comp);
7810 +
7811 + twi_writel(twi, IER, mask);
7812 +
7813 + if (!wait_for_completion_timeout(&twi->comp, timeout)) {
7814 + /* RESET TWI interface */
7815 + twi_writel(twi, CR, TWI_BIT(SWRST));
7816 +
7817 + /* Reinitialize TWI */
7818 + twi_hwinit(twi);
7819 +
7820 + return -ETIMEDOUT;
7821 + }
7822 + return 0;
7823 +}
7824 +
7825 +/*
7826 + * Generic i2c master transfer entrypoint.
7827 + */
7828 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
7829 +{
7830 + struct atmel_twi *twi = to_atmel_twi(adap);
7831 + int i;
7832 +
7833 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
7834 +
7835 + twi->status = 0;
7836 + for (i = 0; i < num; i++, pmsg++) {
7837 + twi->len = pmsg->len;
7838 + twi->buf = pmsg->buf;
7839 + twi->acks_left = pmsg->len;
7840 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
7841 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
7842 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
7843 +
7844 + dev_dbg(&adap->dev,
7845 + "#%d: %s %d byte%s %s dev 0x%02x\n",
7846 + i,
7847 + pmsg->flags & I2C_M_RD ? "reading" : "writing",
7848 + pmsg->len,
7849 + pmsg->len > 1 ? "s" : "",
7850 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
7851 +
7852 + /* enable */
7853 + twi_writel(twi, CR, TWI_BIT(MSEN));
7854 +
7855 + if (pmsg->flags & I2C_M_RD) {
7856 + /* cleanup after previous RX overruns */
7857 + while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
7858 + twi_readl(twi, RHR);
7859 +
7860 + if (twi->len == 1)
7861 + twi_writel(twi, CR,
7862 + TWI_BIT(START) | TWI_BIT(STOP));
7863 + else
7864 + twi_writel(twi, CR, TWI_BIT(START));
7865 +
7866 + if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
7867 + dev_dbg(&adap->dev, "RX[%d] timeout. "
7868 + "Stopped with %d bytes left\n",
7869 + i, twi->acks_left);
7870 + return -ETIMEDOUT;
7871 + }
7872 + } else {
7873 + twi_writel(twi, THR, twi->buf[0]);
7874 + twi->acks_left--;
7875 + /* REVISIT: some chips don't start automagically:
7876 + * twi_writel(twi, CR, TWI_BIT(START));
7877 + */
7878 + if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
7879 + dev_dbg(&adap->dev, "TX[%d] timeout. "
7880 + "Stopped with %d bytes left\n",
7881 + i, twi->acks_left);
7882 + return -ETIMEDOUT;
7883 + }
7884 + /* REVISIT: an erratum workaround may be needed here;
7885 + * see sam9261 "STOP not generated" (START either).
7886 + */
7887 + }
7888 +
7889 + /* Disable TWI interface */
7890 + twi_writel(twi, CR, TWI_BIT(MSDIS));
7891 +
7892 + if (twi->status)
7893 + return twi->status;
7894 +
7895 + /* WARNING: This driver lies about properly supporting
7896 + * repeated start, or it would *ALWAYS* return here. It
7897 + * has issued a STOP. Continuing is a false claim -- that
7898 + * a second (or third, etc.) message is part of the same
7899 + * "combined" (no STOPs between parts) message.
7900 + */
7901 +
7902 + } /* end cur msg */
7903 +
7904 + return i;
7905 +}
7906 +
7907 +
7908 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
7909 +{
7910 + struct atmel_twi *twi = dev_id;
7911 + int status = twi_readl(twi, SR);
7912 +
7913 + /* Save state for later debug prints */
7914 + int old_status = status;
7915 +
7916 + if (twi->mask & status) {
7917 +
7918 + status &= twi->mask;
7919 +
7920 + if (status & TWI_BIT(RXRDY)) {
7921 + if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
7922 + /* Note weakness in fault reporting model:
7923 + * we can't say "the first N of these data
7924 + * bytes are valid".
7925 + */
7926 + dev_err(&twi->adapter.dev,
7927 + "OVERRUN RX! %04x, lost %d\n",
7928 + old_status, twi->acks_left);
7929 + twi->acks_left = 0;
7930 + twi_writel(twi, CR, TWI_BIT(STOP));
7931 + twi->status = -EOVERFLOW;
7932 + } else if (twi->acks_left > 0) {
7933 + twi->buf[twi->len - twi->acks_left] =
7934 + twi_readl(twi, RHR);
7935 + twi->acks_left--;
7936 + }
7937 + if (status & TWI_BIT(TXCOMP))
7938 + goto done;
7939 + if (twi->acks_left == 1)
7940 + twi_writel(twi, CR, TWI_BIT(STOP));
7941 +
7942 + } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
7943 + goto done;
7944 +
7945 + } else if (status & TWI_BIT(TXRDY)) {
7946 + if (twi->acks_left > 0) {
7947 + twi_writel(twi, THR,
7948 + twi->buf[twi->len - twi->acks_left]);
7949 + twi->acks_left--;
7950 + } else
7951 + twi_writel(twi, CR, TWI_BIT(STOP));
7952 + }
7953 +
7954 + if (twi->acks_left == 0)
7955 + twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
7956 + }
7957 +
7958 + /* enabling this message helps trigger overruns/underruns ... */
7959 + dev_vdbg(&twi->adapter.dev,
7960 + "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
7961 + old_status,
7962 + twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
7963 + twi->acks_left);
7964 +
7965 + return IRQ_HANDLED;
7966 +
7967 +done:
7968 + /* Note weak fault reporting model: we can't report how many
7969 + * bytes we sent before the NAK, or let upper layers choose
7970 + * whether to continue. The I2C stack doesn't allow that...
7971 + */
7972 + if (status & TWI_BIT(NACK)) {
7973 + dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
7974 + twi->acks_left);
7975 + twi->status = -EPIPE;
7976 +
7977 + /* TX underrun morphs automagically into a premature STOP;
7978 + * we'll probably observe UVRE even when it's not documented.
7979 + */
7980 + } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
7981 + dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
7982 + old_status, twi->acks_left);
7983 + twi->status = -ENOSR;
7984 + }
7985 +
7986 + twi_writel(twi, IDR, ~0UL);
7987 + complete(&twi->comp);
7988 +
7989 + dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
7990 + old_status, twi->acks_left, twi->status);
7991 +
7992 + return IRQ_HANDLED;
7993 +}
7994 +
7995 +
7996 +/*
7997 + * Return list of supported functionality.
7998 + *
7999 + * NOTE: see warning above about repeated starts; this driver is falsely
8000 + * claiming to support "combined" transfers. The mid-message STOPs mean
8001 + * some slaves will never work with this driver. (Use i2c-gpio...)
8002 + */
8003 +static u32 twi_func(struct i2c_adapter *adapter)
8004 +{
8005 + return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
8006 + & ~I2C_FUNC_SMBUS_QUICK;
8007 +}
8008 +
8009 +static struct i2c_algorithm twi_algorithm = {
8010 + .master_xfer = twi_xfer,
8011 + .functionality = twi_func,
8012 +};
8013 +
8014 +/*
8015 + * Main initialization routine.
8016 + */
8017 +static int __init twi_probe(struct platform_device *pdev)
8018 +{
8019 + struct atmel_twi *twi;
8020 + struct resource *regs;
8021 + struct clk *pclk;
8022 + struct i2c_adapter *adapter;
8023 + int rc, irq;
8024 +
8025 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8026 + if (!regs)
8027 + return -ENXIO;
8028 +
8029 + pclk = clk_get(&pdev->dev, "twi_pclk");
8030 + if (IS_ERR(pclk))
8031 + return PTR_ERR(pclk);
8032 + clk_enable(pclk);
8033 +
8034 + rc = -ENOMEM;
8035 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
8036 + if (!twi) {
8037 + dev_dbg(&pdev->dev, "can't allocate interface!\n");
8038 + goto err_alloc_twi;
8039 + }
8040 +
8041 + twi->pclk = pclk;
8042 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
8043 + if (!twi->regs)
8044 + goto err_ioremap;
8045 +
8046 + irq = platform_get_irq(pdev, 0);
8047 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
8048 + if (rc) {
8049 + dev_dbg(&pdev->dev, "can't bind irq!\n");
8050 + goto err_irq;
8051 + }
8052 + twi->irq = irq;
8053 +
8054 + rc = twi_hwinit(twi);
8055 + if (rc) {
8056 + dev_err(&pdev->dev, "Unable to set baudrate\n");
8057 + goto err_hw_init;
8058 + }
8059 +
8060 + adapter = &twi->adapter;
8061 + sprintf(adapter->name, "TWI");
8062 + adapter->algo = &twi_algorithm;
8063 + adapter->class = I2C_CLASS_ALL;
8064 + adapter->nr = pdev->id;
8065 + adapter->dev.parent = &pdev->dev;
8066 +
8067 + platform_set_drvdata(pdev, twi);
8068 +
8069 + rc = i2c_add_numbered_adapter(adapter);
8070 + if (rc) {
8071 + dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
8072 + adapter->name);
8073 + goto err_register;
8074 + }
8075 +
8076 + dev_info(&pdev->dev,
8077 + "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
8078 + baudrate/1000, (unsigned long)regs->start);
8079 +
8080 + return 0;
8081 +
8082 +
8083 +err_register:
8084 + platform_set_drvdata(pdev, NULL);
8085 +
8086 +err_hw_init:
8087 + free_irq(irq, twi);
8088 +
8089 +err_irq:
8090 + iounmap(twi->regs);
8091 +
8092 +err_ioremap:
8093 + kfree(twi);
8094 +
8095 +err_alloc_twi:
8096 + clk_disable(pclk);
8097 + clk_put(pclk);
8098 +
8099 + return rc;
8100 +}
8101 +
8102 +static int __exit twi_remove(struct platform_device *pdev)
8103 +{
8104 + struct atmel_twi *twi = platform_get_drvdata(pdev);
8105 + int res;
8106 +
8107 + platform_set_drvdata(pdev, NULL);
8108 + res = i2c_del_adapter(&twi->adapter);
8109 + twi_writel(twi, CR, TWI_BIT(MSDIS));
8110 + iounmap(twi->regs);
8111 + clk_disable(twi->pclk);
8112 + clk_put(twi->pclk);
8113 + free_irq(twi->irq, twi);
8114 + kfree(twi);
8115 +
8116 + return res;
8117 +}
8118 +
8119 +static struct platform_driver twi_driver = {
8120 + .remove = __exit_p(twi_remove),
8121 + .driver = {
8122 + .name = "atmel_twi",
8123 + .owner = THIS_MODULE,
8124 + },
8125 +};
8126 +
8127 +static int __init atmel_twi_init(void)
8128 +{
8129 + return platform_driver_probe(&twi_driver, twi_probe);
8130 +}
8131 +
8132 +static void __exit atmel_twi_exit(void)
8133 +{
8134 + platform_driver_unregister(&twi_driver);
8135 +}
8136 +
8137 +module_init(atmel_twi_init);
8138 +module_exit(atmel_twi_exit);
8139 +
8140 +MODULE_AUTHOR("Espen Krangnes");
8141 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
8142 +MODULE_LICENSE("GPL");
8143 --- /dev/null
8144 +++ b/drivers/i2c/busses/i2c-atmeltwi.h
8145 @@ -0,0 +1,117 @@
8146 +/*
8147 + * Register definitions for the Atmel Two-Wire Interface
8148 + */
8149 +
8150 +#ifndef __ATMELTWI_H__
8151 +#define __ATMELTWI_H__
8152 +
8153 +/* TWI register offsets */
8154 +#define TWI_CR 0x0000
8155 +#define TWI_MMR 0x0004
8156 +#define TWI_SMR 0x0008
8157 +#define TWI_IADR 0x000c
8158 +#define TWI_CWGR 0x0010
8159 +#define TWI_SR 0x0020
8160 +#define TWI_IER 0x0024
8161 +#define TWI_IDR 0x0028
8162 +#define TWI_IMR 0x002c
8163 +#define TWI_RHR 0x0030
8164 +#define TWI_THR 0x0034
8165 +
8166 +/* Bitfields in CR */
8167 +#define TWI_START_OFFSET 0
8168 +#define TWI_START_SIZE 1
8169 +#define TWI_STOP_OFFSET 1
8170 +#define TWI_STOP_SIZE 1
8171 +#define TWI_MSEN_OFFSET 2
8172 +#define TWI_MSEN_SIZE 1
8173 +#define TWI_MSDIS_OFFSET 3
8174 +#define TWI_MSDIS_SIZE 1
8175 +#define TWI_SVEN_OFFSET 4
8176 +#define TWI_SVEN_SIZE 1
8177 +#define TWI_SVDIS_OFFSET 5
8178 +#define TWI_SVDIS_SIZE 1
8179 +#define TWI_SWRST_OFFSET 7
8180 +#define TWI_SWRST_SIZE 1
8181 +
8182 +/* Bitfields in MMR */
8183 +#define TWI_IADRSZ_OFFSET 8
8184 +#define TWI_IADRSZ_SIZE 2
8185 +#define TWI_MREAD_OFFSET 12
8186 +#define TWI_MREAD_SIZE 1
8187 +#define TWI_DADR_OFFSET 16
8188 +#define TWI_DADR_SIZE 7
8189 +
8190 +/* Bitfields in SMR */
8191 +#define TWI_SADR_OFFSET 16
8192 +#define TWI_SADR_SIZE 7
8193 +
8194 +/* Bitfields in IADR */
8195 +#define TWI_IADR_OFFSET 0
8196 +#define TWI_IADR_SIZE 24
8197 +
8198 +/* Bitfields in CWGR */
8199 +#define TWI_CLDIV_OFFSET 0
8200 +#define TWI_CLDIV_SIZE 8
8201 +#define TWI_CHDIV_OFFSET 8
8202 +#define TWI_CHDIV_SIZE 8
8203 +#define TWI_CKDIV_OFFSET 16
8204 +#define TWI_CKDIV_SIZE 3
8205 +
8206 +/* Bitfields in SR */
8207 +#define TWI_TXCOMP_OFFSET 0
8208 +#define TWI_TXCOMP_SIZE 1
8209 +#define TWI_RXRDY_OFFSET 1
8210 +#define TWI_RXRDY_SIZE 1
8211 +#define TWI_TXRDY_OFFSET 2
8212 +#define TWI_TXRDY_SIZE 1
8213 +#define TWI_SVDIR_OFFSET 3
8214 +#define TWI_SVDIR_SIZE 1
8215 +#define TWI_SVACC_OFFSET 4
8216 +#define TWI_SVACC_SIZE 1
8217 +#define TWI_GCACC_OFFSET 5
8218 +#define TWI_GCACC_SIZE 1
8219 +#define TWI_OVRE_OFFSET 6
8220 +#define TWI_OVRE_SIZE 1
8221 +#define TWI_UNRE_OFFSET 7
8222 +#define TWI_UNRE_SIZE 1
8223 +#define TWI_NACK_OFFSET 8
8224 +#define TWI_NACK_SIZE 1
8225 +#define TWI_ARBLST_OFFSET 9
8226 +#define TWI_ARBLST_SIZE 1
8227 +
8228 +/* Bitfields in RHR */
8229 +#define TWI_RXDATA_OFFSET 0
8230 +#define TWI_RXDATA_SIZE 8
8231 +
8232 +/* Bitfields in THR */
8233 +#define TWI_TXDATA_OFFSET 0
8234 +#define TWI_TXDATA_SIZE 8
8235 +
8236 +/* Constants for IADRSZ */
8237 +#define TWI_IADRSZ_NO_ADDR 0
8238 +#define TWI_IADRSZ_ONE_BYTE 1
8239 +#define TWI_IADRSZ_TWO_BYTES 2
8240 +#define TWI_IADRSZ_THREE_BYTES 3
8241 +
8242 +/* Bit manipulation macros */
8243 +#define TWI_BIT(name) \
8244 + (1 << TWI_##name##_OFFSET)
8245 +#define TWI_BF(name, value) \
8246 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
8247 + << TWI_##name##_OFFSET)
8248 +#define TWI_BFEXT(name, value) \
8249 + (((value) >> TWI_##name##_OFFSET) \
8250 + & ((1 << TWI_##name##_SIZE) - 1))
8251 +#define TWI_BFINS(name, value, old) \
8252 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
8253 + << TWI_##name##_OFFSET)) \
8254 + | TWI_BF(name, (value)))
8255 +
8256 +/* Register access macros */
8257 +#define twi_readl(port, reg) \
8258 + __raw_readl((port)->regs + TWI_##reg)
8259 +#define twi_writel(port, reg, value) \
8260 + __raw_writel((value), (port)->regs + TWI_##reg)
8261 +
8262 +#endif /* __ATMELTWI_H__ */
8263 --- a/drivers/i2c/busses/Kconfig
8264 +++ b/drivers/i2c/busses/Kconfig
8265 @@ -88,6 +88,14 @@
8266 to support combined I2C messages. Use the i2c-gpio driver
8267 unless your system can cope with those limitations.
8268
8269 +config I2C_ATMELTWI
8270 + tristate "Atmel Two-Wire Interface (TWI)"
8271 + depends on I2C && (ARCH_AT91 || PLATFORM_AT32AP)
8272 + help
8273 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
8274 + AT91-based device and want to use its built-in TWI
8275 + functionality.
8276 +
8277 config I2C_AU1550
8278 tristate "Au1550/Au1200 SMBus interface"
8279 depends on SOC_AU1550 || SOC_AU1200
8280 --- a/drivers/i2c/busses/Makefile
8281 +++ b/drivers/i2c/busses/Makefile
8282 @@ -52,6 +52,7 @@
8283 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
8284 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
8285 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
8286 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
8287
8288 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
8289 EXTRA_CFLAGS += -DDEBUG
8290 --- /dev/null
8291 +++ b/drivers/input/serio/at32psif.c
8292 @@ -0,0 +1,351 @@
8293 +/*
8294 + * Copyright (C) 2007 Atmel Corporation
8295 + *
8296 + * Driver for the AT32AP700X PS/2 controller (PSIF).
8297 + *
8298 + * This program is free software; you can redistribute it and/or modify it
8299 + * under the terms of the GNU General Public License version 2 as published
8300 + * by the Free Software Foundation.
8301 + */
8302 +#include <linux/kernel.h>
8303 +#include <linux/module.h>
8304 +#include <linux/device.h>
8305 +#include <linux/init.h>
8306 +#include <linux/serio.h>
8307 +#include <linux/timer.h>
8308 +#include <linux/interrupt.h>
8309 +#include <linux/err.h>
8310 +#include <linux/io.h>
8311 +#include <linux/clk.h>
8312 +#include <linux/platform_device.h>
8313 +
8314 +#include "at32psif.h"
8315 +
8316 +#define PSIF_BUF_SIZE 16
8317 +
8318 +#define ring_is_empty(_psif) (_psif->head == _psif->tail)
8319 +#define ring_next_head(_psif) ((_psif->head + 1) & (PSIF_BUF_SIZE - 1))
8320 +#define ring_next_tail(_psif) ((_psif->tail + 1) & (PSIF_BUF_SIZE - 1))
8321 +
8322 +struct psif {
8323 + struct platform_device *pdev;
8324 + struct clk *pclk;
8325 + struct serio *io;
8326 + struct timer_list tx_timer;
8327 + void __iomem *regs;
8328 + unsigned int irq;
8329 + unsigned int open;
8330 + /* Prevent concurrent writes to circular buffer. */
8331 + spinlock_t lock;
8332 + unsigned int head;
8333 + unsigned int tail;
8334 + unsigned char buffer[PSIF_BUF_SIZE];
8335 +};
8336 +
8337 +static irqreturn_t psif_interrupt(int irq, void *_ptr)
8338 +{
8339 + struct psif *psif = _ptr;
8340 + int retval = IRQ_NONE;
8341 + unsigned int io_flags = 0;
8342 + unsigned long status;
8343 +
8344 + status = psif_readl(psif, SR);
8345 +
8346 + if (status & PSIF_BIT(RXRDY)) {
8347 + unsigned char val = (unsigned char) psif_readl(psif, RHR);
8348 +
8349 + if (status & PSIF_BIT(PARITY))
8350 + io_flags |= SERIO_PARITY;
8351 + if (status & PSIF_BIT(OVRUN))
8352 + dev_err(&psif->pdev->dev, "overrun read error\n");
8353 +
8354 + serio_interrupt(psif->io, val, io_flags);
8355 +
8356 + retval = IRQ_HANDLED;
8357 + }
8358 +
8359 + spin_lock(&psif->lock);
8360 +
8361 + if (status & PSIF_BIT(TXEMPTY)) {
8362 + if (status & PSIF_BIT(NACK))
8363 + dev_err(&psif->pdev->dev, "NACK error\n");
8364 +
8365 + psif_writel(psif, IDR, PSIF_BIT(TXEMPTY));
8366 +
8367 + if (!ring_is_empty(psif))
8368 + mod_timer(&psif->tx_timer,
8369 + jiffies + msecs_to_jiffies(1));
8370 +
8371 + retval = IRQ_HANDLED;
8372 + }
8373 +
8374 + spin_unlock(&psif->lock);
8375 +
8376 + return retval;
8377 +}
8378 +
8379 +static void psif_transmit_data(unsigned long data)
8380 +{
8381 + struct psif *psif = (struct psif *)data;
8382 + unsigned long flags;
8383 +
8384 + spin_lock_irqsave(&psif->lock, flags);
8385 +
8386 + psif_writel(psif, THR, psif->buffer[psif->tail]);
8387 + psif->tail = ring_next_tail(psif);
8388 +
8389 + if (!ring_is_empty(psif))
8390 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
8391 +
8392 + spin_unlock_irqrestore(&psif->lock, flags);
8393 +}
8394 +
8395 +static int psif_write(struct serio *io, unsigned char val)
8396 +{
8397 + struct psif *psif = io->port_data;
8398 + unsigned long flags;
8399 + unsigned int head;
8400 +
8401 + spin_lock_irqsave(&psif->lock, flags);
8402 +
8403 + head = ring_next_head(psif);
8404 +
8405 + if (head != psif->tail) {
8406 + psif->buffer[psif->head] = val;
8407 + psif->head = head;
8408 + } else {
8409 + dev_err(&psif->pdev->dev, "underrun write error\n");
8410 + }
8411 +
8412 + spin_unlock_irqrestore(&psif->lock, flags);
8413 +
8414 + /* Make sure TXEMPTY interrupt is enabled. */
8415 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
8416 +
8417 + return 0;
8418 +}
8419 +
8420 +static int psif_open(struct serio *io)
8421 +{
8422 + struct psif *psif = io->port_data;
8423 + int retval;
8424 +
8425 + retval = clk_enable(psif->pclk);
8426 + if (retval)
8427 + goto out;
8428 +
8429 + psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
8430 + psif_writel(psif, IER, PSIF_BIT(RXRDY));
8431 +
8432 + psif->open = 1;
8433 +out:
8434 + return retval;
8435 +}
8436 +
8437 +static void psif_close(struct serio *io)
8438 +{
8439 + struct psif *psif = io->port_data;
8440 +
8441 + psif->open = 0;
8442 +
8443 + psif_writel(psif, IDR, ~0UL);
8444 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
8445 +
8446 + clk_disable(psif->pclk);
8447 +}
8448 +
8449 +static void psif_set_prescaler(struct psif *psif)
8450 +{
8451 + unsigned long prscv;
8452 + unsigned long rate = clk_get_rate(psif->pclk);
8453 +
8454 + /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
8455 + prscv = 100 * (rate / 1000000UL);
8456 +
8457 + if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
8458 + prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
8459 + dev_dbg(&psif->pdev->dev, "pclk too fast, "
8460 + "prescaler set to max\n");
8461 + }
8462 +
8463 + clk_enable(psif->pclk);
8464 + psif_writel(psif, PSR, prscv);
8465 + clk_disable(psif->pclk);
8466 +}
8467 +
8468 +static int __init psif_probe(struct platform_device *pdev)
8469 +{
8470 + struct resource *regs;
8471 + struct psif *psif;
8472 + struct serio *io;
8473 + struct clk *pclk;
8474 + int irq;
8475 + int ret;
8476 +
8477 + psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
8478 + if (!psif) {
8479 + dev_dbg(&pdev->dev, "out of memory\n");
8480 + ret = -ENOMEM;
8481 + goto out;
8482 + }
8483 + psif->pdev = pdev;
8484 +
8485 + io = kzalloc(sizeof(struct serio), GFP_KERNEL);
8486 + if (!io) {
8487 + dev_dbg(&pdev->dev, "out of memory\n");
8488 + ret = -ENOMEM;
8489 + goto out_free_psif;
8490 + }
8491 + psif->io = io;
8492 +
8493 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8494 + if (!regs) {
8495 + dev_dbg(&pdev->dev, "no mmio resources defined\n");
8496 + ret = -ENOMEM;
8497 + goto out_free_io;
8498 + }
8499 +
8500 + psif->regs = ioremap(regs->start, regs->end - regs->start + 1);
8501 + if (!psif->regs) {
8502 + ret = -ENOMEM;
8503 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
8504 + goto out_free_io;
8505 + }
8506 +
8507 + pclk = clk_get(&pdev->dev, "pclk");
8508 + if (IS_ERR(pclk)) {
8509 + dev_dbg(&pdev->dev, "could not get peripheral clock\n");
8510 + ret = PTR_ERR(pclk);
8511 + goto out_iounmap;
8512 + }
8513 + psif->pclk = pclk;
8514 +
8515 + /* Reset the PSIF to enter at a known state. */
8516 + ret = clk_enable(pclk);
8517 + if (ret) {
8518 + dev_dbg(&pdev->dev, "could not enable pclk\n");
8519 + goto out_put_clk;
8520 + }
8521 + psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
8522 + clk_disable(pclk);
8523 +
8524 + setup_timer(&psif->tx_timer, psif_transmit_data, (unsigned long)psif);
8525 +
8526 + irq = platform_get_irq(pdev, 0);
8527 + if (irq < 0) {
8528 + dev_dbg(&pdev->dev, "could not get irq\n");
8529 + ret = -ENXIO;
8530 + goto out_put_clk;
8531 + }
8532 + ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
8533 + if (ret) {
8534 + dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
8535 + goto out_put_clk;
8536 + }
8537 + psif->irq = irq;
8538 +
8539 + io->id.type = SERIO_8042;
8540 + io->write = psif_write;
8541 + io->open = psif_open;
8542 + io->close = psif_close;
8543 + strlcpy(io->name, pdev->dev.bus_id, sizeof(io->name));
8544 + strlcpy(io->phys, pdev->dev.bus_id, sizeof(io->phys));
8545 + io->port_data = psif;
8546 + io->dev.parent = &pdev->dev;
8547 +
8548 + psif_set_prescaler(psif);
8549 +
8550 + spin_lock_init(&psif->lock);
8551 + serio_register_port(psif->io);
8552 + platform_set_drvdata(pdev, psif);
8553 +
8554 + dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
8555 + (int)psif->regs, psif->irq);
8556 +
8557 + return 0;
8558 +
8559 +out_put_clk:
8560 + clk_put(psif->pclk);
8561 +out_iounmap:
8562 + iounmap(psif->regs);
8563 +out_free_io:
8564 + kfree(io);
8565 +out_free_psif:
8566 + kfree(psif);
8567 +out:
8568 + return ret;
8569 +}
8570 +
8571 +static int __exit psif_remove(struct platform_device *pdev)
8572 +{
8573 + struct psif *psif = platform_get_drvdata(pdev);
8574 +
8575 + psif_writel(psif, IDR, ~0UL);
8576 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
8577 +
8578 + serio_unregister_port(psif->io);
8579 + iounmap(psif->regs);
8580 + free_irq(psif->irq, psif);
8581 + clk_put(psif->pclk);
8582 + kfree(psif);
8583 +
8584 + platform_set_drvdata(pdev, NULL);
8585 +
8586 + return 0;
8587 +}
8588 +
8589 +#ifdef CONFIG_PM
8590 +static int psif_suspend(struct platform_device *pdev, pm_message_t state)
8591 +{
8592 + struct psif *psif = platform_get_drvdata(pdev);
8593 +
8594 + if (psif->open) {
8595 + psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
8596 + clk_disable(psif->pclk);
8597 + }
8598 +
8599 + return 0;
8600 +}
8601 +
8602 +static int psif_resume(struct platform_device *pdev)
8603 +{
8604 + struct psif *psif = platform_get_drvdata(pdev);
8605 +
8606 + if (psif->open) {
8607 + clk_enable(psif->pclk);
8608 + psif_set_prescaler(psif);
8609 + psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
8610 + }
8611 +
8612 + return 0;
8613 +}
8614 +#else
8615 +#define psif_suspend NULL
8616 +#define psif_resume NULL
8617 +#endif
8618 +
8619 +static struct platform_driver psif_driver = {
8620 + .remove = __exit_p(psif_remove),
8621 + .driver = {
8622 + .name = "atmel_psif",
8623 + },
8624 + .suspend = psif_suspend,
8625 + .resume = psif_resume,
8626 +};
8627 +
8628 +static int __init psif_init(void)
8629 +{
8630 + return platform_driver_probe(&psif_driver, psif_probe);
8631 +}
8632 +
8633 +static void __exit psif_exit(void)
8634 +{
8635 + platform_driver_unregister(&psif_driver);
8636 +}
8637 +
8638 +module_init(psif_init);
8639 +module_exit(psif_exit);
8640 +
8641 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
8642 +MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
8643 +MODULE_LICENSE("GPL");
8644 --- /dev/null
8645 +++ b/drivers/input/serio/at32psif.h
8646 @@ -0,0 +1,82 @@
8647 +/*
8648 + * Copyright (C) 2007 Atmel Corporation
8649 + *
8650 + * Driver for the AT32AP700X PS/2 controller (PSIF).
8651 + *
8652 + * This program is free software; you can redistribute it and/or modify it
8653 + * under the terms of the GNU General Public License version 2 as published
8654 + * by the Free Software Foundation.
8655 + */
8656 +
8657 +#ifndef _AT32PSIF_H
8658 +#define _AT32PSIF_H
8659 +
8660 +/* PSIF register offsets */
8661 +#define PSIF_CR 0x00
8662 +#define PSIF_RHR 0x04
8663 +#define PSIF_THR 0x08
8664 +#define PSIF_SR 0x10
8665 +#define PSIF_IER 0x14
8666 +#define PSIF_IDR 0x18
8667 +#define PSIF_IMR 0x1c
8668 +#define PSIF_PSR 0x24
8669 +
8670 +/* Bitfields in control register. */
8671 +#define PSIF_CR_RXDIS_OFFSET 1
8672 +#define PSIF_CR_RXDIS_SIZE 1
8673 +#define PSIF_CR_RXEN_OFFSET 0
8674 +#define PSIF_CR_RXEN_SIZE 1
8675 +#define PSIF_CR_SWRST_OFFSET 15
8676 +#define PSIF_CR_SWRST_SIZE 1
8677 +#define PSIF_CR_TXDIS_OFFSET 9
8678 +#define PSIF_CR_TXDIS_SIZE 1
8679 +#define PSIF_CR_TXEN_OFFSET 8
8680 +#define PSIF_CR_TXEN_SIZE 1
8681 +
8682 +/* Bitfields in interrupt disable, enable, mask and status register. */
8683 +#define PSIF_NACK_OFFSET 8
8684 +#define PSIF_NACK_SIZE 1
8685 +#define PSIF_OVRUN_OFFSET 5
8686 +#define PSIF_OVRUN_SIZE 1
8687 +#define PSIF_PARITY_OFFSET 9
8688 +#define PSIF_PARITY_SIZE 1
8689 +#define PSIF_RXRDY_OFFSET 4
8690 +#define PSIF_RXRDY_SIZE 1
8691 +#define PSIF_TXEMPTY_OFFSET 1
8692 +#define PSIF_TXEMPTY_SIZE 1
8693 +#define PSIF_TXRDY_OFFSET 0
8694 +#define PSIF_TXRDY_SIZE 1
8695 +
8696 +/* Bitfields in prescale register. */
8697 +#define PSIF_PSR_PRSCV_OFFSET 0
8698 +#define PSIF_PSR_PRSCV_SIZE 12
8699 +
8700 +/* Bitfields in receive hold register. */
8701 +#define PSIF_RHR_RXDATA_OFFSET 0
8702 +#define PSIF_RHR_RXDATA_SIZE 8
8703 +
8704 +/* Bitfields in transmit hold register. */
8705 +#define PSIF_THR_TXDATA_OFFSET 0
8706 +#define PSIF_THR_TXDATA_SIZE 8
8707 +
8708 +/* Bit manipulation macros */
8709 +#define PSIF_BIT(name) \
8710 + (1 << PSIF_##name##_OFFSET)
8711 +#define PSIF_BF(name, value) \
8712 + (((value) & ((1 << PSIF_##name##_SIZE) - 1)) \
8713 + << PSIF_##name##_OFFSET)
8714 +#define PSIF_BFEXT(name, value)\
8715 + (((value) >> PSIF_##name##_OFFSET) \
8716 + & ((1 << PSIF_##name##_SIZE) - 1))
8717 +#define PSIF_BFINS(name, value, old) \
8718 + (((old) & ~(((1 << PSIF_##name##_SIZE) - 1) \
8719 + << PSIF_##name##_OFFSET)) \
8720 + | PSIF_BF(name, value))
8721 +
8722 +/* Register access macros */
8723 +#define psif_readl(port, reg) \
8724 + __raw_readl((port)->regs + PSIF_##reg)
8725 +#define psif_writel(port, reg, value) \
8726 + __raw_writel((value), (port)->regs + PSIF_##reg)
8727 +
8728 +#endif /* _AT32PSIF_H */
8729 --- a/drivers/input/serio/Kconfig
8730 +++ b/drivers/input/serio/Kconfig
8731 @@ -88,6 +88,17 @@
8732 To compile this driver as a module, choose M here: the
8733 module will be called rpckbd.
8734
8735 +config SERIO_AT32PSIF
8736 + tristate "AVR32 PSIF PS/2 keyboard and mouse controller"
8737 + depends on AVR32
8738 + default n
8739 + help
8740 + Say Y here if you want to use the PSIF peripheral on AVR32 devices
8741 + and connect a PS/2 keyboard and/or mouse to it.
8742 +
8743 + To compile this driver as a module, choose M here: the module will
8744 + be called at32psif.
8745 +
8746 config SERIO_AMBAKMI
8747 tristate "AMBA KMI keyboard controller"
8748 depends on ARM_AMBA
8749 --- a/drivers/input/serio/Makefile
8750 +++ b/drivers/input/serio/Makefile
8751 @@ -12,6 +12,7 @@
8752 obj-$(CONFIG_SERIO_RPCKBD) += rpckbd.o
8753 obj-$(CONFIG_SERIO_SA1111) += sa1111ps2.o
8754 obj-$(CONFIG_SERIO_AMBAKMI) += ambakmi.o
8755 +obj-$(CONFIG_SERIO_AT32PSIF) += at32psif.o
8756 obj-$(CONFIG_SERIO_Q40KBD) += q40kbd.o
8757 obj-$(CONFIG_SERIO_GSCPS2) += gscps2.o
8758 obj-$(CONFIG_HP_SDC) += hp_sdc.o
8759 --- /dev/null
8760 +++ b/drivers/misc/atmel_tclib.c
8761 @@ -0,0 +1,161 @@
8762 +#include <linux/atmel_tc.h>
8763 +#include <linux/clk.h>
8764 +#include <linux/err.h>
8765 +#include <linux/init.h>
8766 +#include <linux/io.h>
8767 +#include <linux/ioport.h>
8768 +#include <linux/kernel.h>
8769 +#include <linux/platform_device.h>
8770 +
8771 +/* Number of bytes to reserve for the iomem resource */
8772 +#define ATMEL_TC_IOMEM_SIZE 256
8773 +
8774 +
8775 +/*
8776 + * This is a thin library to solve the problem of how to portably allocate
8777 + * one of the TC blocks. For simplicity, it doesn't currently expect to
8778 + * share individual timers between different drivers.
8779 + */
8780 +
8781 +#if defined(CONFIG_AVR32)
8782 +/* AVR32 has these divide PBB */
8783 +const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
8784 +EXPORT_SYMBOL(atmel_tc_divisors);
8785 +
8786 +#elif defined(CONFIG_ARCH_AT91)
8787 +/* AT91 has these divide MCK */
8788 +const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
8789 +EXPORT_SYMBOL(atmel_tc_divisors);
8790 +
8791 +#endif
8792 +
8793 +static DEFINE_SPINLOCK(tc_list_lock);
8794 +static LIST_HEAD(tc_list);
8795 +
8796 +/**
8797 + * atmel_tc_alloc - allocate a specified TC block
8798 + * @block: which block to allocate
8799 + * @name: name to be associated with the iomem resource
8800 + *
8801 + * Caller allocates a block. If it is available, a pointer to a
8802 + * pre-initialized struct atmel_tc is returned. The caller can access
8803 + * the registers directly through the "regs" field.
8804 + */
8805 +struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
8806 +{
8807 + struct atmel_tc *tc;
8808 + struct platform_device *pdev = NULL;
8809 + struct resource *r;
8810 +
8811 + spin_lock(&tc_list_lock);
8812 + list_for_each_entry(tc, &tc_list, node) {
8813 + if (tc->pdev->id == block) {
8814 + pdev = tc->pdev;
8815 + break;
8816 + }
8817 + }
8818 +
8819 + if (!pdev || tc->iomem)
8820 + goto fail;
8821 +
8822 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8823 + r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
8824 + if (!r)
8825 + goto fail;
8826 +
8827 + tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
8828 + if (!tc->regs)
8829 + goto fail_ioremap;
8830 +
8831 + tc->iomem = r;
8832 +
8833 +out:
8834 + spin_unlock(&tc_list_lock);
8835 + return tc;
8836 +
8837 +fail_ioremap:
8838 + release_resource(r);
8839 +fail:
8840 + tc = NULL;
8841 + goto out;
8842 +}
8843 +EXPORT_SYMBOL_GPL(atmel_tc_alloc);
8844 +
8845 +/**
8846 + * atmel_tc_free - release a specified TC block
8847 + * @tc: Timer/counter block that was returned by atmel_tc_alloc()
8848 + *
8849 + * This reverses the effect of atmel_tc_alloc(), unmapping the I/O
8850 + * registers, invalidating the resource returned by that routine and
8851 + * making the TC available to other drivers.
8852 + */
8853 +void atmel_tc_free(struct atmel_tc *tc)
8854 +{
8855 + spin_lock(&tc_list_lock);
8856 + if (tc->regs) {
8857 + iounmap(tc->regs);
8858 + release_resource(tc->iomem);
8859 + tc->regs = NULL;
8860 + tc->iomem = NULL;
8861 + }
8862 + spin_unlock(&tc_list_lock);
8863 +}
8864 +EXPORT_SYMBOL_GPL(atmel_tc_free);
8865 +
8866 +static int __init tc_probe(struct platform_device *pdev)
8867 +{
8868 + struct atmel_tc *tc;
8869 + struct clk *clk;
8870 + int irq;
8871 +
8872 + if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
8873 + return -EINVAL;
8874 +
8875 + irq = platform_get_irq(pdev, 0);
8876 + if (irq < 0)
8877 + return -EINVAL;
8878 +
8879 + tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
8880 + if (!tc)
8881 + return -ENOMEM;
8882 +
8883 + tc->pdev = pdev;
8884 +
8885 + clk = clk_get(&pdev->dev, "t0_clk");
8886 + if (IS_ERR(clk)) {
8887 + kfree(tc);
8888 + return -EINVAL;
8889 + }
8890 +
8891 + tc->clk[0] = clk;
8892 + tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
8893 + if (IS_ERR(tc->clk[1]))
8894 + tc->clk[1] = clk;
8895 + tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
8896 + if (IS_ERR(tc->clk[2]))
8897 + tc->clk[2] = clk;
8898 +
8899 + tc->irq[0] = irq;
8900 + tc->irq[1] = platform_get_irq(pdev, 1);
8901 + if (tc->irq[1] < 0)
8902 + tc->irq[1] = irq;
8903 + tc->irq[2] = platform_get_irq(pdev, 2);
8904 + if (tc->irq[2] < 0)
8905 + tc->irq[2] = irq;
8906 +
8907 + spin_lock(&tc_list_lock);
8908 + list_add_tail(&tc->node, &tc_list);
8909 + spin_unlock(&tc_list_lock);
8910 +
8911 + return 0;
8912 +}
8913 +
8914 +static struct platform_driver tc_driver = {
8915 + .driver.name = "atmel_tcb",
8916 +};
8917 +
8918 +static int __init tc_init(void)
8919 +{
8920 + return platform_driver_probe(&tc_driver, tc_probe);
8921 +}
8922 +arch_initcall(tc_init);
8923 --- a/drivers/misc/Kconfig
8924 +++ b/drivers/misc/Kconfig
8925 @@ -22,6 +22,39 @@
8926 purposes including software controlled power-efficent backlights
8927 on LCD displays, motor control, and waveform generation.
8928
8929 +config ATMEL_TCLIB
8930 + bool "Atmel AT32/AT91 Timer/Counter Library"
8931 + depends on (AVR32 || ARCH_AT91)
8932 + help
8933 + Select this if you want a library to allocate the Timer/Counter
8934 + blocks found on many Atmel processors. This facilitates using
8935 + these blocks by different drivers despite processor differences.
8936 +
8937 +config ATMEL_TCB_CLKSRC
8938 + bool "TC Block Clocksource"
8939 + depends on ATMEL_TCLIB && GENERIC_TIME
8940 + default y
8941 + help
8942 + Select this to get a high precision clocksource based on a
8943 + TC block with a 5+ MHz base clock rate. Two timer channels
8944 + are combined to make a single 32-bit timer.
8945 +
8946 + When GENERIC_CLOCKEVENTS is defined, the third timer channel
8947 + may be used as a clock event device supporting oneshot mode
8948 + (delays of up to two seconds) based on the 32 KiHz clock.
8949 +
8950 +config ATMEL_TCB_CLKSRC_BLOCK
8951 + int
8952 + depends on ATMEL_TCB_CLKSRC
8953 + prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
8954 + default 0
8955 + range 0 1
8956 + help
8957 + Some chips provide more than one TC block, so you have the
8958 + choice of which one to use for the clock framework. The other
8959 + TC can be used for other purposes, such as PWM generation and
8960 + interval timing.
8961 +
8962 config IBM_ASM
8963 tristate "Device driver for IBM RSA service processor"
8964 depends on X86 && PCI && INPUT && EXPERIMENTAL
8965 --- a/drivers/misc/Makefile
8966 +++ b/drivers/misc/Makefile
8967 @@ -10,6 +10,7 @@
8968 obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
8969 obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
8970 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
8971 +obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
8972 obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
8973 obj-$(CONFIG_LKDTM) += lkdtm.o
8974 obj-$(CONFIG_TIFM_CORE) += tifm_core.o
8975 --- /dev/null
8976 +++ b/drivers/mmc/host/atmel-mci.c
8977 @@ -0,0 +1,1220 @@
8978 +/*
8979 + * Atmel MultiMedia Card Interface driver
8980 + *
8981 + * Copyright (C) 2004-2006 Atmel Corporation
8982 + *
8983 + * This program is free software; you can redistribute it and/or modify
8984 + * it under the terms of the GNU General Public License version 2 as
8985 + * published by the Free Software Foundation.
8986 + */
8987 +#include <linux/blkdev.h>
8988 +#include <linux/clk.h>
8989 +#include <linux/device.h>
8990 +#include <linux/dma-mapping.h>
8991 +#include <linux/init.h>
8992 +#include <linux/interrupt.h>
8993 +#include <linux/ioport.h>
8994 +#include <linux/module.h>
8995 +#include <linux/platform_device.h>
8996 +
8997 +#include <linux/mmc/host.h>
8998 +
8999 +#include <asm/dma-controller.h>
9000 +#include <asm/io.h>
9001 +#include <asm/arch/board.h>
9002 +#include <asm/arch/gpio.h>
9003 +
9004 +#include "atmel-mci.h"
9005 +
9006 +#define DRIVER_NAME "atmel_mci"
9007 +
9008 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
9009 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
9010 +
9011 +enum {
9012 + EVENT_CMD_COMPLETE = 0,
9013 + EVENT_DATA_COMPLETE,
9014 + EVENT_DATA_ERROR,
9015 + EVENT_STOP_SENT,
9016 + EVENT_STOP_COMPLETE,
9017 + EVENT_DMA_COMPLETE,
9018 + EVENT_DMA_ERROR,
9019 +};
9020 +
9021 +struct atmel_mci_dma {
9022 + struct dma_request_sg req;
9023 + unsigned short rx_periph_id;
9024 + unsigned short tx_periph_id;
9025 +};
9026 +
9027 +struct atmel_mci {
9028 + struct mmc_host *mmc;
9029 + void __iomem *regs;
9030 + struct atmel_mci_dma dma;
9031 +
9032 + struct mmc_request *mrq;
9033 + struct mmc_command *cmd;
9034 + struct mmc_data *data;
9035 +
9036 + u32 cmd_status;
9037 + u32 data_status;
9038 + u32 stop_status;
9039 + u32 stop_cmdr;
9040 +
9041 + struct tasklet_struct tasklet;
9042 + unsigned long pending_events;
9043 + unsigned long completed_events;
9044 +
9045 + int present;
9046 + int detect_pin;
9047 + int wp_pin;
9048 +
9049 + /* For detect pin debouncing */
9050 + struct timer_list detect_timer;
9051 +
9052 + unsigned long bus_hz;
9053 + unsigned long mapbase;
9054 + struct clk *mck;
9055 + struct platform_device *pdev;
9056 +
9057 +#ifdef CONFIG_DEBUG_FS
9058 + struct dentry *debugfs_root;
9059 + struct dentry *debugfs_regs;
9060 + struct dentry *debugfs_req;
9061 + struct dentry *debugfs_pending_events;
9062 + struct dentry *debugfs_completed_events;
9063 +#endif
9064 +};
9065 +
9066 +/* Those printks take an awful lot of time... */
9067 +#ifndef DEBUG
9068 +static unsigned int fmax = 15000000U;
9069 +#else
9070 +static unsigned int fmax = 1000000U;
9071 +#endif
9072 +module_param(fmax, uint, 0444);
9073 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
9074 +
9075 +/* Test bit macros for completed events */
9076 +#define mci_cmd_is_complete(host) \
9077 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9078 +#define mci_data_is_complete(host) \
9079 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9080 +#define mci_data_error_is_complete(host) \
9081 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
9082 +#define mci_stop_sent_is_complete(host) \
9083 + test_bit(EVENT_STOP_SENT, &host->completed_events)
9084 +#define mci_stop_is_complete(host) \
9085 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9086 +#define mci_dma_is_complete(host) \
9087 + test_bit(EVENT_DMA_COMPLETE, &host->completed_events)
9088 +#define mci_dma_error_is_complete(host) \
9089 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
9090 +
9091 +/* Test and clear bit macros for pending events */
9092 +#define mci_clear_cmd_is_pending(host) \
9093 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9094 +#define mci_clear_data_is_pending(host) \
9095 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9096 +#define mci_clear_data_error_is_pending(host) \
9097 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
9098 +#define mci_clear_stop_sent_is_pending(host) \
9099 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
9100 +#define mci_clear_stop_is_pending(host) \
9101 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9102 +#define mci_clear_dma_error_is_pending(host) \
9103 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
9104 +
9105 +/* Test and set bit macros for completed events */
9106 +#define mci_set_cmd_is_completed(host) \
9107 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9108 +#define mci_set_data_is_completed(host) \
9109 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9110 +#define mci_set_data_error_is_completed(host) \
9111 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
9112 +#define mci_set_stop_sent_is_completed(host) \
9113 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
9114 +#define mci_set_stop_is_completed(host) \
9115 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9116 +#define mci_set_dma_error_is_completed(host) \
9117 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
9118 +
9119 +/* Set bit macros for completed events */
9120 +#define mci_set_cmd_complete(host) \
9121 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
9122 +#define mci_set_data_complete(host) \
9123 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
9124 +#define mci_set_data_error_complete(host) \
9125 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
9126 +#define mci_set_stop_sent_complete(host) \
9127 + set_bit(EVENT_STOP_SENT, &host->completed_events)
9128 +#define mci_set_stop_complete(host) \
9129 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
9130 +#define mci_set_dma_complete(host) \
9131 + set_bit(EVENT_DMA_COMPLETE, &host->completed_events)
9132 +#define mci_set_dma_error_complete(host) \
9133 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
9134 +
9135 +/* Set bit macros for pending events */
9136 +#define mci_set_cmd_pending(host) \
9137 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9138 +#define mci_set_data_pending(host) \
9139 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9140 +#define mci_set_data_error_pending(host) \
9141 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
9142 +#define mci_set_stop_sent_pending(host) \
9143 + set_bit(EVENT_STOP_SENT, &host->pending_events)
9144 +#define mci_set_stop_pending(host) \
9145 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9146 +#define mci_set_dma_error_pending(host) \
9147 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
9148 +
9149 +/* Clear bit macros for pending events */
9150 +#define mci_clear_cmd_pending(host) \
9151 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
9152 +#define mci_clear_data_pending(host) \
9153 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
9154 +#define mci_clear_data_error_pending(host) \
9155 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
9156 +#define mci_clear_stop_sent_pending(host) \
9157 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
9158 +#define mci_clear_stop_pending(host) \
9159 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
9160 +#define mci_clear_dma_error_pending(host) \
9161 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
9162 +
9163 +
9164 +#ifdef CONFIG_DEBUG_FS
9165 +#include <linux/debugfs.h>
9166 +
9167 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
9168 +
9169 +struct req_dbg_data {
9170 + unsigned int nbytes;
9171 + char str[DBG_REQ_BUF_SIZE];
9172 +};
9173 +
9174 +static int req_dbg_open(struct inode *inode, struct file *file)
9175 +{
9176 + struct atmel_mci *host;
9177 + struct mmc_request *mrq;
9178 + struct mmc_command *cmd, *stop;
9179 + struct mmc_data *data;
9180 + struct req_dbg_data *priv;
9181 + char *str;
9182 + unsigned long n = 0;
9183 +
9184 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
9185 + if (!priv)
9186 + return -ENOMEM;
9187 + str = priv->str;
9188 +
9189 + mutex_lock(&inode->i_mutex);
9190 + host = inode->i_private;
9191 +
9192 + spin_lock_irq(&host->mmc->lock);
9193 + mrq = host->mrq;
9194 + if (mrq) {
9195 + cmd = mrq->cmd;
9196 + data = mrq->data;
9197 + stop = mrq->stop;
9198 + n = snprintf(str, DBG_REQ_BUF_SIZE,
9199 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
9200 + cmd->opcode, cmd->arg, cmd->flags,
9201 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
9202 + cmd->resp[3], cmd->error);
9203 + if (n < DBG_REQ_BUF_SIZE && data)
9204 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
9205 + "DATA %u * %u (%u) %x (err %u)\n",
9206 + data->blocks, data->blksz,
9207 + data->bytes_xfered, data->flags,
9208 + data->error);
9209 + if (n < DBG_REQ_BUF_SIZE && stop)
9210 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
9211 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
9212 + stop->opcode, stop->arg, stop->flags,
9213 + stop->resp[0], stop->resp[1],
9214 + stop->resp[2], stop->resp[3],
9215 + stop->error);
9216 + }
9217 + spin_unlock_irq(&host->mmc->lock);
9218 + mutex_unlock(&inode->i_mutex);
9219 +
9220 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
9221 + file->private_data = priv;
9222 +
9223 + return 0;
9224 +}
9225 +
9226 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
9227 + size_t nbytes, loff_t *ppos)
9228 +{
9229 + struct req_dbg_data *priv = file->private_data;
9230 +
9231 + return simple_read_from_buffer(buf, nbytes, ppos,
9232 + priv->str, priv->nbytes);
9233 +}
9234 +
9235 +static int req_dbg_release(struct inode *inode, struct file *file)
9236 +{
9237 + kfree(file->private_data);
9238 + return 0;
9239 +}
9240 +
9241 +static const struct file_operations req_dbg_fops = {
9242 + .owner = THIS_MODULE,
9243 + .open = req_dbg_open,
9244 + .llseek = no_llseek,
9245 + .read = req_dbg_read,
9246 + .release = req_dbg_release,
9247 +};
9248 +
9249 +static int regs_dbg_open(struct inode *inode, struct file *file)
9250 +{
9251 + struct atmel_mci *host;
9252 + unsigned int i;
9253 + u32 *data;
9254 + int ret = -ENOMEM;
9255 +
9256 + mutex_lock(&inode->i_mutex);
9257 + host = inode->i_private;
9258 + data = kmalloc(inode->i_size, GFP_KERNEL);
9259 + if (!data)
9260 + goto out;
9261 +
9262 + spin_lock_irq(&host->mmc->lock);
9263 + for (i = 0; i < inode->i_size / 4; i++)
9264 + data[i] = __raw_readl(host->regs + i * 4);
9265 + spin_unlock_irq(&host->mmc->lock);
9266 +
9267 + file->private_data = data;
9268 + ret = 0;
9269 +
9270 +out:
9271 + mutex_unlock(&inode->i_mutex);
9272 +
9273 + return ret;
9274 +}
9275 +
9276 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
9277 + size_t nbytes, loff_t *ppos)
9278 +{
9279 + struct inode *inode = file->f_dentry->d_inode;
9280 + int ret;
9281 +
9282 + mutex_lock(&inode->i_mutex);
9283 + ret = simple_read_from_buffer(buf, nbytes, ppos,
9284 + file->private_data,
9285 + file->f_dentry->d_inode->i_size);
9286 + mutex_unlock(&inode->i_mutex);
9287 +
9288 + return ret;
9289 +}
9290 +
9291 +static int regs_dbg_release(struct inode *inode, struct file *file)
9292 +{
9293 + kfree(file->private_data);
9294 + return 0;
9295 +}
9296 +
9297 +static const struct file_operations regs_dbg_fops = {
9298 + .owner = THIS_MODULE,
9299 + .open = regs_dbg_open,
9300 + .llseek = generic_file_llseek,
9301 + .read = regs_dbg_read,
9302 + .release = regs_dbg_release,
9303 +};
9304 +
9305 +static void atmci_init_debugfs(struct atmel_mci *host)
9306 +{
9307 + struct mmc_host *mmc;
9308 + struct dentry *root, *regs;
9309 + struct resource *res;
9310 +
9311 + mmc = host->mmc;
9312 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
9313 + if (IS_ERR(root) || !root)
9314 + goto err_root;
9315 + host->debugfs_root = root;
9316 +
9317 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
9318 + if (!regs)
9319 + goto err_regs;
9320 +
9321 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
9322 + regs->d_inode->i_size = res->end - res->start + 1;
9323 + host->debugfs_regs = regs;
9324 +
9325 + host->debugfs_req = debugfs_create_file("req", 0400, root,
9326 + host, &req_dbg_fops);
9327 + if (!host->debugfs_req)
9328 + goto err_req;
9329 +
9330 + host->debugfs_pending_events
9331 + = debugfs_create_u32("pending_events", 0400, root,
9332 + (u32 *)&host->pending_events);
9333 + if (!host->debugfs_pending_events)
9334 + goto err_pending_events;
9335 +
9336 + host->debugfs_completed_events
9337 + = debugfs_create_u32("completed_events", 0400, root,
9338 + (u32 *)&host->completed_events);
9339 + if (!host->debugfs_completed_events)
9340 + goto err_completed_events;
9341 +
9342 + return;
9343 +
9344 +err_completed_events:
9345 + debugfs_remove(host->debugfs_pending_events);
9346 +err_pending_events:
9347 + debugfs_remove(host->debugfs_req);
9348 +err_req:
9349 + debugfs_remove(host->debugfs_regs);
9350 +err_regs:
9351 + debugfs_remove(host->debugfs_root);
9352 +err_root:
9353 + host->debugfs_root = NULL;
9354 + dev_err(&host->pdev->dev,
9355 + "failed to initialize debugfs for %s\n",
9356 + mmc_hostname(mmc));
9357 +}
9358 +
9359 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
9360 +{
9361 + if (host->debugfs_root) {
9362 + debugfs_remove(host->debugfs_completed_events);
9363 + debugfs_remove(host->debugfs_pending_events);
9364 + debugfs_remove(host->debugfs_req);
9365 + debugfs_remove(host->debugfs_regs);
9366 + debugfs_remove(host->debugfs_root);
9367 + host->debugfs_root = NULL;
9368 + }
9369 +}
9370 +#else
9371 +static inline void atmci_init_debugfs(struct atmel_mci *host)
9372 +{
9373 +
9374 +}
9375 +
9376 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
9377 +{
9378 +
9379 +}
9380 +#endif /* CONFIG_DEBUG_FS */
9381 +
9382 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
9383 + unsigned int ns)
9384 +{
9385 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
9386 +}
9387 +
9388 +static void atmci_set_timeout(struct atmel_mci *host,
9389 + struct mmc_data *data)
9390 +{
9391 + static unsigned dtomul_to_shift[] = {
9392 + 0, 4, 7, 8, 10, 12, 16, 20
9393 + };
9394 + unsigned timeout;
9395 + unsigned dtocyc, dtomul;
9396 +
9397 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
9398 +
9399 + for (dtomul = 0; dtomul < 8; dtomul++) {
9400 + unsigned shift = dtomul_to_shift[dtomul];
9401 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
9402 + if (dtocyc < 15)
9403 + break;
9404 + }
9405 +
9406 + if (dtomul >= 8) {
9407 + dtomul = 7;
9408 + dtocyc = 15;
9409 + }
9410 +
9411 + dev_dbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
9412 + dtocyc << dtomul_to_shift[dtomul]);
9413 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
9414 + | MCI_BF(DTOCYC, dtocyc)));
9415 +}
9416 +
9417 +/*
9418 + * Return mask with command flags to be enabled for this command.
9419 + */
9420 +static u32 atmci_prepare_command(struct mmc_host *mmc,
9421 + struct mmc_command *cmd)
9422 +{
9423 + u32 cmdr;
9424 +
9425 + cmd->error = 0;
9426 +
9427 + cmdr = MCI_BF(CMDNB, cmd->opcode);
9428 +
9429 + if (cmd->flags & MMC_RSP_PRESENT) {
9430 + if (cmd->flags & MMC_RSP_136)
9431 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
9432 + else
9433 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
9434 + }
9435 +
9436 + /*
9437 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
9438 + * it's too difficult to determine whether this is an ACMD or
9439 + * not. Better make it 64.
9440 + */
9441 + cmdr |= MCI_BIT(MAXLAT);
9442 +
9443 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
9444 + cmdr |= MCI_BIT(OPDCMD);
9445 +
9446 + dev_dbg(&mmc->class_dev,
9447 + "cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
9448 + cmd->opcode, cmd->arg, cmd->flags, (unsigned long)cmdr);
9449 +
9450 + return cmdr;
9451 +}
9452 +
9453 +static void atmci_start_command(struct atmel_mci *host,
9454 + struct mmc_command *cmd,
9455 + u32 cmd_flags)
9456 +{
9457 + WARN_ON(host->cmd);
9458 + host->cmd = cmd;
9459 +
9460 + mci_writel(host, ARGR, cmd->arg);
9461 + mci_writel(host, CMDR, cmd_flags);
9462 +
9463 + if (cmd->data)
9464 + dma_start_request(host->dma.req.req.dmac,
9465 + host->dma.req.req.channel);
9466 +}
9467 +
9468 +/*
9469 + * Returns a mask of flags to be set in the command register when the
9470 + * command to start the transfer is to be sent.
9471 + */
9472 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
9473 +{
9474 + struct atmel_mci *host = mmc_priv(mmc);
9475 + u32 cmd_flags;
9476 +
9477 + WARN_ON(host->data);
9478 + host->data = data;
9479 +
9480 + atmci_set_timeout(host, data);
9481 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
9482 + | MCI_BF(BLKLEN, data->blksz)));
9483 + host->dma.req.block_size = data->blksz;
9484 + host->dma.req.nr_blocks = data->blocks;
9485 +
9486 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
9487 + if (data->flags & MMC_DATA_STREAM)
9488 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
9489 + else if (data->blocks > 1)
9490 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
9491 + else
9492 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
9493 +
9494 + if (data->flags & MMC_DATA_READ) {
9495 + cmd_flags |= MCI_BIT(TRDIR);
9496 + host->dma.req.nr_sg
9497 + = dma_map_sg(&host->pdev->dev, data->sg,
9498 + data->sg_len, DMA_FROM_DEVICE);
9499 + host->dma.req.periph_id = host->dma.rx_periph_id;
9500 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
9501 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
9502 + } else {
9503 + host->dma.req.nr_sg
9504 + = dma_map_sg(&host->pdev->dev, data->sg,
9505 + data->sg_len, DMA_TO_DEVICE);
9506 + host->dma.req.periph_id = host->dma.tx_periph_id;
9507 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
9508 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
9509 + }
9510 + host->dma.req.sg = data->sg;
9511 +
9512 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
9513 +
9514 + return cmd_flags;
9515 +}
9516 +
9517 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
9518 +{
9519 + struct atmel_mci *host = mmc_priv(mmc);
9520 + struct mmc_data *data = mrq->data;
9521 + u32 iflags;
9522 + u32 cmdflags = 0;
9523 +
9524 + iflags = mci_readl(host, IMR);
9525 + if (iflags)
9526 + dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
9527 + mci_readl(host, IMR));
9528 +
9529 + WARN_ON(host->mrq != NULL);
9530 +
9531 + /*
9532 + * We may "know" the card is gone even though there's still an
9533 + * electrical connection. If so, we really need to communicate
9534 + * this to the MMC core since there won't be any more
9535 + * interrupts as the card is completely removed. Otherwise,
9536 + * the MMC core might believe the card is still there even
9537 + * though the card was just removed very slowly.
9538 + */
9539 + if (!host->present) {
9540 + mrq->cmd->error = -ENOMEDIUM;
9541 + mmc_request_done(mmc, mrq);
9542 + return;
9543 + }
9544 +
9545 + host->mrq = mrq;
9546 + host->pending_events = 0;
9547 + host->completed_events = 0;
9548 +
9549 + iflags = MCI_BIT(CMDRDY);
9550 + cmdflags = atmci_prepare_command(mmc, mrq->cmd);
9551 +
9552 + if (mrq->stop) {
9553 + WARN_ON(!data);
9554 +
9555 + host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
9556 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
9557 + if (!(data->flags & MMC_DATA_WRITE))
9558 + host->stop_cmdr |= MCI_BIT(TRDIR);
9559 + if (data->flags & MMC_DATA_STREAM)
9560 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
9561 + else
9562 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
9563 + }
9564 + if (data) {
9565 + cmdflags |= atmci_prepare_data(mmc, data);
9566 + iflags |= MCI_DATA_ERROR_FLAGS;
9567 + }
9568 +
9569 + atmci_start_command(host, mrq->cmd, cmdflags);
9570 + mci_writel(host, IER, iflags);
9571 +}
9572 +
9573 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
9574 +{
9575 + struct atmel_mci *host = mmc_priv(mmc);
9576 + u32 mr;
9577 +
9578 + if (ios->clock) {
9579 + u32 clkdiv;
9580 +
9581 + /* Set clock rate */
9582 + clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
9583 + if (clkdiv > 255) {
9584 + dev_warn(&mmc->class_dev,
9585 + "clock %u too slow; using %lu\n",
9586 + ios->clock, host->bus_hz / (2 * 256));
9587 + clkdiv = 255;
9588 + }
9589 +
9590 + mr = mci_readl(host, MR);
9591 + mr = MCI_BFINS(CLKDIV, clkdiv, mr)
9592 + | MCI_BIT(WRPROOF) | MCI_BIT(RDPROOF);
9593 + mci_writel(host, MR, mr);
9594 +
9595 + /* Enable the MCI controller */
9596 + mci_writel(host, CR, MCI_BIT(MCIEN));
9597 + } else {
9598 + /* Disable the MCI controller */
9599 + mci_writel(host, CR, MCI_BIT(MCIDIS));
9600 + }
9601 +
9602 + switch (ios->bus_width) {
9603 + case MMC_BUS_WIDTH_1:
9604 + mci_writel(host, SDCR, 0);
9605 + break;
9606 + case MMC_BUS_WIDTH_4:
9607 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
9608 + break;
9609 + }
9610 +
9611 + switch (ios->power_mode) {
9612 + case MMC_POWER_ON:
9613 + /* Send init sequence (74 clock cycles) */
9614 + mci_writel(host, IDR, ~0UL);
9615 + mci_writel(host, CMDR, MCI_BF(SPCMD, MCI_SPCMD_INIT_CMD));
9616 + while (!(mci_readl(host, SR) & MCI_BIT(CMDRDY)))
9617 + cpu_relax();
9618 + break;
9619 + default:
9620 + /*
9621 + * TODO: None of the currently available AVR32-based
9622 + * boards allow MMC power to be turned off. Implement
9623 + * power control when this can be tested properly.
9624 + */
9625 + break;
9626 + }
9627 +}
9628 +
9629 +static int atmci_get_ro(struct mmc_host *mmc)
9630 +{
9631 + int read_only = 0;
9632 + struct atmel_mci *host = mmc_priv(mmc);
9633 +
9634 + if (host->wp_pin >= 0) {
9635 + read_only = gpio_get_value(host->wp_pin);
9636 + dev_dbg(&mmc->class_dev, "card is %s\n",
9637 + read_only ? "read-only" : "read-write");
9638 + } else {
9639 + dev_dbg(&mmc->class_dev,
9640 + "no pin for checking read-only switch."
9641 + " Assuming write-enable.\n");
9642 + }
9643 +
9644 + return read_only;
9645 +}
9646 +
9647 +static struct mmc_host_ops atmci_ops = {
9648 + .request = atmci_request,
9649 + .set_ios = atmci_set_ios,
9650 + .get_ro = atmci_get_ro,
9651 +};
9652 +
9653 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
9654 +{
9655 + struct atmel_mci *host = mmc_priv(mmc);
9656 +
9657 + WARN_ON(host->cmd || host->data);
9658 + host->mrq = NULL;
9659 +
9660 + mmc_request_done(mmc, mrq);
9661 +}
9662 +
9663 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
9664 + u32 flags)
9665 +{
9666 + struct atmel_mci *host = mmc_priv(mmc);
9667 +
9668 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
9669 + mci_writel(host, IER, MCI_BIT(CMDRDY));
9670 +}
9671 +
9672 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
9673 +{
9674 + host->data = NULL;
9675 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
9676 + ((data->flags & MMC_DATA_WRITE)
9677 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
9678 +
9679 + /*
9680 + * Data might complete before command for very short transfers
9681 + * (like READ_SCR)
9682 + */
9683 + if (mci_cmd_is_complete(host)
9684 + && (!data->stop || mci_stop_is_complete(host)))
9685 + atmci_request_end(host->mmc, data->mrq);
9686 +}
9687 +
9688 +static void atmci_command_complete(struct atmel_mci *host,
9689 + struct mmc_command *cmd, u32 status)
9690 +{
9691 + if (status & MCI_BIT(RTOE))
9692 + cmd->error = -ETIMEDOUT;
9693 + else if ((cmd->flags & MMC_RSP_CRC)
9694 + && (status & MCI_BIT(RCRCE)))
9695 + cmd->error = -EILSEQ;
9696 + else if (status & (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | MCI_BIT(RENDE)))
9697 + cmd->error = -EIO;
9698 +
9699 + if (cmd->error) {
9700 + dev_dbg(&host->mmc->class_dev,
9701 + "command error: op=0x%x status=0x%08x\n",
9702 + cmd->opcode, status);
9703 +
9704 + if (cmd->data) {
9705 + dma_stop_request(host->dma.req.req.dmac,
9706 + host->dma.req.req.channel);
9707 + mci_writel(host, IDR, MCI_BIT(NOTBUSY)
9708 + | MCI_DATA_ERROR_FLAGS);
9709 + host->data = NULL;
9710 + }
9711 + }
9712 +}
9713 +
9714 +static void atmci_detect_change(unsigned long data)
9715 +{
9716 + struct atmel_mci *host = (struct atmel_mci *)data;
9717 + struct mmc_request *mrq = host->mrq;
9718 + int present;
9719 +
9720 + /*
9721 + * atmci_remove() sets detect_pin to -1 before freeing the
9722 + * interrupt. We must not re-enable the interrupt if it has
9723 + * been freed.
9724 + */
9725 + smp_rmb();
9726 + if (host->detect_pin < 0)
9727 + return;
9728 +
9729 + enable_irq(gpio_to_irq(host->detect_pin));
9730 + present = !gpio_get_value(host->detect_pin);
9731 +
9732 + dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
9733 + present, host->present);
9734 +
9735 + if (present != host->present) {
9736 + dev_dbg(&host->mmc->class_dev, "card %s\n",
9737 + present ? "inserted" : "removed");
9738 + host->present = present;
9739 +
9740 + /* Reset controller if card is gone */
9741 + if (!present) {
9742 + mci_writel(host, CR, MCI_BIT(SWRST));
9743 + mci_writel(host, IDR, ~0UL);
9744 + mci_writel(host, CR, MCI_BIT(MCIEN));
9745 + }
9746 +
9747 + /* Clean up queue if present */
9748 + if (mrq) {
9749 + if (!mci_cmd_is_complete(host))
9750 + mrq->cmd->error = -ENOMEDIUM;
9751 + if (mrq->data && !mci_data_is_complete(host)
9752 + && !mci_data_error_is_complete(host)) {
9753 + dma_stop_request(host->dma.req.req.dmac,
9754 + host->dma.req.req.channel);
9755 + host->data->error = -ENOMEDIUM;
9756 + atmci_data_complete(host, host->data);
9757 + }
9758 + if (mrq->stop && !mci_stop_is_complete(host))
9759 + mrq->stop->error = -ENOMEDIUM;
9760 +
9761 + host->cmd = NULL;
9762 + atmci_request_end(host->mmc, mrq);
9763 + }
9764 +
9765 + mmc_detect_change(host->mmc, 0);
9766 + }
9767 +}
9768 +
9769 +static void atmci_tasklet_func(unsigned long priv)
9770 +{
9771 + struct mmc_host *mmc = (struct mmc_host *)priv;
9772 + struct atmel_mci *host = mmc_priv(mmc);
9773 + struct mmc_request *mrq = host->mrq;
9774 + struct mmc_data *data = host->data;
9775 +
9776 + dev_vdbg(&mmc->class_dev,
9777 + "tasklet: pending/completed/mask %lx/%lx/%x\n",
9778 + host->pending_events, host->completed_events,
9779 + mci_readl(host, IMR));
9780 +
9781 + if (mci_clear_cmd_is_pending(host)) {
9782 + mci_set_cmd_complete(host);
9783 + atmci_command_complete(host, mrq->cmd, host->cmd_status);
9784 + if (!host->data || mci_data_is_complete(host)
9785 + || mci_data_error_is_complete(host))
9786 + atmci_request_end(mmc, mrq);
9787 + }
9788 + if (mci_clear_stop_is_pending(host)) {
9789 + mci_set_stop_complete(host);
9790 + atmci_command_complete(host, mrq->stop, host->stop_status);
9791 + if (mci_data_is_complete(host)
9792 + || mci_data_error_is_complete(host))
9793 + atmci_request_end(mmc, mrq);
9794 + }
9795 + if (mci_clear_dma_error_is_pending(host)) {
9796 + mci_set_dma_error_complete(host);
9797 + mci_clear_data_pending(host);
9798 +
9799 + /* DMA controller got bus error => invalid address */
9800 + data->error = -EIO;
9801 +
9802 + dev_dbg(&mmc->class_dev, "dma error after %u bytes xfered\n",
9803 + host->data->bytes_xfered);
9804 +
9805 + if (data->stop
9806 + && !mci_set_stop_sent_is_completed(host))
9807 + /* TODO: Check if card is still present */
9808 + send_stop_cmd(host->mmc, data, 0);
9809 +
9810 + atmci_data_complete(host, data);
9811 + }
9812 + if (mci_clear_data_error_is_pending(host)) {
9813 + u32 status = host->data_status;
9814 +
9815 + mci_set_data_error_complete(host);
9816 + mci_clear_data_pending(host);
9817 +
9818 + dma_stop_request(host->dma.req.req.dmac,
9819 + host->dma.req.req.channel);
9820 +
9821 + if (status & MCI_BIT(DCRCE)) {
9822 + dev_dbg(&mmc->class_dev, "data CRC error\n");
9823 + data->error = -EILSEQ;
9824 + } else if (status & MCI_BIT(DTOE)) {
9825 + dev_dbg(&mmc->class_dev, "data timeout error\n");
9826 + data->error = -ETIMEDOUT;
9827 + } else {
9828 + dev_dbg(&mmc->class_dev, "data FIFO error\n");
9829 + data->error = -EIO;
9830 + }
9831 + dev_dbg(&mmc->class_dev, "bytes xfered: %u\n",
9832 + data->bytes_xfered);
9833 +
9834 + if (data->stop
9835 + && !mci_set_stop_sent_is_completed(host))
9836 + /* TODO: Check if card is still present */
9837 + send_stop_cmd(host->mmc, data, 0);
9838 +
9839 + atmci_data_complete(host, data);
9840 + }
9841 + if (mci_clear_data_is_pending(host)) {
9842 + mci_set_data_complete(host);
9843 + data->bytes_xfered = data->blocks * data->blksz;
9844 + atmci_data_complete(host, data);
9845 + }
9846 +}
9847 +
9848 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
9849 +{
9850 + struct atmel_mci *host = mmc_priv(mmc);
9851 + struct mmc_command *cmd = host->cmd;
9852 +
9853 + /*
9854 + * Read the response now so that we're free to send a new
9855 + * command immediately.
9856 + */
9857 + cmd->resp[0] = mci_readl(host, RSPR);
9858 + cmd->resp[1] = mci_readl(host, RSPR);
9859 + cmd->resp[2] = mci_readl(host, RSPR);
9860 + cmd->resp[3] = mci_readl(host, RSPR);
9861 +
9862 + mci_writel(host, IDR, MCI_BIT(CMDRDY));
9863 + host->cmd = NULL;
9864 +
9865 + if (mci_stop_sent_is_complete(host)) {
9866 + host->stop_status = status;
9867 + mci_set_stop_pending(host);
9868 + } else {
9869 + struct mmc_request *mrq = host->mrq;
9870 +
9871 + if (mrq->stop && mci_dma_is_complete(host)
9872 + && !mci_set_stop_sent_is_completed(host))
9873 + send_stop_cmd(host->mmc, mrq->data, 0);
9874 + host->cmd_status = status;
9875 + mci_set_cmd_pending(host);
9876 + }
9877 +
9878 + tasklet_schedule(&host->tasklet);
9879 +}
9880 +
9881 +static void atmci_xfer_complete(struct dma_request *_req)
9882 +{
9883 + struct dma_request_sg *req = to_dma_request_sg(_req);
9884 + struct atmel_mci_dma *dma;
9885 + struct atmel_mci *host;
9886 + struct mmc_data *data;
9887 +
9888 + dma = container_of(req, struct atmel_mci_dma, req);
9889 + host = container_of(dma, struct atmel_mci, dma);
9890 + data = host->data;
9891 +
9892 + /*
9893 + * This callback may be called before we see the CMDRDY
9894 + * interrupt under heavy irq load (possibly caused by other
9895 + * drivers) or when interrupts are disabled for a long time.
9896 + */
9897 + mci_set_dma_complete(host);
9898 + if (data->stop && mci_cmd_is_complete(host)
9899 + && !mci_set_stop_sent_is_completed(host))
9900 + send_stop_cmd(host->mmc, data, 0);
9901 +
9902 + /*
9903 + * Regardless of what the documentation says, we have to wait
9904 + * for NOTBUSY even after block read operations.
9905 + *
9906 + * When the DMA transfer is complete, the controller may still
9907 + * be reading the CRC from the card, i.e. the data transfer is
9908 + * still in progress and we haven't seen all the potential
9909 + * error bits yet.
9910 + */
9911 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
9912 +}
9913 +
9914 +static void atmci_dma_error(struct dma_request *_req)
9915 +{
9916 + struct dma_request_sg *req = to_dma_request_sg(_req);
9917 + struct atmel_mci_dma *dma;
9918 + struct atmel_mci *host;
9919 +
9920 + dma = container_of(req, struct atmel_mci_dma, req);
9921 + host = container_of(dma, struct atmel_mci, dma);
9922 +
9923 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
9924 + | MCI_DATA_ERROR_FLAGS));
9925 +
9926 + mci_set_dma_error_pending(host);
9927 + tasklet_schedule(&host->tasklet);
9928 +}
9929 +
9930 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
9931 +{
9932 + struct mmc_host *mmc = dev_id;
9933 + struct atmel_mci *host = mmc_priv(mmc);
9934 + u32 status, mask, pending;
9935 +
9936 + spin_lock(&mmc->lock);
9937 +
9938 + status = mci_readl(host, SR);
9939 + mask = mci_readl(host, IMR);
9940 + pending = status & mask;
9941 +
9942 + do {
9943 + if (pending & MCI_DATA_ERROR_FLAGS) {
9944 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
9945 + | MCI_DATA_ERROR_FLAGS));
9946 + host->data_status = status;
9947 + mci_set_data_error_pending(host);
9948 + tasklet_schedule(&host->tasklet);
9949 + break;
9950 + }
9951 + if (pending & MCI_BIT(CMDRDY))
9952 + atmci_cmd_interrupt(mmc, status);
9953 + if (pending & MCI_BIT(NOTBUSY)) {
9954 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
9955 + | MCI_DATA_ERROR_FLAGS));
9956 + mci_set_data_pending(host);
9957 + tasklet_schedule(&host->tasklet);
9958 + }
9959 +
9960 + status = mci_readl(host, SR);
9961 + mask = mci_readl(host, IMR);
9962 + pending = status & mask;
9963 + } while (pending);
9964 +
9965 + spin_unlock(&mmc->lock);
9966 +
9967 + return IRQ_HANDLED;
9968 +}
9969 +
9970 +static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
9971 +{
9972 + struct mmc_host *mmc = dev_id;
9973 + struct atmel_mci *host = mmc_priv(mmc);
9974 +
9975 + /*
9976 + * Disable interrupts until the pin has stabilized and check
9977 + * the state then. Use mod_timer() since we may be in the
9978 + * middle of the timer routine when this interrupt triggers.
9979 + */
9980 + disable_irq_nosync(irq);
9981 + mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
9982 +
9983 + return IRQ_HANDLED;
9984 +}
9985 +
9986 +static int __devinit atmci_probe(struct platform_device *pdev)
9987 +{
9988 + struct mci_platform_data *board;
9989 + struct atmel_mci *host;
9990 + struct mmc_host *mmc;
9991 + struct resource *regs;
9992 + int irq;
9993 + int ret;
9994 +
9995 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9996 + if (!regs)
9997 + return -ENXIO;
9998 + irq = platform_get_irq(pdev, 0);
9999 + if (irq < 0)
10000 + return irq;
10001 +
10002 + board = pdev->dev.platform_data;
10003 +
10004 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
10005 + if (!mmc)
10006 + return -ENOMEM;
10007 +
10008 + host = mmc_priv(mmc);
10009 + host->pdev = pdev;
10010 + host->mmc = mmc;
10011 + if (board) {
10012 + host->detect_pin = board->detect_pin;
10013 + host->wp_pin = board->wp_pin;
10014 + } else {
10015 + host->detect_pin = -1;
10016 + host->wp_pin = -1;
10017 + }
10018 +
10019 + host->mck = clk_get(&pdev->dev, "mci_clk");
10020 + if (IS_ERR(host->mck)) {
10021 + ret = PTR_ERR(host->mck);
10022 + goto out_free_host;
10023 + }
10024 + clk_enable(host->mck);
10025 +
10026 + ret = -ENOMEM;
10027 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
10028 + if (!host->regs)
10029 + goto out_disable_clk;
10030 +
10031 + host->bus_hz = clk_get_rate(host->mck);
10032 + host->mapbase = regs->start;
10033 +
10034 + mmc->ops = &atmci_ops;
10035 + mmc->f_min = (host->bus_hz + 511) / 512;
10036 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
10037 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
10038 + mmc->caps |= MMC_CAP_4_BIT_DATA;
10039 +
10040 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
10041 +
10042 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
10043 + if (ret)
10044 + goto out_unmap;
10045 +
10046 + /* Assume card is present if we don't have a detect pin */
10047 + host->present = 1;
10048 + if (host->detect_pin >= 0) {
10049 + if (gpio_request(host->detect_pin, "mmc_detect")) {
10050 + dev_dbg(&mmc->class_dev, "no detect pin available\n");
10051 + host->detect_pin = -1;
10052 + } else {
10053 + host->present = !gpio_get_value(host->detect_pin);
10054 + }
10055 + }
10056 + if (host->wp_pin >= 0) {
10057 + if (gpio_request(host->wp_pin, "mmc_wp")) {
10058 + dev_dbg(&mmc->class_dev, "no WP pin available\n");
10059 + host->wp_pin = -1;
10060 + }
10061 + }
10062 +
10063 + /* TODO: Get this information from platform data */
10064 + ret = -ENOMEM;
10065 + host->dma.req.req.dmac = find_dma_controller(0);
10066 + if (!host->dma.req.req.dmac) {
10067 + dev_dbg(&mmc->class_dev, "no DMA controller available\n");
10068 + goto out_free_irq;
10069 + }
10070 + ret = dma_alloc_channel(host->dma.req.req.dmac);
10071 + if (ret < 0) {
10072 + dev_dbg(&mmc->class_dev, "unable to allocate DMA channel\n");
10073 + goto out_free_irq;
10074 + }
10075 + host->dma.req.req.channel = ret;
10076 + host->dma.req.width = DMA_WIDTH_32BIT;
10077 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
10078 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
10079 + host->dma.req.req.error = atmci_dma_error;
10080 + host->dma.rx_periph_id = 0;
10081 + host->dma.tx_periph_id = 1;
10082 +
10083 + mci_writel(host, CR, MCI_BIT(SWRST));
10084 + mci_writel(host, IDR, ~0UL);
10085 +
10086 + platform_set_drvdata(pdev, host);
10087 +
10088 + mmc_add_host(mmc);
10089 +
10090 + if (host->detect_pin >= 0) {
10091 + setup_timer(&host->detect_timer, atmci_detect_change,
10092 + (unsigned long)host);
10093 +
10094 + ret = request_irq(gpio_to_irq(host->detect_pin),
10095 + atmci_detect_interrupt,
10096 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
10097 + DRIVER_NAME, mmc);
10098 + if (ret) {
10099 + dev_dbg(&mmc->class_dev,
10100 + "could not request IRQ %d for detect pin\n",
10101 + gpio_to_irq(host->detect_pin));
10102 + gpio_free(host->detect_pin);
10103 + host->detect_pin = -1;
10104 + }
10105 + }
10106 +
10107 + dev_info(&mmc->class_dev, "Atmel MCI controller at 0x%08lx irq %d\n",
10108 + host->mapbase, irq);
10109 +
10110 + atmci_init_debugfs(host);
10111 +
10112 + return 0;
10113 +
10114 +out_free_irq:
10115 + if (host->detect_pin >= 0)
10116 + gpio_free(host->detect_pin);
10117 + if (host->wp_pin >= 0)
10118 + gpio_free(host->wp_pin);
10119 + free_irq(irq, mmc);
10120 +out_unmap:
10121 + iounmap(host->regs);
10122 +out_disable_clk:
10123 + clk_disable(host->mck);
10124 + clk_put(host->mck);
10125 +out_free_host:
10126 + mmc_free_host(mmc);
10127 + return ret;
10128 +}
10129 +
10130 +static int __devexit atmci_remove(struct platform_device *pdev)
10131 +{
10132 + struct atmel_mci *host = platform_get_drvdata(pdev);
10133 +
10134 + platform_set_drvdata(pdev, NULL);
10135 +
10136 + if (host) {
10137 + atmci_cleanup_debugfs(host);
10138 +
10139 + if (host->detect_pin >= 0) {
10140 + int pin = host->detect_pin;
10141 +
10142 + /* Make sure our timer doesn't enable the interrupt */
10143 + host->detect_pin = -1;
10144 + smp_wmb();
10145 +
10146 + free_irq(gpio_to_irq(pin), host->mmc);
10147 + del_timer_sync(&host->detect_timer);
10148 + cancel_delayed_work(&host->mmc->detect);
10149 + gpio_free(pin);
10150 + }
10151 +
10152 + mmc_remove_host(host->mmc);
10153 +
10154 + mci_writel(host, IDR, ~0UL);
10155 + mci_writel(host, CR, MCI_BIT(MCIDIS));
10156 + mci_readl(host, SR);
10157 +
10158 + dma_release_channel(host->dma.req.req.dmac,
10159 + host->dma.req.req.channel);
10160 +
10161 + if (host->wp_pin >= 0)
10162 + gpio_free(host->wp_pin);
10163 +
10164 + free_irq(platform_get_irq(pdev, 0), host->mmc);
10165 + iounmap(host->regs);
10166 +
10167 + clk_disable(host->mck);
10168 + clk_put(host->mck);
10169 +
10170 + mmc_free_host(host->mmc);
10171 + }
10172 + return 0;
10173 +}
10174 +
10175 +static struct platform_driver atmci_driver = {
10176 + .probe = atmci_probe,
10177 + .remove = __devexit_p(atmci_remove),
10178 + .driver = {
10179 + .name = DRIVER_NAME,
10180 + },
10181 +};
10182 +
10183 +static int __init atmci_init(void)
10184 +{
10185 + return platform_driver_register(&atmci_driver);
10186 +}
10187 +
10188 +static void __exit atmci_exit(void)
10189 +{
10190 + platform_driver_unregister(&atmci_driver);
10191 +}
10192 +
10193 +module_init(atmci_init);
10194 +module_exit(atmci_exit);
10195 +
10196 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
10197 +MODULE_LICENSE("GPL");
10198 --- /dev/null
10199 +++ b/drivers/mmc/host/atmel-mci.h
10200 @@ -0,0 +1,192 @@
10201 +/*
10202 + * Atmel MultiMedia Card Interface driver
10203 + *
10204 + * Copyright (C) 2004-2006 Atmel Corporation
10205 + *
10206 + * This program is free software; you can redistribute it and/or modify
10207 + * it under the terms of the GNU General Public License version 2 as
10208 + * published by the Free Software Foundation.
10209 + */
10210 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
10211 +#define __DRIVERS_MMC_ATMEL_MCI_H__
10212 +
10213 +/* MCI register offsets */
10214 +#define MCI_CR 0x0000
10215 +#define MCI_MR 0x0004
10216 +#define MCI_DTOR 0x0008
10217 +#define MCI_SDCR 0x000c
10218 +#define MCI_ARGR 0x0010
10219 +#define MCI_CMDR 0x0014
10220 +#define MCI_BLKR 0x0018
10221 +#define MCI_RSPR 0x0020
10222 +#define MCI_RSPR1 0x0024
10223 +#define MCI_RSPR2 0x0028
10224 +#define MCI_RSPR3 0x002c
10225 +#define MCI_RDR 0x0030
10226 +#define MCI_TDR 0x0034
10227 +#define MCI_SR 0x0040
10228 +#define MCI_IER 0x0044
10229 +#define MCI_IDR 0x0048
10230 +#define MCI_IMR 0x004c
10231 +
10232 +/* Bitfields in CR */
10233 +#define MCI_MCIEN_OFFSET 0
10234 +#define MCI_MCIEN_SIZE 1
10235 +#define MCI_MCIDIS_OFFSET 1
10236 +#define MCI_MCIDIS_SIZE 1
10237 +#define MCI_PWSEN_OFFSET 2
10238 +#define MCI_PWSEN_SIZE 1
10239 +#define MCI_PWSDIS_OFFSET 3
10240 +#define MCI_PWSDIS_SIZE 1
10241 +#define MCI_SWRST_OFFSET 7
10242 +#define MCI_SWRST_SIZE 1
10243 +
10244 +/* Bitfields in MR */
10245 +#define MCI_CLKDIV_OFFSET 0
10246 +#define MCI_CLKDIV_SIZE 8
10247 +#define MCI_PWSDIV_OFFSET 8
10248 +#define MCI_PWSDIV_SIZE 3
10249 +#define MCI_RDPROOF_OFFSET 11
10250 +#define MCI_RDPROOF_SIZE 1
10251 +#define MCI_WRPROOF_OFFSET 12
10252 +#define MCI_WRPROOF_SIZE 1
10253 +#define MCI_DMAPADV_OFFSET 14
10254 +#define MCI_DMAPADV_SIZE 1
10255 +#define MCI_BLKLEN_OFFSET 16
10256 +#define MCI_BLKLEN_SIZE 16
10257 +
10258 +/* Bitfields in DTOR */
10259 +#define MCI_DTOCYC_OFFSET 0
10260 +#define MCI_DTOCYC_SIZE 4
10261 +#define MCI_DTOMUL_OFFSET 4
10262 +#define MCI_DTOMUL_SIZE 3
10263 +
10264 +/* Bitfields in SDCR */
10265 +#define MCI_SDCSEL_OFFSET 0
10266 +#define MCI_SDCSEL_SIZE 4
10267 +#define MCI_SDCBUS_OFFSET 7
10268 +#define MCI_SDCBUS_SIZE 1
10269 +
10270 +/* Bitfields in ARGR */
10271 +#define MCI_ARG_OFFSET 0
10272 +#define MCI_ARG_SIZE 32
10273 +
10274 +/* Bitfields in CMDR */
10275 +#define MCI_CMDNB_OFFSET 0
10276 +#define MCI_CMDNB_SIZE 6
10277 +#define MCI_RSPTYP_OFFSET 6
10278 +#define MCI_RSPTYP_SIZE 2
10279 +#define MCI_SPCMD_OFFSET 8
10280 +#define MCI_SPCMD_SIZE 3
10281 +#define MCI_OPDCMD_OFFSET 11
10282 +#define MCI_OPDCMD_SIZE 1
10283 +#define MCI_MAXLAT_OFFSET 12
10284 +#define MCI_MAXLAT_SIZE 1
10285 +#define MCI_TRCMD_OFFSET 16
10286 +#define MCI_TRCMD_SIZE 2
10287 +#define MCI_TRDIR_OFFSET 18
10288 +#define MCI_TRDIR_SIZE 1
10289 +#define MCI_TRTYP_OFFSET 19
10290 +#define MCI_TRTYP_SIZE 2
10291 +
10292 +/* Bitfields in BLKR */
10293 +#define MCI_BCNT_OFFSET 0
10294 +#define MCI_BCNT_SIZE 16
10295 +
10296 +/* Bitfields in RSPRn */
10297 +#define MCI_RSP_OFFSET 0
10298 +#define MCI_RSP_SIZE 32
10299 +
10300 +/* Bitfields in SR/IER/IDR/IMR */
10301 +#define MCI_CMDRDY_OFFSET 0
10302 +#define MCI_CMDRDY_SIZE 1
10303 +#define MCI_RXRDY_OFFSET 1
10304 +#define MCI_RXRDY_SIZE 1
10305 +#define MCI_TXRDY_OFFSET 2
10306 +#define MCI_TXRDY_SIZE 1
10307 +#define MCI_BLKE_OFFSET 3
10308 +#define MCI_BLKE_SIZE 1
10309 +#define MCI_DTIP_OFFSET 4
10310 +#define MCI_DTIP_SIZE 1
10311 +#define MCI_NOTBUSY_OFFSET 5
10312 +#define MCI_NOTBUSY_SIZE 1
10313 +#define MCI_ENDRX_OFFSET 6
10314 +#define MCI_ENDRX_SIZE 1
10315 +#define MCI_ENDTX_OFFSET 7
10316 +#define MCI_ENDTX_SIZE 1
10317 +#define MCI_RXBUFF_OFFSET 14
10318 +#define MCI_RXBUFF_SIZE 1
10319 +#define MCI_TXBUFE_OFFSET 15
10320 +#define MCI_TXBUFE_SIZE 1
10321 +#define MCI_RINDE_OFFSET 16
10322 +#define MCI_RINDE_SIZE 1
10323 +#define MCI_RDIRE_OFFSET 17
10324 +#define MCI_RDIRE_SIZE 1
10325 +#define MCI_RCRCE_OFFSET 18
10326 +#define MCI_RCRCE_SIZE 1
10327 +#define MCI_RENDE_OFFSET 19
10328 +#define MCI_RENDE_SIZE 1
10329 +#define MCI_RTOE_OFFSET 20
10330 +#define MCI_RTOE_SIZE 1
10331 +#define MCI_DCRCE_OFFSET 21
10332 +#define MCI_DCRCE_SIZE 1
10333 +#define MCI_DTOE_OFFSET 22
10334 +#define MCI_DTOE_SIZE 1
10335 +#define MCI_OVRE_OFFSET 30
10336 +#define MCI_OVRE_SIZE 1
10337 +#define MCI_UNRE_OFFSET 31
10338 +#define MCI_UNRE_SIZE 1
10339 +
10340 +/* Constants for DTOMUL */
10341 +#define MCI_DTOMUL_1_CYCLE 0
10342 +#define MCI_DTOMUL_16_CYCLES 1
10343 +#define MCI_DTOMUL_128_CYCLES 2
10344 +#define MCI_DTOMUL_256_CYCLES 3
10345 +#define MCI_DTOMUL_1024_CYCLES 4
10346 +#define MCI_DTOMUL_4096_CYCLES 5
10347 +#define MCI_DTOMUL_65536_CYCLES 6
10348 +#define MCI_DTOMUL_1048576_CYCLES 7
10349 +
10350 +/* Constants for RSPTYP */
10351 +#define MCI_RSPTYP_NO_RESP 0
10352 +#define MCI_RSPTYP_48_BIT 1
10353 +#define MCI_RSPTYP_136_BIT 2
10354 +
10355 +/* Constants for SPCMD */
10356 +#define MCI_SPCMD_NO_SPEC_CMD 0
10357 +#define MCI_SPCMD_INIT_CMD 1
10358 +#define MCI_SPCMD_SYNC_CMD 2
10359 +#define MCI_SPCMD_INT_CMD 4
10360 +#define MCI_SPCMD_INT_RESP 5
10361 +
10362 +/* Constants for TRCMD */
10363 +#define MCI_TRCMD_NO_TRANS 0
10364 +#define MCI_TRCMD_START_TRANS 1
10365 +#define MCI_TRCMD_STOP_TRANS 2
10366 +
10367 +/* Constants for TRTYP */
10368 +#define MCI_TRTYP_BLOCK 0
10369 +#define MCI_TRTYP_MULTI_BLOCK 1
10370 +#define MCI_TRTYP_STREAM 2
10371 +
10372 +/* Bit manipulation macros */
10373 +#define MCI_BIT(name) \
10374 + (1 << MCI_##name##_OFFSET)
10375 +#define MCI_BF(name,value) \
10376 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
10377 + << MCI_##name##_OFFSET)
10378 +#define MCI_BFEXT(name,value) \
10379 + (((value) >> MCI_##name##_OFFSET) \
10380 + & ((1 << MCI_##name##_SIZE) - 1))
10381 +#define MCI_BFINS(name,value,old) \
10382 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
10383 + << MCI_##name##_OFFSET)) \
10384 + | MCI_BF(name,value))
10385 +
10386 +/* Register access macros */
10387 +#define mci_readl(port,reg) \
10388 + __raw_readl((port)->regs + MCI_##reg)
10389 +#define mci_writel(port,reg,value) \
10390 + __raw_writel((value), (port)->regs + MCI_##reg)
10391 +
10392 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
10393 --- a/drivers/mmc/host/Kconfig
10394 +++ b/drivers/mmc/host/Kconfig
10395 @@ -91,6 +91,16 @@
10396
10397 If unsure, say N.
10398
10399 +config MMC_ATMELMCI
10400 + tristate "Atmel Multimedia Card Interface support"
10401 + depends on AVR32 && MMC
10402 + help
10403 + This selects the Atmel Multimedia Card Interface. If you have
10404 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
10405 + slot, say Y or M here.
10406 +
10407 + If unsure, say N.
10408 +
10409 config MMC_IMX
10410 tristate "Motorola i.MX Multimedia Card Interface support"
10411 depends on ARCH_IMX
10412 --- a/drivers/mmc/host/Makefile
10413 +++ b/drivers/mmc/host/Makefile
10414 @@ -15,6 +15,7 @@
10415 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
10416 obj-$(CONFIG_MMC_OMAP) += omap.o
10417 obj-$(CONFIG_MMC_AT91) += at91_mci.o
10418 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
10419 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
10420 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
10421
10422 --- a/drivers/mtd/nand/at91_nand.c
10423 +++ /dev/null
10424 @@ -1,236 +0,0 @@
10425 -/*
10426 - * drivers/mtd/nand/at91_nand.c
10427 - *
10428 - * Copyright (C) 2003 Rick Bronson
10429 - *
10430 - * Derived from drivers/mtd/nand/autcpu12.c
10431 - * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
10432 - *
10433 - * Derived from drivers/mtd/spia.c
10434 - * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
10435 - *
10436 - * This program is free software; you can redistribute it and/or modify
10437 - * it under the terms of the GNU General Public License version 2 as
10438 - * published by the Free Software Foundation.
10439 - *
10440 - */
10441 -
10442 -#include <linux/slab.h>
10443 -#include <linux/module.h>
10444 -#include <linux/platform_device.h>
10445 -#include <linux/mtd/mtd.h>
10446 -#include <linux/mtd/nand.h>
10447 -#include <linux/mtd/partitions.h>
10448 -
10449 -#include <asm/io.h>
10450 -#include <asm/sizes.h>
10451 -
10452 -#include <asm/hardware.h>
10453 -#include <asm/arch/board.h>
10454 -#include <asm/arch/gpio.h>
10455 -
10456 -struct at91_nand_host {
10457 - struct nand_chip nand_chip;
10458 - struct mtd_info mtd;
10459 - void __iomem *io_base;
10460 - struct at91_nand_data *board;
10461 -};
10462 -
10463 -/*
10464 - * Hardware specific access to control-lines
10465 - */
10466 -static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
10467 -{
10468 - struct nand_chip *nand_chip = mtd->priv;
10469 - struct at91_nand_host *host = nand_chip->priv;
10470 -
10471 - if (cmd == NAND_CMD_NONE)
10472 - return;
10473 -
10474 - if (ctrl & NAND_CLE)
10475 - writeb(cmd, host->io_base + (1 << host->board->cle));
10476 - else
10477 - writeb(cmd, host->io_base + (1 << host->board->ale));
10478 -}
10479 -
10480 -/*
10481 - * Read the Device Ready pin.
10482 - */
10483 -static int at91_nand_device_ready(struct mtd_info *mtd)
10484 -{
10485 - struct nand_chip *nand_chip = mtd->priv;
10486 - struct at91_nand_host *host = nand_chip->priv;
10487 -
10488 - return at91_get_gpio_value(host->board->rdy_pin);
10489 -}
10490 -
10491 -/*
10492 - * Enable NAND.
10493 - */
10494 -static void at91_nand_enable(struct at91_nand_host *host)
10495 -{
10496 - if (host->board->enable_pin)
10497 - at91_set_gpio_value(host->board->enable_pin, 0);
10498 -}
10499 -
10500 -/*
10501 - * Disable NAND.
10502 - */
10503 -static void at91_nand_disable(struct at91_nand_host *host)
10504 -{
10505 - if (host->board->enable_pin)
10506 - at91_set_gpio_value(host->board->enable_pin, 1);
10507 -}
10508 -
10509 -#ifdef CONFIG_MTD_PARTITIONS
10510 -const char *part_probes[] = { "cmdlinepart", NULL };
10511 -#endif
10512 -
10513 -/*
10514 - * Probe for the NAND device.
10515 - */
10516 -static int __init at91_nand_probe(struct platform_device *pdev)
10517 -{
10518 - struct at91_nand_host *host;
10519 - struct mtd_info *mtd;
10520 - struct nand_chip *nand_chip;
10521 - int res;
10522 -
10523 -#ifdef CONFIG_MTD_PARTITIONS
10524 - struct mtd_partition *partitions = NULL;
10525 - int num_partitions = 0;
10526 -#endif
10527 -
10528 - /* Allocate memory for the device structure (and zero it) */
10529 - host = kzalloc(sizeof(struct at91_nand_host), GFP_KERNEL);
10530 - if (!host) {
10531 - printk(KERN_ERR "at91_nand: failed to allocate device structure.\n");
10532 - return -ENOMEM;
10533 - }
10534 -
10535 - host->io_base = ioremap(pdev->resource[0].start,
10536 - pdev->resource[0].end - pdev->resource[0].start + 1);
10537 - if (host->io_base == NULL) {
10538 - printk(KERN_ERR "at91_nand: ioremap failed\n");
10539 - kfree(host);
10540 - return -EIO;
10541 - }
10542 -
10543 - mtd = &host->mtd;
10544 - nand_chip = &host->nand_chip;
10545 - host->board = pdev->dev.platform_data;
10546 -
10547 - nand_chip->priv = host; /* link the private data structures */
10548 - mtd->priv = nand_chip;
10549 - mtd->owner = THIS_MODULE;
10550 -
10551 - /* Set address of NAND IO lines */
10552 - nand_chip->IO_ADDR_R = host->io_base;
10553 - nand_chip->IO_ADDR_W = host->io_base;
10554 - nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
10555 -
10556 - if (host->board->rdy_pin)
10557 - nand_chip->dev_ready = at91_nand_device_ready;
10558 -
10559 - nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
10560 - nand_chip->chip_delay = 20; /* 20us command delay time */
10561 -
10562 - if (host->board->bus_width_16) /* 16-bit bus width */
10563 - nand_chip->options |= NAND_BUSWIDTH_16;
10564 -
10565 - platform_set_drvdata(pdev, host);
10566 - at91_nand_enable(host);
10567 -
10568 - if (host->board->det_pin) {
10569 - if (at91_get_gpio_value(host->board->det_pin)) {
10570 - printk ("No SmartMedia card inserted.\n");
10571 - res = ENXIO;
10572 - goto out;
10573 - }
10574 - }
10575 -
10576 - /* Scan to find existance of the device */
10577 - if (nand_scan(mtd, 1)) {
10578 - res = -ENXIO;
10579 - goto out;
10580 - }
10581 -
10582 -#ifdef CONFIG_MTD_PARTITIONS
10583 -#ifdef CONFIG_MTD_CMDLINE_PARTS
10584 - mtd->name = "at91_nand";
10585 - num_partitions = parse_mtd_partitions(mtd, part_probes,
10586 - &partitions, 0);
10587 -#endif
10588 - if (num_partitions <= 0 && host->board->partition_info)
10589 - partitions = host->board->partition_info(mtd->size,
10590 - &num_partitions);
10591 -
10592 - if ((!partitions) || (num_partitions == 0)) {
10593 - printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
10594 - res = ENXIO;
10595 - goto release;
10596 - }
10597 -
10598 - res = add_mtd_partitions(mtd, partitions, num_partitions);
10599 -#else
10600 - res = add_mtd_device(mtd);
10601 -#endif
10602 -
10603 - if (!res)
10604 - return res;
10605 -
10606 -release:
10607 - nand_release(mtd);
10608 -out:
10609 - at91_nand_disable(host);
10610 - platform_set_drvdata(pdev, NULL);
10611 - iounmap(host->io_base);
10612 - kfree(host);
10613 - return res;
10614 -}
10615 -
10616 -/*
10617 - * Remove a NAND device.
10618 - */
10619 -static int __devexit at91_nand_remove(struct platform_device *pdev)
10620 -{
10621 - struct at91_nand_host *host = platform_get_drvdata(pdev);
10622 - struct mtd_info *mtd = &host->mtd;
10623 -
10624 - nand_release(mtd);
10625 -
10626 - at91_nand_disable(host);
10627 -
10628 - iounmap(host->io_base);
10629 - kfree(host);
10630 -
10631 - return 0;
10632 -}
10633 -
10634 -static struct platform_driver at91_nand_driver = {
10635 - .probe = at91_nand_probe,
10636 - .remove = at91_nand_remove,
10637 - .driver = {
10638 - .name = "at91_nand",
10639 - .owner = THIS_MODULE,
10640 - },
10641 -};
10642 -
10643 -static int __init at91_nand_init(void)
10644 -{
10645 - return platform_driver_register(&at91_nand_driver);
10646 -}
10647 -
10648 -
10649 -static void __exit at91_nand_exit(void)
10650 -{
10651 - platform_driver_unregister(&at91_nand_driver);
10652 -}
10653 -
10654 -
10655 -module_init(at91_nand_init);
10656 -module_exit(at91_nand_exit);
10657 -
10658 -MODULE_LICENSE("GPL");
10659 -MODULE_AUTHOR("Rick Bronson");
10660 -MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
10661 --- /dev/null
10662 +++ b/drivers/mtd/nand/atmel_nand.c
10663 @@ -0,0 +1,650 @@
10664 +/*
10665 + * Copyright (C) 2003 Rick Bronson
10666 + *
10667 + * Derived from drivers/mtd/nand/autcpu12.c
10668 + * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
10669 + *
10670 + * Derived from drivers/mtd/spia.c
10671 + * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
10672 + *
10673 + *
10674 + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
10675 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
10676 + *
10677 + * Derived from Das U-Boot source code
10678 + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
10679 + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
10680 + *
10681 + *
10682 + * This program is free software; you can redistribute it and/or modify
10683 + * it under the terms of the GNU General Public License version 2 as
10684 + * published by the Free Software Foundation.
10685 + *
10686 + */
10687 +
10688 +#include <linux/slab.h>
10689 +#include <linux/module.h>
10690 +#include <linux/platform_device.h>
10691 +#include <linux/mtd/mtd.h>
10692 +#include <linux/mtd/nand.h>
10693 +#include <linux/mtd/partitions.h>
10694 +
10695 +#include <linux/gpio.h>
10696 +#include <linux/io.h>
10697 +
10698 +#include <asm/arch/board.h>
10699 +#include <asm/arch/cpu.h>
10700 +
10701 +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
10702 +#define hard_ecc 1
10703 +#else
10704 +#define hard_ecc 0
10705 +#endif
10706 +
10707 +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
10708 +#define no_ecc 1
10709 +#else
10710 +#define no_ecc 0
10711 +#endif
10712 +
10713 +/* Register access macros */
10714 +#define ecc_readl(add, reg) \
10715 + __raw_readl(add + ATMEL_ECC_##reg)
10716 +#define ecc_writel(add, reg, value) \
10717 + __raw_writel((value), add + ATMEL_ECC_##reg)
10718 +
10719 +#include "atmel_nand_ecc.h" /* Hardware ECC registers */
10720 +
10721 +/* oob layout for large page size
10722 + * bad block info is on bytes 0 and 1
10723 + * the bytes have to be consecutives to avoid
10724 + * several NAND_CMD_RNDOUT during read
10725 + */
10726 +static struct nand_ecclayout atmel_oobinfo_large = {
10727 + .eccbytes = 4,
10728 + .eccpos = {60, 61, 62, 63},
10729 + .oobfree = {
10730 + {2, 58}
10731 + },
10732 +};
10733 +
10734 +/* oob layout for small page size
10735 + * bad block info is on bytes 4 and 5
10736 + * the bytes have to be consecutives to avoid
10737 + * several NAND_CMD_RNDOUT during read
10738 + */
10739 +static struct nand_ecclayout atmel_oobinfo_small = {
10740 + .eccbytes = 4,
10741 + .eccpos = {0, 1, 2, 3},
10742 + .oobfree = {
10743 + {6, 10}
10744 + },
10745 +};
10746 +
10747 +struct atmel_nand_host {
10748 + struct nand_chip nand_chip;
10749 + struct mtd_info mtd;
10750 + void __iomem *io_base;
10751 + struct atmel_nand_data *board;
10752 + struct device *dev;
10753 + void __iomem *ecc;
10754 +};
10755 +
10756 +/*
10757 + * Enable NAND.
10758 + */
10759 +static void atmel_nand_enable(struct atmel_nand_host *host)
10760 +{
10761 + if (host->board->enable_pin)
10762 + gpio_set_value(host->board->enable_pin, 0);
10763 +}
10764 +
10765 +/*
10766 + * Disable NAND.
10767 + */
10768 +static void atmel_nand_disable(struct atmel_nand_host *host)
10769 +{
10770 + if (host->board->enable_pin)
10771 + gpio_set_value(host->board->enable_pin, 1);
10772 +}
10773 +
10774 +/*
10775 + * Hardware specific access to control-lines
10776 + */
10777 +static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
10778 +{
10779 + struct nand_chip *nand_chip = mtd->priv;
10780 + struct atmel_nand_host *host = nand_chip->priv;
10781 +
10782 + if (ctrl & NAND_CTRL_CHANGE) {
10783 + if (ctrl & NAND_NCE)
10784 + atmel_nand_enable(host);
10785 + else
10786 + atmel_nand_disable(host);
10787 + }
10788 + if (cmd == NAND_CMD_NONE)
10789 + return;
10790 +
10791 + if (ctrl & NAND_CLE)
10792 + writeb(cmd, host->io_base + (1 << host->board->cle));
10793 + else
10794 + writeb(cmd, host->io_base + (1 << host->board->ale));
10795 +}
10796 +
10797 +/*
10798 + * Read the Device Ready pin.
10799 + */
10800 +static int atmel_nand_device_ready(struct mtd_info *mtd)
10801 +{
10802 + struct nand_chip *nand_chip = mtd->priv;
10803 + struct atmel_nand_host *host = nand_chip->priv;
10804 +
10805 + return gpio_get_value(host->board->rdy_pin);
10806 +}
10807 +
10808 +/*
10809 + * Minimal-overhead PIO for data access.
10810 + */
10811 +static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
10812 +{
10813 + struct nand_chip *nand_chip = mtd->priv;
10814 +
10815 + __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
10816 +}
10817 +
10818 +static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
10819 +{
10820 + struct nand_chip *nand_chip = mtd->priv;
10821 +
10822 + __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
10823 +}
10824 +
10825 +static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
10826 +{
10827 + struct nand_chip *nand_chip = mtd->priv;
10828 +
10829 + __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
10830 +}
10831 +
10832 +static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
10833 +{
10834 + struct nand_chip *nand_chip = mtd->priv;
10835 +
10836 + __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
10837 +}
10838 +
10839 +/*
10840 + * write oob for small pages
10841 + */
10842 +static int atmel_nand_write_oob_512(struct mtd_info *mtd,
10843 + struct nand_chip *chip, int page)
10844 +{
10845 + int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
10846 + int eccsize = chip->ecc.size, length = mtd->oobsize;
10847 + int len, pos, status = 0;
10848 + const uint8_t *bufpoi = chip->oob_poi;
10849 +
10850 + pos = eccsize + chunk;
10851 +
10852 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
10853 + len = min_t(int, length, chunk);
10854 + chip->write_buf(mtd, bufpoi, len);
10855 + bufpoi += len;
10856 + length -= len;
10857 + if (length > 0)
10858 + chip->write_buf(mtd, bufpoi, length);
10859 +
10860 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
10861 + status = chip->waitfunc(mtd, chip);
10862 +
10863 + return status & NAND_STATUS_FAIL ? -EIO : 0;
10864 +
10865 +}
10866 +
10867 +/*
10868 + * read oob for small pages
10869 + */
10870 +static int atmel_nand_read_oob_512(struct mtd_info *mtd,
10871 + struct nand_chip *chip, int page, int sndcmd)
10872 +{
10873 + if (sndcmd) {
10874 + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
10875 + sndcmd = 0;
10876 + }
10877 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
10878 + return sndcmd;
10879 +}
10880 +
10881 +/*
10882 + * Calculate HW ECC
10883 + *
10884 + * function called after a write
10885 + *
10886 + * mtd: MTD block structure
10887 + * dat: raw data (unused)
10888 + * ecc_code: buffer for ECC
10889 + */
10890 +static int atmel_nand_calculate(struct mtd_info *mtd,
10891 + const u_char *dat, unsigned char *ecc_code)
10892 +{
10893 + struct nand_chip *nand_chip = mtd->priv;
10894 + struct atmel_nand_host *host = nand_chip->priv;
10895 + uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
10896 + unsigned int ecc_value;
10897 +
10898 + /* get the first 2 ECC bytes */
10899 + ecc_value = ecc_readl(host->ecc, PR);
10900 +
10901 + ecc_code[eccpos[0]] = ecc_value & 0xFF;
10902 + ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;
10903 +
10904 + /* get the last 2 ECC bytes */
10905 + ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
10906 +
10907 + ecc_code[eccpos[2]] = ecc_value & 0xFF;
10908 + ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;
10909 +
10910 + return 0;
10911 +}
10912 +
10913 +/*
10914 + * HW ECC read page function
10915 + *
10916 + * mtd: mtd info structure
10917 + * chip: nand chip info structure
10918 + * buf: buffer to store read data
10919 + */
10920 +static int atmel_nand_read_page(struct mtd_info *mtd,
10921 + struct nand_chip *chip, uint8_t *buf)
10922 +{
10923 + int eccsize = chip->ecc.size;
10924 + int eccbytes = chip->ecc.bytes;
10925 + uint32_t *eccpos = chip->ecc.layout->eccpos;
10926 + uint8_t *p = buf;
10927 + uint8_t *oob = chip->oob_poi;
10928 + uint8_t *ecc_pos;
10929 + int stat;
10930 +
10931 + /*
10932 + * Errata: ALE is incorrectly wired up to the ECC controller
10933 + * on the AP7000, so it will include the address cycles in the
10934 + * ECC calculation.
10935 + *
10936 + * Workaround: Reset the parity registers before reading the
10937 + * actual data.
10938 + */
10939 + if (cpu_is_at32ap7000()) {
10940 + struct atmel_nand_host *host = chip->priv;
10941 + ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
10942 + }
10943 +
10944 + /* read the page */
10945 + chip->read_buf(mtd, p, eccsize);
10946 +
10947 + /* move to ECC position if needed */
10948 + if (eccpos[0] != 0) {
10949 + /* This only works on large pages
10950 + * because the ECC controller waits for
10951 + * NAND_CMD_RNDOUTSTART after the
10952 + * NAND_CMD_RNDOUT.
10953 + * anyway, for small pages, the eccpos[0] == 0
10954 + */
10955 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
10956 + mtd->writesize + eccpos[0], -1);
10957 + }
10958 +
10959 + /* the ECC controller needs to read the ECC just after the data */
10960 + ecc_pos = oob + eccpos[0];
10961 + chip->read_buf(mtd, ecc_pos, eccbytes);
10962 +
10963 + /* check if there's an error */
10964 + stat = chip->ecc.correct(mtd, p, oob, NULL);
10965 +
10966 + if (stat < 0)
10967 + mtd->ecc_stats.failed++;
10968 + else
10969 + mtd->ecc_stats.corrected += stat;
10970 +
10971 + /* get back to oob start (end of page) */
10972 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
10973 +
10974 + /* read the oob */
10975 + chip->read_buf(mtd, oob, mtd->oobsize);
10976 +
10977 + return 0;
10978 +}
10979 +
10980 +/*
10981 + * HW ECC Correction
10982 + *
10983 + * function called after a read
10984 + *
10985 + * mtd: MTD block structure
10986 + * dat: raw data read from the chip
10987 + * read_ecc: ECC from the chip (unused)
10988 + * isnull: unused
10989 + *
10990 + * Detect and correct a 1 bit error for a page
10991 + */
10992 +static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
10993 + u_char *read_ecc, u_char *isnull)
10994 +{
10995 + struct nand_chip *nand_chip = mtd->priv;
10996 + struct atmel_nand_host *host = nand_chip->priv;
10997 + unsigned int ecc_status;
10998 + unsigned int ecc_word, ecc_bit;
10999 +
11000 + /* get the status from the Status Register */
11001 + ecc_status = ecc_readl(host->ecc, SR);
11002 +
11003 + /* if there's no error */
11004 + if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
11005 + return 0;
11006 +
11007 + /* get error bit offset (4 bits) */
11008 + ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
11009 + /* get word address (12 bits) */
11010 + ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
11011 + ecc_word >>= 4;
11012 +
11013 + /* if there are multiple errors */
11014 + if (ecc_status & ATMEL_ECC_MULERR) {
11015 + /* check if it is a freshly erased block
11016 + * (filled with 0xff) */
11017 + if ((ecc_bit == ATMEL_ECC_BITADDR)
11018 + && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
11019 + /* the block has just been erased, return OK */
11020 + return 0;
11021 + }
11022 + /* it doesn't seems to be a freshly
11023 + * erased block.
11024 + * We can't correct so many errors */
11025 + dev_dbg(host->dev, "atmel_nand : multiple errors detected."
11026 + " Unable to correct.\n");
11027 + return -EIO;
11028 + }
11029 +
11030 + /* if there's a single bit error : we can correct it */
11031 + if (ecc_status & ATMEL_ECC_ECCERR) {
11032 + /* there's nothing much to do here.
11033 + * the bit error is on the ECC itself.
11034 + */
11035 + dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
11036 + " Nothing to correct\n");
11037 + return 0;
11038 + }
11039 +
11040 + dev_dbg(host->dev, "atmel_nand : one bit error on data."
11041 + " (word offset in the page :"
11042 + " 0x%x bit offset : 0x%x)\n",
11043 + ecc_word, ecc_bit);
11044 + /* correct the error */
11045 + if (nand_chip->options & NAND_BUSWIDTH_16) {
11046 + /* 16 bits words */
11047 + ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
11048 + } else {
11049 + /* 8 bits words */
11050 + dat[ecc_word] ^= (1 << ecc_bit);
11051 + }
11052 + dev_dbg(host->dev, "atmel_nand : error corrected\n");
11053 + return 1;
11054 +}
11055 +
11056 +/*
11057 + * Enable HW ECC : unused on most chips
11058 + */
11059 +static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
11060 +{
11061 + if (cpu_is_at32ap7000()) {
11062 + struct nand_chip *nand_chip = mtd->priv;
11063 + struct atmel_nand_host *host = nand_chip->priv;
11064 + ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
11065 + }
11066 +}
11067 +
11068 +#ifdef CONFIG_MTD_PARTITIONS
11069 +static const char *part_probes[] = { "cmdlinepart", NULL };
11070 +#endif
11071 +
11072 +/*
11073 + * Probe for the NAND device.
11074 + */
11075 +static int __init atmel_nand_probe(struct platform_device *pdev)
11076 +{
11077 + struct atmel_nand_host *host;
11078 + struct mtd_info *mtd;
11079 + struct nand_chip *nand_chip;
11080 + struct resource *regs;
11081 + struct resource *mem;
11082 + int res;
11083 +
11084 +#ifdef CONFIG_MTD_PARTITIONS
11085 + struct mtd_partition *partitions = NULL;
11086 + int num_partitions = 0;
11087 +#endif
11088 +
11089 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
11090 + if (!mem) {
11091 + printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
11092 + return -ENXIO;
11093 + }
11094 +
11095 + /* Allocate memory for the device structure (and zero it) */
11096 + host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
11097 + if (!host) {
11098 + printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
11099 + return -ENOMEM;
11100 + }
11101 +
11102 + host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
11103 + if (host->io_base == NULL) {
11104 + printk(KERN_ERR "atmel_nand: ioremap failed\n");
11105 + res = -EIO;
11106 + goto err_nand_ioremap;
11107 + }
11108 +
11109 + mtd = &host->mtd;
11110 + nand_chip = &host->nand_chip;
11111 + host->board = pdev->dev.platform_data;
11112 + host->dev = &pdev->dev;
11113 +
11114 + nand_chip->priv = host; /* link the private data structures */
11115 + mtd->priv = nand_chip;
11116 + mtd->owner = THIS_MODULE;
11117 +
11118 + /* Set address of NAND IO lines */
11119 + nand_chip->IO_ADDR_R = host->io_base;
11120 + nand_chip->IO_ADDR_W = host->io_base;
11121 + nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
11122 +
11123 + if (host->board->rdy_pin)
11124 + nand_chip->dev_ready = atmel_nand_device_ready;
11125 +
11126 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
11127 + if (!regs && hard_ecc) {
11128 + printk(KERN_ERR "atmel_nand: can't get I/O resource "
11129 + "regs\nFalling back on software ECC\n");
11130 + }
11131 +
11132 + nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
11133 + if (no_ecc)
11134 + nand_chip->ecc.mode = NAND_ECC_NONE;
11135 + if (hard_ecc && regs) {
11136 + host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
11137 + if (host->ecc == NULL) {
11138 + printk(KERN_ERR "atmel_nand: ioremap failed\n");
11139 + res = -EIO;
11140 + goto err_ecc_ioremap;
11141 + }
11142 + nand_chip->ecc.mode = NAND_ECC_HW_SYNDROME;
11143 + nand_chip->ecc.calculate = atmel_nand_calculate;
11144 + nand_chip->ecc.correct = atmel_nand_correct;
11145 + nand_chip->ecc.hwctl = atmel_nand_hwctl;
11146 + nand_chip->ecc.read_page = atmel_nand_read_page;
11147 + nand_chip->ecc.bytes = 4;
11148 + nand_chip->ecc.prepad = 0;
11149 + nand_chip->ecc.postpad = 0;
11150 + }
11151 +
11152 + nand_chip->chip_delay = 20; /* 20us command delay time */
11153 +
11154 + if (host->board->bus_width_16) { /* 16-bit bus width */
11155 + nand_chip->options |= NAND_BUSWIDTH_16;
11156 + nand_chip->read_buf = atmel_read_buf16;
11157 + nand_chip->write_buf = atmel_write_buf16;
11158 + } else {
11159 + nand_chip->read_buf = atmel_read_buf;
11160 + nand_chip->write_buf = atmel_write_buf;
11161 + }
11162 +
11163 + platform_set_drvdata(pdev, host);
11164 + atmel_nand_enable(host);
11165 +
11166 + if (host->board->det_pin) {
11167 + if (gpio_get_value(host->board->det_pin)) {
11168 + printk("No SmartMedia card inserted.\n");
11169 + res = ENXIO;
11170 + goto err_no_card;
11171 + }
11172 + }
11173 +
11174 + /* first scan to find the device and get the page size */
11175 + if (nand_scan_ident(mtd, 1)) {
11176 + res = -ENXIO;
11177 + goto err_scan_ident;
11178 + }
11179 +
11180 + if (nand_chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
11181 + /* ECC is calculated for the whole page (1 step) */
11182 + nand_chip->ecc.size = mtd->writesize;
11183 +
11184 + /* set ECC page size and oob layout */
11185 + switch (mtd->writesize) {
11186 + case 512:
11187 + nand_chip->ecc.layout = &atmel_oobinfo_small;
11188 + nand_chip->ecc.read_oob = atmel_nand_read_oob_512;
11189 + nand_chip->ecc.write_oob = atmel_nand_write_oob_512;
11190 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
11191 + break;
11192 + case 1024:
11193 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11194 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
11195 + break;
11196 + case 2048:
11197 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11198 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
11199 + break;
11200 + case 4096:
11201 + nand_chip->ecc.layout = &atmel_oobinfo_large;
11202 + ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
11203 + break;
11204 + default:
11205 + /* page size not handled by HW ECC */
11206 + /* switching back to soft ECC */
11207 + nand_chip->ecc.mode = NAND_ECC_SOFT;
11208 + nand_chip->ecc.calculate = NULL;
11209 + nand_chip->ecc.correct = NULL;
11210 + nand_chip->ecc.hwctl = NULL;
11211 + nand_chip->ecc.read_page = NULL;
11212 + nand_chip->ecc.postpad = 0;
11213 + nand_chip->ecc.prepad = 0;
11214 + nand_chip->ecc.bytes = 0;
11215 + break;
11216 + }
11217 + }
11218 +
11219 + /* second phase scan */
11220 + if (nand_scan_tail(mtd)) {
11221 + res = -ENXIO;
11222 + goto err_scan_tail;
11223 + }
11224 +
11225 +#ifdef CONFIG_MTD_PARTITIONS
11226 +#ifdef CONFIG_MTD_CMDLINE_PARTS
11227 + mtd->name = "atmel_nand";
11228 + num_partitions = parse_mtd_partitions(mtd, part_probes,
11229 + &partitions, 0);
11230 +#endif
11231 + if (num_partitions <= 0 && host->board->partition_info)
11232 + partitions = host->board->partition_info(mtd->size,
11233 + &num_partitions);
11234 +
11235 + if ((!partitions) || (num_partitions == 0)) {
11236 + printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
11237 + res = ENXIO;
11238 + goto err_no_partitions;
11239 + }
11240 +
11241 + res = add_mtd_partitions(mtd, partitions, num_partitions);
11242 +#else
11243 + res = add_mtd_device(mtd);
11244 +#endif
11245 +
11246 + if (!res)
11247 + return res;
11248 +
11249 +#ifdef CONFIG_MTD_PARTITIONS
11250 +err_no_partitions:
11251 +#endif
11252 + nand_release(mtd);
11253 +err_scan_tail:
11254 +err_scan_ident:
11255 +err_no_card:
11256 + atmel_nand_disable(host);
11257 + platform_set_drvdata(pdev, NULL);
11258 + if (host->ecc)
11259 + iounmap(host->ecc);
11260 +err_ecc_ioremap:
11261 + iounmap(host->io_base);
11262 +err_nand_ioremap:
11263 + kfree(host);
11264 + return res;
11265 +}
11266 +
11267 +/*
11268 + * Remove a NAND device.
11269 + */
11270 +static int __exit atmel_nand_remove(struct platform_device *pdev)
11271 +{
11272 + struct atmel_nand_host *host = platform_get_drvdata(pdev);
11273 + struct mtd_info *mtd = &host->mtd;
11274 +
11275 + nand_release(mtd);
11276 +
11277 + atmel_nand_disable(host);
11278 +
11279 + if (host->ecc)
11280 + iounmap(host->ecc);
11281 + iounmap(host->io_base);
11282 + kfree(host);
11283 +
11284 + return 0;
11285 +}
11286 +
11287 +static struct platform_driver atmel_nand_driver = {
11288 + .remove = __exit_p(atmel_nand_remove),
11289 + .driver = {
11290 + .name = "atmel_nand",
11291 + .owner = THIS_MODULE,
11292 + },
11293 +};
11294 +
11295 +static int __init atmel_nand_init(void)
11296 +{
11297 + return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
11298 +}
11299 +
11300 +
11301 +static void __exit atmel_nand_exit(void)
11302 +{
11303 + platform_driver_unregister(&atmel_nand_driver);
11304 +}
11305 +
11306 +
11307 +module_init(atmel_nand_init);
11308 +module_exit(atmel_nand_exit);
11309 +
11310 +MODULE_LICENSE("GPL");
11311 +MODULE_AUTHOR("Rick Bronson");
11312 +MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
11313 +MODULE_ALIAS("platform:atmel_nand");
11314 --- /dev/null
11315 +++ b/drivers/mtd/nand/atmel_nand_ecc.h
11316 @@ -0,0 +1,36 @@
11317 +/*
11318 + * Error Corrected Code Controller (ECC) - System peripherals regsters.
11319 + * Based on AT91SAM9260 datasheet revision B.
11320 + *
11321 + * This program is free software; you can redistribute it and/or modify it
11322 + * under the terms of the GNU General Public License as published by the
11323 + * Free Software Foundation; either version 2 of the License, or (at your
11324 + * option) any later version.
11325 + */
11326 +
11327 +#ifndef ATMEL_NAND_ECC_H
11328 +#define ATMEL_NAND_ECC_H
11329 +
11330 +#define ATMEL_ECC_CR 0x00 /* Control register */
11331 +#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
11332 +
11333 +#define ATMEL_ECC_MR 0x04 /* Mode register */
11334 +#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
11335 +#define ATMEL_ECC_PAGESIZE_528 (0)
11336 +#define ATMEL_ECC_PAGESIZE_1056 (1)
11337 +#define ATMEL_ECC_PAGESIZE_2112 (2)
11338 +#define ATMEL_ECC_PAGESIZE_4224 (3)
11339 +
11340 +#define ATMEL_ECC_SR 0x08 /* Status register */
11341 +#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
11342 +#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
11343 +#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
11344 +
11345 +#define ATMEL_ECC_PR 0x0c /* Parity register */
11346 +#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
11347 +#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
11348 +
11349 +#define ATMEL_ECC_NPR 0x10 /* NParity register */
11350 +#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
11351 +
11352 +#endif
11353 --- a/drivers/mtd/nand/bf5xx_nand.c
11354 +++ b/drivers/mtd/nand/bf5xx_nand.c
11355 @@ -803,3 +803,4 @@
11356 MODULE_LICENSE("GPL");
11357 MODULE_AUTHOR(DRV_AUTHOR);
11358 MODULE_DESCRIPTION(DRV_DESC);
11359 +MODULE_ALIAS("platform:" DRV_NAME);
11360 --- a/drivers/mtd/nand/Kconfig
11361 +++ b/drivers/mtd/nand/Kconfig
11362 @@ -272,12 +272,54 @@
11363
11364 If you say "m", the module will be called "cs553x_nand.ko".
11365
11366 -config MTD_NAND_AT91
11367 - bool "Support for NAND Flash / SmartMedia on AT91"
11368 - depends on ARCH_AT91
11369 +config MTD_NAND_ATMEL
11370 + bool "Support for NAND Flash / SmartMedia on AT91 and AVR32"
11371 + depends on ARCH_AT91 || AVR32
11372 help
11373 Enables support for NAND Flash / Smart Media Card interface
11374 - on Atmel AT91 processors.
11375 + on Atmel AT91 and AVR32 processors.
11376 +choice
11377 + prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32"
11378 + depends on MTD_NAND_ATMEL
11379 +
11380 +config MTD_NAND_ATMEL_ECC_HW
11381 + bool "Hardware ECC"
11382 + depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32
11383 + help
11384 + Use hardware ECC instead of software ECC when the chip
11385 + supports it.
11386 +
11387 + The hardware ECC controller is capable of single bit error
11388 + correction and 2-bit random detection per page.
11389 +
11390 + NB : hardware and software ECC schemes are incompatible.
11391 + If you switch from one to another, you'll have to erase your
11392 + mtd partition.
11393 +
11394 + If unsure, say Y
11395 +
11396 +config MTD_NAND_ATMEL_ECC_SOFT
11397 + bool "Software ECC"
11398 + help
11399 + Use software ECC.
11400 +
11401 + NB : hardware and software ECC schemes are incompatible.
11402 + If you switch from one to another, you'll have to erase your
11403 + mtd partition.
11404 +
11405 +config MTD_NAND_ATMEL_ECC_NONE
11406 + bool "No ECC (testing only, DANGEROUS)"
11407 + depends on DEBUG_KERNEL
11408 + help
11409 + No ECC will be used.
11410 + It's not a good idea and it should be reserved for testing
11411 + purpose only.
11412 +
11413 + If unsure, say N
11414 +
11415 + endchoice
11416 +
11417 +endchoice
11418
11419 config MTD_NAND_CM_X270
11420 tristate "Support for NAND Flash on CM-X270 modules"
11421 --- a/drivers/mtd/nand/Makefile
11422 +++ b/drivers/mtd/nand/Makefile
11423 @@ -24,7 +24,7 @@
11424 obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
11425 obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
11426 obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
11427 -obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o
11428 +obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
11429 obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
11430 obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
11431 obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
11432 --- a/drivers/mtd/nand/ndfc.c
11433 +++ b/drivers/mtd/nand/ndfc.c
11434 @@ -317,3 +317,5 @@
11435 MODULE_LICENSE("GPL");
11436 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
11437 MODULE_DESCRIPTION("Platform driver for NDFC");
11438 +MODULE_ALIAS("platform:ndfc-chip");
11439 +MODULE_ALIAS("platform:ndfc-nand");
11440 --- a/drivers/mtd/nand/orion_nand.c
11441 +++ b/drivers/mtd/nand/orion_nand.c
11442 @@ -169,3 +169,4 @@
11443 MODULE_LICENSE("GPL");
11444 MODULE_AUTHOR("Tzachi Perelstein");
11445 MODULE_DESCRIPTION("NAND glue for Orion platforms");
11446 +MODULE_ALIAS("platform:orion_nand");
11447 --- a/drivers/mtd/nand/plat_nand.c
11448 +++ b/drivers/mtd/nand/plat_nand.c
11449 @@ -161,3 +161,4 @@
11450 MODULE_LICENSE("GPL");
11451 MODULE_AUTHOR("Vitaly Wool");
11452 MODULE_DESCRIPTION("Simple generic NAND driver");
11453 +MODULE_ALIAS("platform:gen_nand");
11454 --- a/drivers/mtd/nand/s3c2410.c
11455 +++ b/drivers/mtd/nand/s3c2410.c
11456 @@ -927,3 +927,6 @@
11457 MODULE_LICENSE("GPL");
11458 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
11459 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
11460 +MODULE_ALIAS("platform:s3c2410-nand");
11461 +MODULE_ALIAS("platform:s3c2412-nand");
11462 +MODULE_ALIAS("platform:s3c2440-nand");
11463 --- a/drivers/net/macb.c
11464 +++ b/drivers/net/macb.c
11465 @@ -1277,8 +1277,45 @@
11466 return 0;
11467 }
11468
11469 +#ifdef CONFIG_PM
11470 +static int macb_suspend(struct platform_device *pdev, pm_message_t state)
11471 +{
11472 + struct net_device *netdev = platform_get_drvdata(pdev);
11473 + struct macb *bp = netdev_priv(netdev);
11474 +
11475 + netif_device_detach(netdev);
11476 +
11477 +#ifndef CONFIG_ARCH_AT91
11478 + clk_disable(bp->hclk);
11479 +#endif
11480 + clk_disable(bp->pclk);
11481 +
11482 + return 0;
11483 +}
11484 +
11485 +static int macb_resume(struct platform_device *pdev)
11486 +{
11487 + struct net_device *netdev = platform_get_drvdata(pdev);
11488 + struct macb *bp = netdev_priv(netdev);
11489 +
11490 + clk_enable(bp->pclk);
11491 +#ifndef CONFIG_ARCH_AT91
11492 + clk_enable(bp->hclk);
11493 +#endif
11494 +
11495 + netif_device_attach(netdev);
11496 +
11497 + return 0;
11498 +}
11499 +#else
11500 +#define macb_suspend NULL
11501 +#define macb_resume NULL
11502 +#endif
11503 +
11504 static struct platform_driver macb_driver = {
11505 .remove = __exit_p(macb_remove),
11506 + .suspend = macb_suspend,
11507 + .resume = macb_resume,
11508 .driver = {
11509 .name = "macb",
11510 },
11511 --- a/drivers/parport/Kconfig
11512 +++ b/drivers/parport/Kconfig
11513 @@ -36,7 +36,7 @@
11514 config PARPORT_PC
11515 tristate "PC-style hardware"
11516 depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
11517 - (!M68K || ISA) && !MN10300
11518 + (!M68K || ISA) && !MN10300 && !AVR32
11519 ---help---
11520 You should say Y here if you have a PC-style parallel port. All
11521 IBM PC compatible computers and some Alphas have PC-style
11522 --- /dev/null
11523 +++ b/drivers/pcmcia/at32_cf.c
11524 @@ -0,0 +1,533 @@
11525 +/*
11526 + * Driver for AVR32 Static Memory Controller: CompactFlash support
11527 + *
11528 + * Copyright (C) 2006 Atmel Norway
11529 + *
11530 + * This program is free software; you can redistribute it and/or
11531 + * modify it under the terms of the GNU General Public License as
11532 + * published by the Free Software Foundation; either version 2 of the
11533 + * License, or (at your option) any later version.
11534 + *
11535 + * This program is distributed in the hope that it will be useful, but
11536 + * WITHOUT ANY WARRANTY; without even the implied warranty of
11537 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11538 + * General Public License for more details.
11539 + *
11540 + * You should have received a copy of the GNU General Public License
11541 + * along with this program; if not, write to the Free Software
11542 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
11543 + * 02111-1307, USA.
11544 + *
11545 + * The full GNU General Public License is included in this
11546 + * distribution in the file called COPYING.
11547 + */
11548 +#include <linux/module.h>
11549 +#include <linux/kernel.h>
11550 +#include <linux/platform_device.h>
11551 +#include <linux/init.h>
11552 +#include <linux/device.h>
11553 +#include <linux/delay.h>
11554 +#include <linux/interrupt.h>
11555 +#include <linux/err.h>
11556 +#include <linux/clk.h>
11557 +#include <linux/dma-mapping.h>
11558 +
11559 +#include <pcmcia/ss.h>
11560 +
11561 +#include <asm/gpio.h>
11562 +#include <asm/io.h>
11563 +#include <asm/arch/board.h>
11564 +
11565 +#include <asm/arch/smc.h>
11566 +
11567 +struct at32_cf_socket {
11568 + struct pcmcia_socket socket;
11569 + int detect_pin;
11570 + int reset_pin;
11571 + int vcc_pin;
11572 + int ready_pin;
11573 + struct resource res_attr;
11574 + struct resource res_mem;
11575 + struct resource res_io;
11576 + struct smc_config smc;
11577 + unsigned int irq;
11578 + unsigned int cf_cs;
11579 + socket_state_t state;
11580 + unsigned present:1;
11581 +};
11582 +#define to_at32_cf(sock) container_of(sock, struct at32_cf_socket, socket)
11583 +
11584 +/*
11585 + * We have the following memory layout relative to the base address:
11586 + *
11587 + * Alt IDE Mode: 00e0 0000 -> 00ff ffff
11588 + * True IDE Mode: 00c0 0000 -> 00df ffff
11589 + * I/O memory: 0080 0000 -> 00bf ffff
11590 + * Common memory: 0040 0000 -> 007f ffff
11591 + * Attribute memory: 0000 0000 -> 003f ffff
11592 + */
11593 +#define CF_ATTR_OFFSET 0x00000000
11594 +#define CF_MEM_OFFSET 0x00400000
11595 +#define CF_IO_OFFSET 0x00800000
11596 +#define CF_RES_SIZE 4096
11597 +
11598 +#ifdef DEBUG
11599 +
11600 +static int pc_debug;
11601 +module_param(pc_debug, int, 0644);
11602 +
11603 +static void at32_cf_debug(struct at32_cf_socket *cf, const char *func,
11604 + int level, const char *fmt, ...)
11605 +{
11606 + va_list args;
11607 +
11608 + if (pc_debug > level) {
11609 + printk(KERN_DEBUG "at32_cf/%u: %s: ", cf->cf_cs, func);
11610 + va_start(args, fmt);
11611 + vprintk(fmt, args);
11612 + va_end(args);
11613 + }
11614 +}
11615 +
11616 +#define debug(cf, lvl, fmt, arg...) \
11617 + at32_cf_debug(cf, __func__, lvl, fmt, ##arg)
11618 +
11619 +#else
11620 +#define debug(cf, lvl, fmt, arg...) do { } while (0)
11621 +#endif
11622 +
11623 +static inline int at32_cf_present(struct at32_cf_socket *cf)
11624 +{
11625 + int present = 1;
11626 +
11627 + /* If we don't have a detect pin, assume the card is present */
11628 + if (cf->detect_pin >= 0)
11629 + present = !gpio_get_value(cf->detect_pin);
11630 +
11631 + return present;
11632 +}
11633 +
11634 +static irqreturn_t at32_cf_irq(int irq, void *dev_id)
11635 +{
11636 + struct at32_cf_socket *cf = dev_id;
11637 + unsigned int present;
11638 +
11639 + present = at32_cf_present(cf);
11640 + if (present != cf->present) {
11641 + cf->present = present;
11642 + debug(cf, 3, "card %s\n", present ? "present" : "gone");
11643 + pcmcia_parse_events(&cf->socket, SS_DETECT);
11644 + }
11645 +
11646 + return IRQ_HANDLED;
11647 +}
11648 +
11649 +static int at32_cf_get_status(struct pcmcia_socket *sock, u_int *value)
11650 +{
11651 + struct at32_cf_socket *cf;
11652 + u_int status = 0;
11653 +
11654 + cf = container_of(sock, struct at32_cf_socket, socket);
11655 +
11656 + if (at32_cf_present(cf)) {
11657 + /* NOTE: gpio on AP7xxx is 3.3V */
11658 + status = SS_DETECT | SS_3VCARD;
11659 + if (cf->ready_pin < 0 || gpio_get_value(cf->ready_pin))
11660 + status |= SS_READY;
11661 + if (cf->vcc_pin < 0 || gpio_get_value(cf->vcc_pin))
11662 + status |= SS_POWERON;
11663 + }
11664 +
11665 + *value = status;
11666 + return 0;
11667 +}
11668 +
11669 +static int at32_cf_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
11670 +{
11671 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
11672 +
11673 + debug(cf, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
11674 + (state->csc_mask==0)?"<NONE> ":"",
11675 + (state->csc_mask&SS_DETECT)?"DETECT ":"",
11676 + (state->csc_mask&SS_READY)?"READY ":"",
11677 + (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
11678 + (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
11679 + (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
11680 + (state->flags==0)?"<NONE> ":"",
11681 + (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
11682 + (state->flags&SS_IOCARD)?"IOCARD ":"",
11683 + (state->flags&SS_RESET)?"RESET ":"",
11684 + (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
11685 + (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
11686 + state->Vcc, state->Vpp, state->io_irq);
11687 +
11688 + /*
11689 + * TODO: Allow boards to override this in case they have level
11690 + * converters.
11691 + */
11692 + switch (state->Vcc) {
11693 + case 0:
11694 + if (cf->vcc_pin >= 0)
11695 + gpio_set_value(cf->vcc_pin, 0);
11696 + break;
11697 + case 33:
11698 + if (cf->vcc_pin >= 0)
11699 + gpio_set_value(cf->vcc_pin, 1);
11700 + break;
11701 + default:
11702 + return -EINVAL;
11703 + }
11704 +
11705 + if (cf->reset_pin >= 0)
11706 + gpio_set_value(cf->reset_pin, state->flags & SS_RESET);
11707 +
11708 + cf->state = *state;
11709 +
11710 + return 0;
11711 +}
11712 +
11713 +static int at32_cf_socket_init(struct pcmcia_socket *sock)
11714 +{
11715 + debug(to_at32_cf(sock), 2, "called\n");
11716 +
11717 + return 0;
11718 +}
11719 +
11720 +static int at32_cf_suspend(struct pcmcia_socket *sock)
11721 +{
11722 + debug(to_at32_cf(sock), 2, "called\n");
11723 +
11724 + at32_cf_set_socket(sock, &dead_socket);
11725 +
11726 + return 0;
11727 +}
11728 +
11729 +static int at32_cf_set_io_map(struct pcmcia_socket *sock,
11730 + struct pccard_io_map *map)
11731 +{
11732 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
11733 + int retval;
11734 +
11735 + debug(cf, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
11736 + map->map, map->speed, map->start, map->stop);
11737 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
11738 + (map->flags == 0) ? "<NONE>":"",
11739 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
11740 + (map->flags & MAP_16BIT) ? "16BIT " : "",
11741 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
11742 + (map->flags & MAP_0WS) ? "0WS " : "",
11743 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
11744 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
11745 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
11746 +
11747 + map->flags &= MAP_ACTIVE | MAP_16BIT | MAP_USE_WAIT;
11748 +
11749 + if (map->flags & MAP_16BIT)
11750 + cf->smc.bus_width = 2;
11751 + else
11752 + cf->smc.bus_width = 1;
11753 +
11754 + if (map->flags & MAP_USE_WAIT)
11755 + cf->smc.nwait_mode = 3;
11756 + else
11757 + cf->smc.nwait_mode = 0;
11758 +
11759 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
11760 + if (retval) {
11761 + printk(KERN_ERR "at32_cf: could not set up SMC for I/O\n");
11762 + return retval;
11763 + }
11764 +
11765 + map->start = cf->socket.io_offset;
11766 + map->stop = map->start + CF_RES_SIZE - 1;
11767 +
11768 + return 0;
11769 +}
11770 +
11771 +static int
11772 +at32_cf_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
11773 +{
11774 + struct at32_cf_socket *cf;
11775 + struct resource *res;
11776 + int retval;
11777 +
11778 + cf = container_of(sock, struct at32_cf_socket, socket);
11779 +
11780 + debug(cf, 2, "map %u speed %u card_start %08x\n",
11781 + map->map, map->speed, map->card_start);
11782 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
11783 + (map->flags==0)?"<NONE>":"",
11784 + (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
11785 + (map->flags&MAP_16BIT)?"16BIT ":"",
11786 + (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
11787 + (map->flags&MAP_0WS)?"0WS ":"",
11788 + (map->flags&MAP_WRPROT)?"WRPROT ":"",
11789 + (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
11790 + (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
11791 +
11792 + if (map->card_start)
11793 + return -EINVAL;
11794 +
11795 + map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT | MAP_USE_WAIT;
11796 +
11797 + if (map->flags & MAP_ATTRIB) {
11798 + res = &cf->res_attr;
11799 +
11800 + /* Linksys WCF12 seems to use WAIT when reading CIS */
11801 + map->flags |= MAP_USE_WAIT;
11802 + } else {
11803 + res = &cf->res_mem;
11804 + }
11805 +
11806 + if (map->flags & MAP_USE_WAIT)
11807 + cf->smc.nwait_mode = 3;
11808 + else
11809 + cf->smc.nwait_mode = 0;
11810 +
11811 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
11812 + if (retval) {
11813 + printk(KERN_ERR "at32_cf: could not set up SMC for mem\n");
11814 + return retval;
11815 + }
11816 +
11817 + map->static_start = res->start;
11818 +
11819 + return 0;
11820 +}
11821 +
11822 +static struct pccard_operations at32_cf_ops = {
11823 + .init = at32_cf_socket_init,
11824 + .suspend = at32_cf_suspend,
11825 + .get_status = at32_cf_get_status,
11826 + .set_socket = at32_cf_set_socket,
11827 + .set_io_map = at32_cf_set_io_map,
11828 + .set_mem_map = at32_cf_set_mem_map,
11829 +};
11830 +
11831 +static int __init request_pin(struct platform_device *pdev,
11832 + unsigned int pin, const char *name)
11833 +{
11834 + if (gpio_request(pin, name)) {
11835 + dev_warn(&pdev->dev, "failed to request %s pin\n", name);
11836 + return -1;
11837 + }
11838 +
11839 + return pin;
11840 +}
11841 +
11842 +static struct smc_timing at32_cf_timing __initdata = {
11843 + .ncs_read_setup = 30,
11844 + .nrd_setup = 100,
11845 + .ncs_write_setup = 30,
11846 + .nwe_setup = 100,
11847 +
11848 + .ncs_read_pulse = 360,
11849 + .nrd_pulse = 290,
11850 + .ncs_write_pulse = 360,
11851 + .nwe_pulse = 290,
11852 +
11853 + .read_cycle = 420,
11854 + .write_cycle = 420,
11855 +};
11856 +
11857 +static int __init at32_cf_probe(struct platform_device *pdev)
11858 +{
11859 + struct at32_cf_socket *cf;
11860 + struct cf_platform_data *board = pdev->dev.platform_data;
11861 + struct resource *res_skt;
11862 + int irq;
11863 + int ret;
11864 +
11865 + dev_dbg(&pdev->dev, "probe");
11866 +
11867 + if (!board)
11868 + return -ENXIO;
11869 +
11870 + res_skt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
11871 + if (!res_skt)
11872 + return -ENXIO;
11873 +
11874 + irq = platform_get_irq(pdev, 0);
11875 + if (irq < 0)
11876 + return irq;
11877 +
11878 + cf = kzalloc(sizeof(struct at32_cf_socket), GFP_KERNEL);
11879 + if (!cf)
11880 + return -ENOMEM;
11881 +
11882 + cf->detect_pin = -1;
11883 + cf->reset_pin = -1;
11884 + cf->vcc_pin = -1;
11885 + cf->ready_pin = -1;
11886 + cf->cf_cs = board->cs;
11887 +
11888 + if (board->detect_pin != GPIO_PIN_NONE)
11889 + cf->detect_pin = request_pin(pdev, board->detect_pin,
11890 + "cf_detect");
11891 + if (board->reset_pin != GPIO_PIN_NONE)
11892 + cf->reset_pin = request_pin(pdev, board->reset_pin,
11893 + "cf_reset");
11894 + if (board->vcc_pin != GPIO_PIN_NONE)
11895 + cf->vcc_pin = request_pin(pdev, board->vcc_pin,
11896 + "cf_vcc");
11897 + if (board->ready_pin != GPIO_PIN_NONE)
11898 + /* READY is also used for irq through EIM */
11899 + cf->ready_pin = board->ready_pin;
11900 +
11901 + debug(cf, 2, "pins: detect=%d reset=%d vcc=%d\n",
11902 + cf->detect_pin, cf->reset_pin, cf->vcc_pin);
11903 +
11904 + cf->socket.pci_irq = irq;
11905 + cf->socket.ops = &at32_cf_ops;
11906 + cf->socket.resource_ops = &pccard_static_ops;
11907 + cf->socket.dev.parent = &pdev->dev;
11908 + cf->socket.owner = THIS_MODULE;
11909 + cf->socket.features =
11910 + SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
11911 + cf->socket.map_size = CF_RES_SIZE;
11912 +
11913 + cf->res_attr.start = res_skt->start + CF_ATTR_OFFSET;
11914 + cf->res_attr.end = cf->res_attr.start + CF_RES_SIZE - 1;
11915 + cf->res_attr.name = "attribute";
11916 + cf->res_attr.flags = IORESOURCE_MEM;
11917 + ret = request_resource(res_skt, &cf->res_attr);
11918 + if (ret)
11919 + goto err_request_res_attr;
11920 +
11921 + cf->res_mem.start = res_skt->start + CF_MEM_OFFSET;
11922 + cf->res_mem.end = cf->res_mem.start + CF_RES_SIZE - 1;
11923 + cf->res_mem.name = "memory";
11924 + cf->res_mem.flags = IORESOURCE_MEM;
11925 + ret = request_resource(res_skt, &cf->res_mem);
11926 + if (ret)
11927 + goto err_request_res_mem;
11928 +
11929 + cf->res_io.start = res_skt->start + CF_IO_OFFSET;
11930 + cf->res_io.end = cf->res_io.start + CF_RES_SIZE - 1;
11931 + cf->res_io.name = "io";
11932 + cf->res_io.flags = IORESOURCE_MEM;
11933 + ret = request_resource(res_skt, &cf->res_io);
11934 + if (ret)
11935 + goto err_request_res_io;
11936 +
11937 + cf->socket.io_offset = cf->res_io.start;
11938 +
11939 + if (cf->detect_pin >= 0) {
11940 + ret = request_irq(gpio_to_irq(cf->detect_pin), at32_cf_irq,
11941 + IRQF_SHARED, "cf_detect", cf);
11942 + if (ret) {
11943 + debug(cf, 1,
11944 + "failed to request cf_detect interrupt\n");
11945 + goto err_detect_irq;
11946 + }
11947 + }
11948 +
11949 + cf->present = at32_cf_present(cf);
11950 +
11951 + /* Setup SMC timings */
11952 + smc_set_timing(&cf->smc, &at32_cf_timing);
11953 +
11954 + cf->smc.bus_width = 2;
11955 + cf->smc.nrd_controlled = 1;
11956 + cf->smc.nwe_controlled = 1;
11957 + cf->smc.nwait_mode = 0;
11958 + cf->smc.byte_write = 0;
11959 + cf->smc.tdf_cycles = 8;
11960 + cf->smc.tdf_mode = 0;
11961 +
11962 + ret = smc_set_configuration(cf->cf_cs, &cf->smc);
11963 + if (ret) {
11964 + debug(cf, 1, "failed to configure SMC\n", ret);
11965 + goto err_smc;
11966 + }
11967 +
11968 + ret = pcmcia_register_socket(&cf->socket);
11969 + if (ret) {
11970 + debug(cf, 1, "failed to register socket: %d\n", ret);
11971 + goto err_register_socket;
11972 + }
11973 +
11974 + if (cf->reset_pin >= 0)
11975 + gpio_direction_output(cf->reset_pin, 0);
11976 +
11977 + platform_set_drvdata(pdev, cf);
11978 +
11979 + dev_info(&pdev->dev, "Atmel SMC CF interface at 0x%08lx\n",
11980 + (unsigned long)res_skt->start);
11981 +
11982 + return 0;
11983 +
11984 +err_register_socket:
11985 +err_smc:
11986 + if (cf->detect_pin >= 0)
11987 + free_irq(gpio_to_irq(cf->detect_pin), cf);
11988 +err_detect_irq:
11989 + release_resource(&cf->res_io);
11990 +err_request_res_io:
11991 + release_resource(&cf->res_mem);
11992 +err_request_res_mem:
11993 + release_resource(&cf->res_attr);
11994 +err_request_res_attr:
11995 + if (cf->vcc_pin >= 0)
11996 + gpio_free(cf->vcc_pin);
11997 + if (cf->reset_pin >= 0)
11998 + gpio_free(cf->reset_pin);
11999 + if (cf->detect_pin >= 0)
12000 + gpio_free(cf->detect_pin);
12001 + kfree(cf);
12002 +
12003 + return ret;
12004 +}
12005 +
12006 +static int __exit at32_cf_remove(struct platform_device *pdev)
12007 +{
12008 + struct at32_cf_socket *cf = platform_get_drvdata(pdev);
12009 +
12010 + pcmcia_unregister_socket(&cf->socket);
12011 + if (cf->detect_pin >= 0) {
12012 + free_irq(gpio_to_irq(cf->detect_pin), cf);
12013 + gpio_free(cf->detect_pin);
12014 + }
12015 + if (cf->vcc_pin >= 0)
12016 + gpio_free(cf->vcc_pin);
12017 + if (cf->reset_pin >= 0)
12018 + gpio_free(cf->reset_pin);
12019 +
12020 + release_resource(&cf->res_io);
12021 + release_resource(&cf->res_mem);
12022 + release_resource(&cf->res_attr);
12023 + kfree(cf);
12024 + platform_set_drvdata(pdev, NULL);
12025 +
12026 + return 0;
12027 +}
12028 +
12029 +static struct platform_driver at32_cf_driver = {
12030 + .remove = __exit_p(at32_cf_remove),
12031 + .driver = {
12032 + .name = "at32_cf",
12033 + .owner = THIS_MODULE,
12034 + },
12035 +};
12036 +
12037 +static int __init at32_cf_init(void)
12038 +{
12039 + int ret;
12040 +
12041 + ret = platform_driver_probe(&at32_cf_driver, at32_cf_probe);
12042 + if (ret)
12043 + printk(KERN_ERR "at32_cf: probe failed: %d\n", ret);
12044 + return ret;
12045 +}
12046 +
12047 +static void __exit at32_cf_exit(void)
12048 +{
12049 + platform_driver_unregister(&at32_cf_driver);
12050 +}
12051 +
12052 +module_init(at32_cf_init);
12053 +module_exit(at32_cf_exit);
12054 +
12055 +MODULE_LICENSE("GPL");
12056 +MODULE_DESCRIPTION("Driver for SMC PCMCIA interface");
12057 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
12058 --- a/drivers/pcmcia/Kconfig
12059 +++ b/drivers/pcmcia/Kconfig
12060 @@ -277,6 +277,13 @@
12061 Say Y here to support the CompactFlash controller on the
12062 PA Semi Electra eval board.
12063
12064 +config AT32_CF
12065 + tristate "AT32AP CompactFlash Controller"
12066 + depends on PCMCIA && AVR32 && PLATFORM_AT32AP
12067 + help
12068 + Say Y here to support the CompactFlash controller on AT32 chips.
12069 + Or choose M to compile the driver as a module named "at32_cf".
12070 +
12071 config PCCARD_NONSTATIC
12072 tristate
12073
12074 --- a/drivers/pcmcia/Makefile
12075 +++ b/drivers/pcmcia/Makefile
12076 @@ -38,6 +38,7 @@
12077 obj-$(CONFIG_OMAP_CF) += omap_cf.o
12078 obj-$(CONFIG_AT91_CF) += at91_cf.o
12079 obj-$(CONFIG_ELECTRA_CF) += electra_cf.o
12080 +obj-$(CONFIG_AT32_CF) += at32_cf.o
12081
12082 sa11xx_core-y += soc_common.o sa11xx_base.o
12083 pxa2xx_core-y += soc_common.o pxa2xx_base.o
12084 --- a/drivers/serial/atmel_serial.c
12085 +++ b/drivers/serial/atmel_serial.c
12086 @@ -1440,6 +1440,15 @@
12087 };
12088
12089 #ifdef CONFIG_PM
12090 +static bool atmel_serial_clk_will_stop(void)
12091 +{
12092 +#ifdef CONFIG_ARCH_AT91
12093 + return at91_suspend_entering_slow_clock();
12094 +#else
12095 + return false;
12096 +#endif
12097 +}
12098 +
12099 static int atmel_serial_suspend(struct platform_device *pdev,
12100 pm_message_t state)
12101 {
12102 @@ -1447,7 +1456,7 @@
12103 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
12104
12105 if (device_may_wakeup(&pdev->dev)
12106 - && !at91_suspend_entering_slow_clock())
12107 + && !atmel_serial_clk_will_stop())
12108 enable_irq_wake(port->irq);
12109 else {
12110 uart_suspend_port(&atmel_uart, port);
12111 --- a/drivers/spi/atmel_spi.c
12112 +++ b/drivers/spi/atmel_spi.c
12113 @@ -51,9 +51,7 @@
12114 u8 stopping;
12115 struct list_head queue;
12116 struct spi_transfer *current_transfer;
12117 - unsigned long current_remaining_bytes;
12118 - struct spi_transfer *next_transfer;
12119 - unsigned long next_remaining_bytes;
12120 + unsigned long remaining_bytes;
12121
12122 void *buffer;
12123 dma_addr_t buffer_dma;
12124 @@ -133,48 +131,6 @@
12125 gpio_set_value(gpio, !active);
12126 }
12127
12128 -static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
12129 - struct spi_transfer *xfer)
12130 -{
12131 - return msg->transfers.prev == &xfer->transfer_list;
12132 -}
12133 -
12134 -static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
12135 -{
12136 - return xfer->delay_usecs == 0 && !xfer->cs_change;
12137 -}
12138 -
12139 -static void atmel_spi_next_xfer_data(struct spi_master *master,
12140 - struct spi_transfer *xfer,
12141 - dma_addr_t *tx_dma,
12142 - dma_addr_t *rx_dma,
12143 - u32 *plen)
12144 -{
12145 - struct atmel_spi *as = spi_master_get_devdata(master);
12146 - u32 len = *plen;
12147 -
12148 - /* use scratch buffer only when rx or tx data is unspecified */
12149 - if (xfer->rx_buf)
12150 - *rx_dma = xfer->rx_dma + xfer->len - len;
12151 - else {
12152 - *rx_dma = as->buffer_dma;
12153 - if (len > BUFFER_SIZE)
12154 - len = BUFFER_SIZE;
12155 - }
12156 - if (xfer->tx_buf)
12157 - *tx_dma = xfer->tx_dma + xfer->len - len;
12158 - else {
12159 - *tx_dma = as->buffer_dma;
12160 - if (len > BUFFER_SIZE)
12161 - len = BUFFER_SIZE;
12162 - memset(as->buffer, 0, len);
12163 - dma_sync_single_for_device(&as->pdev->dev,
12164 - as->buffer_dma, len, DMA_TO_DEVICE);
12165 - }
12166 -
12167 - *plen = len;
12168 -}
12169 -
12170 /*
12171 * Submit next transfer for DMA.
12172 * lock is held, spi irq is blocked
12173 @@ -184,78 +140,53 @@
12174 {
12175 struct atmel_spi *as = spi_master_get_devdata(master);
12176 struct spi_transfer *xfer;
12177 - u32 len, remaining, total;
12178 + u32 len;
12179 dma_addr_t tx_dma, rx_dma;
12180
12181 - if (!as->current_transfer)
12182 - xfer = list_entry(msg->transfers.next,
12183 - struct spi_transfer, transfer_list);
12184 - else if (!as->next_transfer)
12185 - xfer = list_entry(as->current_transfer->transfer_list.next,
12186 - struct spi_transfer, transfer_list);
12187 - else
12188 - xfer = NULL;
12189 -
12190 - if (xfer) {
12191 - len = xfer->len;
12192 - atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
12193 - remaining = xfer->len - len;
12194 -
12195 - spi_writel(as, RPR, rx_dma);
12196 - spi_writel(as, TPR, tx_dma);
12197 -
12198 - if (msg->spi->bits_per_word > 8)
12199 - len >>= 1;
12200 - spi_writel(as, RCR, len);
12201 - spi_writel(as, TCR, len);
12202 -
12203 - dev_dbg(&msg->spi->dev,
12204 - " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
12205 - xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
12206 - xfer->rx_buf, xfer->rx_dma);
12207 - } else {
12208 - xfer = as->next_transfer;
12209 - remaining = as->next_remaining_bytes;
12210 + xfer = as->current_transfer;
12211 + if (!xfer || as->remaining_bytes == 0) {
12212 + if (xfer)
12213 + xfer = list_entry(xfer->transfer_list.next,
12214 + struct spi_transfer, transfer_list);
12215 + else
12216 + xfer = list_entry(msg->transfers.next,
12217 + struct spi_transfer, transfer_list);
12218 + as->remaining_bytes = xfer->len;
12219 + as->current_transfer = xfer;
12220 }
12221
12222 - as->current_transfer = xfer;
12223 - as->current_remaining_bytes = remaining;
12224 -
12225 - if (remaining > 0)
12226 - len = remaining;
12227 - else if (!atmel_spi_xfer_is_last(msg, xfer)
12228 - && atmel_spi_xfer_can_be_chained(xfer)) {
12229 - xfer = list_entry(xfer->transfer_list.next,
12230 - struct spi_transfer, transfer_list);
12231 - len = xfer->len;
12232 - } else
12233 - xfer = NULL;
12234 + len = as->remaining_bytes;
12235
12236 - as->next_transfer = xfer;
12237 + tx_dma = xfer->tx_dma + xfer->len - len;
12238 + rx_dma = xfer->rx_dma + xfer->len - len;
12239
12240 - if (xfer) {
12241 - total = len;
12242 - atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
12243 - as->next_remaining_bytes = total - len;
12244 -
12245 - spi_writel(as, RNPR, rx_dma);
12246 - spi_writel(as, TNPR, tx_dma);
12247 -
12248 - if (msg->spi->bits_per_word > 8)
12249 - len >>= 1;
12250 - spi_writel(as, RNCR, len);
12251 - spi_writel(as, TNCR, len);
12252 -
12253 - dev_dbg(&msg->spi->dev,
12254 - " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
12255 - xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
12256 - xfer->rx_buf, xfer->rx_dma);
12257 - } else {
12258 - spi_writel(as, RNCR, 0);
12259 - spi_writel(as, TNCR, 0);
12260 + /* use scratch buffer only when rx or tx data is unspecified */
12261 + if (!xfer->rx_buf) {
12262 + rx_dma = as->buffer_dma;
12263 + if (len > BUFFER_SIZE)
12264 + len = BUFFER_SIZE;
12265 }
12266 + if (!xfer->tx_buf) {
12267 + tx_dma = as->buffer_dma;
12268 + if (len > BUFFER_SIZE)
12269 + len = BUFFER_SIZE;
12270 + memset(as->buffer, 0, len);
12271 + dma_sync_single_for_device(&as->pdev->dev,
12272 + as->buffer_dma, len, DMA_TO_DEVICE);
12273 + }
12274 +
12275 + spi_writel(as, RPR, rx_dma);
12276 + spi_writel(as, TPR, tx_dma);
12277
12278 - /* REVISIT: We're waiting for ENDRX before we start the next
12279 + as->remaining_bytes -= len;
12280 + if (msg->spi->bits_per_word > 8)
12281 + len >>= 1;
12282 +
12283 + /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
12284 + * mechanism might help avoid the IRQ latency between transfers
12285 + * (and improve the nCS0 errata handling on at91rm9200 chips)
12286 + *
12287 + * We're also waiting for ENDRX before we start the next
12288 * transfer because we need to handle some difficult timing
12289 * issues otherwise. If we wait for ENDTX in one transfer and
12290 * then starts waiting for ENDRX in the next, it's difficult
12291 @@ -265,7 +196,17 @@
12292 *
12293 * It should be doable, though. Just not now...
12294 */
12295 + spi_writel(as, TNCR, 0);
12296 + spi_writel(as, RNCR, 0);
12297 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
12298 +
12299 + dev_dbg(&msg->spi->dev,
12300 + " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
12301 + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
12302 + xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
12303 +
12304 + spi_writel(as, RCR, len);
12305 + spi_writel(as, TCR, len);
12306 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
12307 }
12308
12309 @@ -363,7 +304,6 @@
12310 spin_lock(&as->lock);
12311
12312 as->current_transfer = NULL;
12313 - as->next_transfer = NULL;
12314
12315 /* continue if needed */
12316 if (list_empty(&as->queue) || as->stopping)
12317 @@ -447,7 +387,7 @@
12318
12319 spi_writel(as, IDR, pending);
12320
12321 - if (as->current_remaining_bytes == 0) {
12322 + if (as->remaining_bytes == 0) {
12323 msg->actual_length += xfer->len;
12324
12325 if (!msg->is_dma_mapped)
12326 @@ -457,7 +397,7 @@
12327 if (xfer->delay_usecs)
12328 udelay(xfer->delay_usecs);
12329
12330 - if (atmel_spi_xfer_is_last(msg, xfer)) {
12331 + if (msg->transfers.prev == &xfer->transfer_list) {
12332 /* report completed message */
12333 atmel_spi_msg_done(master, as, msg, 0,
12334 xfer->cs_change);
12335 --- a/drivers/usb/gadget/atmel_usba_udc.c
12336 +++ b/drivers/usb/gadget/atmel_usba_udc.c
12337 @@ -18,6 +18,7 @@
12338 #include <linux/platform_device.h>
12339 #include <linux/usb/ch9.h>
12340 #include <linux/usb/gadget.h>
12341 +#include <linux/usb/atmel_usba_udc.h>
12342 #include <linux/delay.h>
12343
12344 #include <asm/gpio.h>
12345 @@ -27,6 +28,7 @@
12346
12347
12348 static struct usba_udc the_udc;
12349 +static struct usba_ep *usba_ep;
12350
12351 #ifdef CONFIG_USB_GADGET_DEBUG_FS
12352 #include <linux/debugfs.h>
12353 @@ -324,53 +326,28 @@
12354 return 1;
12355 }
12356
12357 -static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
12358 -{
12359 - unsigned long tmp;
12360 +#if defined(CONFIG_AVR32)
12361
12362 - DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
12363 - for (; len > 0; len -= 4, buf += 4, fifo += 4) {
12364 - tmp = *(unsigned long *)buf;
12365 - if (len >= 4) {
12366 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
12367 - __raw_writel(tmp, fifo);
12368 - } else {
12369 - do {
12370 - DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
12371 - __raw_writeb(tmp >> 24, fifo);
12372 - fifo++;
12373 - tmp <<= 8;
12374 - } while (--len);
12375 - break;
12376 - }
12377 - }
12378 +static void toggle_bias(int is_on)
12379 +{
12380 }
12381
12382 -static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
12383 +#elif defined(CONFIG_ARCH_AT91)
12384 +
12385 +#include <asm/arch/at91_pmc.h>
12386 +
12387 +static void toggle_bias(int is_on)
12388 {
12389 - union {
12390 - unsigned long *w;
12391 - unsigned char *b;
12392 - } p;
12393 - unsigned long tmp;
12394 -
12395 - DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
12396 - for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
12397 - if (len >= 4) {
12398 - tmp = __raw_readl(fifo);
12399 - *p.w = tmp;
12400 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
12401 - } else {
12402 - do {
12403 - tmp = __raw_readb(fifo);
12404 - *p.b = tmp;
12405 - DBG(DBG_FIFO, " -> %02lx\n", tmp);
12406 - fifo++, p.b++;
12407 - } while (--len);
12408 - }
12409 - }
12410 + unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
12411 +
12412 + if (is_on)
12413 + at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
12414 + else
12415 + at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
12416 }
12417
12418 +#endif /* CONFIG_ARCH_AT91 */
12419 +
12420 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
12421 {
12422 unsigned int transaction_len;
12423 @@ -387,7 +364,7 @@
12424 ep->ep.name, req, transaction_len,
12425 req->last_transaction ? ", done" : "");
12426
12427 - copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
12428 + memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
12429 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
12430 req->req.actual += transaction_len;
12431 }
12432 @@ -476,7 +453,7 @@
12433 bytecount = req->req.length - req->req.actual;
12434 }
12435
12436 - copy_from_fifo(req->req.buf + req->req.actual,
12437 + memcpy_fromio(req->req.buf + req->req.actual,
12438 ep->fifo, bytecount);
12439 req->req.actual += bytecount;
12440
12441 @@ -1029,33 +1006,6 @@
12442 .set_selfpowered = usba_udc_set_selfpowered,
12443 };
12444
12445 -#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
12446 -{ \
12447 - .ep = { \
12448 - .ops = &usba_ep_ops, \
12449 - .name = nam, \
12450 - .maxpacket = maxpkt, \
12451 - }, \
12452 - .udc = &the_udc, \
12453 - .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
12454 - .fifo_size = maxpkt, \
12455 - .nr_banks = maxbk, \
12456 - .index = idx, \
12457 - .can_dma = dma, \
12458 - .can_isoc = isoc, \
12459 -}
12460 -
12461 -static struct usba_ep usba_ep[] = {
12462 - EP("ep0", 0, 64, 1, 0, 0),
12463 - EP("ep1in-bulk", 1, 512, 2, 1, 1),
12464 - EP("ep2out-bulk", 2, 512, 2, 1, 1),
12465 - EP("ep3in-int", 3, 64, 3, 1, 0),
12466 - EP("ep4out-int", 4, 64, 3, 1, 0),
12467 - EP("ep5in-iso", 5, 1024, 3, 1, 1),
12468 - EP("ep6out-iso", 6, 1024, 3, 1, 1),
12469 -};
12470 -#undef EP
12471 -
12472 static struct usb_endpoint_descriptor usba_ep0_desc = {
12473 .bLength = USB_DT_ENDPOINT_SIZE,
12474 .bDescriptorType = USB_DT_ENDPOINT,
12475 @@ -1074,7 +1024,6 @@
12476 static struct usba_udc the_udc = {
12477 .gadget = {
12478 .ops = &usba_udc_ops,
12479 - .ep0 = &usba_ep[0].ep,
12480 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
12481 .is_dualspeed = 1,
12482 .name = "atmel_usba_udc",
12483 @@ -1231,7 +1180,7 @@
12484 } else {
12485 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
12486 usba_writel(udc, TST, USBA_TST_PKT_MODE);
12487 - copy_to_fifo(ep->fifo, test_packet_buffer,
12488 + memcpy_toio(ep->fifo, test_packet_buffer,
12489 sizeof(test_packet_buffer));
12490 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
12491 dev_info(dev, "Entering Test_Packet mode...\n");
12492 @@ -1530,13 +1479,13 @@
12493 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
12494 if (pkt_len != sizeof(crq)) {
12495 pr_warning("udc: Invalid packet length %u "
12496 - "(expected %lu)\n", pkt_len, sizeof(crq));
12497 + "(expected %zu)\n", pkt_len, sizeof(crq));
12498 set_protocol_stall(udc, ep);
12499 return;
12500 }
12501
12502 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
12503 - copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
12504 + memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
12505
12506 /* Free up one bank in the FIFO so that we can
12507 * generate or receive a reply right away. */
12508 @@ -1688,6 +1637,7 @@
12509 DBG(DBG_INT, "irq, status=%#08x\n", status);
12510
12511 if (status & USBA_DET_SUSPEND) {
12512 + toggle_bias(0);
12513 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
12514 DBG(DBG_BUS, "Suspend detected\n");
12515 if (udc->gadget.speed != USB_SPEED_UNKNOWN
12516 @@ -1699,6 +1649,7 @@
12517 }
12518
12519 if (status & USBA_WAKE_UP) {
12520 + toggle_bias(1);
12521 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
12522 DBG(DBG_BUS, "Wake Up CPU detected\n");
12523 }
12524 @@ -1792,12 +1743,14 @@
12525 vbus = gpio_get_value(udc->vbus_pin);
12526 if (vbus != udc->vbus_prev) {
12527 if (vbus) {
12528 - usba_writel(udc, CTRL, USBA_EN_USBA);
12529 + toggle_bias(1);
12530 + usba_writel(udc, CTRL, USBA_ENABLE_MASK);
12531 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
12532 } else {
12533 udc->gadget.speed = USB_SPEED_UNKNOWN;
12534 reset_all_endpoints(udc);
12535 - usba_writel(udc, CTRL, 0);
12536 + toggle_bias(0);
12537 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
12538 spin_unlock(&udc->lock);
12539 udc->driver->disconnect(&udc->gadget);
12540 spin_lock(&udc->lock);
12541 @@ -1850,7 +1803,8 @@
12542 /* If Vbus is present, enable the controller and wait for reset */
12543 spin_lock_irqsave(&udc->lock, flags);
12544 if (vbus_is_present(udc) && udc->vbus_prev == 0) {
12545 - usba_writel(udc, CTRL, USBA_EN_USBA);
12546 + toggle_bias(1);
12547 + usba_writel(udc, CTRL, USBA_ENABLE_MASK);
12548 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
12549 }
12550 spin_unlock_irqrestore(&udc->lock, flags);
12551 @@ -1883,7 +1837,8 @@
12552 spin_unlock_irqrestore(&udc->lock, flags);
12553
12554 /* This will also disable the DP pullup */
12555 - usba_writel(udc, CTRL, 0);
12556 + toggle_bias(0);
12557 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
12558
12559 driver->unbind(&udc->gadget);
12560 udc->gadget.dev.driver = NULL;
12561 @@ -1908,7 +1863,7 @@
12562
12563 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
12564 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
12565 - if (!regs || !fifo)
12566 + if (!regs || !fifo || !pdata)
12567 return -ENXIO;
12568
12569 irq = platform_get_irq(pdev, 0);
12570 @@ -1953,19 +1908,48 @@
12571
12572 /* Make sure we start from a clean slate */
12573 clk_enable(pclk);
12574 - usba_writel(udc, CTRL, 0);
12575 + toggle_bias(0);
12576 + usba_writel(udc, CTRL, USBA_DISABLE_MASK);
12577 clk_disable(pclk);
12578
12579 + usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
12580 + GFP_KERNEL);
12581 + if (!usba_ep)
12582 + goto err_alloc_ep;
12583 +
12584 + the_udc.gadget.ep0 = &usba_ep[0].ep;
12585 +
12586 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
12587 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
12588 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
12589 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
12590 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
12591 + usba_ep[0].ep.ops = &usba_ep_ops;
12592 + usba_ep[0].ep.name = pdata->ep[0].name;
12593 + usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
12594 + usba_ep[0].udc = &the_udc;
12595 + INIT_LIST_HEAD(&usba_ep[0].queue);
12596 + usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
12597 + usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
12598 + usba_ep[0].index = pdata->ep[0].index;
12599 + usba_ep[0].can_dma = pdata->ep[0].can_dma;
12600 + usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
12601 +
12602 + for (i = 1; i < pdata->num_ep; i++) {
12603 struct usba_ep *ep = &usba_ep[i];
12604
12605 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
12606 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
12607 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
12608 + ep->ep.ops = &usba_ep_ops;
12609 + ep->ep.name = pdata->ep[i].name;
12610 + ep->ep.maxpacket = pdata->ep[i].fifo_size;
12611 + ep->udc = &the_udc;
12612 + INIT_LIST_HEAD(&ep->queue);
12613 + ep->fifo_size = pdata->ep[i].fifo_size;
12614 + ep->nr_banks = pdata->ep[i].nr_banks;
12615 + ep->index = pdata->ep[i].index;
12616 + ep->can_dma = pdata->ep[i].can_dma;
12617 + ep->can_isoc = pdata->ep[i].can_isoc;
12618
12619 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
12620 }
12621 @@ -1984,7 +1968,7 @@
12622 goto err_device_add;
12623 }
12624
12625 - if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
12626 + if (pdata->vbus_pin >= 0) {
12627 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
12628 udc->vbus_pin = pdata->vbus_pin;
12629
12630 @@ -2004,7 +1988,7 @@
12631 }
12632
12633 usba_init_debugfs(udc);
12634 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
12635 + for (i = 1; i < pdata->num_ep; i++)
12636 usba_ep_init_debugfs(udc, &usba_ep[i]);
12637
12638 return 0;
12639 @@ -2012,6 +1996,8 @@
12640 err_device_add:
12641 free_irq(irq, udc);
12642 err_request_irq:
12643 + kfree(usba_ep);
12644 +err_alloc_ep:
12645 iounmap(udc->fifo);
12646 err_map_fifo:
12647 iounmap(udc->regs);
12648 @@ -2029,10 +2015,11 @@
12649 {
12650 struct usba_udc *udc;
12651 int i;
12652 + struct usba_platform_data *pdata = pdev->dev.platform_data;
12653
12654 udc = platform_get_drvdata(pdev);
12655
12656 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
12657 + for (i = 1; i < pdata->num_ep; i++)
12658 usba_ep_cleanup_debugfs(&usba_ep[i]);
12659 usba_cleanup_debugfs(udc);
12660
12661 @@ -2040,6 +2027,7 @@
12662 gpio_free(udc->vbus_pin);
12663
12664 free_irq(udc->irq, udc);
12665 + kfree(usba_ep);
12666 iounmap(udc->fifo);
12667 iounmap(udc->regs);
12668 clk_put(udc->hclk);
12669 --- a/drivers/usb/gadget/atmel_usba_udc.h
12670 +++ b/drivers/usb/gadget/atmel_usba_udc.h
12671 @@ -41,6 +41,15 @@
12672 #define USBA_EN_USBA (1 << 8)
12673 #define USBA_DETACH (1 << 9)
12674 #define USBA_REMOTE_WAKE_UP (1 << 10)
12675 +#define USBA_PULLD_DIS (1 << 11)
12676 +
12677 +#if defined(CONFIG_AVR32)
12678 +#define USBA_ENABLE_MASK USBA_EN_USBA
12679 +#define USBA_DISABLE_MASK 0
12680 +#elif defined(CONFIG_ARCH_AT91)
12681 +#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
12682 +#define USBA_DISABLE_MASK USBA_DETACH
12683 +#endif /* CONFIG_ARCH_AT91 */
12684
12685 /* Bitfields in FNUM */
12686 #define USBA_MICRO_FRAME_NUM_OFFSET 0
12687 --- a/drivers/usb/gadget/Kconfig
12688 +++ b/drivers/usb/gadget/Kconfig
12689 @@ -118,10 +118,10 @@
12690 config USB_GADGET_ATMEL_USBA
12691 boolean "Atmel USBA"
12692 select USB_GADGET_DUALSPEED
12693 - depends on AVR32
12694 + depends on AVR32 || ARCH_AT91CAP9
12695 help
12696 USBA is the integrated high-speed USB Device controller on
12697 - the AT32AP700x processors from Atmel.
12698 + the AT32AP700x and AT91CAP9 processors from Atmel.
12699
12700 config USB_ATMEL_USBA
12701 tristate
12702 --- a/drivers/video/atmel_lcdfb.c
12703 +++ b/drivers/video/atmel_lcdfb.c
12704 @@ -38,7 +38,9 @@
12705 #endif
12706
12707 #if defined(CONFIG_ARCH_AT91)
12708 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
12709 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
12710 + | FBINFO_PARTIAL_PAN_OK \
12711 + | FBINFO_HWACCEL_YPAN)
12712
12713 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
12714 struct fb_var_screeninfo *var)
12715 @@ -176,7 +178,7 @@
12716 .type = FB_TYPE_PACKED_PIXELS,
12717 .visual = FB_VISUAL_TRUECOLOR,
12718 .xpanstep = 0,
12719 - .ypanstep = 0,
12720 + .ypanstep = 1,
12721 .ywrapstep = 0,
12722 .accel = FB_ACCEL_NONE,
12723 };
12724 @@ -250,6 +252,8 @@
12725 return -ENOMEM;
12726 }
12727
12728 + memset(info->screen_base, 0, info->fix.smem_len);
12729 +
12730 return 0;
12731 }
12732
12733 @@ -634,7 +638,6 @@
12734 struct fb_info *info = sinfo->info;
12735 int ret = 0;
12736
12737 - memset_io(info->screen_base, 0, info->fix.smem_len);
12738 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
12739
12740 dev_info(info->device,
12741 @@ -764,6 +767,11 @@
12742 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
12743 if (!info->screen_base)
12744 goto release_intmem;
12745 +
12746 + /*
12747 + * Don't clear the framebuffer -- someone may have set
12748 + * up a splash image.
12749 + */
12750 } else {
12751 /* alocate memory buffer */
12752 ret = atmel_lcdfb_alloc_video_memory(sinfo);
12753 --- a/fs/fs-writeback.c
12754 +++ b/fs/fs-writeback.c
12755 @@ -385,8 +385,6 @@
12756 * WB_SYNC_HOLD is a hack for sys_sync(): reattach the inode to sb->s_dirty so
12757 * that it can be located for waiting on in __writeback_single_inode().
12758 *
12759 - * Called under inode_lock.
12760 - *
12761 * If `bdi' is non-zero then we're being asked to writeback a specific queue.
12762 * This function assumes that the blockdev superblock's inodes are backed by
12763 * a variety of queues, so all inodes are searched. For other superblocks,
12764 @@ -402,11 +400,12 @@
12765 * on the writer throttling path, and we get decent balancing between many
12766 * throttled threads: we don't want them all piling up on inode_sync_wait.
12767 */
12768 -static void
12769 -sync_sb_inodes(struct super_block *sb, struct writeback_control *wbc)
12770 +void generic_sync_sb_inodes(struct super_block *sb,
12771 + struct writeback_control *wbc)
12772 {
12773 const unsigned long start = jiffies; /* livelock avoidance */
12774
12775 + spin_lock(&inode_lock);
12776 if (!wbc->for_kupdate || list_empty(&sb->s_io))
12777 queue_io(sb, wbc->older_than_this);
12778
12779 @@ -485,8 +484,16 @@
12780 if (!list_empty(&sb->s_more_io))
12781 wbc->more_io = 1;
12782 }
12783 + spin_unlock(&inode_lock);
12784 return; /* Leave any unwritten inodes on s_io */
12785 }
12786 +EXPORT_SYMBOL_GPL(generic_sync_sb_inodes);
12787 +
12788 +static void sync_sb_inodes(struct super_block *sb,
12789 + struct writeback_control *wbc)
12790 +{
12791 + generic_sync_sb_inodes(sb, wbc);
12792 +}
12793
12794 /*
12795 * Start writeback of dirty pagecache data against all unlocked inodes.
12796 @@ -526,11 +533,8 @@
12797 * be unmounted by the time it is released.
12798 */
12799 if (down_read_trylock(&sb->s_umount)) {
12800 - if (sb->s_root) {
12801 - spin_lock(&inode_lock);
12802 + if (sb->s_root)
12803 sync_sb_inodes(sb, wbc);
12804 - spin_unlock(&inode_lock);
12805 - }
12806 up_read(&sb->s_umount);
12807 }
12808 spin_lock(&sb_lock);
12809 @@ -568,9 +572,7 @@
12810 (inodes_stat.nr_inodes - inodes_stat.nr_unused) +
12811 nr_dirty + nr_unstable;
12812 wbc.nr_to_write += wbc.nr_to_write / 2; /* Bit more for luck */
12813 - spin_lock(&inode_lock);
12814 sync_sb_inodes(sb, &wbc);
12815 - spin_unlock(&inode_lock);
12816 }
12817
12818 /*
12819 --- a/include/asm-avr32/arch-at32ap/board.h
12820 +++ b/include/asm-avr32/arch-at32ap/board.h
12821 @@ -8,6 +8,12 @@
12822
12823 #define GPIO_PIN_NONE (-1)
12824
12825 +/*
12826 + * Clock rates for various on-board oscillators. The number of entries
12827 + * in this array is chip-dependent.
12828 + */
12829 +extern unsigned long at32_board_osc_rates[];
12830 +
12831 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
12832 void at32_add_system_devices(void);
12833
12834 @@ -36,11 +42,10 @@
12835 struct atmel_lcdfb_info;
12836 struct platform_device *
12837 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
12838 - unsigned long fbmem_start, unsigned long fbmem_len);
12839 + unsigned long fbmem_start, unsigned long fbmem_len,
12840 + unsigned int pin_config);
12841
12842 -struct usba_platform_data {
12843 - int vbus_pin;
12844 -};
12845 +struct usba_platform_data;
12846 struct platform_device *
12847 at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
12848
12849 @@ -68,8 +73,17 @@
12850 struct platform_device *
12851 at32_add_device_ssc(unsigned int id, unsigned int flags);
12852
12853 -struct platform_device *at32_add_device_twi(unsigned int id);
12854 -struct platform_device *at32_add_device_mci(unsigned int id);
12855 +struct i2c_board_info;
12856 +struct platform_device *at32_add_device_twi(unsigned int id,
12857 + struct i2c_board_info *b,
12858 + unsigned int n);
12859 +
12860 +struct mci_platform_data {
12861 + int detect_pin;
12862 + int wp_pin;
12863 +};
12864 +struct platform_device *
12865 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
12866 struct platform_device *at32_add_device_ac97c(unsigned int id);
12867 struct platform_device *at32_add_device_abdac(unsigned int id);
12868
12869 @@ -84,4 +98,20 @@
12870 at32_add_device_cf(unsigned int id, unsigned int extint,
12871 struct cf_platform_data *data);
12872
12873 +struct platform_device *
12874 +at32_add_device_psif(unsigned int id);
12875 +
12876 +/* NAND / SmartMedia */
12877 +struct atmel_nand_data {
12878 + int enable_pin; /* chip enable */
12879 + int det_pin; /* card detect */
12880 + int rdy_pin; /* ready/busy */
12881 + u8 ale; /* address line number connected to ALE */
12882 + u8 cle; /* address line number connected to CLE */
12883 + u8 bus_width_16; /* buswidth is 16 bit */
12884 + struct mtd_partition *(*partition_info)(int size, int *num_partitions);
12885 +};
12886 +struct platform_device *
12887 +at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
12888 +
12889 #endif /* __ASM_ARCH_BOARD_H */
12890 --- a/include/asm-avr32/arch-at32ap/init.h
12891 +++ b/include/asm-avr32/arch-at32ap/init.h
12892 @@ -13,10 +13,6 @@
12893 void setup_platform(void);
12894 void setup_board(void);
12895
12896 -/* Called by setup_platform */
12897 -void at32_clock_init(void);
12898 -void at32_portmux_init(void);
12899 -
12900 void at32_setup_serial_console(unsigned int usart_id);
12901
12902 #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
12903 --- /dev/null
12904 +++ b/include/asm-avr32/arch-at32ap/pm.h
12905 @@ -0,0 +1,51 @@
12906 +/*
12907 + * AVR32 AP Power Management.
12908 + *
12909 + * Copyright (C) 2008 Atmel Corporation
12910 + *
12911 + * This program is free software; you can redistribute it and/or modify
12912 + * it under the terms of the GNU General Public License version 2 as
12913 + * published by the Free Software Foundation.
12914 + */
12915 +#ifndef __ASM_AVR32_ARCH_PM_H
12916 +#define __ASM_AVR32_ARCH_PM_H
12917 +
12918 +/* Possible arguments to the "sleep" instruction */
12919 +#define CPU_SLEEP_IDLE 0
12920 +#define CPU_SLEEP_FROZEN 1
12921 +#define CPU_SLEEP_STANDBY 2
12922 +#define CPU_SLEEP_STOP 3
12923 +#define CPU_SLEEP_STATIC 5
12924 +
12925 +#ifndef __ASSEMBLY__
12926 +extern void cpu_enter_idle(void);
12927 +extern void cpu_enter_standby(unsigned long sdramc_base);
12928 +
12929 +extern bool disable_idle_sleep;
12930 +
12931 +static inline void cpu_disable_idle_sleep(void)
12932 +{
12933 + disable_idle_sleep = true;
12934 +}
12935 +
12936 +static inline void cpu_enable_idle_sleep(void)
12937 +{
12938 + disable_idle_sleep = false;
12939 +}
12940 +
12941 +static inline void cpu_idle_sleep(void)
12942 +{
12943 + /*
12944 + * If we're using the COUNT and COMPARE registers for
12945 + * timekeeping, we can't use the IDLE state.
12946 + */
12947 + if (disable_idle_sleep)
12948 + cpu_relax();
12949 + else
12950 + cpu_enter_idle();
12951 +}
12952 +
12953 +void intc_set_suspend_handler(unsigned long offset);
12954 +#endif
12955 +
12956 +#endif /* __ASM_AVR32_ARCH_PM_H */
12957 --- a/include/asm-avr32/arch-at32ap/portmux.h
12958 +++ b/include/asm-avr32/arch-at32ap/portmux.h
12959 @@ -26,4 +26,16 @@
12960 void at32_select_gpio(unsigned int pin, unsigned long flags);
12961 void at32_reserve_pin(unsigned int pin);
12962
12963 +#ifdef CONFIG_GPIO_DEV
12964 +
12965 +/* Gang allocators and accessors; used by the GPIO /dev driver */
12966 +int at32_gpio_port_is_valid(unsigned int port);
12967 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
12968 +void at32_deselect_pins(unsigned int port, u32 pins);
12969 +
12970 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
12971 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
12972 +
12973 +#endif /* CONFIG_GPIO_DEV */
12974 +
12975 #endif /* __ASM_ARCH_PORTMUX_H__ */
12976 --- /dev/null
12977 +++ b/include/asm-avr32/arch-at32ap/sram.h
12978 @@ -0,0 +1,30 @@
12979 +/*
12980 + * Simple SRAM allocator
12981 + *
12982 + * Copyright (C) 2008 Atmel Corporation
12983 + *
12984 + * This program is free software; you can redistribute it and/or modify
12985 + * it under the terms of the GNU General Public License version 2 as
12986 + * published by the Free Software Foundation.
12987 + */
12988 +#ifndef __ASM_AVR32_ARCH_SRAM_H
12989 +#define __ASM_AVR32_ARCH_SRAM_H
12990 +
12991 +#include <linux/genalloc.h>
12992 +
12993 +extern struct gen_pool *sram_pool;
12994 +
12995 +static inline unsigned long sram_alloc(size_t len)
12996 +{
12997 + if (!sram_pool)
12998 + return 0UL;
12999 +
13000 + return gen_pool_alloc(sram_pool, len);
13001 +}
13002 +
13003 +static inline void sram_free(unsigned long addr, size_t len)
13004 +{
13005 + return gen_pool_free(sram_pool, addr, len);
13006 +}
13007 +
13008 +#endif /* __ASM_AVR32_ARCH_SRAM_H */
13009 --- a/include/asm-avr32/arch-at32ap/time.h
13010 +++ /dev/null
13011 @@ -1,112 +0,0 @@
13012 -/*
13013 - * Copyright (C) 2007 Atmel Corporation
13014 - *
13015 - * This program is free software; you can redistribute it and/or modify
13016 - * it under the terms of the GNU General Public License version 2 as
13017 - * published by the Free Software Foundation.
13018 - */
13019 -
13020 -#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
13021 -#define _ASM_AVR32_ARCH_AT32AP_TIME_H
13022 -
13023 -#include <linux/platform_device.h>
13024 -
13025 -extern struct irqaction timer_irqaction;
13026 -extern struct platform_device at32_systc0_device;
13027 -extern void local_timer_interrupt(int irq, void *dev_id);
13028 -
13029 -#define TIMER_BCR 0x000000c0
13030 -#define TIMER_BCR_SYNC 0
13031 -#define TIMER_BMR 0x000000c4
13032 -#define TIMER_BMR_TC0XC0S 0
13033 -#define TIMER_BMR_TC1XC1S 2
13034 -#define TIMER_BMR_TC2XC2S 4
13035 -#define TIMER_CCR 0x00000000
13036 -#define TIMER_CCR_CLKDIS 1
13037 -#define TIMER_CCR_CLKEN 0
13038 -#define TIMER_CCR_SWTRG 2
13039 -#define TIMER_CMR 0x00000004
13040 -#define TIMER_CMR_ABETRG 10
13041 -#define TIMER_CMR_ACPA 16
13042 -#define TIMER_CMR_ACPC 18
13043 -#define TIMER_CMR_AEEVT 20
13044 -#define TIMER_CMR_ASWTRG 22
13045 -#define TIMER_CMR_BCPB 24
13046 -#define TIMER_CMR_BCPC 26
13047 -#define TIMER_CMR_BEEVT 28
13048 -#define TIMER_CMR_BSWTRG 30
13049 -#define TIMER_CMR_BURST 4
13050 -#define TIMER_CMR_CLKI 3
13051 -#define TIMER_CMR_CPCDIS 7
13052 -#define TIMER_CMR_CPCSTOP 6
13053 -#define TIMER_CMR_CPCTRG 14
13054 -#define TIMER_CMR_EEVT 10
13055 -#define TIMER_CMR_EEVTEDG 8
13056 -#define TIMER_CMR_ENETRG 12
13057 -#define TIMER_CMR_ETRGEDG 8
13058 -#define TIMER_CMR_LDBDIS 7
13059 -#define TIMER_CMR_LDBSTOP 6
13060 -#define TIMER_CMR_LDRA 16
13061 -#define TIMER_CMR_LDRB 18
13062 -#define TIMER_CMR_TCCLKS 0
13063 -#define TIMER_CMR_WAVE 15
13064 -#define TIMER_CMR_WAVSEL 13
13065 -#define TIMER_CV 0x00000010
13066 -#define TIMER_CV_CV 0
13067 -#define TIMER_IDR 0x00000028
13068 -#define TIMER_IDR_COVFS 0
13069 -#define TIMER_IDR_CPAS 2
13070 -#define TIMER_IDR_CPBS 3
13071 -#define TIMER_IDR_CPCS 4
13072 -#define TIMER_IDR_ETRGS 7
13073 -#define TIMER_IDR_LDRAS 5
13074 -#define TIMER_IDR_LDRBS 6
13075 -#define TIMER_IDR_LOVRS 1
13076 -#define TIMER_IER 0x00000024
13077 -#define TIMER_IER_COVFS 0
13078 -#define TIMER_IER_CPAS 2
13079 -#define TIMER_IER_CPBS 3
13080 -#define TIMER_IER_CPCS 4
13081 -#define TIMER_IER_ETRGS 7
13082 -#define TIMER_IER_LDRAS 5
13083 -#define TIMER_IER_LDRBS 6
13084 -#define TIMER_IER_LOVRS 1
13085 -#define TIMER_IMR 0x0000002c
13086 -#define TIMER_IMR_COVFS 0
13087 -#define TIMER_IMR_CPAS 2
13088 -#define TIMER_IMR_CPBS 3
13089 -#define TIMER_IMR_CPCS 4
13090 -#define TIMER_IMR_ETRGS 7
13091 -#define TIMER_IMR_LDRAS 5
13092 -#define TIMER_IMR_LDRBS 6
13093 -#define TIMER_IMR_LOVRS 1
13094 -#define TIMER_RA 0x00000014
13095 -#define TIMER_RA_RA 0
13096 -#define TIMER_RB 0x00000018
13097 -#define TIMER_RB_RB 0
13098 -#define TIMER_RC 0x0000001c
13099 -#define TIMER_RC_RC 0
13100 -#define TIMER_SR 0x00000020
13101 -#define TIMER_SR_CLKSTA 16
13102 -#define TIMER_SR_COVFS 0
13103 -#define TIMER_SR_CPAS 2
13104 -#define TIMER_SR_CPBS 3
13105 -#define TIMER_SR_CPCS 4
13106 -#define TIMER_SR_ETRGS 7
13107 -#define TIMER_SR_LDRAS 5
13108 -#define TIMER_SR_LDRBS 6
13109 -#define TIMER_SR_LOVRS 1
13110 -#define TIMER_SR_MTIOA 17
13111 -#define TIMER_SR_MTIOB 18
13112 -
13113 -/* Bit manipulation macros */
13114 -#define TIMER_BIT(name) (1 << TIMER_##name)
13115 -#define TIMER_BF(name,value) ((value) << TIMER_##name)
13116 -
13117 -/* Register access macros */
13118 -#define timer_read(port,instance,reg) \
13119 - __raw_readl(port + (0x40 * instance) + TIMER_##reg)
13120 -#define timer_write(port,instance,reg,value) \
13121 - __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
13122 -
13123 -#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
13124 --- a/include/asm-avr32/asm.h
13125 +++ b/include/asm-avr32/asm.h
13126 @@ -12,10 +12,10 @@
13127 #include <asm/asm-offsets.h>
13128 #include <asm/thread_info.h>
13129
13130 -#define mask_interrupts ssrf SR_GM_BIT
13131 -#define mask_exceptions ssrf SR_EM_BIT
13132 -#define unmask_interrupts csrf SR_GM_BIT
13133 -#define unmask_exceptions csrf SR_EM_BIT
13134 +#define mask_interrupts ssrf SYSREG_GM_OFFSET
13135 +#define mask_exceptions ssrf SYSREG_EM_OFFSET
13136 +#define unmask_interrupts csrf SYSREG_GM_OFFSET
13137 +#define unmask_exceptions csrf SYSREG_EM_OFFSET
13138
13139 #ifdef CONFIG_FRAME_POINTER
13140 .macro save_fp
13141 --- /dev/null
13142 +++ b/include/asm-avr32/dma-controller.h
13143 @@ -0,0 +1,166 @@
13144 +/*
13145 + * Copyright (C) 2005-2006 Atmel Corporation
13146 + *
13147 + * This program is free software; you can redistribute it and/or modify
13148 + * it under the terms of the GNU General Public License version 2 as
13149 + * published by the Free Software Foundation.
13150 + */
13151 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
13152 +#define __ASM_AVR32_DMA_CONTROLLER_H
13153 +
13154 +#include <linux/device.h>
13155 +
13156 +#define DMA_DIR_MEM_TO_MEM 0x0000
13157 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
13158 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
13159 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
13160 +
13161 +#define DMA_WIDTH_8BIT 0
13162 +#define DMA_WIDTH_16BIT 1
13163 +#define DMA_WIDTH_32BIT 2
13164 +
13165 +struct dma_request {
13166 + struct dma_controller *dmac;
13167 + struct list_head list;
13168 +
13169 + unsigned short channel;
13170 +
13171 + void (*xfer_complete)(struct dma_request *req);
13172 + void (*block_complete)(struct dma_request *req);
13173 + void (*error)(struct dma_request *req);
13174 +};
13175 +
13176 +struct dma_request_sg {
13177 + struct dma_request req;
13178 +
13179 + int nr_sg;
13180 + struct scatterlist *sg;
13181 + unsigned long block_size;
13182 + unsigned int nr_blocks;
13183 +
13184 + dma_addr_t data_reg;
13185 + unsigned short periph_id;
13186 +
13187 + unsigned char direction;
13188 + unsigned char width;
13189 +};
13190 +#define to_dma_request_sg(_req) \
13191 + container_of(_req, struct dma_request_sg, req)
13192 +
13193 +struct dma_request_cyclic {
13194 + struct dma_request req;
13195 +
13196 + int periods;
13197 + unsigned long buffer_size;
13198 +
13199 + dma_addr_t buffer_start;
13200 + dma_addr_t data_reg;
13201 +
13202 + unsigned short periph_id;
13203 + unsigned char direction;
13204 + unsigned char width;
13205 +
13206 + void *dev_id;
13207 +};
13208 +#define to_dma_request_cyclic(_req) \
13209 + container_of(_req, struct dma_request_cyclic, req)
13210 +
13211 +struct dma_request_memcpy {
13212 + struct dma_request req;
13213 +
13214 + dma_addr_t src_addr;
13215 + unsigned int src_width;
13216 + unsigned int src_stride;
13217 +
13218 + dma_addr_t dst_addr;
13219 + unsigned int dst_width;
13220 + unsigned int dst_stride;
13221 +
13222 + size_t length;
13223 +
13224 + unsigned short src_reverse:1;
13225 + unsigned short dst_reverse:1;
13226 +};
13227 +#define to_dma_request_memcpy(_req) \
13228 + container_of(_req, struct dma_request_memcpy, req)
13229 +
13230 +struct dma_controller {
13231 + struct list_head list;
13232 + int id;
13233 + struct device *dev;
13234 +
13235 + int (*alloc_channel)(struct dma_controller *dmac);
13236 + void (*release_channel)(struct dma_controller *dmac,
13237 + int channel);
13238 + int (*prepare_request_sg)(struct dma_controller *dmac,
13239 + struct dma_request_sg *req);
13240 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
13241 + struct dma_request_cyclic *req);
13242 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
13243 + struct dma_request_memcpy *req);
13244 + int (*start_request)(struct dma_controller *dmac,
13245 + unsigned int channel);
13246 + int (*stop_request)(struct dma_controller *dmac,
13247 + unsigned int channel);
13248 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
13249 + unsigned int channel);
13250 +};
13251 +
13252 +static inline int
13253 +dma_alloc_channel(struct dma_controller *dmac)
13254 +{
13255 + return dmac->alloc_channel(dmac);
13256 +}
13257 +
13258 +static inline void
13259 +dma_release_channel(struct dma_controller *dmac, int chan)
13260 +{
13261 + dmac->release_channel(dmac, chan);
13262 +}
13263 +
13264 +static inline int
13265 +dma_prepare_request_sg(struct dma_controller *dmac,
13266 + struct dma_request_sg *req)
13267 +{
13268 + return dmac->prepare_request_sg(dmac, req);
13269 +}
13270 +
13271 +static inline int
13272 +dma_prepare_request_cyclic(struct dma_controller *dmac,
13273 + struct dma_request_cyclic *req)
13274 +{
13275 + return dmac->prepare_request_cyclic(dmac, req);
13276 +}
13277 +
13278 +static inline int
13279 +dma_prepare_request_memcpy(struct dma_controller *dmac,
13280 + struct dma_request_memcpy *req)
13281 +{
13282 + return dmac->prepare_request_memcpy(dmac, req);
13283 +}
13284 +
13285 +static inline int
13286 +dma_start_request(struct dma_controller *dmac,
13287 + unsigned int channel)
13288 +{
13289 + return dmac->start_request(dmac, channel);
13290 +}
13291 +
13292 +static inline int
13293 +dma_stop_request(struct dma_controller *dmac,
13294 + unsigned int channel)
13295 +{
13296 + return dmac->stop_request(dmac, channel);
13297 +}
13298 +
13299 +static inline dma_addr_t
13300 +dma_get_current_pos(struct dma_controller *dmac,
13301 + unsigned int channel)
13302 +{
13303 + return dmac->get_current_pos(dmac, channel);
13304 +}
13305 +
13306 +extern int register_dma_controller(struct dma_controller *dmac);
13307 +extern struct dma_controller *find_dma_controller(int id);
13308 +
13309 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
13310 --- a/include/asm-avr32/intc.h
13311 +++ /dev/null
13312 @@ -1,128 +0,0 @@
13313 -#ifndef __ASM_AVR32_INTC_H
13314 -#define __ASM_AVR32_INTC_H
13315 -
13316 -#include <linux/sysdev.h>
13317 -#include <linux/interrupt.h>
13318 -
13319 -struct irq_controller;
13320 -struct irqaction;
13321 -struct pt_regs;
13322 -
13323 -struct platform_device;
13324 -
13325 -/* Information about the internal interrupt controller */
13326 -struct intc_device {
13327 - /* ioremapped address of configuration block */
13328 - void __iomem *regs;
13329 -
13330 - /* the physical device */
13331 - struct platform_device *pdev;
13332 -
13333 - /* Number of interrupt lines per group. */
13334 - unsigned int irqs_per_group;
13335 -
13336 - /* The highest group ID + 1 */
13337 - unsigned int nr_groups;
13338 -
13339 - /*
13340 - * Bitfield indicating which groups are actually in use. The
13341 - * size of the array is
13342 - * ceil(group_max / (8 * sizeof(unsigned int))).
13343 - */
13344 - unsigned int group_mask[];
13345 -};
13346 -
13347 -struct irq_controller_class {
13348 - /*
13349 - * A short name identifying this kind of controller.
13350 - */
13351 - const char *typename;
13352 - /*
13353 - * Handle the IRQ. Must do any necessary acking and masking.
13354 - */
13355 - irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
13356 - /*
13357 - * Register a new IRQ handler.
13358 - */
13359 - int (*setup)(struct irq_controller *ctrl, unsigned int irq,
13360 - struct irqaction *action);
13361 - /*
13362 - * Unregister a IRQ handler.
13363 - */
13364 - void (*free)(struct irq_controller *ctrl, unsigned int irq,
13365 - void *dev_id);
13366 - /*
13367 - * Mask the IRQ in the interrupt controller.
13368 - */
13369 - void (*mask)(struct irq_controller *ctrl, unsigned int irq);
13370 - /*
13371 - * Unmask the IRQ in the interrupt controller.
13372 - */
13373 - void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
13374 - /*
13375 - * Set the type of the IRQ. See below for possible types.
13376 - * Return -EINVAL if a given type is not supported
13377 - */
13378 - int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
13379 - unsigned int type);
13380 - /*
13381 - * Return the IRQ type currently set
13382 - */
13383 - unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
13384 -};
13385 -
13386 -struct irq_controller {
13387 - struct irq_controller_class *class;
13388 - unsigned int irq_group;
13389 - unsigned int first_irq;
13390 - unsigned int nr_irqs;
13391 - struct list_head list;
13392 -};
13393 -
13394 -struct intc_group_desc {
13395 - struct irq_controller *ctrl;
13396 - irqreturn_t (*handle)(int, void *, struct pt_regs *);
13397 - unsigned long flags;
13398 - void *dev_id;
13399 - const char *devname;
13400 -};
13401 -
13402 -/*
13403 - * The internal interrupt controller. Defined in board/part-specific
13404 - * devices.c.
13405 - * TODO: Should probably be defined per-cpu.
13406 - */
13407 -extern struct intc_device intc;
13408 -
13409 -extern int request_internal_irq(unsigned int irq,
13410 - irqreturn_t (*handler)(int, void *, struct pt_regs *),
13411 - unsigned long irqflags,
13412 - const char *devname, void *dev_id);
13413 -extern void free_internal_irq(unsigned int irq);
13414 -
13415 -/* Only used by time_init() */
13416 -extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
13417 -
13418 -/*
13419 - * Set interrupt priority for a given group. `group' can be found by
13420 - * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
13421 - * (highest). Higher-priority interrupts will preempt lower-priority
13422 - * interrupts (unless interrupts are masked globally).
13423 - *
13424 - * This function does not check for conflicts within a group.
13425 - */
13426 -extern int intc_set_priority(unsigned int group,
13427 - unsigned int priority);
13428 -
13429 -/*
13430 - * Returns a bitmask of pending interrupts in a group.
13431 - */
13432 -extern unsigned long intc_get_pending(unsigned int group);
13433 -
13434 -/*
13435 - * Register a new external interrupt controller. Returns the first
13436 - * external IRQ number that is assigned to the new controller.
13437 - */
13438 -extern int intc_register_controller(struct irq_controller *ctrl);
13439 -
13440 -#endif /* __ASM_AVR32_INTC_H */
13441 --- a/include/asm-avr32/irq.h
13442 +++ b/include/asm-avr32/irq.h
13443 @@ -14,6 +14,11 @@
13444 #ifndef __ASSEMBLER__
13445 int nmi_enable(void);
13446 void nmi_disable(void);
13447 +
13448 +/*
13449 + * Returns a bitmask of pending interrupts in a group.
13450 + */
13451 +extern unsigned long intc_get_pending(unsigned int group);
13452 #endif
13453
13454 #endif /* __ASM_AVR32_IOCTLS_H */
13455 --- a/include/asm-avr32/page.h
13456 +++ b/include/asm-avr32/page.h
13457 @@ -8,13 +8,11 @@
13458 #ifndef __ASM_AVR32_PAGE_H
13459 #define __ASM_AVR32_PAGE_H
13460
13461 +#include <linux/const.h>
13462 +
13463 /* PAGE_SHIFT determines the page size */
13464 #define PAGE_SHIFT 12
13465 -#ifdef __ASSEMBLY__
13466 -#define PAGE_SIZE (1 << PAGE_SHIFT)
13467 -#else
13468 -#define PAGE_SIZE (1UL << PAGE_SHIFT)
13469 -#endif
13470 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
13471 #define PAGE_MASK (~(PAGE_SIZE-1))
13472 #define PTE_MASK PAGE_MASK
13473
13474 --- a/include/asm-avr32/pci.h
13475 +++ b/include/asm-avr32/pci.h
13476 @@ -5,4 +5,6 @@
13477
13478 #define PCI_DMA_BUS_IS_PHYS (1)
13479
13480 +#include <asm-generic/pci-dma-compat.h>
13481 +
13482 #endif /* __ASM_AVR32_PCI_H__ */
13483 --- /dev/null
13484 +++ b/include/asm-avr32/serial.h
13485 @@ -0,0 +1,13 @@
13486 +#ifndef _ASM_SERIAL_H
13487 +#define _ASM_SERIAL_H
13488 +
13489 +/*
13490 + * This assumes you have a 1.8432 MHz clock for your UART.
13491 + *
13492 + * It'd be nice if someone built a serial card with a 24.576 MHz
13493 + * clock, since the 16550A is capable of handling a top speed of 1.5
13494 + * megabits/second; but this requires the faster clock.
13495 + */
13496 +#define BASE_BAUD (1843200 / 16)
13497 +
13498 +#endif /* _ASM_SERIAL_H */
13499 --- a/include/asm-avr32/thread_info.h
13500 +++ b/include/asm-avr32/thread_info.h
13501 @@ -88,6 +88,7 @@
13502 #define TIF_MEMDIE 6
13503 #define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
13504 #define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
13505 +#define TIF_FREEZE 29
13506 #define TIF_DEBUG 30 /* debugging enabled */
13507 #define TIF_USERSPACE 31 /* true if FS sets userspace */
13508
13509 --- /dev/null
13510 +++ b/include/asm-avr32/xor.h
13511 @@ -0,0 +1,6 @@
13512 +#ifndef _ASM_XOR_H
13513 +#define _ASM_XOR_H
13514 +
13515 +#include <asm-generic/xor.h>
13516 +
13517 +#endif
13518 --- /dev/null
13519 +++ b/include/linux/atmel_tc.h
13520 @@ -0,0 +1,252 @@
13521 +/*
13522 + * Timer/Counter Unit (TC) registers.
13523 + *
13524 + * This program is free software; you can redistribute it and/or modify
13525 + * it under the terms of the GNU General Public License as published by
13526 + * the Free Software Foundation; either version 2 of the License, or
13527 + * (at your option) any later version.
13528 + */
13529 +
13530 +#ifndef ATMEL_TC_H
13531 +#define ATMEL_TC_H
13532 +
13533 +#include <linux/compiler.h>
13534 +#include <linux/list.h>
13535 +
13536 +/*
13537 + * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
13538 + * three general-purpose 16-bit timers. These timers share one register bank.
13539 + * Depending on the SOC, each timer may have its own clock and IRQ, or those
13540 + * may be shared by the whole TC block.
13541 + *
13542 + * These TC blocks may have up to nine external pins: TCLK0..2 signals for
13543 + * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
13544 + * or triggering. Those pins need to be set up for use with the TC block,
13545 + * else they will be used as GPIOs or for a different controller.
13546 + *
13547 + * Although we expect each TC block to have a platform_device node, those
13548 + * nodes are not what drivers bind to. Instead, they ask for a specific
13549 + * TC block, by number ... which is a common approach on systems with many
13550 + * timers. Then they use clk_get() and platform_get_irq() to get clock and
13551 + * IRQ resources.
13552 + */
13553 +
13554 +struct clk;
13555 +
13556 +/**
13557 + * struct atmel_tc - information about a Timer/Counter Block
13558 + * @pdev: physical device
13559 + * @iomem: resource associated with the I/O register
13560 + * @regs: mapping through which the I/O registers can be accessed
13561 + * @irq: irq for each of the three channels
13562 + * @clk: internal clock source for each of the three channels
13563 + * @node: list node, for tclib internal use
13564 + *
13565 + * On some platforms, each TC channel has its own clocks and IRQs,
13566 + * while on others, all TC channels share the same clock and IRQ.
13567 + * Drivers should clk_enable() all the clocks they need even though
13568 + * all the entries in @clk may point to the same physical clock.
13569 + * Likewise, drivers should request irqs independently for each
13570 + * channel, but they must use IRQF_SHARED in case some of the entries
13571 + * in @irq are actually the same IRQ.
13572 + */
13573 +struct atmel_tc {
13574 + struct platform_device *pdev;
13575 + struct resource *iomem;
13576 + void __iomem *regs;
13577 + int irq[3];
13578 + struct clk *clk[3];
13579 + struct list_head node;
13580 +};
13581 +
13582 +extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
13583 +extern void atmel_tc_free(struct atmel_tc *tc);
13584 +
13585 +/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
13586 +extern const u8 atmel_tc_divisors[5];
13587 +
13588 +
13589 +/*
13590 + * Two registers have block-wide controls. These are: configuring the three
13591 + * "external" clocks (or event sources) used by the timer channels; and
13592 + * synchronizing the timers by resetting them all at once.
13593 + *
13594 + * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
13595 + * signals. Or, it can mean "external to timer", using the TIOA output from
13596 + * one of the other two timers that's being run in waveform mode.
13597 + */
13598 +
13599 +#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
13600 +#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
13601 +
13602 +#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
13603 +#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
13604 +#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
13605 +#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
13606 +#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
13607 +#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
13608 +#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
13609 +#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
13610 +#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
13611 +#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
13612 +#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
13613 +#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
13614 +#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
13615 +#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
13616 +#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
13617 +#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
13618 +
13619 +
13620 +/*
13621 + * Each TC block has three "channels", each with one counter and controls.
13622 + *
13623 + * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
13624 + * when it's not "external") is silicon-specific. AT91 platforms use one
13625 + * set of definitions; AVR32 platforms use a different set. Don't hard-wire
13626 + * such knowledge into your code, use the global "atmel_tc_divisors" ...
13627 + * where index N is the divisor for clock N+1, else zero to indicate it uses
13628 + * the 32 KiHz clock.
13629 + *
13630 + * The timers can be chained in various ways, and operated in "waveform"
13631 + * generation mode (including PWM) or "capture" mode (to time events). In
13632 + * both modes, behavior can be configured in many ways.
13633 + *
13634 + * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
13635 + * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
13636 + * uses them only as inputs.
13637 + */
13638 +#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
13639 +#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
13640 +
13641 +#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
13642 +#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
13643 +#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
13644 +#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
13645 +
13646 +#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
13647 +
13648 +/* Both modes share some CMR bits */
13649 +#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
13650 +#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
13651 +#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
13652 +#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
13653 +#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
13654 +#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
13655 +#define ATMEL_TC_XC0 (5 << 0)
13656 +#define ATMEL_TC_XC1 (6 << 0)
13657 +#define ATMEL_TC_XC2 (7 << 0)
13658 +#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
13659 +#define ATMEL_TC_BURST (3 << 4) /* clock gating */
13660 +#define ATMEL_TC_GATE_NONE (0 << 4)
13661 +#define ATMEL_TC_GATE_XC0 (1 << 4)
13662 +#define ATMEL_TC_GATE_XC1 (2 << 4)
13663 +#define ATMEL_TC_GATE_XC2 (3 << 4)
13664 +#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
13665 +
13666 +/* CAPTURE mode CMR bits */
13667 +#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
13668 +#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
13669 +#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
13670 +#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
13671 +#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
13672 +#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
13673 +#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
13674 +#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
13675 +#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
13676 +#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
13677 +#define ATMEL_TC_LDRA_NONE (0 << 16)
13678 +#define ATMEL_TC_LDRA_RISING (1 << 16)
13679 +#define ATMEL_TC_LDRA_FALLING (2 << 16)
13680 +#define ATMEL_TC_LDRA_BOTH (3 << 16)
13681 +#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
13682 +#define ATMEL_TC_LDRB_NONE (0 << 18)
13683 +#define ATMEL_TC_LDRB_RISING (1 << 18)
13684 +#define ATMEL_TC_LDRB_FALLING (2 << 18)
13685 +#define ATMEL_TC_LDRB_BOTH (3 << 18)
13686 +
13687 +/* WAVEFORM mode CMR bits */
13688 +#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
13689 +#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
13690 +#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
13691 +#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
13692 +#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
13693 +#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
13694 +#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
13695 +#define ATMEL_TC_EEVT (3 << 10) /* external event source */
13696 +#define ATMEL_TC_EEVT_TIOB (0 << 10)
13697 +#define ATMEL_TC_EEVT_XC0 (1 << 10)
13698 +#define ATMEL_TC_EEVT_XC1 (2 << 10)
13699 +#define ATMEL_TC_EEVT_XC2 (3 << 10)
13700 +#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
13701 +#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
13702 +#define ATMEL_TC_WAVESEL_UP (0 << 13)
13703 +#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
13704 +#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
13705 +#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
13706 +#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
13707 +#define ATMEL_TC_ACPA_NONE (0 << 16)
13708 +#define ATMEL_TC_ACPA_SET (1 << 16)
13709 +#define ATMEL_TC_ACPA_CLEAR (2 << 16)
13710 +#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
13711 +#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
13712 +#define ATMEL_TC_ACPC_NONE (0 << 18)
13713 +#define ATMEL_TC_ACPC_SET (1 << 18)
13714 +#define ATMEL_TC_ACPC_CLEAR (2 << 18)
13715 +#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
13716 +#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
13717 +#define ATMEL_TC_AEEVT_NONE (0 << 20)
13718 +#define ATMEL_TC_AEEVT_SET (1 << 20)
13719 +#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
13720 +#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
13721 +#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
13722 +#define ATMEL_TC_ASWTRG_NONE (0 << 22)
13723 +#define ATMEL_TC_ASWTRG_SET (1 << 22)
13724 +#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
13725 +#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
13726 +#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
13727 +#define ATMEL_TC_BCPB_NONE (0 << 24)
13728 +#define ATMEL_TC_BCPB_SET (1 << 24)
13729 +#define ATMEL_TC_BCPB_CLEAR (2 << 24)
13730 +#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
13731 +#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
13732 +#define ATMEL_TC_BCPC_NONE (0 << 26)
13733 +#define ATMEL_TC_BCPC_SET (1 << 26)
13734 +#define ATMEL_TC_BCPC_CLEAR (2 << 26)
13735 +#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
13736 +#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
13737 +#define ATMEL_TC_BEEVT_NONE (0 << 28)
13738 +#define ATMEL_TC_BEEVT_SET (1 << 28)
13739 +#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
13740 +#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
13741 +#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
13742 +#define ATMEL_TC_BSWTRG_NONE (0 << 30)
13743 +#define ATMEL_TC_BSWTRG_SET (1 << 30)
13744 +#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
13745 +#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
13746 +
13747 +#define ATMEL_TC_CV 0x10 /* counter Value */
13748 +#define ATMEL_TC_RA 0x14 /* register A */
13749 +#define ATMEL_TC_RB 0x18 /* register B */
13750 +#define ATMEL_TC_RC 0x1c /* register C */
13751 +
13752 +#define ATMEL_TC_SR 0x20 /* status (read-only) */
13753 +/* Status-only flags */
13754 +#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
13755 +#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
13756 +#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
13757 +
13758 +#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
13759 +#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
13760 +#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
13761 +
13762 +/* Status and IRQ flags */
13763 +#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
13764 +#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
13765 +#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
13766 +#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
13767 +#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
13768 +#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
13769 +#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
13770 +#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
13771 +
13772 +#endif
13773 --- a/include/linux/fs.h
13774 +++ b/include/linux/fs.h
13775 @@ -1691,6 +1691,8 @@
13776 extern int invalidate_inode_pages2(struct address_space *mapping);
13777 extern int invalidate_inode_pages2_range(struct address_space *mapping,
13778 pgoff_t start, pgoff_t end);
13779 +extern void generic_sync_sb_inodes(struct super_block *sb,
13780 + struct writeback_control *wbc);
13781 extern int write_inode_now(struct inode *, int);
13782 extern int filemap_fdatawrite(struct address_space *);
13783 extern int filemap_flush(struct address_space *);
13784 --- /dev/null
13785 +++ b/include/linux/usb/atmel_usba_udc.h
13786 @@ -0,0 +1,22 @@
13787 +/*
13788 + * Platform data definitions for Atmel USBA gadget driver.
13789 + */
13790 +#ifndef __LINUX_USB_USBA_H
13791 +#define __LINUX_USB_USBA_H
13792 +
13793 +struct usba_ep_data {
13794 + char *name;
13795 + int index;
13796 + int fifo_size;
13797 + int nr_banks;
13798 + int can_dma;
13799 + int can_isoc;
13800 +};
13801 +
13802 +struct usba_platform_data {
13803 + int vbus_pin;
13804 + int num_ep;
13805 + struct usba_ep_data ep[0];
13806 +};
13807 +
13808 +#endif /* __LINUX_USB_USBA_H */
13809 --- a/include/mtd/Kbuild
13810 +++ b/include/mtd/Kbuild
13811 @@ -3,5 +3,4 @@
13812 header-y += mtd-abi.h
13813 header-y += mtd-user.h
13814 header-y += nftl-user.h
13815 -header-y += ubi-header.h
13816 header-y += ubi-user.h
13817 --- a/include/mtd/ubi-header.h
13818 +++ /dev/null
13819 @@ -1,372 +0,0 @@
13820 -/*
13821 - * Copyright (c) International Business Machines Corp., 2006
13822 - *
13823 - * This program is free software; you can redistribute it and/or modify
13824 - * it under the terms of the GNU General Public License as published by
13825 - * the Free Software Foundation; either version 2 of the License, or
13826 - * (at your option) any later version.
13827 - *
13828 - * This program is distributed in the hope that it will be useful,
13829 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
13830 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
13831 - * the GNU General Public License for more details.
13832 - *
13833 - * You should have received a copy of the GNU General Public License
13834 - * along with this program; if not, write to the Free Software
13835 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
13836 - *
13837 - * Authors: Artem Bityutskiy (Битюцкий Артём)
13838 - * Thomas Gleixner
13839 - * Frank Haverkamp
13840 - * Oliver Lohmann
13841 - * Andreas Arnez
13842 - */
13843 -
13844 -/*
13845 - * This file defines the layout of UBI headers and all the other UBI on-flash
13846 - * data structures. May be included by user-space.
13847 - */
13848 -
13849 -#ifndef __UBI_HEADER_H__
13850 -#define __UBI_HEADER_H__
13851 -
13852 -#include <asm/byteorder.h>
13853 -
13854 -/* The version of UBI images supported by this implementation */
13855 -#define UBI_VERSION 1
13856 -
13857 -/* The highest erase counter value supported by this implementation */
13858 -#define UBI_MAX_ERASECOUNTER 0x7FFFFFFF
13859 -
13860 -/* The initial CRC32 value used when calculating CRC checksums */
13861 -#define UBI_CRC32_INIT 0xFFFFFFFFU
13862 -
13863 -/* Erase counter header magic number (ASCII "UBI#") */
13864 -#define UBI_EC_HDR_MAGIC 0x55424923
13865 -/* Volume identifier header magic number (ASCII "UBI!") */
13866 -#define UBI_VID_HDR_MAGIC 0x55424921
13867 -
13868 -/*
13869 - * Volume type constants used in the volume identifier header.
13870 - *
13871 - * @UBI_VID_DYNAMIC: dynamic volume
13872 - * @UBI_VID_STATIC: static volume
13873 - */
13874 -enum {
13875 - UBI_VID_DYNAMIC = 1,
13876 - UBI_VID_STATIC = 2
13877 -};
13878 -
13879 -/*
13880 - * Volume flags used in the volume table record.
13881 - *
13882 - * @UBI_VTBL_AUTORESIZE_FLG: auto-resize this volume
13883 - *
13884 - * %UBI_VTBL_AUTORESIZE_FLG flag can be set only for one volume in the volume
13885 - * table. UBI automatically re-sizes the volume which has this flag and makes
13886 - * the volume to be of largest possible size. This means that if after the
13887 - * initialization UBI finds out that there are available physical eraseblocks
13888 - * present on the device, it automatically appends all of them to the volume
13889 - * (the physical eraseblocks reserved for bad eraseblocks handling and other
13890 - * reserved physical eraseblocks are not taken). So, if there is a volume with
13891 - * the %UBI_VTBL_AUTORESIZE_FLG flag set, the amount of available logical
13892 - * eraseblocks will be zero after UBI is loaded, because all of them will be
13893 - * reserved for this volume. Note, the %UBI_VTBL_AUTORESIZE_FLG bit is cleared
13894 - * after the volume had been initialized.
13895 - *
13896 - * The auto-resize feature is useful for device production purposes. For
13897 - * example, different NAND flash chips may have different amount of initial bad
13898 - * eraseblocks, depending of particular chip instance. Manufacturers of NAND
13899 - * chips usually guarantee that the amount of initial bad eraseblocks does not
13900 - * exceed certain percent, e.g. 2%. When one creates an UBI image which will be
13901 - * flashed to the end devices in production, he does not know the exact amount
13902 - * of good physical eraseblocks the NAND chip on the device will have, but this
13903 - * number is required to calculate the volume sized and put them to the volume
13904 - * table of the UBI image. In this case, one of the volumes (e.g., the one
13905 - * which will store the root file system) is marked as "auto-resizable", and
13906 - * UBI will adjust its size on the first boot if needed.
13907 - *
13908 - * Note, first UBI reserves some amount of physical eraseblocks for bad
13909 - * eraseblock handling, and then re-sizes the volume, not vice-versa. This
13910 - * means that the pool of reserved physical eraseblocks will always be present.
13911 - */
13912 -enum {
13913 - UBI_VTBL_AUTORESIZE_FLG = 0x01,
13914 -};
13915 -
13916 -/*
13917 - * Compatibility constants used by internal volumes.
13918 - *
13919 - * @UBI_COMPAT_DELETE: delete this internal volume before anything is written
13920 - * to the flash
13921 - * @UBI_COMPAT_RO: attach this device in read-only mode
13922 - * @UBI_COMPAT_PRESERVE: preserve this internal volume - do not touch its
13923 - * physical eraseblocks, don't allow the wear-leveling unit to move them
13924 - * @UBI_COMPAT_REJECT: reject this UBI image
13925 - */
13926 -enum {
13927 - UBI_COMPAT_DELETE = 1,
13928 - UBI_COMPAT_RO = 2,
13929 - UBI_COMPAT_PRESERVE = 4,
13930 - UBI_COMPAT_REJECT = 5
13931 -};
13932 -
13933 -/* Sizes of UBI headers */
13934 -#define UBI_EC_HDR_SIZE sizeof(struct ubi_ec_hdr)
13935 -#define UBI_VID_HDR_SIZE sizeof(struct ubi_vid_hdr)
13936 -
13937 -/* Sizes of UBI headers without the ending CRC */
13938 -#define UBI_EC_HDR_SIZE_CRC (UBI_EC_HDR_SIZE - sizeof(__be32))
13939 -#define UBI_VID_HDR_SIZE_CRC (UBI_VID_HDR_SIZE - sizeof(__be32))
13940 -
13941 -/**
13942 - * struct ubi_ec_hdr - UBI erase counter header.
13943 - * @magic: erase counter header magic number (%UBI_EC_HDR_MAGIC)
13944 - * @version: version of UBI implementation which is supposed to accept this
13945 - * UBI image
13946 - * @padding1: reserved for future, zeroes
13947 - * @ec: the erase counter
13948 - * @vid_hdr_offset: where the VID header starts
13949 - * @data_offset: where the user data start
13950 - * @padding2: reserved for future, zeroes
13951 - * @hdr_crc: erase counter header CRC checksum
13952 - *
13953 - * The erase counter header takes 64 bytes and has a plenty of unused space for
13954 - * future usage. The unused fields are zeroed. The @version field is used to
13955 - * indicate the version of UBI implementation which is supposed to be able to
13956 - * work with this UBI image. If @version is greater then the current UBI
13957 - * version, the image is rejected. This may be useful in future if something
13958 - * is changed radically. This field is duplicated in the volume identifier
13959 - * header.
13960 - *
13961 - * The @vid_hdr_offset and @data_offset fields contain the offset of the the
13962 - * volume identifier header and user data, relative to the beginning of the
13963 - * physical eraseblock. These values have to be the same for all physical
13964 - * eraseblocks.
13965 - */
13966 -struct ubi_ec_hdr {
13967 - __be32 magic;
13968 - __u8 version;
13969 - __u8 padding1[3];
13970 - __be64 ec; /* Warning: the current limit is 31-bit anyway! */
13971 - __be32 vid_hdr_offset;
13972 - __be32 data_offset;
13973 - __u8 padding2[36];
13974 - __be32 hdr_crc;
13975 -} __attribute__ ((packed));
13976 -
13977 -/**
13978 - * struct ubi_vid_hdr - on-flash UBI volume identifier header.
13979 - * @magic: volume identifier header magic number (%UBI_VID_HDR_MAGIC)
13980 - * @version: UBI implementation version which is supposed to accept this UBI
13981 - * image (%UBI_VERSION)
13982 - * @vol_type: volume type (%UBI_VID_DYNAMIC or %UBI_VID_STATIC)
13983 - * @copy_flag: if this logical eraseblock was copied from another physical
13984 - * eraseblock (for wear-leveling reasons)
13985 - * @compat: compatibility of this volume (%0, %UBI_COMPAT_DELETE,
13986 - * %UBI_COMPAT_IGNORE, %UBI_COMPAT_PRESERVE, or %UBI_COMPAT_REJECT)
13987 - * @vol_id: ID of this volume
13988 - * @lnum: logical eraseblock number
13989 - * @leb_ver: version of this logical eraseblock (IMPORTANT: obsolete, to be
13990 - * removed, kept only for not breaking older UBI users)
13991 - * @data_size: how many bytes of data this logical eraseblock contains
13992 - * @used_ebs: total number of used logical eraseblocks in this volume
13993 - * @data_pad: how many bytes at the end of this physical eraseblock are not
13994 - * used
13995 - * @data_crc: CRC checksum of the data stored in this logical eraseblock
13996 - * @padding1: reserved for future, zeroes
13997 - * @sqnum: sequence number
13998 - * @padding2: reserved for future, zeroes
13999 - * @hdr_crc: volume identifier header CRC checksum
14000 - *
14001 - * The @sqnum is the value of the global sequence counter at the time when this
14002 - * VID header was created. The global sequence counter is incremented each time
14003 - * UBI writes a new VID header to the flash, i.e. when it maps a logical
14004 - * eraseblock to a new physical eraseblock. The global sequence counter is an
14005 - * unsigned 64-bit integer and we assume it never overflows. The @sqnum
14006 - * (sequence number) is used to distinguish between older and newer versions of
14007 - * logical eraseblocks.
14008 - *
14009 - * There are 2 situations when there may be more then one physical eraseblock
14010 - * corresponding to the same logical eraseblock, i.e., having the same @vol_id
14011 - * and @lnum values in the volume identifier header. Suppose we have a logical
14012 - * eraseblock L and it is mapped to the physical eraseblock P.
14013 - *
14014 - * 1. Because UBI may erase physical eraseblocks asynchronously, the following
14015 - * situation is possible: L is asynchronously erased, so P is scheduled for
14016 - * erasure, then L is written to,i.e. mapped to another physical eraseblock P1,
14017 - * so P1 is written to, then an unclean reboot happens. Result - there are 2
14018 - * physical eraseblocks P and P1 corresponding to the same logical eraseblock
14019 - * L. But P1 has greater sequence number, so UBI picks P1 when it attaches the
14020 - * flash.
14021 - *
14022 - * 2. From time to time UBI moves logical eraseblocks to other physical
14023 - * eraseblocks for wear-leveling reasons. If, for example, UBI moves L from P
14024 - * to P1, and an unclean reboot happens before P is physically erased, there
14025 - * are two physical eraseblocks P and P1 corresponding to L and UBI has to
14026 - * select one of them when the flash is attached. The @sqnum field says which
14027 - * PEB is the original (obviously P will have lower @sqnum) and the copy. But
14028 - * it is not enough to select the physical eraseblock with the higher sequence
14029 - * number, because the unclean reboot could have happen in the middle of the
14030 - * copying process, so the data in P is corrupted. It is also not enough to
14031 - * just select the physical eraseblock with lower sequence number, because the
14032 - * data there may be old (consider a case if more data was added to P1 after
14033 - * the copying). Moreover, the unclean reboot may happen when the erasure of P
14034 - * was just started, so it result in unstable P, which is "mostly" OK, but
14035 - * still has unstable bits.
14036 - *
14037 - * UBI uses the @copy_flag field to indicate that this logical eraseblock is a
14038 - * copy. UBI also calculates data CRC when the data is moved and stores it at
14039 - * the @data_crc field of the copy (P1). So when UBI needs to pick one physical
14040 - * eraseblock of two (P or P1), the @copy_flag of the newer one (P1) is
14041 - * examined. If it is cleared, the situation* is simple and the newer one is
14042 - * picked. If it is set, the data CRC of the copy (P1) is examined. If the CRC
14043 - * checksum is correct, this physical eraseblock is selected (P1). Otherwise
14044 - * the older one (P) is selected.
14045 - *
14046 - * Note, there is an obsolete @leb_ver field which was used instead of @sqnum
14047 - * in the past. But it is not used anymore and we keep it in order to be able
14048 - * to deal with old UBI images. It will be removed at some point.
14049 - *
14050 - * There are 2 sorts of volumes in UBI: user volumes and internal volumes.
14051 - * Internal volumes are not seen from outside and are used for various internal
14052 - * UBI purposes. In this implementation there is only one internal volume - the
14053 - * layout volume. Internal volumes are the main mechanism of UBI extensions.
14054 - * For example, in future one may introduce a journal internal volume. Internal
14055 - * volumes have their own reserved range of IDs.
14056 - *
14057 - * The @compat field is only used for internal volumes and contains the "degree
14058 - * of their compatibility". It is always zero for user volumes. This field
14059 - * provides a mechanism to introduce UBI extensions and to be still compatible
14060 - * with older UBI binaries. For example, if someone introduced a journal in
14061 - * future, he would probably use %UBI_COMPAT_DELETE compatibility for the
14062 - * journal volume. And in this case, older UBI binaries, which know nothing
14063 - * about the journal volume, would just delete this volume and work perfectly
14064 - * fine. This is similar to what Ext2fs does when it is fed by an Ext3fs image
14065 - * - it just ignores the Ext3fs journal.
14066 - *
14067 - * The @data_crc field contains the CRC checksum of the contents of the logical
14068 - * eraseblock if this is a static volume. In case of dynamic volumes, it does
14069 - * not contain the CRC checksum as a rule. The only exception is when the
14070 - * data of the physical eraseblock was moved by the wear-leveling unit, then
14071 - * the wear-leveling unit calculates the data CRC and stores it in the
14072 - * @data_crc field. And of course, the @copy_flag is %in this case.
14073 - *
14074 - * The @data_size field is used only for static volumes because UBI has to know
14075 - * how many bytes of data are stored in this eraseblock. For dynamic volumes,
14076 - * this field usually contains zero. The only exception is when the data of the
14077 - * physical eraseblock was moved to another physical eraseblock for
14078 - * wear-leveling reasons. In this case, UBI calculates CRC checksum of the
14079 - * contents and uses both @data_crc and @data_size fields. In this case, the
14080 - * @data_size field contains data size.
14081 - *
14082 - * The @used_ebs field is used only for static volumes and indicates how many
14083 - * eraseblocks the data of the volume takes. For dynamic volumes this field is
14084 - * not used and always contains zero.
14085 - *
14086 - * The @data_pad is calculated when volumes are created using the alignment
14087 - * parameter. So, effectively, the @data_pad field reduces the size of logical
14088 - * eraseblocks of this volume. This is very handy when one uses block-oriented
14089 - * software (say, cramfs) on top of the UBI volume.
14090 - */
14091 -struct ubi_vid_hdr {
14092 - __be32 magic;
14093 - __u8 version;
14094 - __u8 vol_type;
14095 - __u8 copy_flag;
14096 - __u8 compat;
14097 - __be32 vol_id;
14098 - __be32 lnum;
14099 - __be32 leb_ver; /* obsolete, to be removed, don't use */
14100 - __be32 data_size;
14101 - __be32 used_ebs;
14102 - __be32 data_pad;
14103 - __be32 data_crc;
14104 - __u8 padding1[4];
14105 - __be64 sqnum;
14106 - __u8 padding2[12];
14107 - __be32 hdr_crc;
14108 -} __attribute__ ((packed));
14109 -
14110 -/* Internal UBI volumes count */
14111 -#define UBI_INT_VOL_COUNT 1
14112 -
14113 -/*
14114 - * Starting ID of internal volumes. There is reserved room for 4096 internal
14115 - * volumes.
14116 - */
14117 -#define UBI_INTERNAL_VOL_START (0x7FFFFFFF - 4096)
14118 -
14119 -/* The layout volume contains the volume table */
14120 -
14121 -#define UBI_LAYOUT_VOLUME_ID UBI_INTERNAL_VOL_START
14122 -#define UBI_LAYOUT_VOLUME_TYPE UBI_VID_DYNAMIC
14123 -#define UBI_LAYOUT_VOLUME_ALIGN 1
14124 -#define UBI_LAYOUT_VOLUME_EBS 2
14125 -#define UBI_LAYOUT_VOLUME_NAME "layout volume"
14126 -#define UBI_LAYOUT_VOLUME_COMPAT UBI_COMPAT_REJECT
14127 -
14128 -/* The maximum number of volumes per one UBI device */
14129 -#define UBI_MAX_VOLUMES 128
14130 -
14131 -/* The maximum volume name length */
14132 -#define UBI_VOL_NAME_MAX 127
14133 -
14134 -/* Size of the volume table record */
14135 -#define UBI_VTBL_RECORD_SIZE sizeof(struct ubi_vtbl_record)
14136 -
14137 -/* Size of the volume table record without the ending CRC */
14138 -#define UBI_VTBL_RECORD_SIZE_CRC (UBI_VTBL_RECORD_SIZE - sizeof(__be32))
14139 -
14140 -/**
14141 - * struct ubi_vtbl_record - a record in the volume table.
14142 - * @reserved_pebs: how many physical eraseblocks are reserved for this volume
14143 - * @alignment: volume alignment
14144 - * @data_pad: how many bytes are unused at the end of the each physical
14145 - * eraseblock to satisfy the requested alignment
14146 - * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
14147 - * @upd_marker: if volume update was started but not finished
14148 - * @name_len: volume name length
14149 - * @name: the volume name
14150 - * @flags: volume flags (%UBI_VTBL_AUTORESIZE_FLG)
14151 - * @padding: reserved, zeroes
14152 - * @crc: a CRC32 checksum of the record
14153 - *
14154 - * The volume table records are stored in the volume table, which is stored in
14155 - * the layout volume. The layout volume consists of 2 logical eraseblock, each
14156 - * of which contains a copy of the volume table (i.e., the volume table is
14157 - * duplicated). The volume table is an array of &struct ubi_vtbl_record
14158 - * objects indexed by the volume ID.
14159 - *
14160 - * If the size of the logical eraseblock is large enough to fit
14161 - * %UBI_MAX_VOLUMES records, the volume table contains %UBI_MAX_VOLUMES
14162 - * records. Otherwise, it contains as many records as it can fit (i.e., size of
14163 - * logical eraseblock divided by sizeof(struct ubi_vtbl_record)).
14164 - *
14165 - * The @upd_marker flag is used to implement volume update. It is set to %1
14166 - * before update and set to %0 after the update. So if the update operation was
14167 - * interrupted, UBI knows that the volume is corrupted.
14168 - *
14169 - * The @alignment field is specified when the volume is created and cannot be
14170 - * later changed. It may be useful, for example, when a block-oriented file
14171 - * system works on top of UBI. The @data_pad field is calculated using the
14172 - * logical eraseblock size and @alignment. The alignment must be multiple to the
14173 - * minimal flash I/O unit. If @alignment is 1, all the available space of
14174 - * the physical eraseblocks is used.
14175 - *
14176 - * Empty records contain all zeroes and the CRC checksum of those zeroes.
14177 - */
14178 -struct ubi_vtbl_record {
14179 - __be32 reserved_pebs;
14180 - __be32 alignment;
14181 - __be32 data_pad;
14182 - __u8 vol_type;
14183 - __u8 upd_marker;
14184 - __be16 name_len;
14185 - __u8 name[UBI_VOL_NAME_MAX+1];
14186 - __u8 flags;
14187 - __u8 padding[23];
14188 - __be32 crc;
14189 -} __attribute__ ((packed));
14190 -
14191 -#endif /* !__UBI_HEADER_H__ */
14192 --- a/init/do_mounts.c
14193 +++ b/init/do_mounts.c
14194 @@ -126,8 +126,14 @@
14195
14196 static int __init rootwait_setup(char *str)
14197 {
14198 - if (*str)
14199 + if (*str && *str != '=')
14200 return 0;
14201 +
14202 + if (*str)
14203 + printk(KERN_WARNING
14204 + "WARNING: \"rootwait=1\" is deprecated, "
14205 + "use \"rootwait\" instead.\n");
14206 +
14207 root_wait = 1;
14208 return 1;
14209 }
14210 @@ -347,7 +353,8 @@
14211
14212 if (saved_root_name[0]) {
14213 root_device_name = saved_root_name;
14214 - if (!strncmp(root_device_name, "mtd", 3)) {
14215 + if (!strncmp(root_device_name, "mtd", 3) ||
14216 + !strncmp(root_device_name, "ubi", 3)) {
14217 mount_block_root(root_device_name, root_mountflags);
14218 goto out;
14219 }
14220 --- /dev/null
14221 +++ b/localversion-atmel
14222 @@ -0,0 +1 @@
14223 +.atmel.1
14224 --- /dev/null
14225 +++ b/sound/avr32/ac97c.c
14226 @@ -0,0 +1,914 @@
14227 +/*
14228 + * Driver for the Atmel AC97 controller
14229 + *
14230 + * Copyright (C) 2005-2007 Atmel Corporation
14231 + *
14232 + * This program is free software; you can redistribute it and/or modify it
14233 + * under the terms of the GNU General Public License version 2 as published by
14234 + * the Free Software Foundation.
14235 + */
14236 +#include <linux/clk.h>
14237 +#include <linux/delay.h>
14238 +#include <linux/dma-mapping.h>
14239 +#include <linux/init.h>
14240 +#include <linux/interrupt.h>
14241 +#include <linux/module.h>
14242 +#include <linux/platform_device.h>
14243 +#include <linux/mutex.h>
14244 +#include <linux/io.h>
14245 +
14246 +#include <sound/driver.h>
14247 +#include <sound/core.h>
14248 +#include <sound/initval.h>
14249 +#include <sound/pcm.h>
14250 +#include <sound/pcm_params.h>
14251 +#include <sound/ac97_codec.h>
14252 +#include <sound/memalloc.h>
14253 +
14254 +#include <asm/dma-controller.h>
14255 +
14256 +#include "ac97c.h"
14257 +
14258 +/* Serialize access to opened */
14259 +static DEFINE_MUTEX(opened_mutex);
14260 +
14261 +struct atmel_ac97_dma_info {
14262 + struct dma_request_cyclic req_tx;
14263 + struct dma_request_cyclic req_rx;
14264 + unsigned short rx_periph_id;
14265 + unsigned short tx_periph_id;
14266 +};
14267 +
14268 +struct atmel_ac97 {
14269 + /* Serialize access to opened */
14270 + spinlock_t lock;
14271 + void __iomem *regs;
14272 + struct snd_pcm_substream *playback_substream;
14273 + struct snd_pcm_substream *capture_substream;
14274 + struct snd_card *card;
14275 + struct snd_pcm *pcm;
14276 + struct snd_ac97 *ac97;
14277 + struct snd_ac97_bus *ac97_bus;
14278 + int opened;
14279 + int period;
14280 + u64 cur_format;
14281 + unsigned int cur_rate;
14282 + struct clk *mck;
14283 + struct platform_device *pdev;
14284 + struct atmel_ac97_dma_info dma;
14285 +};
14286 +
14287 +#define get_chip(card) ((struct atmel_ac97 *)(card)->private_data)
14288 +
14289 +#define ac97c_writel(chip, reg, val) \
14290 + __raw_writel((val), (chip)->regs + AC97C_##reg)
14291 +#define ac97c_readl(chip, reg) \
14292 + __raw_readl((chip)->regs + AC97C_##reg)
14293 +
14294 +/*
14295 + * PCM part
14296 + */
14297 +static struct snd_pcm_hardware snd_atmel_ac97_playback_hw = {
14298 + .info = (SNDRV_PCM_INFO_INTERLEAVED
14299 + | SNDRV_PCM_INFO_MMAP
14300 + | SNDRV_PCM_INFO_MMAP_VALID
14301 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
14302 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
14303 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
14304 + | SNDRV_PCM_FMTBIT_S16_LE),
14305 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
14306 + .rate_min = 4000,
14307 + .rate_max = 48000,
14308 + .channels_min = 1,
14309 + .channels_max = 6,
14310 + .buffer_bytes_max = 64*1024,
14311 + .period_bytes_min = 512,
14312 + .period_bytes_max = 4095,
14313 + .periods_min = 8,
14314 + .periods_max = 1024,
14315 +};
14316 +
14317 +static struct snd_pcm_hardware snd_atmel_ac97_capture_hw = {
14318 + .info = (SNDRV_PCM_INFO_INTERLEAVED
14319 + | SNDRV_PCM_INFO_MMAP
14320 + | SNDRV_PCM_INFO_MMAP_VALID
14321 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
14322 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
14323 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
14324 + | SNDRV_PCM_FMTBIT_S16_LE),
14325 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
14326 + .rate_min = 4000,
14327 + .rate_max = 48000,
14328 + .channels_min = 1,
14329 + .channels_max = 2,
14330 + .buffer_bytes_max = 64*1024,
14331 + .period_bytes_min = 512,
14332 + .period_bytes_max = 4095,
14333 + .periods_min = 8,
14334 + .periods_max = 1024,
14335 +};
14336 +
14337 +/*
14338 + * PCM functions
14339 + */
14340 +static int
14341 +snd_atmel_ac97_playback_open(struct snd_pcm_substream *substream)
14342 +{
14343 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14344 + struct snd_pcm_runtime *runtime = substream->runtime;
14345 +
14346 + mutex_lock(&opened_mutex);
14347 + chip->opened++;
14348 + runtime->hw = snd_atmel_ac97_playback_hw;
14349 + if (chip->cur_rate) {
14350 + runtime->hw.rate_min = chip->cur_rate;
14351 + runtime->hw.rate_max = chip->cur_rate;
14352 + }
14353 + if (chip->cur_format)
14354 + runtime->hw.formats = (1ULL << chip->cur_format);
14355 + mutex_unlock(&opened_mutex);
14356 + chip->playback_substream = substream;
14357 + chip->period = 0;
14358 + return 0;
14359 +}
14360 +
14361 +static int
14362 +snd_atmel_ac97_capture_open(struct snd_pcm_substream *substream)
14363 +{
14364 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14365 + struct snd_pcm_runtime *runtime = substream->runtime;
14366 +
14367 + mutex_lock(&opened_mutex);
14368 + chip->opened++;
14369 + runtime->hw = snd_atmel_ac97_capture_hw;
14370 + if (chip->cur_rate) {
14371 + runtime->hw.rate_min = chip->cur_rate;
14372 + runtime->hw.rate_max = chip->cur_rate;
14373 + }
14374 + if (chip->cur_format)
14375 + runtime->hw.formats = (1ULL << chip->cur_format);
14376 + mutex_unlock(&opened_mutex);
14377 + chip->capture_substream = substream;
14378 + chip->period = 0;
14379 + return 0;
14380 +}
14381 +
14382 +static int snd_atmel_ac97_playback_close(struct snd_pcm_substream *substream)
14383 +{
14384 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14385 + mutex_lock(&opened_mutex);
14386 + chip->opened--;
14387 + if (!chip->opened) {
14388 + chip->cur_rate = 0;
14389 + chip->cur_format = 0;
14390 + }
14391 + mutex_unlock(&opened_mutex);
14392 + return 0;
14393 +}
14394 +
14395 +static int snd_atmel_ac97_capture_close(struct snd_pcm_substream *substream)
14396 +{
14397 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14398 + mutex_lock(&opened_mutex);
14399 + chip->opened--;
14400 + if (!chip->opened) {
14401 + chip->cur_rate = 0;
14402 + chip->cur_format = 0;
14403 + }
14404 + mutex_unlock(&opened_mutex);
14405 + return 0;
14406 +}
14407 +
14408 +static int
14409 +snd_atmel_ac97_playback_hw_params(struct snd_pcm_substream *substream,
14410 + struct snd_pcm_hw_params *hw_params)
14411 +{
14412 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14413 + int err;
14414 +
14415 + err = snd_pcm_lib_malloc_pages(substream,
14416 + params_buffer_bytes(hw_params));
14417 + if (err < 0)
14418 + return err;
14419 +
14420 + /* Set restrictions to params */
14421 + mutex_lock(&opened_mutex);
14422 + chip->cur_rate = params_rate(hw_params);
14423 + chip->cur_format = params_format(hw_params);
14424 + mutex_unlock(&opened_mutex);
14425 +
14426 + return 0;
14427 +}
14428 +
14429 +static int
14430 +snd_atmel_ac97_capture_hw_params(struct snd_pcm_substream *substream,
14431 + struct snd_pcm_hw_params *hw_params)
14432 +{
14433 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14434 + int err;
14435 +
14436 + err = snd_pcm_lib_malloc_pages(substream,
14437 + params_buffer_bytes(hw_params));
14438 + if (err < 0)
14439 + return err;
14440 +
14441 + /* Set restrictions to params */
14442 + mutex_lock(&opened_mutex);
14443 + chip->cur_rate = params_rate(hw_params);
14444 + chip->cur_format = params_format(hw_params);
14445 + mutex_unlock(&opened_mutex);
14446 +
14447 + return 0;
14448 +}
14449 +
14450 +static int snd_atmel_ac97_playback_hw_free(struct snd_pcm_substream *substream)
14451 +{
14452 + return snd_pcm_lib_free_pages(substream);
14453 +}
14454 +
14455 +static int snd_atmel_ac97_capture_hw_free(struct snd_pcm_substream *substream)
14456 +{
14457 +
14458 + return snd_pcm_lib_free_pages(substream);
14459 +}
14460 +
14461 +static int snd_atmel_ac97_playback_prepare(struct snd_pcm_substream *substream)
14462 +{
14463 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14464 + struct platform_device *pdev = chip->pdev;
14465 + struct snd_pcm_runtime *runtime = substream->runtime;
14466 + int block_size = frames_to_bytes(runtime, runtime->period_size);
14467 + unsigned long word = 0;
14468 + unsigned long buffer_size = 0;
14469 +
14470 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
14471 + block_size * 2, DMA_TO_DEVICE);
14472 +
14473 + /* Assign slots to channels */
14474 + switch (substream->runtime->channels) {
14475 + case 1:
14476 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
14477 + break;
14478 + case 2:
14479 + /* Assign Left and Right slot to Channel A */
14480 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
14481 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
14482 + break;
14483 + default:
14484 + /* TODO: support more than two channels */
14485 + return -EINVAL;
14486 + break;
14487 + }
14488 + ac97c_writel(chip, OCA, word);
14489 +
14490 + /* Configure sample format and size */
14491 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
14492 +
14493 + switch (runtime->format) {
14494 + case SNDRV_PCM_FORMAT_S16_LE:
14495 + word |= AC97C_CMR_CEM_LITTLE;
14496 + break;
14497 + case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
14498 + default:
14499 + word &= ~AC97C_CMR_CEM_LITTLE;
14500 + break;
14501 + }
14502 +
14503 + ac97c_writel(chip, CAMR, word);
14504 +
14505 + /* Set variable rate if needed */
14506 + if (runtime->rate != 48000) {
14507 + word = ac97c_readl(chip, MR);
14508 + word |= AC97C_MR_VRA;
14509 + ac97c_writel(chip, MR, word);
14510 + } else {
14511 + /* Clear Variable Rate Bit */
14512 + word = ac97c_readl(chip, MR);
14513 + word &= ~AC97C_MR_VRA;
14514 + ac97c_writel(chip, MR, word);
14515 + }
14516 +
14517 + /* Set rate */
14518 + snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
14519 +
14520 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
14521 + runtime->periods;
14522 +
14523 + chip->dma.req_tx.buffer_size = buffer_size;
14524 + chip->dma.req_tx.periods = runtime->periods;
14525 +
14526 + BUG_ON(chip->dma.req_tx.buffer_size !=
14527 + (chip->dma.req_tx.periods *
14528 + frames_to_bytes(runtime, runtime->period_size)));
14529 +
14530 + chip->dma.req_tx.buffer_start = runtime->dma_addr;
14531 + chip->dma.req_tx.data_reg = (dma_addr_t)(chip->regs + AC97C_CATHR + 2);
14532 + chip->dma.req_tx.periph_id = chip->dma.tx_periph_id;
14533 + chip->dma.req_tx.direction = DMA_DIR_MEM_TO_PERIPH;
14534 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
14535 + chip->dma.req_tx.dev_id = chip;
14536 +
14537 + return 0;
14538 +}
14539 +
14540 +static int snd_atmel_ac97_capture_prepare(struct snd_pcm_substream *substream)
14541 +{
14542 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14543 + struct platform_device *pdev = chip->pdev;
14544 + struct snd_pcm_runtime *runtime = substream->runtime;
14545 + int block_size = frames_to_bytes(runtime, runtime->period_size);
14546 + unsigned long word = 0;
14547 + unsigned long buffer_size = 0;
14548 +
14549 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
14550 + block_size * 2, DMA_FROM_DEVICE);
14551 +
14552 + /* Assign slots to channels */
14553 + switch (substream->runtime->channels) {
14554 + case 1:
14555 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
14556 + break;
14557 + case 2:
14558 + /* Assign Left and Right slot to Channel A */
14559 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
14560 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
14561 + break;
14562 + default:
14563 + /* TODO: support more than two channels */
14564 + return -EINVAL;
14565 + break;
14566 + }
14567 + ac97c_writel(chip, ICA, word);
14568 +
14569 + /* Configure sample format and size */
14570 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
14571 +
14572 + switch (runtime->format) {
14573 + case SNDRV_PCM_FORMAT_S16_LE:
14574 + word |= AC97C_CMR_CEM_LITTLE;
14575 + break;
14576 + case SNDRV_PCM_FORMAT_S16_BE:
14577 + default:
14578 + word &= ~(AC97C_CMR_CEM_LITTLE);
14579 + break;
14580 + }
14581 +
14582 + ac97c_writel(chip, CAMR, word);
14583 +
14584 + /* Set variable rate if needed */
14585 + if (runtime->rate != 48000) {
14586 + word = ac97c_readl(chip, MR);
14587 + word |= AC97C_MR_VRA;
14588 + ac97c_writel(chip, MR, word);
14589 + } else {
14590 + /* Clear Variable Rate Bit */
14591 + word = ac97c_readl(chip, MR);
14592 + word &= ~(AC97C_MR_VRA);
14593 + ac97c_writel(chip, MR, word);
14594 + }
14595 +
14596 + /* Set rate */
14597 + snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
14598 +
14599 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
14600 + runtime->periods;
14601 +
14602 + chip->dma.req_rx.buffer_size = buffer_size;
14603 + chip->dma.req_rx.periods = runtime->periods;
14604 +
14605 + BUG_ON(chip->dma.req_rx.buffer_size !=
14606 + (chip->dma.req_rx.periods *
14607 + frames_to_bytes(runtime, runtime->period_size)));
14608 +
14609 + chip->dma.req_rx.buffer_start = runtime->dma_addr;
14610 + chip->dma.req_rx.data_reg = (dma_addr_t)(chip->regs + AC97C_CARHR + 2);
14611 + chip->dma.req_rx.periph_id = chip->dma.rx_periph_id;
14612 + chip->dma.req_rx.direction = DMA_DIR_PERIPH_TO_MEM;
14613 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
14614 + chip->dma.req_rx.dev_id = chip;
14615 +
14616 + return 0;
14617 +}
14618 +
14619 + static int
14620 +snd_atmel_ac97_playback_trigger(struct snd_pcm_substream *substream, int cmd)
14621 +{
14622 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14623 + unsigned long camr;
14624 + int flags, err = 0;
14625 +
14626 + spin_lock_irqsave(&chip->lock, flags);
14627 + camr = ac97c_readl(chip, CAMR);
14628 +
14629 + switch (cmd) {
14630 + case SNDRV_PCM_TRIGGER_START:
14631 + err = dma_prepare_request_cyclic(chip->dma.req_tx.req.dmac,
14632 + &chip->dma.req_tx);
14633 + dma_start_request(chip->dma.req_tx.req.dmac,
14634 + chip->dma.req_tx.req.channel);
14635 + camr |= AC97C_CMR_CENA;
14636 + break;
14637 + case SNDRV_PCM_TRIGGER_STOP:
14638 + err = dma_stop_request(chip->dma.req_tx.req.dmac,
14639 + chip->dma.req_tx.req.channel);
14640 + if (chip->opened <= 1)
14641 + camr &= ~AC97C_CMR_CENA;
14642 + break;
14643 + default:
14644 + err = -EINVAL;
14645 + break;
14646 + }
14647 +
14648 + ac97c_writel(chip, CAMR, camr);
14649 +
14650 + spin_unlock_irqrestore(&chip->lock, flags);
14651 + return err;
14652 +}
14653 +
14654 + static int
14655 +snd_atmel_ac97_capture_trigger(struct snd_pcm_substream *substream, int cmd)
14656 +{
14657 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14658 + unsigned long camr;
14659 + int flags, err = 0;
14660 +
14661 + spin_lock_irqsave(&chip->lock, flags);
14662 + camr = ac97c_readl(chip, CAMR);
14663 +
14664 + switch (cmd) {
14665 + case SNDRV_PCM_TRIGGER_START:
14666 + err = dma_prepare_request_cyclic(chip->dma.req_rx.req.dmac,
14667 + &chip->dma.req_rx);
14668 + dma_start_request(chip->dma.req_rx.req.dmac,
14669 + chip->dma.req_rx.req.channel);
14670 + camr |= AC97C_CMR_CENA;
14671 + break;
14672 + case SNDRV_PCM_TRIGGER_STOP:
14673 + err = dma_stop_request(chip->dma.req_rx.req.dmac,
14674 + chip->dma.req_rx.req.channel);
14675 + mutex_lock(&opened_mutex);
14676 + if (chip->opened <= 1)
14677 + camr &= ~AC97C_CMR_CENA;
14678 + mutex_unlock(&opened_mutex);
14679 + break;
14680 + default:
14681 + err = -EINVAL;
14682 + break;
14683 + }
14684 +
14685 + ac97c_writel(chip, CAMR, camr);
14686 +
14687 + spin_unlock_irqrestore(&chip->lock, flags);
14688 + return err;
14689 +}
14690 +
14691 + static snd_pcm_uframes_t
14692 +snd_atmel_ac97_playback_pointer(struct snd_pcm_substream *substream)
14693 +{
14694 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14695 + struct snd_pcm_runtime *runtime = substream->runtime;
14696 + snd_pcm_uframes_t pos;
14697 + unsigned long bytes;
14698 +
14699 + bytes = (dma_get_current_pos
14700 + (chip->dma.req_tx.req.dmac,
14701 + chip->dma.req_tx.req.channel) - runtime->dma_addr);
14702 + pos = bytes_to_frames(runtime, bytes);
14703 + if (pos >= runtime->buffer_size)
14704 + pos -= runtime->buffer_size;
14705 +
14706 + return pos;
14707 +}
14708 +
14709 + static snd_pcm_uframes_t
14710 +snd_atmel_ac97_capture_pointer(struct snd_pcm_substream *substream)
14711 +{
14712 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
14713 + struct snd_pcm_runtime *runtime = substream->runtime;
14714 + snd_pcm_uframes_t pos;
14715 + unsigned long bytes;
14716 +
14717 + bytes = (dma_get_current_pos
14718 + (chip->dma.req_rx.req.dmac,
14719 + chip->dma.req_rx.req.channel)
14720 + - runtime->dma_addr);
14721 + pos = bytes_to_frames(runtime, bytes);
14722 + if (pos >= runtime->buffer_size)
14723 + pos -= runtime->buffer_size;
14724 +
14725 +
14726 + return pos;
14727 +}
14728 +
14729 +static struct snd_pcm_ops atmel_ac97_playback_ops = {
14730 + .open = snd_atmel_ac97_playback_open,
14731 + .close = snd_atmel_ac97_playback_close,
14732 + .ioctl = snd_pcm_lib_ioctl,
14733 + .hw_params = snd_atmel_ac97_playback_hw_params,
14734 + .hw_free = snd_atmel_ac97_playback_hw_free,
14735 + .prepare = snd_atmel_ac97_playback_prepare,
14736 + .trigger = snd_atmel_ac97_playback_trigger,
14737 + .pointer = snd_atmel_ac97_playback_pointer,
14738 +};
14739 +
14740 +static struct snd_pcm_ops atmel_ac97_capture_ops = {
14741 + .open = snd_atmel_ac97_capture_open,
14742 + .close = snd_atmel_ac97_capture_close,
14743 + .ioctl = snd_pcm_lib_ioctl,
14744 + .hw_params = snd_atmel_ac97_capture_hw_params,
14745 + .hw_free = snd_atmel_ac97_capture_hw_free,
14746 + .prepare = snd_atmel_ac97_capture_prepare,
14747 + .trigger = snd_atmel_ac97_capture_trigger,
14748 + .pointer = snd_atmel_ac97_capture_pointer,
14749 +};
14750 +
14751 +static struct ac97_pcm atmel_ac97_pcm_defs[] __devinitdata = {
14752 + /* Playback */
14753 + {
14754 + .exclusive = 1,
14755 + .r = { {
14756 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
14757 + | (1 << AC97_SLOT_PCM_RIGHT)
14758 + | (1 << AC97_SLOT_PCM_CENTER)
14759 + | (1 << AC97_SLOT_PCM_SLEFT)
14760 + | (1 << AC97_SLOT_PCM_SRIGHT)
14761 + | (1 << AC97_SLOT_LFE)),
14762 + } }
14763 + },
14764 + /* PCM in */
14765 + {
14766 + .stream = 1,
14767 + .exclusive = 1,
14768 + .r = { {
14769 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
14770 + | (1 << AC97_SLOT_PCM_RIGHT)),
14771 + } }
14772 + },
14773 + /* Mic in */
14774 + {
14775 + .stream = 1,
14776 + .exclusive = 1,
14777 + .r = { {
14778 + .slots = (1<<AC97_SLOT_MIC),
14779 + } }
14780 + },
14781 +};
14782 +
14783 +static int __devinit snd_atmel_ac97_pcm_new(struct atmel_ac97 *chip)
14784 +{
14785 + struct snd_pcm *pcm;
14786 + int err;
14787 +
14788 + err = snd_ac97_pcm_assign(chip->ac97_bus,
14789 + ARRAY_SIZE(atmel_ac97_pcm_defs),
14790 + atmel_ac97_pcm_defs);
14791 + if (err)
14792 + return err;
14793 +
14794 + err = snd_pcm_new(chip->card, "Atmel-AC97", 0, 1, 1, &pcm);
14795 + if (err)
14796 + return err;
14797 +
14798 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
14799 + &atmel_ac97_playback_ops);
14800 +
14801 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
14802 + &atmel_ac97_capture_ops);
14803 +
14804 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
14805 + &chip->pdev->dev,
14806 + 128 * 1024, 128 * 1024);
14807 +
14808 + pcm->private_data = chip;
14809 + pcm->info_flags = 0;
14810 + strcpy(pcm->name, "Atmel-AC97");
14811 + chip->pcm = pcm;
14812 +
14813 + return 0;
14814 +}
14815 +
14816 +/*
14817 + * Mixer part.
14818 + */
14819 +static int snd_atmel_ac97_mixer_new(struct atmel_ac97 *chip)
14820 +{
14821 + int err;
14822 + struct snd_ac97_template template;
14823 +
14824 + memset(&template, 0, sizeof(template));
14825 + template.private_data = chip;
14826 + err = snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
14827 +
14828 + return err;
14829 +}
14830 +
14831 +static void atmel_ac97_error(struct dma_request *_req)
14832 +{
14833 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
14834 + struct atmel_ac97 *chip = req->dev_id;
14835 +
14836 + dev_dbg(&chip->pdev->dev, "DMA Controller error, channel %d\n",
14837 + req->req.channel);
14838 +}
14839 +
14840 +static void atmel_ac97_block_complete(struct dma_request *_req)
14841 +{
14842 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
14843 + struct atmel_ac97 *chip = req->dev_id;
14844 + if (req->periph_id == chip->dma.tx_periph_id)
14845 + snd_pcm_period_elapsed(chip->playback_substream);
14846 + else
14847 + snd_pcm_period_elapsed(chip->capture_substream);
14848 +}
14849 +
14850 +/*
14851 + * Codec part.
14852 + */
14853 +static void snd_atmel_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
14854 + unsigned short val)
14855 +{
14856 + struct atmel_ac97 *chip = get_chip(ac97);
14857 + unsigned long word;
14858 + int timeout = 40;
14859 +
14860 + word = (reg & 0x7f) << 16 | val;
14861 +
14862 + do {
14863 + if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
14864 + ac97c_writel(chip, COTHR, word);
14865 + return;
14866 + }
14867 + udelay(1);
14868 + } while (--timeout);
14869 +
14870 + dev_dbg(&chip->pdev->dev, "codec write timeout\n");
14871 +}
14872 +
14873 +static unsigned short snd_atmel_ac97_read(struct snd_ac97 *ac97,
14874 + unsigned short reg)
14875 +{
14876 + struct atmel_ac97 *chip = get_chip(ac97);
14877 + unsigned long word;
14878 + int timeout = 40;
14879 + int write = 10;
14880 +
14881 + word = (0x80 | (reg & 0x7f)) << 16;
14882 +
14883 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
14884 + ac97c_readl(chip, CORHR);
14885 +
14886 +retry_write:
14887 + timeout = 40;
14888 +
14889 + do {
14890 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
14891 + ac97c_writel(chip, COTHR, word);
14892 + goto read_reg;
14893 + }
14894 + udelay(10);
14895 + } while (--timeout);
14896 +
14897 + if (!--write)
14898 + goto timed_out;
14899 + goto retry_write;
14900 +
14901 +read_reg:
14902 + do {
14903 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
14904 + unsigned short val = ac97c_readl(chip, CORHR);
14905 + return val;
14906 + }
14907 + udelay(10);
14908 + } while (--timeout);
14909 +
14910 + if (!--write)
14911 + goto timed_out;
14912 + goto retry_write;
14913 +
14914 +timed_out:
14915 + dev_dbg(&chip->pdev->dev, "codec read timeout\n");
14916 + return 0xffff;
14917 +}
14918 +
14919 +static void snd_atmel_ac97_reset(struct atmel_ac97 *chip)
14920 +{
14921 + ac97c_writel(chip, MR, AC97C_MR_WRST);
14922 + mdelay(1);
14923 + ac97c_writel(chip, MR, AC97C_MR_ENA);
14924 +}
14925 +
14926 +static void snd_atmel_ac97_destroy(struct snd_card *card)
14927 +{
14928 + struct atmel_ac97 *chip = get_chip(card);
14929 +
14930 + if (chip->regs)
14931 + iounmap(chip->regs);
14932 +
14933 + if (chip->mck) {
14934 + clk_disable(chip->mck);
14935 + clk_put(chip->mck);
14936 + }
14937 +
14938 + if (chip->dma.req_tx.req.dmac) {
14939 + dma_release_channel(chip->dma.req_tx.req.dmac,
14940 + chip->dma.req_tx.req.channel);
14941 + }
14942 + if (chip->dma.req_rx.req.dmac) {
14943 + dma_release_channel(chip->dma.req_rx.req.dmac,
14944 + chip->dma.req_rx.req.channel);
14945 + }
14946 +}
14947 +
14948 +static int __devinit snd_atmel_ac97_create(struct snd_card *card,
14949 + struct platform_device *pdev)
14950 +{
14951 + static struct snd_ac97_bus_ops ops = {
14952 + .write = snd_atmel_ac97_write,
14953 + .read = snd_atmel_ac97_read,
14954 + };
14955 + struct atmel_ac97 *chip = get_chip(card);
14956 + struct resource *regs;
14957 + struct clk *mck;
14958 + int err;
14959 +
14960 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
14961 + if (!regs)
14962 + return -ENXIO;
14963 +
14964 + mck = clk_get(&pdev->dev, "pclk");
14965 + if (IS_ERR(mck))
14966 + return PTR_ERR(mck);
14967 + clk_enable(mck);
14968 + chip->mck = mck;
14969 +
14970 + card->private_free = snd_atmel_ac97_destroy;
14971 +
14972 + spin_lock_init(&chip->lock);
14973 + chip->card = card;
14974 + chip->pdev = pdev;
14975 +
14976 + chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
14977 + if (!chip->regs)
14978 + return -ENOMEM;
14979 +
14980 + snd_card_set_dev(card, &pdev->dev);
14981 +
14982 + err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
14983 +
14984 + return err;
14985 +}
14986 +
14987 +static int __devinit snd_atmel_ac97_probe(struct platform_device *pdev)
14988 +{
14989 + static int dev;
14990 + struct snd_card *card;
14991 + struct atmel_ac97 *chip;
14992 + int err;
14993 + int ch;
14994 +
14995 + mutex_init(&opened_mutex);
14996 +
14997 + err = -ENOMEM;
14998 + card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
14999 + THIS_MODULE, sizeof(struct atmel_ac97));
15000 + if (!card)
15001 + goto out;
15002 + chip = get_chip(card);
15003 +
15004 + err = snd_atmel_ac97_create(card, pdev);
15005 + if (err)
15006 + goto out_free_card;
15007 +
15008 + snd_atmel_ac97_reset(chip);
15009 +
15010 + err = snd_atmel_ac97_mixer_new(chip);
15011 + if (err)
15012 + goto out_free_card;
15013 +
15014 + err = snd_atmel_ac97_pcm_new(chip);
15015 + if (err)
15016 + goto out_free_card;
15017 +
15018 + /* TODO: Get this information from the platform device */
15019 + chip->dma.req_tx.req.dmac = find_dma_controller(0);
15020 + if (!chip->dma.req_tx.req.dmac) {
15021 + dev_dbg(&chip->pdev->dev, "DMA controller for TX missing\n");
15022 + err = -ENODEV;
15023 + goto out_free_card;
15024 + }
15025 + chip->dma.req_rx.req.dmac = find_dma_controller(0);
15026 + if (!chip->dma.req_rx.req.dmac) {
15027 + dev_dbg(&chip->pdev->dev, "DMA controller for RX missing\n");
15028 + err = -ENODEV;
15029 + goto out_free_card;
15030 + }
15031 +
15032 + chip->dma.rx_periph_id = 3;
15033 + chip->dma.tx_periph_id = 4;
15034 +
15035 + ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
15036 + if (ch < 0) {
15037 + dev_dbg(&chip->pdev->dev,
15038 + "could not allocate TX DMA channel\n");
15039 + err = ch;
15040 + goto out_free_card;
15041 + }
15042 + chip->dma.req_tx.req.channel = ch;
15043 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
15044 + chip->dma.req_tx.req.block_complete = atmel_ac97_block_complete;
15045 + chip->dma.req_tx.req.error = atmel_ac97_error;
15046 +
15047 + ch = dma_alloc_channel(chip->dma.req_rx.req.dmac);
15048 + if (ch < 0) {
15049 + dev_dbg(&chip->pdev->dev,
15050 + "could not allocate RX DMA channel\n");
15051 + err = ch;
15052 + goto out_free_card;
15053 + }
15054 + chip->dma.req_rx.req.channel = ch;
15055 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
15056 + chip->dma.req_rx.req.block_complete = atmel_ac97_block_complete;
15057 + chip->dma.req_rx.req.error = atmel_ac97_error;
15058 +
15059 + strcpy(card->driver, "atmel_ac97c");
15060 + strcpy(card->shortname, "atmel_ac97c");
15061 + sprintf(card->longname, "Atmel AVR32 AC97 controller");
15062 +
15063 + err = snd_card_register(card);
15064 + if (err)
15065 + goto out_free_card;
15066 +
15067 + platform_set_drvdata(pdev, card);
15068 + dev++;
15069 +
15070 + dev_info(&pdev->dev, "Atmel AVR32 AC97 controller at 0x%p\n",
15071 + chip->regs);
15072 +
15073 + return 0;
15074 +
15075 +out_free_card:
15076 + snd_card_free(card);
15077 +out:
15078 + return err;
15079 +}
15080 +
15081 +#ifdef CONFIG_PM
15082 + static int
15083 +snd_atmel_ac97_suspend(struct platform_device *pdev, pm_message_t msg)
15084 +{
15085 + struct snd_card *card = platform_get_drvdata(pdev);
15086 + struct atmel_ac97 *chip = card->private_data;
15087 +
15088 + clk_disable(chip->mck);
15089 +
15090 + return 0;
15091 +}
15092 +
15093 +static int snd_atmel_ac97_resume(struct platform_device *pdev)
15094 +{
15095 + struct snd_card *card = dev_get_drvdata(pdev);
15096 + struct atmel_ac97 *chip = card->private_data;
15097 +
15098 + clk_enable(chip->mck);
15099 +
15100 + return 0;
15101 +}
15102 +#else
15103 +#define snd_atmel_ac97_suspend NULL
15104 +#define snd_atmel_ac97_resume NULL
15105 +#endif
15106 +
15107 +static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
15108 +{
15109 + struct snd_card *card = platform_get_drvdata(pdev);
15110 +
15111 + snd_card_free(card);
15112 + platform_set_drvdata(pdev, NULL);
15113 + return 0;
15114 +}
15115 +
15116 +static struct platform_driver atmel_ac97_driver = {
15117 + .remove = __devexit_p(snd_atmel_ac97_remove),
15118 + .driver = {
15119 + .name = "atmel_ac97c",
15120 + },
15121 + .suspend = snd_atmel_ac97_suspend,
15122 + .resume = snd_atmel_ac97_resume,
15123 +};
15124 +
15125 +static int __init atmel_ac97_init(void)
15126 +{
15127 + return platform_driver_probe(&atmel_ac97_driver,
15128 + snd_atmel_ac97_probe);
15129 +}
15130 +module_init(atmel_ac97_init);
15131 +
15132 +static void __exit atmel_ac97_exit(void)
15133 +{
15134 + platform_driver_unregister(&atmel_ac97_driver);
15135 +}
15136 +module_exit(atmel_ac97_exit);
15137 +
15138 +MODULE_LICENSE("GPL");
15139 +MODULE_DESCRIPTION("Driver for Atmel AC97 Controller");
15140 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
15141 --- /dev/null
15142 +++ b/sound/avr32/ac97c.h
15143 @@ -0,0 +1,71 @@
15144 +/*
15145 + * Register definitions for the Atmel AC97 Controller.
15146 + *
15147 + * Copyright (C) 2005-2006 Atmel Corporation
15148 + *
15149 + * This program is free software; you can redistribute it and/or modify
15150 + * it under the terms of the GNU General Public License version 2 as
15151 + * published by the Free Software Foundation.
15152 + */
15153 +#ifndef __SOUND_AVR32_AC97C_H
15154 +#define __SOUND_AVR32_AC97C_H
15155 +
15156 +#define AC97C_MR 0x08
15157 +#define AC97C_ICA 0x10
15158 +#define AC97C_OCA 0x14
15159 +#define AC97C_CARHR 0x20
15160 +#define AC97C_CATHR 0x24
15161 +#define AC97C_CASR 0x28
15162 +#define AC97C_CAMR 0x2c
15163 +#define AC97C_CBRHR 0x30
15164 +#define AC97C_CBTHR 0x34
15165 +#define AC97C_CBSR 0x38
15166 +#define AC97C_CBMR 0x3c
15167 +#define AC97C_CORHR 0x40
15168 +#define AC97C_COTHR 0x44
15169 +#define AC97C_COSR 0x48
15170 +#define AC97C_COMR 0x4c
15171 +#define AC97C_SR 0x50
15172 +#define AC97C_IER 0x54
15173 +#define AC97C_IDR 0x58
15174 +#define AC97C_IMR 0x5c
15175 +#define AC97C_VERSION 0xfc
15176 +
15177 +#define AC97C_CATPR PDC_TPR
15178 +#define AC97C_CATCR PDC_TCR
15179 +#define AC97C_CATNPR PDC_TNPR
15180 +#define AC97C_CATNCR PDC_TNCR
15181 +#define AC97C_CARPR PDC_RPR
15182 +#define AC97C_CARCR PDC_RCR
15183 +#define AC97C_CARNPR PDC_RNPR
15184 +#define AC97C_CARNCR PDC_RNCR
15185 +#define AC97C_PTCR PDC_PTCR
15186 +
15187 +#define AC97C_MR_ENA (1 << 0)
15188 +#define AC97C_MR_WRST (1 << 1)
15189 +#define AC97C_MR_VRA (1 << 2)
15190 +
15191 +#define AC97C_CSR_TXRDY (1 << 0)
15192 +#define AC97C_CSR_UNRUN (1 << 2)
15193 +#define AC97C_CSR_RXRDY (1 << 4)
15194 +#define AC97C_CSR_ENDTX (1 << 10)
15195 +#define AC97C_CSR_ENDRX (1 << 14)
15196 +
15197 +#define AC97C_CMR_SIZE_20 (0 << 16)
15198 +#define AC97C_CMR_SIZE_18 (1 << 16)
15199 +#define AC97C_CMR_SIZE_16 (2 << 16)
15200 +#define AC97C_CMR_SIZE_10 (3 << 16)
15201 +#define AC97C_CMR_CEM_LITTLE (1 << 18)
15202 +#define AC97C_CMR_CEM_BIG (0 << 18)
15203 +#define AC97C_CMR_CENA (1 << 21)
15204 +#define AC97C_CMR_PDCEN (1 << 22)
15205 +
15206 +#define AC97C_SR_CAEVT (1 << 3)
15207 +
15208 +#define AC97C_CH_ASSIGN(slot, channel) \
15209 + (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
15210 +#define AC97C_CHANNEL_NONE 0x0
15211 +#define AC97C_CHANNEL_A 0x1
15212 +#define AC97C_CHANNEL_B 0x2
15213 +
15214 +#endif /* __SOUND_AVR32_AC97C_H */
15215 --- /dev/null
15216 +++ b/sound/avr32/Kconfig
15217 @@ -0,0 +1,11 @@
15218 +menu "AVR32 devices"
15219 + depends on SND != n && AVR32
15220 +
15221 +config SND_ATMEL_AC97
15222 + tristate "Atmel AC97 Controller Driver"
15223 + select SND_PCM
15224 + select SND_AC97_CODEC
15225 + help
15226 + ALSA sound driver for the Atmel AC97 controller.
15227 +
15228 +endmenu
15229 --- /dev/null
15230 +++ b/sound/avr32/Makefile
15231 @@ -0,0 +1,3 @@
15232 +snd-atmel-ac97-objs := ac97c.o
15233 +
15234 +obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
15235 --- a/sound/Kconfig
15236 +++ b/sound/Kconfig
15237 @@ -63,6 +63,8 @@
15238
15239 source "sound/arm/Kconfig"
15240
15241 +source "sound/avr32/Kconfig"
15242 +
15243 if SPI
15244 source "sound/spi/Kconfig"
15245 endif
15246 --- a/sound/Makefile
15247 +++ b/sound/Makefile
15248 @@ -6,7 +6,7 @@
15249 obj-$(CONFIG_SOUND_PRIME) += oss/
15250 obj-$(CONFIG_DMASOUND) += oss/
15251 obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
15252 - sparc/ spi/ parisc/ pcmcia/ mips/ soc/
15253 + sparc/ spi/ parisc/ pcmcia/ mips/ soc/ avr32/
15254 obj-$(CONFIG_SND_AOA) += aoa/
15255
15256 # This one must be compilable even if sound is configured out
15257 --- /dev/null
15258 +++ b/sound/oss/at32_abdac.c
15259 @@ -0,0 +1,722 @@
15260 +/*
15261 + * OSS Sound Driver for the Atmel AT32 on-chip DAC.
15262 + *
15263 + * Copyright (C) 2006 Atmel Corporation
15264 + *
15265 + * This program is free software; you can redistribute it and/or modify
15266 + * it under the terms of the GNU General Public License version 2 as
15267 + * published by the Free Software Foundation.
15268 + */
15269 +#include <linux/clk.h>
15270 +#include <linux/dma-mapping.h>
15271 +#include <linux/fs.h>
15272 +#include <linux/init.h>
15273 +#include <linux/interrupt.h>
15274 +#include <linux/kernel.h>
15275 +#include <linux/module.h>
15276 +#include <linux/platform_device.h>
15277 +#include <linux/sound.h>
15278 +#include <linux/soundcard.h>
15279 +
15280 +#include <asm/byteorder.h>
15281 +#include <asm/dma-controller.h>
15282 +#include <asm/io.h>
15283 +#include <asm/uaccess.h>
15284 +
15285 +/* We want to use the "bizarre" swap-bytes-in-each-halfword macro */
15286 +#include <linux/byteorder/swabb.h>
15287 +
15288 +#include "at32_abdac.h"
15289 +
15290 +#define DMA_BUFFER_SIZE 32768
15291 +#define DMA_PERIOD_SHIFT 10
15292 +#define DMA_PERIOD_SIZE (1 << DMA_PERIOD_SHIFT)
15293 +#define DMA_WRITE_THRESHOLD DMA_PERIOD_SIZE
15294 +
15295 +struct sound_settings {
15296 + unsigned int format;
15297 + unsigned int channels;
15298 + unsigned int sample_rate;
15299 + /* log2(bytes per sample) */
15300 + unsigned int input_order;
15301 +};
15302 +
15303 +struct at32_dac {
15304 + spinlock_t lock;
15305 + void __iomem *regs;
15306 +
15307 + /* head and tail refer to number of words */
15308 + struct {
15309 + u32 *buf;
15310 + int head;
15311 + int tail;
15312 + } dma;
15313 +
15314 + struct semaphore sem;
15315 + wait_queue_head_t write_wait;
15316 +
15317 + /*
15318 + * Read at most ucount bytes from ubuf, translate to 2-channel
15319 + * signed 16-bit big endian format and write to the DMA buffer
15320 + * as long as there is room left. Return the number of bytes
15321 + * successfully copied from ubuf, or -EFAULT if the first
15322 + * sample from ubuf couldn't be read. This function is not
15323 + * called unless there is room for at least one sample (4
15324 + * bytes) in the DMA buffer.
15325 + */
15326 + ssize_t (*trans)(struct at32_dac *dac, const char __user *ubuf,
15327 + size_t ucount);
15328 +
15329 + struct sound_settings dsp_settings;
15330 + struct dma_request_cyclic req;
15331 +
15332 + struct clk *mck;
15333 + struct clk *sample_clk;
15334 + struct platform_device *pdev;
15335 + int busy;
15336 + int playing;
15337 + int dev_dsp;
15338 +};
15339 +static struct at32_dac *the_dac;
15340 +
15341 +static inline unsigned int abdac_get_head(struct at32_dac *dac)
15342 +{
15343 + return dac->dma.head & ((DMA_BUFFER_SIZE / 4) - 1);
15344 +}
15345 +
15346 +static inline unsigned int abdac_get_tail(struct at32_dac *dac)
15347 +{
15348 + return dac->dma.tail & ((DMA_BUFFER_SIZE / 4) - 1);
15349 +}
15350 +
15351 +static inline unsigned int abdac_dma_space(struct at32_dac *dac)
15352 +{
15353 + unsigned int space;
15354 +
15355 + space = ((dac->dma.tail - dac->dma.head - 1)
15356 + & ((DMA_BUFFER_SIZE / 4) - 1));
15357 + return space;
15358 +}
15359 +
15360 +static void abdac_update_dma_tail(struct at32_dac *dac)
15361 +{
15362 + dma_addr_t dma_addr;
15363 + unsigned int new_tail;
15364 +
15365 + if (dac->playing) {
15366 + dma_addr = dma_get_current_pos(dac->req.req.dmac,
15367 + dac->req.req.channel);
15368 + new_tail = (dma_addr - dac->req.buffer_start) / 4;
15369 + if (new_tail >= dac->dma.head
15370 + && (dac->dma.tail < dac->dma.head
15371 + || dac->dma.tail > new_tail))
15372 + dev_notice(&dac->pdev->dev, "DMA underrun detected!\n");
15373 + dac->dma.tail = new_tail;
15374 + dev_dbg(&dac->pdev->dev, "update tail: 0x%x - 0x%x = %u\n",
15375 + dma_addr, dac->req.buffer_start, dac->dma.tail);
15376 + }
15377 +}
15378 +
15379 +static int abdac_start(struct at32_dac *dac)
15380 +{
15381 + int ret;
15382 +
15383 + if (dac->playing)
15384 + return 0;
15385 +
15386 + memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
15387 +
15388 + clk_enable(dac->sample_clk);
15389 +
15390 + ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
15391 + if (ret)
15392 + goto out_stop_clock;
15393 +
15394 + dev_dbg(&dac->pdev->dev, "starting DMA...\n");
15395 + ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
15396 + if (ret)
15397 + goto out_stop_request;
15398 +
15399 + dac_writel(dac, CTRL, DAC_BIT(EN));
15400 + dac->playing = 1;
15401 +
15402 + return 0;
15403 +
15404 +out_stop_request:
15405 + dma_stop_request(dac->req.req.dmac,
15406 + dac->req.req.channel);
15407 +out_stop_clock:
15408 + clk_disable(dac->sample_clk);
15409 + return ret;
15410 +}
15411 +
15412 +static int abdac_stop(struct at32_dac *dac)
15413 +{
15414 + if (dac->playing) {
15415 + dma_stop_request(dac->req.req.dmac, dac->req.req.channel);
15416 + dac_writel(dac, DATA, 0);
15417 + dac_writel(dac, CTRL, 0);
15418 + dac->playing = 0;
15419 + clk_disable(dac->sample_clk);
15420 + }
15421 +
15422 + return 0;
15423 +}
15424 +
15425 +static int abdac_dma_prepare(struct at32_dac *dac)
15426 +{
15427 + dac->dma.buf = dma_alloc_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
15428 + &dac->req.buffer_start, GFP_KERNEL);
15429 + if (!dac->dma.buf)
15430 + return -ENOMEM;
15431 +
15432 + dac->dma.head = dac->dma.tail = 0;
15433 + dac->req.periods = DMA_BUFFER_SIZE / DMA_PERIOD_SIZE;
15434 + dac->req.buffer_size = DMA_BUFFER_SIZE;
15435 +
15436 + return 0;
15437 +}
15438 +
15439 +static void abdac_dma_cleanup(struct at32_dac *dac)
15440 +{
15441 + if (dac->dma.buf)
15442 + dma_free_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
15443 + dac->dma.buf, dac->req.buffer_start);
15444 + dac->dma.buf = NULL;
15445 +}
15446 +
15447 +static void abdac_dma_block_complete(struct dma_request *req)
15448 +{
15449 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
15450 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
15451 +
15452 + wake_up(&dac->write_wait);
15453 +}
15454 +
15455 +static void abdac_dma_error(struct dma_request *req)
15456 +{
15457 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
15458 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
15459 +
15460 + dev_err(&dac->pdev->dev, "DMA error\n");
15461 +}
15462 +
15463 +static irqreturn_t abdac_interrupt(int irq, void *dev_id)
15464 +{
15465 + struct at32_dac *dac = dev_id;
15466 + u32 status;
15467 +
15468 + status = dac_readl(dac, INT_STATUS);
15469 + if (status & DAC_BIT(UNDERRUN)) {
15470 + dev_err(&dac->pdev->dev, "Underrun detected!\n");
15471 + dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
15472 + } else {
15473 + dev_err(&dac->pdev->dev, "Spurious interrupt (status=0x%x)\n",
15474 + status);
15475 + dac_writel(dac, INT_CLR, status);
15476 + }
15477 +
15478 + return IRQ_HANDLED;
15479 +}
15480 +
15481 +static ssize_t trans_s16be(struct at32_dac *dac, const char __user *ubuf,
15482 + size_t ucount)
15483 +{
15484 + ssize_t ret;
15485 +
15486 + if (dac->dsp_settings.channels == 2) {
15487 + const u32 __user *up = (const u32 __user *)ubuf;
15488 + u32 sample;
15489 +
15490 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
15491 + if (!abdac_dma_space(dac))
15492 + break;
15493 +
15494 + if (unlikely(__get_user(sample, up++))) {
15495 + if (ret == 0)
15496 + ret = -EFAULT;
15497 + break;
15498 + }
15499 + dac->dma.buf[abdac_get_head(dac)] = sample;
15500 + dac->dma.head++;
15501 + }
15502 + } else {
15503 + const u16 __user *up = (const u16 __user *)ubuf;
15504 + u16 sample;
15505 +
15506 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
15507 + if (!abdac_dma_space(dac))
15508 + break;
15509 +
15510 + if (unlikely(__get_user(sample, up++))) {
15511 + if (ret == 0)
15512 + ret = -EFAULT;
15513 + break;
15514 + }
15515 + dac->dma.buf[abdac_get_head(dac)]
15516 + = (sample << 16) | sample;
15517 + dac->dma.head++;
15518 + }
15519 + }
15520 +
15521 + return ret;
15522 +}
15523 +
15524 +static ssize_t trans_s16le(struct at32_dac *dac, const char __user *ubuf,
15525 + size_t ucount)
15526 +{
15527 + ssize_t ret;
15528 +
15529 + if (dac->dsp_settings.channels == 2) {
15530 + const u32 __user *up = (const u32 __user *)ubuf;
15531 + u32 sample;
15532 +
15533 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
15534 + if (!abdac_dma_space(dac))
15535 + break;
15536 +
15537 + if (unlikely(__get_user(sample, up++))) {
15538 + if (ret == 0)
15539 + ret = -EFAULT;
15540 + break;
15541 + }
15542 + /* Swap bytes in each halfword */
15543 + dac->dma.buf[abdac_get_head(dac)] = swahb32(sample);
15544 + dac->dma.head++;
15545 + }
15546 + } else {
15547 + const u16 __user *up = (const u16 __user *)ubuf;
15548 + u16 sample;
15549 +
15550 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
15551 + if (!abdac_dma_space(dac))
15552 + break;
15553 +
15554 + if (unlikely(__get_user(sample, up++))) {
15555 + if (ret == 0)
15556 + ret = -EFAULT;
15557 + break;
15558 + }
15559 + sample = swab16(sample);
15560 + dac->dma.buf[abdac_get_head(dac)]
15561 + = (sample << 16) | sample;
15562 + dac->dma.head++;
15563 + }
15564 + }
15565 +
15566 + return ret;
15567 +}
15568 +
15569 +static ssize_t abdac_dma_translate_from_user(struct at32_dac *dac,
15570 + const char __user *buffer,
15571 + size_t count)
15572 +{
15573 + /* At least one buffer must be available at this point */
15574 + dev_dbg(&dac->pdev->dev, "copying %zu bytes from user...\n", count);
15575 +
15576 + return dac->trans(dac, buffer, count);
15577 +}
15578 +
15579 +static int abdac_set_format(struct at32_dac *dac, int format)
15580 +{
15581 + unsigned int order;
15582 +
15583 + switch (format) {
15584 + case AFMT_S16_BE:
15585 + order = 1;
15586 + dac->trans = trans_s16be;
15587 + break;
15588 + case AFMT_S16_LE:
15589 + order = 1;
15590 + dac->trans = trans_s16le;
15591 + break;
15592 + default:
15593 + dev_dbg(&dac->pdev->dev, "unsupported format: %d\n", format);
15594 + return -EINVAL;
15595 + }
15596 +
15597 + if (dac->dsp_settings.channels == 2)
15598 + order++;
15599 +
15600 + dac->dsp_settings.input_order = order;
15601 + dac->dsp_settings.format = format;
15602 + return 0;
15603 +}
15604 +
15605 +static int abdac_set_sample_rate(struct at32_dac *dac, unsigned long rate)
15606 +{
15607 + unsigned long new_rate;
15608 + int ret;
15609 +
15610 + ret = clk_set_rate(dac->sample_clk, 256 * rate);
15611 + if (ret < 0)
15612 + return ret;
15613 +
15614 + /* TODO: mplayer seems to have a problem with this */
15615 +#if 0
15616 + new_rate = clk_get_rate(dac->sample_clk);
15617 + dac->dsp_settings.sample_rate = new_rate / 256;
15618 +#else
15619 + dac->dsp_settings.sample_rate = rate;
15620 +#endif
15621 +
15622 + return 0;
15623 +}
15624 +
15625 +static ssize_t abdac_dsp_write(struct file *file,
15626 + const char __user *buffer,
15627 + size_t count, loff_t *ppos)
15628 +{
15629 + struct at32_dac *dac = file->private_data;
15630 + DECLARE_WAITQUEUE(wait, current);
15631 + unsigned int avail;
15632 + ssize_t copied;
15633 + ssize_t ret;
15634 +
15635 + /* Avoid address space checking in the translation functions */
15636 + if (!access_ok(buffer, count, VERIFY_READ))
15637 + return -EFAULT;
15638 +
15639 + down(&dac->sem);
15640 +
15641 + if (!dac->dma.buf) {
15642 + ret = abdac_dma_prepare(dac);
15643 + if (ret)
15644 + goto out;
15645 + }
15646 +
15647 + add_wait_queue(&dac->write_wait, &wait);
15648 + ret = 0;
15649 + while (count > 0) {
15650 + do {
15651 + abdac_update_dma_tail(dac);
15652 + avail = abdac_dma_space(dac);
15653 + set_current_state(TASK_INTERRUPTIBLE);
15654 + if (avail >= DMA_WRITE_THRESHOLD)
15655 + break;
15656 +
15657 + if (file->f_flags & O_NONBLOCK) {
15658 + if (!ret)
15659 + ret = -EAGAIN;
15660 + goto out;
15661 + }
15662 +
15663 + pr_debug("Going to wait (avail = %u, count = %zu)\n",
15664 + avail, count);
15665 +
15666 + up(&dac->sem);
15667 + schedule();
15668 + if (signal_pending(current)) {
15669 + if (!ret)
15670 + ret = -ERESTARTSYS;
15671 + goto out_nosem;
15672 + }
15673 + down(&dac->sem);
15674 + } while (1);
15675 +
15676 + copied = abdac_dma_translate_from_user(dac, buffer, count);
15677 + if (copied < 0) {
15678 + if (!ret)
15679 + ret = -EFAULT;
15680 + goto out;
15681 + }
15682 +
15683 + abdac_start(dac);
15684 +
15685 + count -= copied;
15686 + ret += copied;
15687 + }
15688 +
15689 +out:
15690 + up(&dac->sem);
15691 +out_nosem:
15692 + remove_wait_queue(&dac->write_wait, &wait);
15693 + set_current_state(TASK_RUNNING);
15694 + return ret;
15695 +}
15696 +
15697 +static int abdac_dsp_ioctl(struct inode *inode, struct file *file,
15698 + unsigned int cmd, unsigned long arg)
15699 +{
15700 + struct at32_dac *dac = file->private_data;
15701 + int __user *up = (int __user *)arg;
15702 + struct audio_buf_info abinfo;
15703 + int val, ret;
15704 +
15705 + switch (cmd) {
15706 + case OSS_GETVERSION:
15707 + return put_user(SOUND_VERSION, up);
15708 +
15709 + case SNDCTL_DSP_SPEED:
15710 + if (get_user(val, up))
15711 + return -EFAULT;
15712 + if (val >= 0) {
15713 + abdac_stop(dac);
15714 + ret = abdac_set_sample_rate(dac, val);
15715 + if (ret)
15716 + return ret;
15717 + }
15718 + return put_user(dac->dsp_settings.sample_rate, up);
15719 +
15720 + case SNDCTL_DSP_STEREO:
15721 + if (get_user(val, up))
15722 + return -EFAULT;
15723 + abdac_stop(dac);
15724 + if (val && dac->dsp_settings.channels == 1)
15725 + dac->dsp_settings.input_order++;
15726 + else if (!val && dac->dsp_settings.channels != 1)
15727 + dac->dsp_settings.input_order--;
15728 + dac->dsp_settings.channels = val ? 2 : 1;
15729 + return 0;
15730 +
15731 + case SNDCTL_DSP_CHANNELS:
15732 + if (get_user(val, up))
15733 + return -EFAULT;
15734 +
15735 + if (val) {
15736 + if (val < 0 || val > 2)
15737 + return -EINVAL;
15738 +
15739 + abdac_stop(dac);
15740 + dac->dsp_settings.input_order
15741 + += val - dac->dsp_settings.channels;
15742 + dac->dsp_settings.channels = val;
15743 + }
15744 + return put_user(val, (int *)arg);
15745 +
15746 + case SNDCTL_DSP_GETFMTS:
15747 + return put_user(AFMT_S16_BE | AFMT_S16_BE, up);
15748 +
15749 + case SNDCTL_DSP_SETFMT:
15750 + if (get_user(val, up))
15751 + return -EFAULT;
15752 +
15753 + if (val == AFMT_QUERY) {
15754 + val = dac->dsp_settings.format;
15755 + } else {
15756 + ret = abdac_set_format(dac, val);
15757 + if (ret)
15758 + return ret;
15759 + }
15760 + return put_user(val, up);
15761 +
15762 + case SNDCTL_DSP_GETOSPACE:
15763 + abdac_update_dma_tail(dac);
15764 + abinfo.fragsize = ((1 << dac->dsp_settings.input_order)
15765 + * (DMA_PERIOD_SIZE / 4));
15766 + abinfo.bytes = (abdac_dma_space(dac)
15767 + << dac->dsp_settings.input_order);
15768 + abinfo.fragstotal = ((DMA_BUFFER_SIZE * 4)
15769 + >> (DMA_PERIOD_SHIFT
15770 + + dac->dsp_settings.input_order));
15771 + abinfo.fragments = ((abinfo.bytes
15772 + >> dac->dsp_settings.input_order)
15773 + / (DMA_PERIOD_SIZE / 4));
15774 + pr_debug("fragments=%d fragstotal=%d fragsize=%d bytes=%d\n",
15775 + abinfo.fragments, abinfo.fragstotal, abinfo.fragsize,
15776 + abinfo.bytes);
15777 + return copy_to_user(up, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
15778 +
15779 + default:
15780 + dev_dbg(&dac->pdev->dev, "Unimplemented ioctl cmd: 0x%x\n", cmd);
15781 + return -EINVAL;
15782 + }
15783 +}
15784 +
15785 +static int abdac_dsp_open(struct inode *inode, struct file *file)
15786 +{
15787 + struct at32_dac *dac = the_dac;
15788 + int ret;
15789 +
15790 + if (file->f_mode & FMODE_READ)
15791 + return -ENXIO;
15792 +
15793 + down(&dac->sem);
15794 + ret = -EBUSY;
15795 + if (dac->busy)
15796 + goto out;
15797 +
15798 + dac->dma.head = dac->dma.tail = 0;
15799 +
15800 + /* FIXME: What are the correct defaults? */
15801 + dac->dsp_settings.channels = 2;
15802 + abdac_set_format(dac, AFMT_S16_BE);
15803 + ret = abdac_set_sample_rate(dac, 8000);
15804 + if (ret)
15805 + goto out;
15806 +
15807 + file->private_data = dac;
15808 + dac->busy = 1;
15809 +
15810 + ret = 0;
15811 +
15812 +out:
15813 + up(&dac->sem);
15814 + return ret;
15815 +}
15816 +
15817 +static int abdac_dsp_release(struct inode *inode, struct file *file)
15818 +{
15819 + struct at32_dac *dac = file->private_data;
15820 +
15821 + down(&dac->sem);
15822 +
15823 + abdac_stop(dac);
15824 + abdac_dma_cleanup(dac);
15825 + dac->busy = 0;
15826 +
15827 + up(&dac->sem);
15828 +
15829 + return 0;
15830 +}
15831 +
15832 +static struct file_operations abdac_dsp_fops = {
15833 + .owner = THIS_MODULE,
15834 + .llseek = no_llseek,
15835 + .write = abdac_dsp_write,
15836 + .ioctl = abdac_dsp_ioctl,
15837 + .open = abdac_dsp_open,
15838 + .release = abdac_dsp_release,
15839 +};
15840 +
15841 +static int __init abdac_probe(struct platform_device *pdev)
15842 +{
15843 + struct at32_dac *dac;
15844 + struct resource *regs;
15845 + struct clk *mck;
15846 + struct clk *sample_clk;
15847 + int irq;
15848 + int ret;
15849 +
15850 + if (the_dac)
15851 + return -EBUSY;
15852 +
15853 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15854 + if (!regs)
15855 + return -ENXIO;
15856 + irq = platform_get_irq(pdev, 0);
15857 + if (irq < 0)
15858 + return irq;
15859 +
15860 + mck = clk_get(&pdev->dev, "pclk");
15861 + if (IS_ERR(mck))
15862 + return PTR_ERR(mck);
15863 + sample_clk = clk_get(&pdev->dev, "sample_clk");
15864 + if (IS_ERR(sample_clk)) {
15865 + ret = PTR_ERR(sample_clk);
15866 + goto out_put_mck;
15867 + }
15868 + clk_enable(mck);
15869 +
15870 + ret = -ENOMEM;
15871 + dac = kzalloc(sizeof(struct at32_dac), GFP_KERNEL);
15872 + if (!dac)
15873 + goto out_disable_clk;
15874 +
15875 + spin_lock_init(&dac->lock);
15876 + init_MUTEX(&dac->sem);
15877 + init_waitqueue_head(&dac->write_wait);
15878 + dac->pdev = pdev;
15879 + dac->mck = mck;
15880 + dac->sample_clk = sample_clk;
15881 +
15882 + dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
15883 + if (!dac->regs)
15884 + goto out_free_dac;
15885 +
15886 + ret = request_irq(irq, abdac_interrupt, 0, "dac", dac);
15887 + if (ret)
15888 + goto out_unmap_regs;
15889 +
15890 + /* FIXME */
15891 + dac->req.req.dmac = find_dma_controller(0);
15892 + if (!dac->req.req.dmac)
15893 + goto out_free_irq;
15894 +
15895 + ret = dma_alloc_channel(dac->req.req.dmac);
15896 + if (ret < 0)
15897 + goto out_free_irq;
15898 +
15899 + dac->req.req.channel = ret;
15900 + dac->req.req.block_complete = abdac_dma_block_complete;
15901 + dac->req.req.error = abdac_dma_error;
15902 + dac->req.data_reg = regs->start + DAC_DATA;
15903 + dac->req.periph_id = 2; /* FIXME */
15904 + dac->req.direction = DMA_DIR_MEM_TO_PERIPH;
15905 + dac->req.width = DMA_WIDTH_32BIT;
15906 +
15907 + /* Make sure the DAC is silent and disabled */
15908 + dac_writel(dac, DATA, 0);
15909 + dac_writel(dac, CTRL, 0);
15910 +
15911 + ret = register_sound_dsp(&abdac_dsp_fops, -1);
15912 + if (ret < 0)
15913 + goto out_free_dma;
15914 + dac->dev_dsp = ret;
15915 +
15916 + /* TODO: Register mixer */
15917 +
15918 + the_dac = dac;
15919 + platform_set_drvdata(pdev, dac);
15920 +
15921 + return 0;
15922 +
15923 +out_free_dma:
15924 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
15925 +out_free_irq:
15926 + free_irq(irq, dac);
15927 +out_unmap_regs:
15928 + iounmap(dac->regs);
15929 +out_free_dac:
15930 + kfree(dac);
15931 +out_disable_clk:
15932 + clk_disable(mck);
15933 + clk_put(sample_clk);
15934 +out_put_mck:
15935 + clk_put(mck);
15936 + return ret;
15937 +}
15938 +
15939 +static int __exit abdac_remove(struct platform_device *pdev)
15940 +{
15941 + struct at32_dac *dac;
15942 +
15943 + dac = platform_get_drvdata(pdev);
15944 + if (dac) {
15945 + unregister_sound_dsp(dac->dev_dsp);
15946 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
15947 + free_irq(platform_get_irq(pdev, 0), dac);
15948 + iounmap(dac->regs);
15949 + clk_disable(dac->mck);
15950 + clk_put(dac->sample_clk);
15951 + clk_put(dac->mck);
15952 + kfree(dac);
15953 + platform_set_drvdata(pdev, NULL);
15954 + the_dac = NULL;
15955 + }
15956 +
15957 + return 0;
15958 +}
15959 +
15960 +static struct platform_driver abdac_driver = {
15961 + .remove = __exit_p(abdac_remove),
15962 + .driver = {
15963 + .name = "abdac",
15964 + },
15965 +};
15966 +
15967 +static int __init abdac_init(void)
15968 +{
15969 + return platform_driver_probe(&abdac_driver, abdac_probe);
15970 +}
15971 +module_init(abdac_init);
15972 +
15973 +static void __exit abdac_exit(void)
15974 +{
15975 + platform_driver_unregister(&abdac_driver);
15976 +}
15977 +module_exit(abdac_exit);
15978 +
15979 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
15980 +MODULE_DESCRIPTION("Sound Driver for the Atmel AT32 ABDAC");
15981 +MODULE_LICENSE("GPL");
15982 --- /dev/null
15983 +++ b/sound/oss/at32_abdac.h
15984 @@ -0,0 +1,59 @@
15985 +/*
15986 + * Register definitions for the Atmel AT32 on-chip DAC.
15987 + *
15988 + * Copyright (C) 2006 Atmel Corporation
15989 + *
15990 + * This program is free software; you can redistribute it and/or modify
15991 + * it under the terms of the GNU General Public License version 2 as
15992 + * published by the Free Software Foundation.
15993 + */
15994 +#ifndef __SOUND_OSS_AT32_ABDAC_H__
15995 +#define __SOUND_OSS_AT32_ABDAC_H__
15996 +
15997 +/* DAC register offsets */
15998 +#define DAC_DATA 0x0000
15999 +#define DAC_CTRL 0x0008
16000 +#define DAC_INT_MASK 0x000c
16001 +#define DAC_INT_EN 0x0010
16002 +#define DAC_INT_DIS 0x0014
16003 +#define DAC_INT_CLR 0x0018
16004 +#define DAC_INT_STATUS 0x001c
16005 +#define DAC_PDC_DATA 0x0020
16006 +
16007 +/* Bitfields in CTRL */
16008 +#define DAC_SWAP_OFFSET 30
16009 +#define DAC_SWAP_SIZE 1
16010 +#define DAC_EN_OFFSET 31
16011 +#define DAC_EN_SIZE 1
16012 +
16013 +/* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
16014 +#define DAC_UNDERRUN_OFFSET 28
16015 +#define DAC_UNDERRUN_SIZE 1
16016 +#define DAC_TX_READY_OFFSET 29
16017 +#define DAC_TX_READY_SIZE 1
16018 +#define DAC_TX_BUFFER_EMPTY_OFFSET 30
16019 +#define DAC_TX_BUFFER_EMPTY_SIZE 1
16020 +#define DAC_CHANNEL_TX_END_OFFSET 31
16021 +#define DAC_CHANNEL_TX_END_SIZE 1
16022 +
16023 +/* Bit manipulation macros */
16024 +#define DAC_BIT(name) \
16025 + (1 << DAC_##name##_OFFSET)
16026 +#define DAC_BF(name, value) \
16027 + (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
16028 + << DAC_##name##_OFFSET)
16029 +#define DAC_BFEXT(name, value) \
16030 + (((value) >> DAC_##name##_OFFSET) \
16031 + & ((1 << DAC_##name##_SIZE) - 1))
16032 +#define DAC_BFINS(name, value, old) \
16033 + (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
16034 + << DAC_##name##_OFFSET)) \
16035 + | DAC_BF(name,value))
16036 +
16037 +/* Register access macros */
16038 +#define dac_readl(port, reg) \
16039 + __raw_readl((port)->regs + DAC_##reg)
16040 +#define dac_writel(port, reg, value) \
16041 + __raw_writel((value), (port)->regs + DAC_##reg)
16042 +
16043 +#endif /* __SOUND_OSS_AT32_ABDAC_H__ */
16044 --- a/sound/oss/Kconfig
16045 +++ b/sound/oss/Kconfig
16046 @@ -654,3 +654,7 @@
16047 int "DAC channel"
16048 default "1"
16049 depends on SOUND_SH_DAC_AUDIO
16050 +
16051 +config SOUND_AT32_ABDAC
16052 + tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
16053 + depends on SOUND_PRIME && AVR32
16054 --- a/sound/oss/Makefile
16055 +++ b/sound/oss/Makefile
16056 @@ -9,6 +9,7 @@
16057
16058 # Please leave it as is, cause the link order is significant !
16059
16060 +obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
16061 obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
16062 obj-$(CONFIG_SOUND_HAL2) += hal2.o
16063 obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
16064 --- a/sound/spi/at73c213.c
16065 +++ b/sound/spi/at73c213.c
16066 @@ -737,7 +737,7 @@
16067 /*
16068 * Device functions
16069 */
16070 -static int snd_at73c213_ssc_init(struct snd_at73c213 *chip)
16071 +static int __devinit snd_at73c213_ssc_init(struct snd_at73c213 *chip)
16072 {
16073 /*
16074 * Continuous clock output.
16075 @@ -767,7 +767,7 @@
16076 return 0;
16077 }
16078
16079 -static int snd_at73c213_chip_init(struct snd_at73c213 *chip)
16080 +static int __devinit snd_at73c213_chip_init(struct snd_at73c213 *chip)
16081 {
16082 int retval;
16083 unsigned char dac_ctrl = 0;
16084 @@ -933,7 +933,7 @@
16085 return retval;
16086 }
16087
16088 -static int snd_at73c213_probe(struct spi_device *spi)
16089 +static int __devinit snd_at73c213_probe(struct spi_device *spi)
16090 {
16091 struct snd_card *card;
16092 struct snd_at73c213 *chip;
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