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fix bcm4710 cache fixes
[openwrt.git] / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmsrom.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmsrom.c
2 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmsrom.c 2006-06-18 15:29:23.000000000 +0200
4 @@ -0,0 +1,481 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2005, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id$
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <osl.h>
20 +#include <bcmutils.h>
21 +#include <bcmsrom.h>
22 +#include <bcmdevs.h>
23 +#include <bcmendian.h>
24 +#include <pcicfg.h>
25 +#include <sbutils.h>
26 +
27 +#include <proto/ethernet.h> /* for sprom content groking */
28 +
29 +#define VARS_MAX 4096 /* should be reduced */
30 +
31 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
32 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
33 +
34 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
35 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
36 +
37 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
38 +
39 +/*
40 + * Initialize local vars from the right source for this platform.
41 + * Return 0 on success, nonzero on error.
42 + */
43 +int
44 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
45 +{
46 + ASSERT(bustype == BUSTYPE(bustype));
47 + if (vars == NULL || count == NULL)
48 + return (0);
49 +
50 + switch (BUSTYPE(bustype)) {
51 +
52 + case PCI_BUS:
53 + ASSERT(curmap); /* can not be NULL */
54 + return initvars_srom_pci(sbh, curmap, vars, count);
55 +
56 + default:
57 + return 0;
58 + }
59 + return (-1);
60 +}
61 +
62 +/* support only 16-bit word read from srom */
63 +int
64 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
65 +{
66 + void *srom;
67 + uint off, nw;
68 +
69 + ASSERT(bustype == BUSTYPE(bustype));
70 +
71 + /* check input - 16-bit access only */
72 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
73 + return 1;
74 +
75 + off = byteoff / 2;
76 + nw = nbytes / 2;
77 +
78 + if (BUSTYPE(bustype) == PCI_BUS) {
79 + if (!curmap)
80 + return 1;
81 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
82 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
83 + return 1;
84 + } else {
85 + return 1;
86 + }
87 +
88 + return 0;
89 +}
90 +
91 +/* support only 16-bit word write into srom */
92 +int
93 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
94 +{
95 + uint16 *srom;
96 + uint i, off, nw, crc_range;
97 + uint16 image[SPROM_SIZE], *p;
98 + uint8 crc;
99 + volatile uint32 val32;
100 +
101 + ASSERT(bustype == BUSTYPE(bustype));
102 +
103 + /* check input - 16-bit access only */
104 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
105 + return 1;
106 +
107 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
108 +
109 + /* if changes made inside crc cover range */
110 + if (byteoff < crc_range) {
111 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
112 + /* read data including entire first 64 words from srom */
113 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
114 + return 1;
115 + /* make changes */
116 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
117 + /* calculate crc */
118 + htol16_buf(image, crc_range);
119 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
120 + ltoh16_buf(image, crc_range);
121 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
122 + p = image;
123 + off = 0;
124 + } else {
125 + p = buf;
126 + off = byteoff / 2;
127 + nw = nbytes / 2;
128 + }
129 +
130 + if (BUSTYPE(bustype) == PCI_BUS) {
131 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
132 + /* enable writes to the SPROM */
133 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
134 + val32 |= SPROM_WRITEEN;
135 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
136 + bcm_mdelay(WRITE_ENABLE_DELAY);
137 + /* write srom */
138 + for (i = 0; i < nw; i++) {
139 + W_REG(&srom[off + i], p[i]);
140 + bcm_mdelay(WRITE_WORD_DELAY);
141 + }
142 + /* disable writes to the SPROM */
143 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
144 + } else {
145 + return 1;
146 + }
147 +
148 + bcm_mdelay(WRITE_ENABLE_DELAY);
149 + return 0;
150 +}
151 +
152 +
153 +/*
154 + * Read in and validate sprom.
155 + * Return 0 on success, nonzero on error.
156 + */
157 +static int
158 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
159 +{
160 + int err = 0;
161 + uint i;
162 +
163 + /* read the sprom */
164 + for (i = 0; i < nwords; i++)
165 + buf[i] = R_REG(&sprom[wordoff + i]);
166 +
167 + if (check_crc) {
168 + /* fixup the endianness so crc8 will pass */
169 + htol16_buf(buf, nwords * 2);
170 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
171 + err = 1;
172 + /* now correct the endianness of the byte array */
173 + ltoh16_buf(buf, nwords * 2);
174 + }
175 +
176 + return err;
177 +}
178 +
179 +/*
180 +* Create variable table from memory.
181 +* Return 0 on success, nonzero on error.
182 +*/
183 +static int
184 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
185 +{
186 + int c = (int)(end - start);
187 +
188 + /* do it only when there is more than just the null string */
189 + if (c > 1) {
190 + char *vp = MALLOC(osh, c);
191 + ASSERT(vp);
192 + if (!vp)
193 + return BCME_NOMEM;
194 + bcopy(start, vp, c);
195 + *vars = vp;
196 + *count = c;
197 + }
198 + else {
199 + *vars = NULL;
200 + *count = 0;
201 + }
202 +
203 + return 0;
204 +}
205 +
206 +/*
207 + * Initialize nonvolatile variable table from sprom.
208 + * Return 0 on success, nonzero on error.
209 + */
210 +static int
211 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
212 +{
213 + uint16 w, b[64];
214 + uint8 sromrev;
215 + struct ether_addr ea;
216 + char eabuf[32];
217 + uint32 w32;
218 + int woff, i;
219 + char *vp, *base;
220 + osl_t *osh = sb_osh(sbh);
221 + int err;
222 +
223 + /*
224 + * Apply CRC over SROM content regardless SROM is present or not,
225 + * and use variable <devpath>sromrev's existance in flash to decide
226 + * if we should return an error when CRC fails or read SROM variables
227 + * from flash.
228 + */
229 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
230 +
231 + /* top word of sprom contains version and crc8 */
232 + sromrev = b[63] & 0xff;
233 + /* bcm4401 sroms misprogrammed */
234 + if (sromrev == 0x10)
235 + sromrev = 1;
236 +
237 + /* srom version check */
238 + if (sromrev > 3)
239 + return (-2);
240 +
241 + ASSERT(vars);
242 + ASSERT(count);
243 +
244 + base = vp = MALLOC(osh, VARS_MAX);
245 + ASSERT(vp);
246 + if (!vp)
247 + return -2;
248 +
249 + vp += sprintf(vp, "sromrev=%d", sromrev);
250 + vp++;
251 +
252 + if (sromrev >= 3) {
253 + /* New section takes over the 3th hardware function space */
254 +
255 + /* Words 22+23 are 11a (mid) ofdm power offsets */
256 + w32 = ((uint32)b[23] << 16) | b[22];
257 + vp += sprintf(vp, "ofdmapo=%d", w32);
258 + vp++;
259 +
260 + /* Words 24+25 are 11a (low) ofdm power offsets */
261 + w32 = ((uint32)b[25] << 16) | b[24];
262 + vp += sprintf(vp, "ofdmalpo=%d", w32);
263 + vp++;
264 +
265 + /* Words 26+27 are 11a (high) ofdm power offsets */
266 + w32 = ((uint32)b[27] << 16) | b[26];
267 + vp += sprintf(vp, "ofdmahpo=%d", w32);
268 + vp++;
269 +
270 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
271 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
272 + vp += sprintf(vp, "gpiotimerval=%d", w32);
273 +
274 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
275 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
276 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
277 + vp += sprintf(vp, "gpiotimerval=%d", w32);
278 +
279 + vp++;
280 + }
281 +
282 + if (sromrev >= 2) {
283 + /* New section takes over the 4th hardware function space */
284 +
285 + /* Word 29 is max power 11a high/low */
286 + w = b[29];
287 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
288 + vp++;
289 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
290 + vp++;
291 +
292 + /* Words 30-32 set the 11alow pa settings,
293 + * 33-35 are the 11ahigh ones.
294 + */
295 + for (i = 0; i < 3; i++) {
296 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
297 + vp++;
298 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
299 + vp++;
300 + }
301 + w = b[59];
302 + if (w == 0)
303 + vp += sprintf(vp, "ccode=");
304 + else
305 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
306 + vp++;
307 +
308 + }
309 +
310 + /* parameter section of sprom starts at byte offset 72 */
311 + woff = 72/2;
312 +
313 + /* first 6 bytes are il0macaddr */
314 + ea.octet[0] = (b[woff] >> 8) & 0xff;
315 + ea.octet[1] = b[woff] & 0xff;
316 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
317 + ea.octet[3] = b[woff+1] & 0xff;
318 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
319 + ea.octet[5] = b[woff+2] & 0xff;
320 + woff += ETHER_ADDR_LEN/2 ;
321 + bcm_ether_ntoa((uchar*)&ea, eabuf);
322 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
323 + vp++;
324 +
325 + /* next 6 bytes are et0macaddr */
326 + ea.octet[0] = (b[woff] >> 8) & 0xff;
327 + ea.octet[1] = b[woff] & 0xff;
328 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
329 + ea.octet[3] = b[woff+1] & 0xff;
330 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
331 + ea.octet[5] = b[woff+2] & 0xff;
332 + woff += ETHER_ADDR_LEN/2 ;
333 + bcm_ether_ntoa((uchar*)&ea, eabuf);
334 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
335 + vp++;
336 +
337 + /* next 6 bytes are et1macaddr */
338 + ea.octet[0] = (b[woff] >> 8) & 0xff;
339 + ea.octet[1] = b[woff] & 0xff;
340 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
341 + ea.octet[3] = b[woff+1] & 0xff;
342 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
343 + ea.octet[5] = b[woff+2] & 0xff;
344 + woff += ETHER_ADDR_LEN/2 ;
345 + bcm_ether_ntoa((uchar*)&ea, eabuf);
346 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
347 + vp++;
348 +
349 + /*
350 + * Enet phy settings one or two singles or a dual
351 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
352 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
353 + * Bit 14 : Mdio for enet0
354 + * Bit 15 : Mdio for enet1
355 + */
356 + w = b[woff];
357 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
358 + vp++;
359 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
360 + vp++;
361 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
362 + vp++;
363 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
364 + vp++;
365 +
366 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
367 + w = b[46];
368 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
369 + vp++;
370 +
371 + if (sromrev > 1)
372 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
373 + else
374 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
375 + vp++;
376 +
377 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
378 + vp++;
379 +
380 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
381 + vp++;
382 +
383 + /* Words 47-49 set the (wl) pa settings */
384 + woff = 47;
385 +
386 + for (i = 0; i < 3; i++) {
387 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
388 + vp++;
389 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
390 + vp++;
391 + }
392 +
393 + /*
394 + * Words 50-51 set the customer-configured wl led behavior.
395 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
396 + * LED behavior values defined in wlioctl.h .
397 + */
398 + w = b[50];
399 + if ((w != 0) && (w != 0xffff)) {
400 + /* gpio0 */
401 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
402 + vp++;
403 +
404 + /* gpio1 */
405 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
406 + vp++;
407 + }
408 + w = b[51];
409 + if ((w != 0) && (w != 0xffff)) {
410 + /* gpio2 */
411 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
412 + vp++;
413 +
414 + /* gpio3 */
415 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
416 + vp++;
417 + }
418 +
419 + /* Word 52 is max power 0/1 */
420 + w = b[52];
421 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
422 + vp++;
423 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
424 + vp++;
425 +
426 + /* Word 56 is idle tssi target 0/1 */
427 + w = b[56];
428 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
429 + vp++;
430 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
431 + vp++;
432 +
433 + /* Word 57 is boardflags, if not programmed make it zero */
434 + w32 = (uint32)b[57];
435 + if (w32 == 0xffff) w32 = 0;
436 + if (sromrev > 1) {
437 + /* Word 28 is the high bits of boardflags */
438 + w32 |= (uint32)b[28] << 16;
439 + }
440 + vp += sprintf(vp, "boardflags=%d", w32);
441 + vp++;
442 +
443 + /* Word 58 is antenna gain 0/1 */
444 + w = b[58];
445 + vp += sprintf(vp, "ag0=%d", w & 0xff);
446 + vp++;
447 +
448 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
449 + vp++;
450 +
451 + if (sromrev == 1) {
452 + /* set the oem string */
453 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
454 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
455 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
456 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
457 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
458 + vp++;
459 + } else if (sromrev == 2) {
460 + /* Word 60 OFDM tx power offset from CCK level */
461 + /* OFDM Power Offset - opo */
462 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
463 + vp++;
464 + } else {
465 + /* Word 60: cck power offsets */
466 + vp += sprintf(vp, "cckpo=%d", b[60]);
467 + vp++;
468 +
469 + /* Words 61+62: 11g ofdm power offsets */
470 + w32 = ((uint32)b[62] << 16) | b[61];
471 + vp += sprintf(vp, "ofdmgpo=%d", w32);
472 + vp++;
473 + }
474 +
475 + /* final nullbyte terminator */
476 + *vp++ = '\0';
477 +
478 + ASSERT((vp - base) <= VARS_MAX);
479 +
480 + err = initvars_table(osh, base, vp, vars, count);
481 +
482 + MFREE(osh, base, VARS_MAX);
483 + return err;
484 +}
485 +
486 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmutils.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmutils.c
487 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
488 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmutils.c 2006-06-18 15:29:23.000000000 +0200
489 @@ -0,0 +1,356 @@
490 +/*
491 + * Misc useful OS-independent routines.
492 + *
493 + * Copyright 2005, Broadcom Corporation
494 + * All Rights Reserved.
495 + *
496 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
497 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
498 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
499 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
500 + * $Id$
501 + */
502 +
503 +#include <typedefs.h>
504 +#include <osl.h>
505 +#include <sbutils.h>
506 +#include <bcmnvram.h>
507 +#include <bcmutils.h>
508 +#include <bcmendian.h>
509 +#include <bcmdevs.h>
510 +
511 +unsigned char bcm_ctype[] = {
512 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
513 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
514 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
515 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
516 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
517 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
518 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
519 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
520 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
521 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
522 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
523 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
524 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
525 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
526 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
527 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
528 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
529 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
530 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
531 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
532 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
533 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
534 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
535 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
536 +};
537 +
538 +uchar
539 +bcm_toupper(uchar c)
540 +{
541 + if (bcm_islower(c))
542 + c -= 'a'-'A';
543 + return (c);
544 +}
545 +
546 +ulong
547 +bcm_strtoul(char *cp, char **endp, uint base)
548 +{
549 + ulong result, value;
550 + bool minus;
551 +
552 + minus = FALSE;
553 +
554 + while (bcm_isspace(*cp))
555 + cp++;
556 +
557 + if (cp[0] == '+')
558 + cp++;
559 + else if (cp[0] == '-') {
560 + minus = TRUE;
561 + cp++;
562 + }
563 +
564 + if (base == 0) {
565 + if (cp[0] == '0') {
566 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
567 + base = 16;
568 + cp = &cp[2];
569 + } else {
570 + base = 8;
571 + cp = &cp[1];
572 + }
573 + } else
574 + base = 10;
575 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
576 + cp = &cp[2];
577 + }
578 +
579 + result = 0;
580 +
581 + while (bcm_isxdigit(*cp) &&
582 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
583 + result = result*base + value;
584 + cp++;
585 + }
586 +
587 + if (minus)
588 + result = (ulong)(result * -1);
589 +
590 + if (endp)
591 + *endp = (char *)cp;
592 +
593 + return (result);
594 +}
595 +
596 +uint
597 +bcm_atoi(char *s)
598 +{
599 + uint n;
600 +
601 + n = 0;
602 +
603 + while (bcm_isdigit(*s))
604 + n = (n * 10) + *s++ - '0';
605 + return (n);
606 +}
607 +
608 +/* return pointer to location of substring 'needle' in 'haystack' */
609 +char*
610 +bcmstrstr(char *haystack, char *needle)
611 +{
612 + int len, nlen;
613 + int i;
614 +
615 + if ((haystack == NULL) || (needle == NULL))
616 + return (haystack);
617 +
618 + nlen = strlen(needle);
619 + len = strlen(haystack) - nlen + 1;
620 +
621 + for (i = 0; i < len; i++)
622 + if (bcmp(needle, &haystack[i], nlen) == 0)
623 + return (&haystack[i]);
624 + return (NULL);
625 +}
626 +
627 +char*
628 +bcmstrcat(char *dest, const char *src)
629 +{
630 + strcpy(&dest[strlen(dest)], src);
631 + return (dest);
632 +}
633 +
634 +
635 +char*
636 +bcm_ether_ntoa(char *ea, char *buf)
637 +{
638 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
639 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
640 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
641 + return (buf);
642 +}
643 +
644 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
645 +int
646 +bcm_ether_atoe(char *p, char *ea)
647 +{
648 + int i = 0;
649 +
650 + for (;;) {
651 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
652 + if (!*p++ || i == 6)
653 + break;
654 + }
655 +
656 + return (i == 6);
657 +}
658 +
659 +void
660 +bcm_mdelay(uint ms)
661 +{
662 + uint i;
663 +
664 + for (i = 0; i < ms; i++) {
665 + OSL_DELAY(1000);
666 + }
667 +}
668 +
669 +/*
670 + * Search the name=value vars for a specific one and return its value.
671 + * Returns NULL if not found.
672 + */
673 +char*
674 +getvar(char *vars, char *name)
675 +{
676 + char *s;
677 + int len;
678 +
679 + len = strlen(name);
680 +
681 + /* first look in vars[] */
682 + for (s = vars; s && *s; ) {
683 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
684 + return (&s[len+1]);
685 +
686 + while (*s++)
687 + ;
688 + }
689 +
690 + /* then query nvram */
691 + return (BCMINIT(nvram_get)(name));
692 +}
693 +
694 +/*
695 + * Search the vars for a specific one and return its value as
696 + * an integer. Returns 0 if not found.
697 + */
698 +int
699 +getintvar(char *vars, char *name)
700 +{
701 + char *val;
702 +
703 + if ((val = getvar(vars, name)) == NULL)
704 + return (0);
705 +
706 + return (bcm_strtoul(val, NULL, 0));
707 +}
708 +
709 +
710 +/* Search for token in comma separated token-string */
711 +static int
712 +findmatch(char *string, char *name)
713 +{
714 + uint len;
715 + char *c;
716 +
717 + len = strlen(name);
718 + while ((c = strchr(string, ',')) != NULL) {
719 + if (len == (uint)(c - string) && !strncmp(string, name, len))
720 + return 1;
721 + string = c + 1;
722 + }
723 +
724 + return (!strcmp(string, name));
725 +}
726 +
727 +/* Return gpio pin number assigned to the named pin */
728 +/*
729 +* Variable should be in format:
730 +*
731 +* gpio<N>=pin_name,pin_name
732 +*
733 +* This format allows multiple features to share the gpio with mutual
734 +* understanding.
735 +*
736 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
737 +* and if def_pin is not used by others.
738 +*/
739 +uint
740 +getgpiopin(char *vars, char *pin_name, uint def_pin)
741 +{
742 + char name[] = "gpioXXXX";
743 + char *val;
744 + uint pin;
745 +
746 + /* Go thru all possibilities till a match in pin name */
747 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
748 + sprintf(name, "gpio%d", pin);
749 + val = getvar(vars, name);
750 + if (val && findmatch(val, pin_name))
751 + return pin;
752 + }
753 +
754 + if (def_pin != GPIO_PIN_NOTDEFINED) {
755 + /* make sure the default pin is not used by someone else */
756 + sprintf(name, "gpio%d", def_pin);
757 + if (getvar(vars, name)) {
758 + def_pin = GPIO_PIN_NOTDEFINED;
759 + }
760 + }
761 +
762 + return def_pin;
763 +}
764 +
765 +
766 +/*******************************************************************************
767 + * crc8
768 + *
769 + * Computes a crc8 over the input data using the polynomial:
770 + *
771 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
772 + *
773 + * The caller provides the initial value (either CRC8_INIT_VALUE
774 + * or the previous returned value) to allow for processing of
775 + * discontiguous blocks of data. When generating the CRC the
776 + * caller is responsible for complementing the final return value
777 + * and inserting it into the byte stream. When checking, a final
778 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
779 + *
780 + * Reference: Dallas Semiconductor Application Note 27
781 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
782 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
783 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
784 + *
785 + ******************************************************************************/
786 +
787 +static uint8 crc8_table[256] = {
788 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
789 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
790 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
791 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
792 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
793 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
794 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
795 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
796 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
797 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
798 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
799 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
800 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
801 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
802 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
803 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
804 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
805 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
806 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
807 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
808 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
809 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
810 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
811 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
812 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
813 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
814 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
815 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
816 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
817 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
818 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
819 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
820 +};
821 +
822 +#define CRC_INNER_LOOP(n, c, x) \
823 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
824 +
825 +uint8
826 +hndcrc8(
827 + uint8 *pdata, /* pointer to array of data to process */
828 + uint nbytes, /* number of input data bytes to process */
829 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
830 +)
831 +{
832 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
833 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
834 + while (nbytes-- > 0)
835 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
836 +
837 + return crc;
838 +}
839 +
840 +#ifdef notdef
841 +#define CLEN 1499
842 +#define CBUFSIZ (CLEN+4)
843 +#define CNBUFS 5
844 +
845 +#endif
846 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/cfe_env.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/cfe_env.c
847 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
848 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/cfe_env.c 2006-06-18 15:29:23.000000000 +0200
849 @@ -0,0 +1,234 @@
850 +/*
851 + * NVRAM variable manipulation (Linux kernel half)
852 + *
853 + * Copyright 2001-2003, Broadcom Corporation
854 + * All Rights Reserved.
855 + *
856 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
857 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
858 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
859 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
860 + *
861 + * $Id$
862 + */
863 +
864 +#include <linux/config.h>
865 +#include <linux/init.h>
866 +#include <linux/module.h>
867 +#include <linux/kernel.h>
868 +#include <linux/string.h>
869 +#include <asm/io.h>
870 +#include <asm/uaccess.h>
871 +
872 +#include <typedefs.h>
873 +#include <osl.h>
874 +#include <bcmendian.h>
875 +#include <bcmutils.h>
876 +
877 +#define NVRAM_SIZE (0x1ff0)
878 +static char _nvdata[NVRAM_SIZE] __initdata;
879 +static char _valuestr[256] __initdata;
880 +
881 +/*
882 + * TLV types. These codes are used in the "type-length-value"
883 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
884 + *
885 + * The layout of the flash/nvram is as follows:
886 + *
887 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
888 + *
889 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
890 + * The "length" field marks the length of the data section, not
891 + * including the type and length fields.
892 + *
893 + * Environment variables are stored as follows:
894 + *
895 + * <type_env> <length> <flags> <name> = <value>
896 + *
897 + * If bit 0 (low bit) is set, the length is an 8-bit value.
898 + * If bit 0 (low bit) is clear, the length is a 16-bit value
899 + *
900 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
901 + * indicates the size of the length field.
902 + *
903 + * Flags are from the constants below:
904 + *
905 + */
906 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
907 +#define ENV_LENGTH_8BITS 0x01
908 +
909 +#define ENV_TYPE_USER 0x80
910 +
911 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
912 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
913 +
914 +/*
915 + * The actual TLV types we support
916 + */
917 +
918 +#define ENV_TLV_TYPE_END 0x00
919 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
920 +
921 +/*
922 + * Environment variable flags
923 + */
924 +
925 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
926 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
927 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
928 +
929 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
930 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
931 +
932 +
933 +/* *********************************************************************
934 + * _nvram_read(buffer,offset,length)
935 + *
936 + * Read data from the NVRAM device
937 + *
938 + * Input parameters:
939 + * buffer - destination buffer
940 + * offset - offset of data to read
941 + * length - number of bytes to read
942 + *
943 + * Return value:
944 + * number of bytes read, or <0 if error occured
945 + ********************************************************************* */
946 +static int
947 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
948 +{
949 + int i;
950 + if (offset > NVRAM_SIZE)
951 + return -1;
952 +
953 + for ( i = 0; i < length; i++) {
954 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
955 + }
956 + return length;
957 +}
958 +
959 +
960 +static char*
961 +_strnchr(const char *dest,int c,size_t cnt)
962 +{
963 + while (*dest && (cnt > 0)) {
964 + if (*dest == c) return (char *) dest;
965 + dest++;
966 + cnt--;
967 + }
968 + return NULL;
969 +}
970 +
971 +
972 +
973 +/*
974 + * Core support API: Externally visible.
975 + */
976 +
977 +/*
978 + * Get the value of an NVRAM variable
979 + * @param name name of variable to get
980 + * @return value of variable or NULL if undefined
981 + */
982 +
983 +char*
984 +cfe_env_get(unsigned char *nv_buf, char* name)
985 +{
986 + int size;
987 + unsigned char *buffer;
988 + unsigned char *ptr;
989 + unsigned char *envval;
990 + unsigned int reclen;
991 + unsigned int rectype;
992 + int offset;
993 + int flg;
994 +
995 + size = NVRAM_SIZE;
996 + buffer = &_nvdata[0];
997 +
998 + ptr = buffer;
999 + offset = 0;
1000 +
1001 + /* Read the record type and length */
1002 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1003 + goto error;
1004 + }
1005 +
1006 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1007 +
1008 + /* Adjust pointer for TLV type */
1009 + rectype = *(ptr);
1010 + offset++;
1011 + size--;
1012 +
1013 + /*
1014 + * Read the length. It can be either 1 or 2 bytes
1015 + * depending on the code
1016 + */
1017 + if (rectype & ENV_LENGTH_8BITS) {
1018 + /* Read the record type and length - 8 bits */
1019 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1020 + goto error;
1021 + }
1022 + reclen = *(ptr);
1023 + size--;
1024 + offset++;
1025 + }
1026 + else {
1027 + /* Read the record type and length - 16 bits, MSB first */
1028 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1029 + goto error;
1030 + }
1031 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1032 + size -= 2;
1033 + offset += 2;
1034 + }
1035 +
1036 + if (reclen > size)
1037 + break; /* should not happen, bad NVRAM */
1038 +
1039 + switch (rectype) {
1040 + case ENV_TLV_TYPE_ENV:
1041 + /* Read the TLV data */
1042 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1043 + goto error;
1044 + flg = *ptr++;
1045 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1046 + if (envval) {
1047 + *envval++ = '\0';
1048 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1049 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1050 +#if 0
1051 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1052 +#endif
1053 + if(!strcmp(ptr, name)){
1054 + return _valuestr;
1055 + }
1056 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1057 + return _valuestr;
1058 + }
1059 + break;
1060 +
1061 + default:
1062 + /* Unknown TLV type, skip it. */
1063 + break;
1064 + }
1065 +
1066 + /*
1067 + * Advance to next TLV
1068 + */
1069 +
1070 + size -= (int)reclen;
1071 + offset += reclen;
1072 +
1073 + /* Read the next record type */
1074 + ptr = buffer;
1075 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1076 + goto error;
1077 + }
1078 +
1079 +error:
1080 + return NULL;
1081 +
1082 +}
1083 +
1084 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/linux_osl.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/linux_osl.c
1085 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1086 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/linux_osl.c 2006-06-18 15:29:23.000000000 +0200
1087 @@ -0,0 +1,102 @@
1088 +/*
1089 + * Linux OS Independent Layer
1090 + *
1091 + * Copyright 2005, Broadcom Corporation
1092 + * All Rights Reserved.
1093 + *
1094 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1095 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1096 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1097 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1098 + *
1099 + * $Id$
1100 + */
1101 +
1102 +#define LINUX_OSL
1103 +
1104 +#include <typedefs.h>
1105 +#include <bcmendian.h>
1106 +#include <linux/module.h>
1107 +#include <linuxver.h>
1108 +#include <osl.h>
1109 +#include <bcmutils.h>
1110 +#include <linux/delay.h>
1111 +#ifdef mips
1112 +#include <asm/paccess.h>
1113 +#endif
1114 +#include <pcicfg.h>
1115 +
1116 +#define PCI_CFG_RETRY 10
1117 +
1118 +#define OS_HANDLE_MAGIC 0x1234abcd
1119 +#define BCM_MEM_FILENAME_LEN 24
1120 +
1121 +typedef struct bcm_mem_link {
1122 + struct bcm_mem_link *prev;
1123 + struct bcm_mem_link *next;
1124 + uint size;
1125 + int line;
1126 + char file[BCM_MEM_FILENAME_LEN];
1127 +} bcm_mem_link_t;
1128 +
1129 +struct os_handle {
1130 + uint magic;
1131 + void *pdev;
1132 + uint malloced;
1133 + uint failed;
1134 + bcm_mem_link_t *dbgmem_list;
1135 +};
1136 +
1137 +uint32
1138 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1139 +{
1140 + uint val;
1141 + uint retry=PCI_CFG_RETRY;
1142 +
1143 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1144 +
1145 + /* only 4byte access supported */
1146 + ASSERT(size == 4);
1147 +
1148 + do {
1149 + pci_read_config_dword(osh->pdev, offset, &val);
1150 + if (val != 0xffffffff)
1151 + break;
1152 + } while (retry--);
1153 +
1154 +
1155 + return (val);
1156 +}
1157 +
1158 +void
1159 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1160 +{
1161 + uint retry=PCI_CFG_RETRY;
1162 +
1163 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1164 +
1165 + /* only 4byte access supported */
1166 + ASSERT(size == 4);
1167 +
1168 + do {
1169 + pci_write_config_dword(osh->pdev, offset, val);
1170 + if (offset!=PCI_BAR0_WIN)
1171 + break;
1172 + if (osl_pci_read_config(osh,offset,size) == val)
1173 + break;
1174 + } while (retry--);
1175 +
1176 +}
1177 +
1178 +void
1179 +osl_delay(uint usec)
1180 +{
1181 + uint d;
1182 +
1183 + while (usec > 0) {
1184 + d = MIN(usec, 1000);
1185 + udelay(d);
1186 + usec -= d;
1187 + }
1188 +}
1189 +
1190 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/Makefile linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/Makefile
1191 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
1192 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/Makefile 2006-06-18 15:29:23.000000000 +0200
1193 @@ -0,0 +1,6 @@
1194 +#
1195 +# Makefile for the BCM47xx specific kernel interface routines
1196 +# under Linux.
1197 +#
1198 +
1199 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
1200 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/nvram.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/nvram.c
1201 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/nvram.c 2006-06-18 15:29:23.000000000 +0200
1203 @@ -0,0 +1,192 @@
1204 +/*
1205 + * NVRAM variable manipulation (Linux kernel half)
1206 + *
1207 + * Copyright 2005, Broadcom Corporation
1208 + * All Rights Reserved.
1209 + *
1210 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1211 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1212 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1213 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1214 + *
1215 + * $Id$
1216 + */
1217 +
1218 +#include <linux/config.h>
1219 +#include <linux/init.h>
1220 +#include <linux/module.h>
1221 +#include <linux/kernel.h>
1222 +#include <linux/string.h>
1223 +#include <linux/interrupt.h>
1224 +#include <linux/spinlock.h>
1225 +#include <linux/slab.h>
1226 +#include <asm/bootinfo.h>
1227 +#include <asm/addrspace.h>
1228 +#include <asm/io.h>
1229 +#include <asm/uaccess.h>
1230 +
1231 +#include <typedefs.h>
1232 +#include <bcmendian.h>
1233 +#include <bcmnvram.h>
1234 +#include <bcmutils.h>
1235 +#include <sbconfig.h>
1236 +#include <sbchipc.h>
1237 +#include <sbutils.h>
1238 +#include <sbmips.h>
1239 +#include <sflash.h>
1240 +
1241 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1242 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1243 +
1244 +/* Global SB handle */
1245 +extern void *sbh;
1246 +extern spinlock_t bcm947xx_sbh_lock;
1247 +static int cfe_env;
1248 +
1249 +extern char *cfe_env_get(char *nv_buf, const char *name);
1250 +
1251 +
1252 +/* Convenience */
1253 +#define sbh_lock bcm947xx_sbh_lock
1254 +#define KB * 1024
1255 +#define MB * 1024 * 1024
1256 +
1257 +/* Probe for NVRAM header */
1258 +static void __init
1259 +early_nvram_init(void)
1260 +{
1261 + struct nvram_header *header;
1262 + chipcregs_t *cc;
1263 + struct sflash *info = NULL;
1264 + int i;
1265 + uint32 base, off, lim;
1266 + u32 *src, *dst;
1267 +
1268 + cfe_env = 0;
1269 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1270 + base = KSEG1ADDR(SB_FLASH2);
1271 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1272 + case PFLASH:
1273 + lim = SB_FLASH2_SZ;
1274 + break;
1275 +
1276 + case SFLASH_ST:
1277 + case SFLASH_AT:
1278 + if ((info = sflash_init(cc)) == NULL)
1279 + return;
1280 + lim = info->size;
1281 + break;
1282 +
1283 + case FLASH_NONE:
1284 + default:
1285 + return;
1286 + }
1287 + } else {
1288 + /* extif assumed, Stop at 4 MB */
1289 + base = KSEG1ADDR(SB_FLASH1);
1290 + lim = SB_FLASH1_SZ;
1291 + }
1292 +
1293 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1294 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1295 + dst = (u32 *) nvram_buf;
1296 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1297 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1298 +
1299 + for (i = 0; i < 0x1ff0; i++) {
1300 + if (*src == 0xFFFFFFFF)
1301 + break;
1302 + *dst++ = *src++;
1303 + }
1304 + cfe_env = 1;
1305 + return;
1306 + }
1307 +
1308 + off = FLASH_MIN;
1309 + while (off <= lim) {
1310 + /* Windowed flash access */
1311 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1312 + if (header->magic == NVRAM_MAGIC)
1313 + goto found;
1314 + off <<= 1;
1315 + }
1316 +
1317 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1318 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1319 + if (header->magic == NVRAM_MAGIC)
1320 + goto found;
1321 +
1322 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1323 + if (header->magic == NVRAM_MAGIC)
1324 + goto found;
1325 +
1326 + return;
1327 +
1328 +found:
1329 + src = (u32 *) header;
1330 + dst = (u32 *) nvram_buf;
1331 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1332 + *dst++ = *src++;
1333 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1334 + *dst++ = ltoh32(*src++);
1335 +}
1336 +
1337 +/* Early (before mm or mtd) read-only access to NVRAM */
1338 +char * __init early_nvram_get(const char *name)
1339 +{
1340 + char *var, *value, *end, *eq;
1341 +
1342 + if (!name)
1343 + return NULL;
1344 +
1345 + /* Too early? */
1346 + if (sbh == NULL)
1347 + return NULL;
1348 +
1349 + if (!nvram_buf[0])
1350 + early_nvram_init();
1351 +
1352 + if (cfe_env)
1353 + return cfe_env_get(nvram_buf, name);
1354 +
1355 + /* Look for name=value and return value */
1356 + var = &nvram_buf[sizeof(struct nvram_header)];
1357 + end = nvram_buf + sizeof(nvram_buf) - 2;
1358 + end[0] = end[1] = '\0';
1359 + for (; *var; var = value + strlen(value) + 1) {
1360 + if (!(eq = strchr(var, '=')))
1361 + break;
1362 + value = eq + 1;
1363 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1364 + return value;
1365 + }
1366 +
1367 + return NULL;
1368 +}
1369 +
1370 +char *nvram_get(const char *name)
1371 +{
1372 + char *var, *value, *end, *eq;
1373 +
1374 + if (!name)
1375 + return NULL;
1376 +
1377 + if (!nvram_buf[0])
1378 + return NULL;
1379 +
1380 + /* Look for name=value and return value */
1381 + var = &nvram_buf[sizeof(struct nvram_header)];
1382 + end = nvram_buf + sizeof(nvram_buf) - 2;
1383 + end[0] = end[1] = '\0';
1384 + for (; *var; var = value + strlen(value) + 1) {
1385 + if (!(eq = strchr(var, '=')))
1386 + break;
1387 + value = eq + 1;
1388 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1389 + return value;
1390 + }
1391 +
1392 + return NULL;
1393 +}
1394 +
1395 +EXPORT_SYMBOL(nvram_get);
1396 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbmips.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbmips.c
1397 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1398 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbmips.c 2006-06-18 15:29:23.000000000 +0200
1399 @@ -0,0 +1,1055 @@
1400 +/*
1401 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1402 + *
1403 + * Copyright 2005, Broadcom Corporation
1404 + * All Rights Reserved.
1405 + *
1406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1410 + *
1411 + * $Id$
1412 + */
1413 +
1414 +#include <typedefs.h>
1415 +#include <osl.h>
1416 +#include <sbutils.h>
1417 +#include <bcmdevs.h>
1418 +#include <bcmnvram.h>
1419 +#include <bcmutils.h>
1420 +#include <hndmips.h>
1421 +#include <sbconfig.h>
1422 +#include <sbextif.h>
1423 +#include <sbchipc.h>
1424 +#include <sbmemc.h>
1425 +#include <mipsinc.h>
1426 +#include <sbutils.h>
1427 +
1428 +/*
1429 + * Returns TRUE if an external UART exists at the given base
1430 + * register.
1431 + */
1432 +static bool
1433 +BCMINITFN(serial_exists)(uint8 *regs)
1434 +{
1435 + uint8 save_mcr, status1;
1436 +
1437 + save_mcr = R_REG(&regs[UART_MCR]);
1438 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1439 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1440 + W_REG(&regs[UART_MCR], save_mcr);
1441 +
1442 + return (status1 == 0x90);
1443 +}
1444 +
1445 +/*
1446 + * Initializes UART access. The callback function will be called once
1447 + * per found UART.
1448 + */
1449 +void
1450 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1451 +{
1452 + void *regs;
1453 + ulong base;
1454 + uint irq;
1455 + int i, n;
1456 +
1457 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1458 + extifregs_t *eir = (extifregs_t *) regs;
1459 + sbconfig_t *sb;
1460 +
1461 + /* Determine external UART register base */
1462 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1463 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1464 +
1465 + /* Determine IRQ */
1466 + irq = sb_irq(sbh);
1467 +
1468 + /* Disable GPIO interrupt initially */
1469 + W_REG(&eir->gpiointpolarity, 0);
1470 + W_REG(&eir->gpiointmask, 0);
1471 +
1472 + /* Search for external UARTs */
1473 + n = 2;
1474 + for (i = 0; i < 2; i++) {
1475 + regs = (void *) REG_MAP(base + (i * 8), 8);
1476 + if (BCMINIT(serial_exists)(regs)) {
1477 + /* Set GPIO 1 to be the external UART IRQ */
1478 + W_REG(&eir->gpiointmask, 2);
1479 + if (add)
1480 + add(regs, irq, 13500000, 0);
1481 + }
1482 + }
1483 +
1484 + /* Add internal UART if enabled */
1485 + if (R_REG(&eir->corecontrol) & CC_UE)
1486 + if (add)
1487 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1488 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1489 + chipcregs_t *cc = (chipcregs_t *) regs;
1490 + uint32 rev, cap, pll, baud_base, div;
1491 +
1492 + /* Determine core revision and capabilities */
1493 + rev = sb_corerev(sbh);
1494 + cap = R_REG(&cc->capabilities);
1495 + pll = cap & CAP_PLL_MASK;
1496 +
1497 + /* Determine IRQ */
1498 + irq = sb_irq(sbh);
1499 +
1500 + if (pll == PLL_TYPE1) {
1501 + /* PLL clock */
1502 + baud_base = sb_clock_rate(pll,
1503 + R_REG(&cc->clockcontrol_n),
1504 + R_REG(&cc->clockcontrol_m2));
1505 + div = 1;
1506 + } else {
1507 + if (rev >= 11) {
1508 + /* Fixed ALP clock */
1509 + baud_base = 20000000;
1510 + div = 1;
1511 + /* Set the override bit so we don't divide it */
1512 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1513 + } else if (rev >= 3) {
1514 + /* Internal backplane clock */
1515 + baud_base = sb_clock(sbh);
1516 + div = 2; /* Minimum divisor */
1517 + W_REG(&cc->clkdiv,
1518 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1519 + } else {
1520 + /* Fixed internal backplane clock */
1521 + baud_base = 88000000;
1522 + div = 48;
1523 + }
1524 +
1525 + /* Clock source depends on strapping if UartClkOverride is unset */
1526 + if ((rev > 0) &&
1527 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1528 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1529 + /* Internal divided backplane clock */
1530 + baud_base /= div;
1531 + } else {
1532 + /* Assume external clock of 1.8432 MHz */
1533 + baud_base = 1843200;
1534 + }
1535 + }
1536 + }
1537 +
1538 + /* Add internal UARTs */
1539 + n = cap & CAP_UARTS_MASK;
1540 + for (i = 0; i < n; i++) {
1541 + /* Register offset changed after revision 0 */
1542 + if (rev)
1543 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1544 + else
1545 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1546 +
1547 + if (add)
1548 + add(regs, irq, baud_base, 0);
1549 + }
1550 + }
1551 +}
1552 +
1553 +/*
1554 + * Initialize jtag master and return handle for
1555 + * jtag_rwreg. Returns NULL on failure.
1556 + */
1557 +void *
1558 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1559 +{
1560 + void *regs;
1561 +
1562 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1563 + chipcregs_t *cc = (chipcregs_t *) regs;
1564 + uint32 tmp;
1565 +
1566 + /*
1567 + * Determine jtagm availability from
1568 + * core revision and capabilities.
1569 + */
1570 + tmp = sb_corerev(sbh);
1571 + /*
1572 + * Corerev 10 has jtagm, but the only chip
1573 + * with it does not have a mips, and
1574 + * the layout of the jtagcmd register is
1575 + * different. We'll only accept >= 11.
1576 + */
1577 + if (tmp < 11)
1578 + return (NULL);
1579 +
1580 + tmp = R_REG(&cc->capabilities);
1581 + if ((tmp & CAP_JTAGP) == 0)
1582 + return (NULL);
1583 +
1584 + /* Set clock divider if requested */
1585 + if (clkd != 0) {
1586 + tmp = R_REG(&cc->clkdiv);
1587 + tmp = (tmp & ~CLKD_JTAG) |
1588 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1589 + W_REG(&cc->clkdiv, tmp);
1590 + }
1591 +
1592 + /* Enable jtagm */
1593 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1594 + W_REG(&cc->jtagctrl, tmp);
1595 + }
1596 +
1597 + return (regs);
1598 +}
1599 +
1600 +void
1601 +sb_jtagm_disable(void *h)
1602 +{
1603 + chipcregs_t *cc = (chipcregs_t *)h;
1604 +
1605 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1606 +}
1607 +
1608 +/*
1609 + * Read/write a jtag register. Assumes a target with
1610 + * 8 bit IR and 32 bit DR.
1611 + */
1612 +#define IRWIDTH 8
1613 +#define DRWIDTH 32
1614 +uint32
1615 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1616 +{
1617 + chipcregs_t *cc = (chipcregs_t *) h;
1618 + uint32 tmp;
1619 +
1620 + W_REG(&cc->jtagir, ir);
1621 + W_REG(&cc->jtagdr, dr);
1622 + tmp = JCMD_START | JCMD_ACC_IRDR |
1623 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1624 + (DRWIDTH - 1);
1625 + W_REG(&cc->jtagcmd, tmp);
1626 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1627 + /* OSL_DELAY(1); */
1628 + }
1629 +
1630 + tmp = R_REG(&cc->jtagdr);
1631 + return (tmp);
1632 +}
1633 +
1634 +/* Returns the SB interrupt flag of the current core. */
1635 +uint32
1636 +sb_flag(sb_t *sbh)
1637 +{
1638 + void *regs;
1639 + sbconfig_t *sb;
1640 +
1641 + regs = sb_coreregs(sbh);
1642 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1643 +
1644 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1645 +}
1646 +
1647 +static const uint32 sbips_int_mask[] = {
1648 + 0,
1649 + SBIPS_INT1_MASK,
1650 + SBIPS_INT2_MASK,
1651 + SBIPS_INT3_MASK,
1652 + SBIPS_INT4_MASK
1653 +};
1654 +
1655 +static const uint32 sbips_int_shift[] = {
1656 + 0,
1657 + 0,
1658 + SBIPS_INT2_SHIFT,
1659 + SBIPS_INT3_SHIFT,
1660 + SBIPS_INT4_SHIFT
1661 +};
1662 +
1663 +/*
1664 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1665 + * 0 is returned.
1666 + */
1667 +uint
1668 +sb_irq(sb_t *sbh)
1669 +{
1670 + uint idx;
1671 + void *regs;
1672 + sbconfig_t *sb;
1673 + uint32 flag, sbipsflag;
1674 + uint irq = 0;
1675 +
1676 + flag = sb_flag(sbh);
1677 +
1678 + idx = sb_coreidx(sbh);
1679 +
1680 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1681 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1682 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1683 +
1684 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1685 + sbipsflag = R_REG(&sb->sbipsflag);
1686 + for (irq = 1; irq <= 4; irq++) {
1687 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1688 + break;
1689 + }
1690 + if (irq == 5)
1691 + irq = 0;
1692 + }
1693 +
1694 + sb_setcoreidx(sbh, idx);
1695 +
1696 + return irq;
1697 +}
1698 +
1699 +/* Clears the specified MIPS IRQ. */
1700 +static void
1701 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1702 +{
1703 + void *regs;
1704 + sbconfig_t *sb;
1705 +
1706 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1707 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1708 + ASSERT(regs);
1709 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1710 +
1711 + if (irq == 0)
1712 + W_REG(&sb->sbintvec, 0);
1713 + else
1714 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1715 +}
1716 +
1717 +/*
1718 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1719 + * IRQ 0 may be assigned more than once.
1720 + */
1721 +static void
1722 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 + uint32 flag;
1727 +
1728 + regs = sb_setcore(sbh, coreid, coreunit);
1729 + ASSERT(regs);
1730 + flag = sb_flag(sbh);
1731 +
1732 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1733 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1734 + ASSERT(regs);
1735 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1736 +
1737 + if (irq == 0)
1738 + OR_REG(&sb->sbintvec, 1 << flag);
1739 + else {
1740 + flag <<= sbips_int_shift[irq];
1741 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1742 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1743 + W_REG(&sb->sbipsflag, flag);
1744 + }
1745 +}
1746 +
1747 +/*
1748 + * Initializes clocks and interrupts. SB and NVRAM access must be
1749 + * initialized prior to calling.
1750 + */
1751 +void
1752 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1753 +{
1754 + ulong hz, ns, tmp;
1755 + extifregs_t *eir;
1756 + chipcregs_t *cc;
1757 + char *value;
1758 + uint irq;
1759 +
1760 + /* Figure out current SB clock speed */
1761 + if ((hz = sb_clock(sbh)) == 0)
1762 + hz = 100000000;
1763 + ns = 1000000000 / hz;
1764 +
1765 + /* Setup external interface timing */
1766 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1767 + /* Initialize extif so we can get to the LEDs and external UART */
1768 + W_REG(&eir->prog_config, CF_EN);
1769 +
1770 + /* Set timing for the flash */
1771 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1772 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1773 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1774 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1775 +
1776 + /* Set programmable interface timing for external uart */
1777 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1778 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1779 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1780 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1781 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1782 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1783 + /* set register for external IO to control LED. */
1784 + W_REG(&cc->prog_config, 0x11);
1785 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1786 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1787 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
1788 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1789 +
1790 + /* Set timing for the flash */
1791 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1792 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1793 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1794 +
1795 + // Added by Chen-I for 5365
1796 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1797 + {
1798 + W_REG(&cc->flash_waitcount, tmp);
1799 + W_REG(&cc->pcmcia_memwait, tmp);
1800 + }
1801 + else
1802 + {
1803 + if (sb_corerev(sbh) < 9)
1804 + W_REG(&cc->flash_waitcount, tmp);
1805 +
1806 + if ((sb_corerev(sbh) < 9) ||
1807 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1808 + W_REG(&cc->pcmcia_memwait, tmp);
1809 + }
1810 + }
1811 + // Added by Chen-I & Yen for enabling 5350 EXTIF
1812 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
1813 + {
1814 + /* Set programmable interface timing for external uart */
1815 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1816 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1817 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1818 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1819 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1820 + }
1821 + }
1822 +
1823 + /* Chip specific initialization */
1824 + switch (BCMINIT(sb_chip)(sbh)) {
1825 + case BCM4710_DEVICE_ID:
1826 + /* Clear interrupt map */
1827 + for (irq = 0; irq <= 4; irq++)
1828 + BCMINIT(sb_clearirq)(sbh, irq);
1829 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1830 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1831 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1832 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1833 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1834 + ASSERT(eir);
1835 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1836 + if (value && !strcmp(value, "31")) {
1837 + /* Enable internal UART */
1838 + W_REG(&eir->corecontrol, CC_UE);
1839 + /* Give USB its own interrupt */
1840 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1841 + } else {
1842 + /* Disable internal UART */
1843 + W_REG(&eir->corecontrol, 0);
1844 + /* Give Ethernet its own interrupt */
1845 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1846 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1847 + }
1848 + break;
1849 + case BCM5350_DEVICE_ID:
1850 + /* Clear interrupt map */
1851 + for (irq = 0; irq <= 4; irq++)
1852 + BCMINIT(sb_clearirq)(sbh, irq);
1853 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1854 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1855 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1856 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1857 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1858 + break;
1859 + }
1860 +}
1861 +
1862 +uint32
1863 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1864 +{
1865 + extifregs_t *eir;
1866 + chipcregs_t *cc;
1867 + uint32 n, m;
1868 + uint idx;
1869 + uint32 pll_type, rate = 0;
1870 +
1871 + /* get index of the current core */
1872 + idx = sb_coreidx(sbh);
1873 + pll_type = PLL_TYPE1;
1874 +
1875 + /* switch to extif or chipc core */
1876 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1877 + n = R_REG(&eir->clockcontrol_n);
1878 + m = R_REG(&eir->clockcontrol_sb);
1879 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1880 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1881 + n = R_REG(&cc->clockcontrol_n);
1882 + if ((pll_type == PLL_TYPE2) ||
1883 + (pll_type == PLL_TYPE4) ||
1884 + (pll_type == PLL_TYPE6) ||
1885 + (pll_type == PLL_TYPE7))
1886 + m = R_REG(&cc->clockcontrol_mips);
1887 + else if (pll_type == PLL_TYPE5) {
1888 + rate = 200000000;
1889 + goto out;
1890 + }
1891 + else if (pll_type == PLL_TYPE3) {
1892 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1893 + rate = 200000000;
1894 + goto out;
1895 + } else
1896 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1897 + } else
1898 + m = R_REG(&cc->clockcontrol_sb);
1899 + } else
1900 + goto out;
1901 +
1902 + // Added by Chen-I for 5365
1903 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1904 + rate = 100000000;
1905 + else
1906 + /* calculate rate */
1907 + rate = sb_clock_rate(pll_type, n, m);
1908 +
1909 + if (pll_type == PLL_TYPE6)
1910 + rate = SB2MIPS_T6(rate);
1911 +
1912 +out:
1913 + /* switch back to previous core */
1914 + sb_setcoreidx(sbh, idx);
1915 +
1916 + return rate;
1917 +}
1918 +
1919 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1920 +
1921 +static void
1922 +BCMINITFN(handler)(void)
1923 +{
1924 + /* Step 11 */
1925 + __asm__ (
1926 + ".set\tmips32\n\t"
1927 + "ssnop\n\t"
1928 + "ssnop\n\t"
1929 + /* Disable interrupts */
1930 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1931 + "mfc0 $15, $12\n\t"
1932 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1933 + "li $14, -31746\n\t"
1934 + "and $15, $15, $14\n\t"
1935 + "mtc0 $15, $12\n\t"
1936 + "eret\n\t"
1937 + "nop\n\t"
1938 + "nop\n\t"
1939 + ".set\tmips0"
1940 + );
1941 +}
1942 +
1943 +/* The following MUST come right after handler() */
1944 +static void
1945 +BCMINITFN(afterhandler)(void)
1946 +{
1947 +}
1948 +
1949 +/*
1950 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1951 + */
1952 +bool
1953 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1954 +{
1955 + extifregs_t *eir = NULL;
1956 + chipcregs_t *cc = NULL;
1957 + mipsregs_t *mipsr = NULL;
1958 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1959 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1960 + uint32 pll_type, sync_mode;
1961 + uint ic_size, ic_lsize;
1962 + uint idx, i;
1963 + typedef struct {
1964 + uint32 mipsclock;
1965 + uint16 n;
1966 + uint32 sb;
1967 + uint32 pci33;
1968 + uint32 pci25;
1969 + } n3m_table_t;
1970 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1971 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1972 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1973 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1974 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1975 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1976 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1977 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1978 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1979 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1980 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1981 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1982 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1983 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1984 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1985 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1986 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1987 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1988 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1989 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1990 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1991 + };
1992 + typedef struct {
1993 + uint32 mipsclock;
1994 + uint16 n;
1995 + uint32 m2; /* that is the clockcontrol_m2 */
1996 + } type3_table_t;
1997 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
1998 + { 150000000, 0x311, 0x4020005 },
1999 + { 200000000, 0x311, 0x4020003 },
2000 + };
2001 + typedef struct {
2002 + uint32 mipsclock;
2003 + uint32 sbclock;
2004 + uint16 n;
2005 + uint32 sb;
2006 + uint32 pci33;
2007 + uint32 m2;
2008 + uint32 m3;
2009 + uint32 ratio_cfg;
2010 + uint32 ratio_parm;
2011 + } n4m_table_t;
2012 +
2013 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2014 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2015 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2016 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2017 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2018 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2019 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2020 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2021 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2023 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2026 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2027 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2028 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2029 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2031 + };
2032 +
2033 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2034 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2035 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2036 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2037 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2038 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2039 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2041 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2042 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2043 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2045 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2047 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2048 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2049 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2050 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2051 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2052 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2053 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2054 + };
2055 +
2056 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2057 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2058 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2059 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2060 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2061 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2062 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2063 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2065 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2066 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2067 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2068 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2070 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2071 + };
2072 +
2073 + ulong start, end, dst;
2074 + bool ret = FALSE;
2075 +
2076 + /* get index of the current core */
2077 + idx = sb_coreidx(sbh);
2078 + clockcontrol_m2 = NULL;
2079 +
2080 + /* switch to extif or chipc core */
2081 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2082 + pll_type = PLL_TYPE1;
2083 + clockcontrol_n = &eir->clockcontrol_n;
2084 + clockcontrol_sb = &eir->clockcontrol_sb;
2085 + clockcontrol_pci = &eir->clockcontrol_pci;
2086 + clockcontrol_m2 = &cc->clockcontrol_m2;
2087 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2088 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2089 + if (pll_type == PLL_TYPE6) {
2090 + clockcontrol_n = NULL;
2091 + clockcontrol_sb = NULL;
2092 + clockcontrol_pci = NULL;
2093 + } else {
2094 + clockcontrol_n = &cc->clockcontrol_n;
2095 + clockcontrol_sb = &cc->clockcontrol_sb;
2096 + clockcontrol_pci = &cc->clockcontrol_pci;
2097 + clockcontrol_m2 = &cc->clockcontrol_m2;
2098 + }
2099 + } else
2100 + goto done;
2101 +
2102 + if (pll_type == PLL_TYPE6) {
2103 + /* Silence compilers */
2104 + orig_n = orig_sb = orig_pci = 0;
2105 + } else {
2106 + /* Store the current clock register values */
2107 + orig_n = R_REG(clockcontrol_n);
2108 + orig_sb = R_REG(clockcontrol_sb);
2109 + orig_pci = R_REG(clockcontrol_pci);
2110 + }
2111 +
2112 + if (pll_type == PLL_TYPE1) {
2113 + /* Keep the current PCI clock if not specified */
2114 + if (pciclock == 0) {
2115 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2116 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2117 + }
2118 +
2119 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2120 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2121 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2122 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2123 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2124 + break;
2125 + }
2126 + if (i == 0) {
2127 + ret = FALSE;
2128 + goto done;
2129 + } else {
2130 + ret = TRUE;
2131 + i--;
2132 + }
2133 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2134 +
2135 + /* No PLL change */
2136 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2137 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2138 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2139 + goto done;
2140 +
2141 + /* Set the PLL controls */
2142 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2143 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2144 + if (pciclock == 25000000)
2145 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2146 + else
2147 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2148 +
2149 + /* Reset */
2150 + sb_watchdog(sbh, 1);
2151 +
2152 + while (1);
2153 + } else if ((pll_type == PLL_TYPE3) &&
2154 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2155 + /* 5350 */
2156 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2157 +
2158 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2159 + if (type3_table[i].mipsclock > mipsclock)
2160 + break;
2161 + }
2162 + if (i == 0) {
2163 + ret = FALSE;
2164 + goto done;
2165 + } else {
2166 + ret = TRUE;
2167 + i--;
2168 + }
2169 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2170 +
2171 + /* No PLL change */
2172 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2173 + if ((orig_n == type3_table[i].n) &&
2174 + (orig_m2 == type3_table[i].m2)) {
2175 + goto done;
2176 + }
2177 +
2178 + /* Set the PLL controls */
2179 + W_REG(clockcontrol_n, type3_table[i].n);
2180 + W_REG(clockcontrol_m2, type3_table[i].m2);
2181 +
2182 + /* Reset */
2183 + sb_watchdog(sbh, 1);
2184 + while (1);
2185 + } else if ((pll_type == PLL_TYPE2) ||
2186 + (pll_type == PLL_TYPE4) ||
2187 + (pll_type == PLL_TYPE6) ||
2188 + (pll_type == PLL_TYPE7)) {
2189 + n4m_table_t *table = NULL, *te;
2190 + uint tabsz = 0;
2191 +
2192 + ASSERT(cc);
2193 +
2194 + orig_mips = R_REG(&cc->clockcontrol_mips);
2195 +
2196 + if (pll_type == PLL_TYPE6) {
2197 + uint32 new_mips = 0;
2198 +
2199 + ret = TRUE;
2200 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2201 + new_mips = CC_T6_MMASK;
2202 +
2203 + if (orig_mips == new_mips)
2204 + goto done;
2205 +
2206 + W_REG(&cc->clockcontrol_mips, new_mips);
2207 + goto end_fill;
2208 + }
2209 +
2210 + if (pll_type == PLL_TYPE2) {
2211 + table = BCMINIT(type2_table);
2212 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2213 + } else if (pll_type == PLL_TYPE4) {
2214 + table = BCMINIT(type4_table);
2215 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2216 + } else if (pll_type == PLL_TYPE7) {
2217 + table = BCMINIT(type7_table);
2218 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2219 + } else
2220 + ASSERT("No table for plltype" == NULL);
2221 +
2222 + /* Store the current clock register values */
2223 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2224 + orig_ratio_parm = 0;
2225 + orig_ratio_cfg = 0;
2226 +
2227 + /* Look up current ratio */
2228 + for (i = 0; i < tabsz; i++) {
2229 + if ((orig_n == table[i].n) &&
2230 + (orig_sb == table[i].sb) &&
2231 + (orig_pci == table[i].pci33) &&
2232 + (orig_m2 == table[i].m2) &&
2233 + (orig_mips == table[i].m3)) {
2234 + orig_ratio_parm = table[i].ratio_parm;
2235 + orig_ratio_cfg = table[i].ratio_cfg;
2236 + break;
2237 + }
2238 + }
2239 +
2240 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2241 + for (i = 0; i < tabsz; i++) {
2242 + ASSERT(table[i].mipsclock ==
2243 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2244 + if ((mipsclock <= table[i].mipsclock) &&
2245 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2246 + break;
2247 + }
2248 + if (i == tabsz) {
2249 + ret = FALSE;
2250 + goto done;
2251 + } else {
2252 + te = &table[i];
2253 + ret = TRUE;
2254 + }
2255 +
2256 + /* No PLL change */
2257 + if ((orig_n == te->n) &&
2258 + (orig_sb == te->sb) &&
2259 + (orig_pci == te->pci33) &&
2260 + (orig_m2 == te->m2) &&
2261 + (orig_mips == te->m3))
2262 + goto done;
2263 +
2264 + /* Set the PLL controls */
2265 + W_REG(clockcontrol_n, te->n);
2266 + W_REG(clockcontrol_sb, te->sb);
2267 + W_REG(clockcontrol_pci, te->pci33);
2268 + W_REG(&cc->clockcontrol_m2, te->m2);
2269 + W_REG(&cc->clockcontrol_mips, te->m3);
2270 +
2271 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2272 + if ((pll_type == PLL_TYPE7) &&
2273 + (te->sb != te->m2) &&
2274 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2275 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2276 +
2277 + /* No ratio change */
2278 + if (orig_ratio_parm == te->ratio_parm)
2279 + goto end_fill;
2280 +
2281 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2282 +
2283 + /* Preload the code into the cache */
2284 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2285 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2286 + while (start < end) {
2287 + cache_op(start, Fill_I);
2288 + start += ic_lsize;
2289 + }
2290 +
2291 + /* Copy the handler */
2292 + start = (ulong) &BCMINIT(handler);
2293 + end = (ulong) &BCMINIT(afterhandler);
2294 + dst = KSEG1ADDR(0x180);
2295 + for (i = 0; i < (end - start); i += 4)
2296 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2297 +
2298 + /* Preload handler into the cache one line at a time */
2299 + for (i = 0; i < (end - start); i += 4)
2300 + cache_op(dst + i, Fill_I);
2301 +
2302 + /* Clear BEV bit */
2303 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2304 +
2305 + /* Enable interrupts */
2306 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2307 +
2308 + /* Enable MIPS timer interrupt */
2309 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2310 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2311 + ASSERT(mipsr);
2312 + W_REG(&mipsr->intmask, 1);
2313 +
2314 + start_fill:
2315 + /* step 1, set clock ratios */
2316 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2317 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2318 +
2319 + /* step 2: program timer intr */
2320 + W_REG(&mipsr->timer, 100);
2321 + (void) R_REG(&mipsr->timer);
2322 +
2323 + /* step 3, switch to async */
2324 + sync_mode = MFC0(C0_BROADCOM, 4);
2325 + MTC0(C0_BROADCOM, 4, 1 << 22);
2326 +
2327 + /* step 4, set cfg active */
2328 + MTC0(C0_BROADCOM, 2, 0x9);
2329 +
2330 +
2331 + /* steps 5 & 6 */
2332 + __asm__ __volatile__ (
2333 + ".set\tmips3\n\t"
2334 + "wait\n\t"
2335 + ".set\tmips0"
2336 + );
2337 +
2338 + /* step 7, clear cfg_active */
2339 + MTC0(C0_BROADCOM, 2, 0);
2340 +
2341 + /* Additional Step: set back to orig sync mode */
2342 + MTC0(C0_BROADCOM, 4, sync_mode);
2343 +
2344 + /* step 8, fake soft reset */
2345 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2346 +
2347 + end_fill:
2348 + /* step 9 set watchdog timer */
2349 + sb_watchdog(sbh, 20);
2350 + (void) R_REG(&cc->chipid);
2351 +
2352 + /* step 11 */
2353 + __asm__ __volatile__ (
2354 + ".set\tmips3\n\t"
2355 + "sync\n\t"
2356 + "wait\n\t"
2357 + ".set\tmips0"
2358 + );
2359 + while (1);
2360 + }
2361 +
2362 +done:
2363 + /* switch back to previous core */
2364 + sb_setcoreidx(sbh, idx);
2365 +
2366 + return ret;
2367 +}
2368 +
2369 +/*
2370 + * This also must be run from the cache on 47xx
2371 + * so there are no mips core BIU ops in progress
2372 + * when the PFC is enabled.
2373 + */
2374 +
2375 +static void
2376 +BCMINITFN(_enable_pfc)(uint32 mode)
2377 +{
2378 + /* write range */
2379 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2380 +
2381 + /* enable */
2382 + *(volatile uint32 *)PFC_CR0 = mode;
2383 +}
2384 +
2385 +void
2386 +BCMINITFN(enable_pfc)(uint32 mode)
2387 +{
2388 + ulong start, end;
2389 + int i;
2390 +
2391 + /* If auto then choose the correct mode for this
2392 + platform, currently we only ever select one mode */
2393 + if (mode == PFC_AUTO)
2394 + mode = PFC_INST;
2395 +
2396 + /* enable prefetch cache if available */
2397 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2398 + start = (ulong) &BCMINIT(_enable_pfc);
2399 + end = (ulong) &BCMINIT(enable_pfc);
2400 +
2401 + /* Preload handler into the cache one line at a time */
2402 + for (i = 0; i < (end - start); i += 4)
2403 + cache_op(start + i, Fill_I);
2404 +
2405 + BCMINIT(_enable_pfc)(mode);
2406 + }
2407 +}
2408 +
2409 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2410 +uint32
2411 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2412 +{
2413 + sbmemcregs_t *memc;
2414 + uint32 ret = 0;
2415 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2416 + uint idx, rev;
2417 +
2418 + idx = sb_coreidx(sbh);
2419 +
2420 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2421 + if (memc == 0)
2422 + goto out;
2423 +
2424 + rev = sb_corerev(sbh);
2425 +
2426 + config = R_REG(&memc->config);
2427 + wr = R_REG(&memc->wrncdlcor);
2428 + rd = R_REG(&memc->rdncdlcor);
2429 + misc = R_REG(&memc->miscdlyctl);
2430 + dqsg = R_REG(&memc->dqsgatencdl);
2431 +
2432 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2433 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2434 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2435 +
2436 + if (config & MEMC_CONFIG_DDR) {
2437 + ret = (wr << 16) | (rd << 8) | dqsg;
2438 + } else {
2439 + if (rev > 0)
2440 + cd = rd;
2441 + else
2442 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2443 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2444 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2445 + ret = (sm << 16) | (sd << 8) | cd;
2446 + }
2447 +
2448 +out:
2449 + /* switch back to previous core */
2450 + sb_setcoreidx(sbh, idx);
2451 +
2452 + return ret;
2453 +}
2454 +
2455 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbpci.c
2456 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2457 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbpci.c 2006-06-18 15:29:23.000000000 +0200
2458 @@ -0,0 +1,534 @@
2459 +/*
2460 + * Low-Level PCI and SB support for BCM47xx
2461 + *
2462 + * Copyright 2005, Broadcom Corporation
2463 + * All Rights Reserved.
2464 + *
2465 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2466 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2467 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2468 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2469 + *
2470 + * $Id$
2471 + */
2472 +
2473 +#include <typedefs.h>
2474 +#include <pcicfg.h>
2475 +#include <bcmdevs.h>
2476 +#include <sbconfig.h>
2477 +#include <osl.h>
2478 +#include <sbutils.h>
2479 +#include <sbpci.h>
2480 +#include <bcmendian.h>
2481 +#include <bcmutils.h>
2482 +#include <bcmnvram.h>
2483 +#include <hndmips.h>
2484 +
2485 +/* Can free sbpci_init() memory after boot */
2486 +#ifndef linux
2487 +#define __init
2488 +#endif
2489 +
2490 +/* Emulated configuration space */
2491 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2492 +
2493 +/* Banned cores */
2494 +static uint16 pci_ban[32] = { 0 };
2495 +static uint pci_banned = 0;
2496 +
2497 +/* CardBus mode */
2498 +static bool cardbus = FALSE;
2499 +
2500 +/* Disable PCI host core */
2501 +static bool pci_disabled = FALSE;
2502 +
2503 +/*
2504 + * Functions for accessing external PCI configuration space
2505 + */
2506 +
2507 +/* Assume one-hot slot wiring */
2508 +#define PCI_SLOT_MAX 16
2509 +
2510 +static uint32
2511 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2512 +{
2513 + uint coreidx;
2514 + sbpciregs_t *regs;
2515 + uint32 addr = 0;
2516 +
2517 + /* CardBusMode supports only one device */
2518 + if (cardbus && dev > 1)
2519 + return 0;
2520 +
2521 + coreidx = sb_coreidx(sbh);
2522 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2523 +
2524 + /* Type 0 transaction */
2525 + if (bus == 1) {
2526 + /* Skip unwired slots */
2527 + if (dev < PCI_SLOT_MAX) {
2528 + /* Slide the PCI window to the appropriate slot */
2529 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2530 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2531 + (func << 8) | (off & ~3);
2532 + }
2533 + }
2534 +
2535 + /* Type 1 transaction */
2536 + else {
2537 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2538 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2539 + }
2540 +
2541 + sb_setcoreidx(sbh, coreidx);
2542 +
2543 + return addr;
2544 +}
2545 +
2546 +static int
2547 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2548 +{
2549 + uint32 addr, *reg = NULL, val;
2550 + int ret = 0;
2551 +
2552 + if (pci_disabled ||
2553 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2554 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2555 + BUSPROBE(val, reg))
2556 + val = 0xffffffff;
2557 +
2558 + val >>= 8 * (off & 3);
2559 + if (len == 4)
2560 + *((uint32 *) buf) = val;
2561 + else if (len == 2)
2562 + *((uint16 *) buf) = (uint16) val;
2563 + else if (len == 1)
2564 + *((uint8 *) buf) = (uint8) val;
2565 + else
2566 + ret = -1;
2567 +
2568 + if (reg)
2569 + REG_UNMAP(reg);
2570 +
2571 + return ret;
2572 +}
2573 +
2574 +static int
2575 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2576 +{
2577 + uint32 addr, *reg = NULL, val;
2578 + int ret = 0;
2579 +
2580 + if (pci_disabled ||
2581 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2582 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2583 + BUSPROBE(val, reg))
2584 + goto done;
2585 +
2586 + if (len == 4)
2587 + val = *((uint32 *) buf);
2588 + else if (len == 2) {
2589 + val &= ~(0xffff << (8 * (off & 3)));
2590 + val |= *((uint16 *) buf) << (8 * (off & 3));
2591 + } else if (len == 1) {
2592 + val &= ~(0xff << (8 * (off & 3)));
2593 + val |= *((uint8 *) buf) << (8 * (off & 3));
2594 + } else
2595 + ret = -1;
2596 +
2597 + W_REG(reg, val);
2598 +
2599 + done:
2600 + if (reg)
2601 + REG_UNMAP(reg);
2602 +
2603 + return ret;
2604 +}
2605 +
2606 +/*
2607 + * Functions for accessing translated SB configuration space
2608 + */
2609 +
2610 +static int
2611 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2612 +{
2613 + pci_config_regs *cfg;
2614 +
2615 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2616 + return -1;
2617 + cfg = &sb_config_regs[dev];
2618 +
2619 + ASSERT(ISALIGNED(off, len));
2620 + ASSERT(ISALIGNED((uintptr)buf, len));
2621 +
2622 + if (len == 4)
2623 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2624 + else if (len == 2)
2625 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2626 + else if (len == 1)
2627 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2628 + else
2629 + return -1;
2630 +
2631 + return 0;
2632 +}
2633 +
2634 +static int
2635 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2636 +{
2637 + uint coreidx, n;
2638 + void *regs;
2639 + sbconfig_t *sb;
2640 + pci_config_regs *cfg;
2641 +
2642 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2643 + return -1;
2644 + cfg = &sb_config_regs[dev];
2645 +
2646 + ASSERT(ISALIGNED(off, len));
2647 + ASSERT(ISALIGNED((uintptr)buf, len));
2648 +
2649 + /* Emulate BAR sizing */
2650 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2651 + len == 4 && *((uint32 *) buf) == ~0) {
2652 + coreidx = sb_coreidx(sbh);
2653 + if ((regs = sb_setcoreidx(sbh, dev))) {
2654 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2655 + /* Highest numbered address match register */
2656 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2657 + if (off == OFFSETOF(pci_config_regs, base[0]))
2658 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2659 +#if 0
2660 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2661 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2662 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2663 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2664 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2665 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2666 +#endif
2667 + }
2668 + sb_setcoreidx(sbh, coreidx);
2669 + return 0;
2670 + }
2671 +
2672 + if (len == 4)
2673 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2674 + else if (len == 2)
2675 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2676 + else if (len == 1)
2677 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2678 + else
2679 + return -1;
2680 +
2681 + return 0;
2682 +}
2683 +
2684 +int
2685 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2686 +{
2687 + if (bus == 0)
2688 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2689 + else
2690 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2691 +}
2692 +
2693 +int
2694 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2695 +{
2696 + if (bus == 0)
2697 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2698 + else
2699 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2700 +}
2701 +
2702 +void
2703 +sbpci_ban(uint16 core)
2704 +{
2705 + if (pci_banned < ARRAYSIZE(pci_ban))
2706 + pci_ban[pci_banned++] = core;
2707 +}
2708 +
2709 +static int
2710 +sbpci_init_pci(sb_t *sbh)
2711 +{
2712 + uint chip, chiprev, chippkg, host;
2713 + uint32 boardflags;
2714 + sbpciregs_t *pci;
2715 + sbconfig_t *sb;
2716 + uint32 val;
2717 +
2718 + chip = sb_chip(sbh);
2719 + chiprev = sb_chiprev(sbh);
2720 + chippkg = sb_chippkg(sbh);
2721 +
2722 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2723 + printf("PCI: no core\n");
2724 + pci_disabled = TRUE;
2725 + return -1;
2726 + }
2727 + sb_core_reset(sbh, 0);
2728 +
2729 + boardflags = (uint32) getintvar(NULL, "boardflags");
2730 +
2731 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2732 + pci_disabled = TRUE;
2733 +
2734 + /*
2735 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2736 + * PCI is bonded out, some boards may leave the pins
2737 + * floating.
2738 + */
2739 + if (((chip == BCM4712_DEVICE_ID) &&
2740 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2741 + (chippkg == BCM4712MID_PKG_ID))) ||
2742 + (chip == BCM5350_DEVICE_ID) ||
2743 + (boardflags & BFL_NOPCI))
2744 + pci_disabled = TRUE;
2745 +
2746 + /*
2747 + * If the PCI core should not be touched (disabled, not bonded
2748 + * out, or pins floating), do not even attempt to access core
2749 + * registers. Otherwise, try to determine if it is in host
2750 + * mode.
2751 + */
2752 + if (pci_disabled)
2753 + host = 0;
2754 + else
2755 + host = !BUSPROBE(val, &pci->control);
2756 +
2757 + if (!host) {
2758 + /* Disable PCI interrupts in client mode */
2759 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2760 + W_REG(&sb->sbintvec, 0);
2761 +
2762 + /* Disable the PCI bridge in client mode */
2763 + sbpci_ban(SB_PCI);
2764 + printf("PCI: Disabled\n");
2765 + } else {
2766 + /* Reset the external PCI bus and enable the clock */
2767 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2768 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2769 + OSL_DELAY(150); /* delay > 100 us */
2770 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2771 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2772 + OSL_DELAY(1); /* delay 1 us */
2773 +
2774 + /* Enable CardBusMode */
2775 + cardbus = nvram_match("cardbus", "1");
2776 + if (cardbus) {
2777 + printf("PCI: Enabling CardBus\n");
2778 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2779 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2780 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2781 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2782 + }
2783 +
2784 + /* 64 MB I/O access window */
2785 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2786 + /* 64 MB configuration access window */
2787 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2788 + /* 1 GB memory access window */
2789 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2790 +
2791 + /* Enable PCI bridge BAR0 prefetch and burst */
2792 + val = 6;
2793 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2794 +
2795 + /* Enable PCI interrupts */
2796 + W_REG(&pci->intmask, PCI_INTA);
2797 + }
2798 +
2799 + return 0;
2800 +}
2801 +
2802 +static int
2803 +sbpci_init_cores(sb_t *sbh)
2804 +{
2805 + uint chip, chiprev, chippkg, coreidx, i;
2806 + sbconfig_t *sb;
2807 + pci_config_regs *cfg;
2808 + void *regs;
2809 + char varname[8];
2810 + uint wlidx = 0;
2811 + uint16 vendor, core;
2812 + uint8 class, subclass, progif;
2813 + uint32 val;
2814 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2815 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2816 +
2817 + chip = sb_chip(sbh);
2818 + chiprev = sb_chiprev(sbh);
2819 + chippkg = sb_chippkg(sbh);
2820 + coreidx = sb_coreidx(sbh);
2821 +
2822 + /* Scan the SB bus */
2823 + bzero(sb_config_regs, sizeof(sb_config_regs));
2824 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2825 + cfg->vendor = 0xffff;
2826 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2827 + continue;
2828 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2829 +
2830 + /* Read ID register and parse vendor and core */
2831 + val = R_REG(&sb->sbidhigh);
2832 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2833 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2834 + progif = 0;
2835 +
2836 + /* Check if this core is banned */
2837 + for (i = 0; i < pci_banned; i++)
2838 + if (core == pci_ban[i])
2839 + break;
2840 + if (i < pci_banned)
2841 + continue;
2842 +
2843 + /* Known vendor translations */
2844 + switch (vendor) {
2845 + case SB_VEND_BCM:
2846 + vendor = VENDOR_BROADCOM;
2847 + break;
2848 + }
2849 +
2850 + /* Determine class based on known core codes */
2851 + switch (core) {
2852 + case SB_ILINE20:
2853 + class = PCI_CLASS_NET;
2854 + subclass = PCI_NET_ETHER;
2855 + core = BCM47XX_ILINE_ID;
2856 + break;
2857 + case SB_ILINE100:
2858 + class = PCI_CLASS_NET;
2859 + subclass = PCI_NET_ETHER;
2860 + core = BCM4610_ILINE_ID;
2861 + break;
2862 + case SB_ENET:
2863 + class = PCI_CLASS_NET;
2864 + subclass = PCI_NET_ETHER;
2865 + core = BCM47XX_ENET_ID;
2866 + break;
2867 + case SB_SDRAM:
2868 + case SB_MEMC:
2869 + class = PCI_CLASS_MEMORY;
2870 + subclass = PCI_MEMORY_RAM;
2871 + break;
2872 + case SB_PCI:
2873 +#if 0
2874 + class = PCI_CLASS_BRIDGE;
2875 + subclass = PCI_BRIDGE_PCI;
2876 + break;
2877 +#endif
2878 + case SB_MIPS:
2879 + case SB_MIPS33:
2880 + class = PCI_CLASS_CPU;
2881 + subclass = PCI_CPU_MIPS;
2882 + break;
2883 + case SB_CODEC:
2884 + class = PCI_CLASS_COMM;
2885 + subclass = PCI_COMM_MODEM;
2886 + core = BCM47XX_V90_ID;
2887 + break;
2888 + case SB_USB:
2889 + class = PCI_CLASS_SERIAL;
2890 + subclass = PCI_SERIAL_USB;
2891 + progif = 0x10; /* OHCI */
2892 + core = BCM47XX_USB_ID;
2893 + break;
2894 + case SB_USB11H:
2895 + class = PCI_CLASS_SERIAL;
2896 + subclass = PCI_SERIAL_USB;
2897 + progif = 0x10; /* OHCI */
2898 + core = BCM47XX_USBH_ID;
2899 + break;
2900 + case SB_USB11D:
2901 + class = PCI_CLASS_SERIAL;
2902 + subclass = PCI_SERIAL_USB;
2903 + core = BCM47XX_USBD_ID;
2904 + break;
2905 + case SB_IPSEC:
2906 + class = PCI_CLASS_CRYPT;
2907 + subclass = PCI_CRYPT_NETWORK;
2908 + core = BCM47XX_IPSEC_ID;
2909 + break;
2910 + case SB_ROBO:
2911 + class = PCI_CLASS_NET;
2912 + subclass = PCI_NET_OTHER;
2913 + core = BCM47XX_ROBO_ID;
2914 + break;
2915 + case SB_EXTIF:
2916 + case SB_CC:
2917 + class = PCI_CLASS_MEMORY;
2918 + subclass = PCI_MEMORY_FLASH;
2919 + break;
2920 + case SB_D11:
2921 + class = PCI_CLASS_NET;
2922 + subclass = PCI_NET_OTHER;
2923 + /* Let an nvram variable override this */
2924 + sprintf(varname, "wl%did", wlidx);
2925 + wlidx++;
2926 + if ((core = getintvar(NULL, varname)) == 0) {
2927 + if (chip == BCM4712_DEVICE_ID) {
2928 + if (chippkg == BCM4712SMALL_PKG_ID)
2929 + core = BCM4306_D11G_ID;
2930 + else
2931 + core = BCM4306_D11DUAL_ID;
2932 + } else {
2933 + /* 4310 */
2934 + core = BCM4310_D11B_ID;
2935 + }
2936 + }
2937 + break;
2938 +
2939 + default:
2940 + class = subclass = progif = 0xff;
2941 + break;
2942 + }
2943 +
2944 + /* Supported translations */
2945 + cfg->vendor = htol16(vendor);
2946 + cfg->device = htol16(core);
2947 + cfg->rev_id = chiprev;
2948 + cfg->prog_if = progif;
2949 + cfg->sub_class = subclass;
2950 + cfg->base_class = class;
2951 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2952 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
2953 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
2954 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
2955 + cfg->base[4] = 0;
2956 + cfg->base[5] = 0;
2957 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2958 + cfg->header_type = PCI_HEADER_BRIDGE;
2959 + else
2960 + cfg->header_type = PCI_HEADER_NORMAL;
2961 + /* Save core interrupt flag */
2962 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2963 + /* Default to MIPS shared interrupt 0 */
2964 + cfg->int_line = 0;
2965 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2966 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2967 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2968 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2969 + val = R_REG(&sb->sbipsflag);
2970 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
2971 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
2972 + break;
2973 + }
2974 + if (cfg->int_line > 4)
2975 + cfg->int_line = 0;
2976 + }
2977 + /* Emulated core */
2978 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
2979 + }
2980 +
2981 + sb_setcoreidx(sbh, coreidx);
2982 + return 0;
2983 +}
2984 +
2985 +int __init
2986 +sbpci_init(sb_t *sbh)
2987 +{
2988 + sbpci_init_pci(sbh);
2989 + sbpci_init_cores(sbh);
2990 + return 0;
2991 +}
2992 +
2993 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbutils.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbutils.c
2994 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
2995 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbutils.c 2006-06-18 15:29:23.000000000 +0200
2996 @@ -0,0 +1,2370 @@
2997 +/*
2998 + * Misc utility routines for accessing chip-specific features
2999 + * of the SiliconBackplane-based Broadcom chips.
3000 + *
3001 + * Copyright 2005, Broadcom Corporation
3002 + * All Rights Reserved.
3003 + *
3004 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3005 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3006 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3007 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3008 + * $Id$
3009 + */
3010 +
3011 +#include <typedefs.h>
3012 +#include <osl.h>
3013 +#include <sbutils.h>
3014 +#include <bcmutils.h>
3015 +#include <bcmdevs.h>
3016 +#include <sbconfig.h>
3017 +#include <sbchipc.h>
3018 +#include <sbpci.h>
3019 +#include <pcicfg.h>
3020 +#include <sbextif.h>
3021 +#include <bcmsrom.h>
3022 +
3023 +/* debug/trace */
3024 +#define SB_ERROR(args)
3025 +
3026 +
3027 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3028 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3029 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3030 +
3031 +/* misc sb info needed by some of the routines */
3032 +typedef struct sb_info {
3033 +
3034 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3035 +
3036 + void *osh; /* osl os handle */
3037 + void *sdh; /* bcmsdh handle */
3038 +
3039 + void *curmap; /* current regs va */
3040 + void *regs[SB_MAXCORES]; /* other regs va */
3041 +
3042 + uint curidx; /* current core index */
3043 + uint dev_coreid; /* the core provides driver functions */
3044 +
3045 + uint gpioidx; /* gpio control core index */
3046 + uint gpioid; /* gpio control coretype */
3047 +
3048 + uint numcores; /* # discovered cores */
3049 + uint coreid[SB_MAXCORES]; /* id of each core */
3050 +
3051 + void *intr_arg; /* interrupt callback function arg */
3052 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3053 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3054 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3055 +
3056 +} sb_info_t;
3057 +
3058 +/* local prototypes */
3059 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3060 + uint bustype, void *sdh, char **vars, int *varsz);
3061 +static void BCMINIT(sb_scan)(sb_info_t *si);
3062 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3063 +static uint _sb_coreidx(sb_info_t *si);
3064 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3065 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3066 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3067 +static int sb_pci_fixcfg(sb_info_t *si);
3068 +
3069 +/* delay needed between the mdio control/ mdiodata register data access */
3070 +#define PR28829_DELAY() OSL_DELAY(10)
3071 +
3072 +
3073 +/* global variable to indicate reservation/release of gpio's*/
3074 +static uint32 sb_gpioreservation = 0;
3075 +
3076 +#define SB_INFO(sbh) (sb_info_t*)sbh
3077 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3078 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3079 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3080 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3081 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3082 +#define BADIDX (SB_MAXCORES+1)
3083 +#define NOREV -1
3084 +
3085 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3086 +
3087 +/* sonicsrev */
3088 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3089 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3090 +
3091 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3092 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3093 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3094 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3095 +
3096 +/*
3097 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3098 + * after core switching to avoid invalid register accesss inside ISR.
3099 + */
3100 +#define INTR_OFF(si, intr_val) \
3101 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3102 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3103 +#define INTR_RESTORE(si, intr_val) \
3104 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3105 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3106 +
3107 +/* dynamic clock control defines */
3108 +#define LPOMINFREQ 25000 /* low power oscillator min */
3109 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3110 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3111 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3112 +#define PCIMINFREQ 25000000 /* 25 MHz */
3113 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3114 +
3115 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3116 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3117 +
3118 +#define MIN_DUMPBUFLEN 32 /* debug */
3119 +
3120 +/* GPIO Based LED powersave defines */
3121 +#define DEFAULT_GPIO_ONTIME 10
3122 +#define DEFAULT_GPIO_OFFTIME 90
3123 +
3124 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3125 +
3126 +static uint32
3127 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3128 +{
3129 + uint32 val = R_REG(sbr);
3130 +
3131 + return (val);
3132 +}
3133 +
3134 +static void
3135 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3136 +{
3137 + W_REG(sbr, v);
3138 +}
3139 +
3140 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3141 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3142 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3143 +
3144 +/* global kernel resource */
3145 +static sb_info_t ksi;
3146 +
3147 +/* generic kernel variant of sb_attach() */
3148 +sb_t *
3149 +BCMINITFN(sb_kattach)()
3150 +{
3151 + uint32 *regs;
3152 +
3153 + if (ksi.curmap == NULL) {
3154 + uint32 cid;
3155 +
3156 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3157 + cid = R_REG((uint32 *)regs);
3158 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3159 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3160 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3161 + uint32 *scc, val;
3162 +
3163 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3164 + val = R_REG(scc);
3165 + SB_ERROR((" initial scc = 0x%x\n", val));
3166 + val |= SCC_SS_XTAL;
3167 + W_REG(scc, val);
3168 + }
3169 +
3170 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3171 + SB_BUS, NULL, NULL, NULL) == NULL) {
3172 + return NULL;
3173 + }
3174 + }
3175 +
3176 + return (sb_t *)&ksi;
3177 +}
3178 +#endif
3179 +
3180 +static sb_info_t *
3181 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3182 + uint bustype, void *sdh, char **vars, int *varsz)
3183 +{
3184 + uint origidx;
3185 + chipcregs_t *cc;
3186 + sbconfig_t *sb;
3187 + uint32 w;
3188 +
3189 + ASSERT(GOODREGS(regs));
3190 +
3191 + bzero((uchar*)si, sizeof (sb_info_t));
3192 +
3193 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3194 +
3195 + si->osh = osh;
3196 + si->curmap = regs;
3197 + si->sdh = sdh;
3198 +
3199 + /* check to see if we are a sb core mimic'ing a pci core */
3200 + if (bustype == PCI_BUS) {
3201 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3202 + bustype = SB_BUS;
3203 + else
3204 + bustype = PCI_BUS;
3205 + }
3206 +
3207 + si->sb.bustype = bustype;
3208 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3209 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3210 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3211 + return NULL;
3212 + }
3213 +
3214 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3215 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3216 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3217 +
3218 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3219 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3220 + if (!GOODCOREADDR(w))
3221 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3222 + }
3223 +
3224 + /* initialize current core index value */
3225 + si->curidx = _sb_coreidx(si);
3226 +
3227 + if (si->curidx == BADIDX) {
3228 + SB_ERROR(("sb_doattach: bad core index\n"));
3229 + return NULL;
3230 + }
3231 +
3232 + /* get sonics backplane revision */
3233 + sb = REGS2SB(si->curmap);
3234 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3235 +
3236 + /* keep and reuse the initial register mapping */
3237 + origidx = si->curidx;
3238 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3239 + si->regs[origidx] = regs;
3240 +
3241 + /* is core-0 a chipcommon core? */
3242 + si->numcores = 1;
3243 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3244 + if (sb_coreid(&si->sb) != SB_CC)
3245 + cc = NULL;
3246 +
3247 + /* determine chip id and rev */
3248 + if (cc) {
3249 + /* chip common core found! */
3250 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3251 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3252 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3253 + } else {
3254 + /* no chip common core -- must convert device id to chip id */
3255 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3256 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3257 + sb_setcoreidx(&si->sb, origidx);
3258 + return NULL;
3259 + }
3260 + }
3261 +
3262 + /* get chipcommon rev */
3263 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3264 +
3265 + /* determine numcores */
3266 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3267 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3268 + else
3269 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3270 +
3271 + /* return to original core */
3272 + sb_setcoreidx(&si->sb, origidx);
3273 +
3274 + /* sanity checks */
3275 + ASSERT(si->sb.chip);
3276 +
3277 + /* scan for cores */
3278 + BCMINIT(sb_scan)(si);
3279 +
3280 + /* fixup necessary chip/core configurations */
3281 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3282 + if (sb_pci_fixcfg(si)) {
3283 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3284 + return NULL;
3285 + }
3286 + }
3287 +
3288 + /* srom_var_init() depends on sb_scan() info */
3289 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3290 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3291 + return (NULL);
3292 + }
3293 +
3294 + if (cc == NULL) {
3295 + /*
3296 + * The chip revision number is hardwired into all
3297 + * of the pci function config rev fields and is
3298 + * independent from the individual core revision numbers.
3299 + * For example, the "A0" silicon of each chip is chip rev 0.
3300 + */
3301 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3302 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3303 + si->sb.chiprev = w & 0xff;
3304 + } else
3305 + si->sb.chiprev = 0;
3306 + }
3307 +
3308 + /* gpio control core is required */
3309 + if (!GOODIDX(si->gpioidx)) {
3310 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3311 + return NULL;
3312 + }
3313 +
3314 + /* get boardtype and boardrev */
3315 + switch (BUSTYPE(si->sb.bustype)) {
3316 + case PCI_BUS:
3317 + /* do a pci config read to get subsystem id and subvendor id */
3318 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3319 + si->sb.boardvendor = w & 0xffff;
3320 + si->sb.boardtype = (w >> 16) & 0xffff;
3321 + break;
3322 +
3323 + case SB_BUS:
3324 + case JTAG_BUS:
3325 + si->sb.boardvendor = VENDOR_BROADCOM;
3326 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3327 + si->sb.boardtype = 0xffff;
3328 + break;
3329 + }
3330 +
3331 + if (si->sb.boardtype == 0) {
3332 + SB_ERROR(("sb_doattach: unknown board type\n"));
3333 + ASSERT(si->sb.boardtype);
3334 + }
3335 +
3336 + /* setup the GPIO based LED powersave register */
3337 + if (si->sb.ccrev >= 16) {
3338 + w = getintvar(*vars, "gpiotimerval");
3339 + if (!w)
3340 + w = DEFAULT_GPIOTIMERVAL;
3341 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3342 + }
3343 +
3344 +
3345 + return (si);
3346 +}
3347 +
3348 +uint
3349 +sb_coreid(sb_t *sbh)
3350 +{
3351 + sb_info_t *si;
3352 + sbconfig_t *sb;
3353 +
3354 + si = SB_INFO(sbh);
3355 + sb = REGS2SB(si->curmap);
3356 +
3357 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3358 +}
3359 +
3360 +uint
3361 +sb_coreidx(sb_t *sbh)
3362 +{
3363 + sb_info_t *si;
3364 +
3365 + si = SB_INFO(sbh);
3366 + return (si->curidx);
3367 +}
3368 +
3369 +/* return current index of core */
3370 +static uint
3371 +_sb_coreidx(sb_info_t *si)
3372 +{
3373 + sbconfig_t *sb;
3374 + uint32 sbaddr = 0;
3375 +
3376 + ASSERT(si);
3377 +
3378 + switch (BUSTYPE(si->sb.bustype)) {
3379 + case SB_BUS:
3380 + sb = REGS2SB(si->curmap);
3381 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3382 + break;
3383 +
3384 + case PCI_BUS:
3385 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3386 + break;
3387 +
3388 +#ifdef BCMJTAG
3389 + case JTAG_BUS:
3390 + sbaddr = (uint32)si->curmap;
3391 + break;
3392 +#endif /* BCMJTAG */
3393 +
3394 + default:
3395 + ASSERT(0);
3396 + }
3397 +
3398 + if (!GOODCOREADDR(sbaddr))
3399 + return BADIDX;
3400 +
3401 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3402 +}
3403 +
3404 +uint
3405 +sb_corevendor(sb_t *sbh)
3406 +{
3407 + sb_info_t *si;
3408 + sbconfig_t *sb;
3409 +
3410 + si = SB_INFO(sbh);
3411 + sb = REGS2SB(si->curmap);
3412 +
3413 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3414 +}
3415 +
3416 +uint
3417 +sb_corerev(sb_t *sbh)
3418 +{
3419 + sb_info_t *si;
3420 + sbconfig_t *sb;
3421 + uint sbidh;
3422 +
3423 + si = SB_INFO(sbh);
3424 + sb = REGS2SB(si->curmap);
3425 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3426 +
3427 + return (SBCOREREV(sbidh));
3428 +}
3429 +
3430 +void *
3431 +sb_osh(sb_t *sbh)
3432 +{
3433 + sb_info_t *si;
3434 +
3435 + si = SB_INFO(sbh);
3436 + return si->osh;
3437 +}
3438 +
3439 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3440 +
3441 +/* set/clear sbtmstatelow core-specific flags */
3442 +uint32
3443 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3444 +{
3445 + sb_info_t *si;
3446 + sbconfig_t *sb;
3447 + uint32 w;
3448 +
3449 + si = SB_INFO(sbh);
3450 + sb = REGS2SB(si->curmap);
3451 +
3452 + ASSERT((val & ~mask) == 0);
3453 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3454 +
3455 + /* mask and set */
3456 + if (mask || val) {
3457 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3458 + W_SBREG(si, &sb->sbtmstatelow, w);
3459 + }
3460 +
3461 + /* return the new value */
3462 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3463 +}
3464 +
3465 +/* set/clear sbtmstatehigh core-specific flags */
3466 +uint32
3467 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3468 +{
3469 + sb_info_t *si;
3470 + sbconfig_t *sb;
3471 + uint32 w;
3472 +
3473 + si = SB_INFO(sbh);
3474 + sb = REGS2SB(si->curmap);
3475 +
3476 + ASSERT((val & ~mask) == 0);
3477 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3478 +
3479 + /* mask and set */
3480 + if (mask || val) {
3481 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3482 + W_SBREG(si, &sb->sbtmstatehigh, w);
3483 + }
3484 +
3485 + /* return the new value */
3486 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3487 +}
3488 +
3489 +/* caller needs to take care of core-specific bist hazards */
3490 +int
3491 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3492 +{
3493 + uint32 sblo;
3494 + uint coreidx;
3495 + sb_info_t *si;
3496 + int result = 0;
3497 +
3498 + si = SB_INFO(sbh);
3499 +
3500 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3501 + if (!GOODIDX(coreidx))
3502 + result = BCME_ERROR;
3503 + else {
3504 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3505 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3506 +
3507 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3508 +
3509 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3510 + result = BCME_ERROR;
3511 +
3512 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3513 + }
3514 +
3515 + return result;
3516 +}
3517 +
3518 +bool
3519 +sb_iscoreup(sb_t *sbh)
3520 +{
3521 + sb_info_t *si;
3522 + sbconfig_t *sb;
3523 +
3524 + si = SB_INFO(sbh);
3525 + sb = REGS2SB(si->curmap);
3526 +
3527 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3528 +}
3529 +
3530 +/*
3531 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3532 + * switch back to the original core, and return the new value.
3533 + */
3534 +static uint
3535 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3536 +{
3537 + uint origidx;
3538 + uint32 *r;
3539 + uint w;
3540 + uint intr_val = 0;
3541 +
3542 + ASSERT(GOODIDX(coreidx));
3543 + ASSERT(regoff < SB_CORE_SIZE);
3544 + ASSERT((val & ~mask) == 0);
3545 +
3546 + INTR_OFF(si, intr_val);
3547 +
3548 + /* save current core index */
3549 + origidx = sb_coreidx(&si->sb);
3550 +
3551 + /* switch core */
3552 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3553 +
3554 + /* mask and set */
3555 + if (mask || val) {
3556 + if (regoff >= SBCONFIGOFF) {
3557 + w = (R_SBREG(si, r) & ~mask) | val;
3558 + W_SBREG(si, r, w);
3559 + } else {
3560 + w = (R_REG(r) & ~mask) | val;
3561 + W_REG(r, w);
3562 + }
3563 + }
3564 +
3565 + /* readback */
3566 + if (regoff >= SBCONFIGOFF)
3567 + w = R_SBREG(si, r);
3568 + else
3569 + w = R_REG(r);
3570 +
3571 + /* restore core index */
3572 + if (origidx != coreidx)
3573 + sb_setcoreidx(&si->sb, origidx);
3574 +
3575 + INTR_RESTORE(si, intr_val);
3576 + return (w);
3577 +}
3578 +
3579 +#define DWORD_ALIGN(x) (x & ~(0x03))
3580 +#define BYTE_POS(x) (x & 0x3)
3581 +#define WORD_POS(x) (x & 0x1)
3582 +
3583 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3584 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3585 +
3586 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3587 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3588 +
3589 +#define read_pci_cfg_byte(a) \
3590 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3591 +
3592 +#define read_pci_cfg_write(a) \
3593 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3594 +
3595 +
3596 +/* scan the sb enumerated space to identify all cores */
3597 +static void
3598 +BCMINITFN(sb_scan)(sb_info_t *si)
3599 +{
3600 + uint origidx;
3601 + uint i;
3602 + bool pci;
3603 + uint pciidx;
3604 + uint pcirev;
3605 +
3606 +
3607 +
3608 + /* numcores should already be set */
3609 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3610 +
3611 + /* save current core index */
3612 + origidx = sb_coreidx(&si->sb);
3613 +
3614 + si->sb.buscorerev = NOREV;
3615 + si->sb.buscoreidx = BADIDX;
3616 +
3617 + si->gpioidx = BADIDX;
3618 +
3619 + pci = FALSE;
3620 + pcirev = NOREV;
3621 + pciidx = BADIDX;
3622 +
3623 + for (i = 0; i < si->numcores; i++) {
3624 + sb_setcoreidx(&si->sb, i);
3625 + si->coreid[i] = sb_coreid(&si->sb);
3626 +
3627 + if (si->coreid[i] == SB_PCI) {
3628 + pciidx = i;
3629 + pcirev = sb_corerev(&si->sb);
3630 + pci = TRUE;
3631 + }
3632 + }
3633 + if (pci) {
3634 + si->sb.buscoretype = SB_PCI;
3635 + si->sb.buscorerev = pcirev;
3636 + si->sb.buscoreidx = pciidx;
3637 + }
3638 +
3639 + /*
3640 + * Find the gpio "controlling core" type and index.
3641 + * Precedence:
3642 + * - if there's a chip common core - use that
3643 + * - else if there's a pci core (rev >= 2) - use that
3644 + * - else there had better be an extif core (4710 only)
3645 + */
3646 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3647 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3648 + si->gpioid = SB_CC;
3649 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3650 + si->gpioidx = si->sb.buscoreidx;
3651 + si->gpioid = SB_PCI;
3652 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3653 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3654 + si->gpioid = SB_EXTIF;
3655 + } else
3656 + ASSERT(si->gpioidx != BADIDX);
3657 +
3658 + /* return to original core index */
3659 + sb_setcoreidx(&si->sb, origidx);
3660 +}
3661 +
3662 +/* may be called with core in reset */
3663 +void
3664 +sb_detach(sb_t *sbh)
3665 +{
3666 + sb_info_t *si;
3667 + uint idx;
3668 +
3669 + si = SB_INFO(sbh);
3670 +
3671 + if (si == NULL)
3672 + return;
3673 +
3674 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3675 + for (idx = 0; idx < SB_MAXCORES; idx++)
3676 + if (si->regs[idx]) {
3677 + REG_UNMAP(si->regs[idx]);
3678 + si->regs[idx] = NULL;
3679 + }
3680 +
3681 + if (si != &ksi)
3682 + MFREE(si->osh, si, sizeof (sb_info_t));
3683 +}
3684 +
3685 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3686 +static uint
3687 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3688 +{
3689 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3690 + return (BCM4710_DEVICE_ID);
3691 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3692 + return (BCM4402_DEVICE_ID);
3693 + if (pcidev == BCM4401_ENET_ID)
3694 + return (BCM4402_DEVICE_ID);
3695 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3696 + return (BCM4307_DEVICE_ID);
3697 + if (pcidev == BCM4301_DEVICE_ID)
3698 + return (BCM4301_DEVICE_ID);
3699 +
3700 + return (0);
3701 +}
3702 +
3703 +/* convert chip number to number of i/o cores */
3704 +static uint
3705 +BCMINITFN(sb_chip2numcores)(uint chip)
3706 +{
3707 + if (chip == BCM4710_DEVICE_ID)
3708 + return (9);
3709 + if (chip == BCM4402_DEVICE_ID)
3710 + return (3);
3711 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3712 + return (5);
3713 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3714 + return (6);
3715 + if (chip == BCM4704_DEVICE_ID)
3716 + return (9);
3717 + if (chip == BCM5365_DEVICE_ID)
3718 + return (7);
3719 +
3720 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3721 + ASSERT(0);
3722 + return (1);
3723 +}
3724 +
3725 +/* return index of coreid or BADIDX if not found */
3726 +static uint
3727 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3728 +{
3729 + uint found;
3730 + uint i;
3731 +
3732 + found = 0;
3733 +
3734 + for (i = 0; i < si->numcores; i++)
3735 + if (si->coreid[i] == coreid) {
3736 + if (found == coreunit)
3737 + return (i);
3738 + found++;
3739 + }
3740 +
3741 + return (BADIDX);
3742 +}
3743 +
3744 +/*
3745 + * this function changes logical "focus" to the indiciated core,
3746 + * must be called with interrupt off.
3747 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3748 + */
3749 +void*
3750 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3751 +{
3752 + sb_info_t *si;
3753 + uint32 sbaddr;
3754 +
3755 + si = SB_INFO(sbh);
3756 +
3757 + if (coreidx >= si->numcores)
3758 + return (NULL);
3759 +
3760 + /*
3761 + * If the user has provided an interrupt mask enabled function,
3762 + * then assert interrupts are disabled before switching the core.
3763 + */
3764 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3765 +
3766 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3767 +
3768 + switch (BUSTYPE(si->sb.bustype)) {
3769 + case SB_BUS:
3770 + /* map new one */
3771 + if (!si->regs[coreidx]) {
3772 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3773 + ASSERT(GOODREGS(si->regs[coreidx]));
3774 + }
3775 + si->curmap = si->regs[coreidx];
3776 + break;
3777 +
3778 + case PCI_BUS:
3779 + /* point bar0 window */
3780 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3781 + break;
3782 +
3783 +#ifdef BCMJTAG
3784 + case JTAG_BUS:
3785 + /* map new one */
3786 + if (!si->regs[coreidx]) {
3787 + si->regs[coreidx] = (void *)sbaddr;
3788 + ASSERT(GOODREGS(si->regs[coreidx]));
3789 + }
3790 + si->curmap = si->regs[coreidx];
3791 + break;
3792 +#endif /* BCMJTAG */
3793 + }
3794 +
3795 + si->curidx = coreidx;
3796 +
3797 + return (si->curmap);
3798 +}
3799 +
3800 +/*
3801 + * this function changes logical "focus" to the indiciated core,
3802 + * must be called with interrupt off.
3803 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3804 + */
3805 +void*
3806 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3807 +{
3808 + sb_info_t *si;
3809 + uint idx;
3810 +
3811 + si = SB_INFO(sbh);
3812 + idx = sb_findcoreidx(si, coreid, coreunit);
3813 + if (!GOODIDX(idx))
3814 + return (NULL);
3815 +
3816 + return (sb_setcoreidx(sbh, idx));
3817 +}
3818 +
3819 +/* return chip number */
3820 +uint
3821 +BCMINITFN(sb_chip)(sb_t *sbh)
3822 +{
3823 + sb_info_t *si;
3824 +
3825 + si = SB_INFO(sbh);
3826 + return (si->sb.chip);
3827 +}
3828 +
3829 +/* return chip revision number */
3830 +uint
3831 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3832 +{
3833 + sb_info_t *si;
3834 +
3835 + si = SB_INFO(sbh);
3836 + return (si->sb.chiprev);
3837 +}
3838 +
3839 +/* return chip common revision number */
3840 +uint
3841 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3842 +{
3843 + sb_info_t *si;
3844 +
3845 + si = SB_INFO(sbh);
3846 + return (si->sb.ccrev);
3847 +}
3848 +
3849 +/* return chip package option */
3850 +uint
3851 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3852 +{
3853 + sb_info_t *si;
3854 +
3855 + si = SB_INFO(sbh);
3856 + return (si->sb.chippkg);
3857 +}
3858 +
3859 +/* return PCI core rev. */
3860 +uint
3861 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3862 +{
3863 + sb_info_t *si;
3864 +
3865 + si = SB_INFO(sbh);
3866 + return (si->sb.buscorerev);
3867 +}
3868 +
3869 +bool
3870 +BCMINITFN(sb_war16165)(sb_t *sbh)
3871 +{
3872 + sb_info_t *si;
3873 +
3874 + si = SB_INFO(sbh);
3875 +
3876 + return (PCI(si) && (si->sb.buscorerev <= 10));
3877 +}
3878 +
3879 +/* return board vendor id */
3880 +uint
3881 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3882 +{
3883 + sb_info_t *si;
3884 +
3885 + si = SB_INFO(sbh);
3886 + return (si->sb.boardvendor);
3887 +}
3888 +
3889 +/* return boardtype */
3890 +uint
3891 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3892 +{
3893 + sb_info_t *si;
3894 + char *var;
3895 +
3896 + si = SB_INFO(sbh);
3897 +
3898 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3899 + /* boardtype format is a hex string */
3900 + si->sb.boardtype = getintvar(NULL, "boardtype");
3901 +
3902 + /* backward compatibility for older boardtype string format */
3903 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3904 + if (!strcmp(var, "bcm94710dev"))
3905 + si->sb.boardtype = BCM94710D_BOARD;
3906 + else if (!strcmp(var, "bcm94710ap"))
3907 + si->sb.boardtype = BCM94710AP_BOARD;
3908 + else if (!strcmp(var, "bu4710"))
3909 + si->sb.boardtype = BU4710_BOARD;
3910 + else if (!strcmp(var, "bcm94702mn"))
3911 + si->sb.boardtype = BCM94702MN_BOARD;
3912 + else if (!strcmp(var, "bcm94710r1"))
3913 + si->sb.boardtype = BCM94710R1_BOARD;
3914 + else if (!strcmp(var, "bcm94710r4"))
3915 + si->sb.boardtype = BCM94710R4_BOARD;
3916 + else if (!strcmp(var, "bcm94702cpci"))
3917 + si->sb.boardtype = BCM94702CPCI_BOARD;
3918 + else if (!strcmp(var, "bcm95380_rr"))
3919 + si->sb.boardtype = BCM95380RR_BOARD;
3920 + }
3921 + }
3922 +
3923 + return (si->sb.boardtype);
3924 +}
3925 +
3926 +/* return bus type of sbh device */
3927 +uint
3928 +sb_bus(sb_t *sbh)
3929 +{
3930 + sb_info_t *si;
3931 +
3932 + si = SB_INFO(sbh);
3933 + return (si->sb.bustype);
3934 +}
3935 +
3936 +/* return bus core type */
3937 +uint
3938 +sb_buscoretype(sb_t *sbh)
3939 +{
3940 + sb_info_t *si;
3941 +
3942 + si = SB_INFO(sbh);
3943 +
3944 + return (si->sb.buscoretype);
3945 +}
3946 +
3947 +/* return bus core revision */
3948 +uint
3949 +sb_buscorerev(sb_t *sbh)
3950 +{
3951 + sb_info_t *si;
3952 + si = SB_INFO(sbh);
3953 +
3954 + return (si->sb.buscorerev);
3955 +}
3956 +
3957 +/* return list of found cores */
3958 +uint
3959 +sb_corelist(sb_t *sbh, uint coreid[])
3960 +{
3961 + sb_info_t *si;
3962 +
3963 + si = SB_INFO(sbh);
3964 +
3965 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
3966 + return (si->numcores);
3967 +}
3968 +
3969 +/* return current register mapping */
3970 +void *
3971 +sb_coreregs(sb_t *sbh)
3972 +{
3973 + sb_info_t *si;
3974 +
3975 + si = SB_INFO(sbh);
3976 + ASSERT(GOODREGS(si->curmap));
3977 +
3978 + return (si->curmap);
3979 +}
3980 +
3981 +
3982 +/* do buffered registers update */
3983 +void
3984 +sb_commit(sb_t *sbh)
3985 +{
3986 + sb_info_t *si;
3987 + uint origidx;
3988 + uint intr_val = 0;
3989 +
3990 + si = SB_INFO(sbh);
3991 +
3992 + origidx = si->curidx;
3993 + ASSERT(GOODIDX(origidx));
3994 +
3995 + INTR_OFF(si, intr_val);
3996 +
3997 + /* switch over to chipcommon core if there is one, else use pci */
3998 + if (si->sb.ccrev != NOREV) {
3999 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4000 +
4001 + /* do the buffer registers update */
4002 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4003 + W_REG(&ccregs->broadcastdata, 0x0);
4004 + } else if (PCI(si)) {
4005 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4006 +
4007 + /* do the buffer registers update */
4008 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4009 + W_REG(&pciregs->bcastdata, 0x0);
4010 + } else
4011 + ASSERT(0);
4012 +
4013 + /* restore core index */
4014 + sb_setcoreidx(sbh, origidx);
4015 + INTR_RESTORE(si, intr_val);
4016 +}
4017 +
4018 +/* reset and re-enable a core */
4019 +void
4020 +sb_core_reset(sb_t *sbh, uint32 bits)
4021 +{
4022 + sb_info_t *si;
4023 + sbconfig_t *sb;
4024 + volatile uint32 dummy;
4025 +
4026 + si = SB_INFO(sbh);
4027 + ASSERT(GOODREGS(si->curmap));
4028 + sb = REGS2SB(si->curmap);
4029 +
4030 + /*
4031 + * Must do the disable sequence first to work for arbitrary current core state.
4032 + */
4033 + sb_core_disable(sbh, bits);
4034 +
4035 + /*
4036 + * Now do the initialization sequence.
4037 + */
4038 +
4039 + /* set reset while enabling the clock and forcing them on throughout the core */
4040 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4041 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4042 + OSL_DELAY(1);
4043 +
4044 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4045 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4046 + }
4047 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4048 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4049 + }
4050 +
4051 + /* clear reset and allow it to propagate throughout the core */
4052 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4053 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4054 + OSL_DELAY(1);
4055 +
4056 + /* leave clock enabled */
4057 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4058 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4059 + OSL_DELAY(1);
4060 +}
4061 +
4062 +void
4063 +sb_core_tofixup(sb_t *sbh)
4064 +{
4065 + sb_info_t *si;
4066 + sbconfig_t *sb;
4067 +
4068 + si = SB_INFO(sbh);
4069 +
4070 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4071 + return;
4072 +
4073 + ASSERT(GOODREGS(si->curmap));
4074 + sb = REGS2SB(si->curmap);
4075 +
4076 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4077 + SET_SBREG(si, &sb->sbimconfiglow,
4078 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4079 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4080 + } else {
4081 + if (sb_coreid(sbh) == SB_PCI) {
4082 + SET_SBREG(si, &sb->sbimconfiglow,
4083 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4084 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4085 + } else {
4086 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4087 + }
4088 + }
4089 +
4090 + sb_commit(sbh);
4091 +}
4092 +
4093 +/*
4094 + * Set the initiator timeout for the "master core".
4095 + * The master core is defined to be the core in control
4096 + * of the chip and so it issues accesses to non-memory
4097 + * locations (Because of dma *any* core can access memeory).
4098 + *
4099 + * The routine uses the bus to decide who is the master:
4100 + * SB_BUS => mips
4101 + * JTAG_BUS => chipc
4102 + * PCI_BUS => pci
4103 + *
4104 + * This routine exists so callers can disable initiator
4105 + * timeouts so accesses to very slow devices like otp
4106 + * won't cause an abort. The routine allows arbitrary
4107 + * settings of the service and request timeouts, though.
4108 + *
4109 + * Returns the timeout state before changing it or -1
4110 + * on error.
4111 + */
4112 +
4113 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4114 +
4115 +uint32
4116 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4117 +{
4118 + sb_info_t *si;
4119 + uint origidx, idx;
4120 + uint intr_val = 0;
4121 + uint32 tmp, ret = 0xffffffff;
4122 + sbconfig_t *sb;
4123 +
4124 + si = SB_INFO(sbh);
4125 +
4126 + if ((to & ~TO_MASK) != 0)
4127 + return ret;
4128 +
4129 + /* Figure out the master core */
4130 + idx = BADIDX;
4131 + switch (BUSTYPE(si->sb.bustype)) {
4132 + case PCI_BUS:
4133 + idx = si->sb.buscoreidx;
4134 + break;
4135 + case JTAG_BUS:
4136 + idx = SB_CC_IDX;
4137 + break;
4138 + case SB_BUS:
4139 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4140 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4141 + break;
4142 + default:
4143 + ASSERT(0);
4144 + }
4145 + if (idx == BADIDX)
4146 + return ret;
4147 +
4148 + INTR_OFF(si, intr_val);
4149 + origidx = sb_coreidx(sbh);
4150 +
4151 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4152 +
4153 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4154 + ret = tmp & TO_MASK;
4155 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4156 +
4157 + sb_commit(sbh);
4158 + sb_setcoreidx(sbh, origidx);
4159 + INTR_RESTORE(si, intr_val);
4160 + return ret;
4161 +}
4162 +
4163 +void
4164 +sb_core_disable(sb_t *sbh, uint32 bits)
4165 +{
4166 + sb_info_t *si;
4167 + volatile uint32 dummy;
4168 + uint32 rej;
4169 + sbconfig_t *sb;
4170 +
4171 + si = SB_INFO(sbh);
4172 +
4173 + ASSERT(GOODREGS(si->curmap));
4174 + sb = REGS2SB(si->curmap);
4175 +
4176 + /* if core is already in reset, just return */
4177 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4178 + return;
4179 +
4180 + /* reject value changed between sonics 2.2 and 2.3 */
4181 + if (si->sb.sonicsrev == SONICS_2_2)
4182 + rej = (1 << SBTML_REJ_SHIFT);
4183 + else
4184 + rej = (2 << SBTML_REJ_SHIFT);
4185 +
4186 + /* if clocks are not enabled, put into reset and return */
4187 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4188 + goto disable;
4189 +
4190 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4191 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4192 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4193 + OSL_DELAY(1);
4194 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4195 +
4196 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4197 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4198 + dummy = R_SBREG(si, &sb->sbimstate);
4199 + OSL_DELAY(1);
4200 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4201 + }
4202 +
4203 + /* set reset and reject while enabling the clocks */
4204 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4205 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4206 + OSL_DELAY(10);
4207 +
4208 + /* don't forget to clear the initiator reject bit */
4209 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4210 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4211 +
4212 +disable:
4213 + /* leave reset and reject asserted */
4214 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4215 + OSL_DELAY(1);
4216 +}
4217 +
4218 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4219 +void
4220 +sb_watchdog(sb_t *sbh, uint ticks)
4221 +{
4222 + sb_info_t *si = SB_INFO(sbh);
4223 +
4224 + /* instant NMI */
4225 + switch (si->gpioid) {
4226 + case SB_CC:
4227 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4228 + break;
4229 + case SB_EXTIF:
4230 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4231 + break;
4232 + }
4233 +}
4234 +
4235 +
4236 +/*
4237 + * Configure the pci core for pci client (NIC) action
4238 + * coremask is the bitvec of cores by index to be enabled.
4239 + */
4240 +void
4241 +sb_pci_setup(sb_t *sbh, uint coremask)
4242 +{
4243 + sb_info_t *si;
4244 + sbconfig_t *sb;
4245 + sbpciregs_t *pciregs;
4246 + uint32 sbflag;
4247 + uint32 w;
4248 + uint idx;
4249 +
4250 + si = SB_INFO(sbh);
4251 +
4252 + /* if not pci bus, we're done */
4253 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4254 + return;
4255 +
4256 + ASSERT(PCI(si));
4257 + ASSERT(si->sb.buscoreidx != BADIDX);
4258 +
4259 + /* get current core index */
4260 + idx = si->curidx;
4261 +
4262 + /* we interrupt on this backplane flag number */
4263 + ASSERT(GOODREGS(si->curmap));
4264 + sb = REGS2SB(si->curmap);
4265 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4266 +
4267 + /* switch over to pci core */
4268 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4269 + sb = REGS2SB(pciregs);
4270 +
4271 + /*
4272 + * Enable sb->pci interrupts. Assume
4273 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4274 + */
4275 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4276 + /* pci config write to set this core bit in PCIIntMask */
4277 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4278 + w |= (coremask << PCI_SBIM_SHIFT);
4279 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4280 + } else {
4281 + /* set sbintvec bit for our flag number */
4282 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4283 + }
4284 +
4285 + if (PCI(si)) {
4286 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4287 + if (si->sb.buscorerev >= 11)
4288 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4289 + if (si->sb.buscorerev < 5) {
4290 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4291 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4292 + sb_commit(sbh);
4293 + }
4294 + }
4295 +
4296 + /* switch back to previous core */
4297 + sb_setcoreidx(sbh, idx);
4298 +}
4299 +
4300 +uint32
4301 +sb_base(uint32 admatch)
4302 +{
4303 + uint32 base;
4304 + uint type;
4305 +
4306 + type = admatch & SBAM_TYPE_MASK;
4307 + ASSERT(type < 3);
4308 +
4309 + base = 0;
4310 +
4311 + if (type == 0) {
4312 + base = admatch & SBAM_BASE0_MASK;
4313 + } else if (type == 1) {
4314 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4315 + base = admatch & SBAM_BASE1_MASK;
4316 + } else if (type == 2) {
4317 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4318 + base = admatch & SBAM_BASE2_MASK;
4319 + }
4320 +
4321 + return (base);
4322 +}
4323 +
4324 +uint32
4325 +sb_size(uint32 admatch)
4326 +{
4327 + uint32 size;
4328 + uint type;
4329 +
4330 + type = admatch & SBAM_TYPE_MASK;
4331 + ASSERT(type < 3);
4332 +
4333 + size = 0;
4334 +
4335 + if (type == 0) {
4336 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4337 + } else if (type == 1) {
4338 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4339 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4340 + } else if (type == 2) {
4341 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4342 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4343 + }
4344 +
4345 + return (size);
4346 +}
4347 +
4348 +/* return the core-type instantiation # of the current core */
4349 +uint
4350 +sb_coreunit(sb_t *sbh)
4351 +{
4352 + sb_info_t *si;
4353 + uint idx;
4354 + uint coreid;
4355 + uint coreunit;
4356 + uint i;
4357 +
4358 + si = SB_INFO(sbh);
4359 + coreunit = 0;
4360 +
4361 + idx = si->curidx;
4362 +
4363 + ASSERT(GOODREGS(si->curmap));
4364 + coreid = sb_coreid(sbh);
4365 +
4366 + /* count the cores of our type */
4367 + for (i = 0; i < idx; i++)
4368 + if (si->coreid[i] == coreid)
4369 + coreunit++;
4370 +
4371 + return (coreunit);
4372 +}
4373 +
4374 +static INLINE uint32
4375 +factor6(uint32 x)
4376 +{
4377 + switch (x) {
4378 + case CC_F6_2: return 2;
4379 + case CC_F6_3: return 3;
4380 + case CC_F6_4: return 4;
4381 + case CC_F6_5: return 5;
4382 + case CC_F6_6: return 6;
4383 + case CC_F6_7: return 7;
4384 + default: return 0;
4385 + }
4386 +}
4387 +
4388 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4389 +uint32
4390 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4391 +{
4392 + uint32 n1, n2, clock, m1, m2, m3, mc;
4393 +
4394 + n1 = n & CN_N1_MASK;
4395 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4396 +
4397 + if (pll_type == PLL_TYPE6) {
4398 + if (m & CC_T6_MMASK)
4399 + return CC_T6_M1;
4400 + else
4401 + return CC_T6_M0;
4402 + } else if ((pll_type == PLL_TYPE1) ||
4403 + (pll_type == PLL_TYPE3) ||
4404 + (pll_type == PLL_TYPE4) ||
4405 + (pll_type == PLL_TYPE7)) {
4406 + n1 = factor6(n1);
4407 + n2 += CC_F5_BIAS;
4408 + } else if (pll_type == PLL_TYPE2) {
4409 + n1 += CC_T2_BIAS;
4410 + n2 += CC_T2_BIAS;
4411 + ASSERT((n1 >= 2) && (n1 <= 7));
4412 + ASSERT((n2 >= 5) && (n2 <= 23));
4413 + } else if (pll_type == PLL_TYPE5) {
4414 + return (100000000);
4415 + } else
4416 + ASSERT(0);
4417 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4418 + if ((pll_type == PLL_TYPE3) ||
4419 + (pll_type == PLL_TYPE7)) {
4420 + clock = CC_CLOCK_BASE2 * n1 * n2;
4421 + }
4422 + else
4423 + clock = CC_CLOCK_BASE1 * n1 * n2;
4424 +
4425 + if (clock == 0)
4426 + return 0;
4427 +
4428 + m1 = m & CC_M1_MASK;
4429 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4430 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4431 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4432 +
4433 + if ((pll_type == PLL_TYPE1) ||
4434 + (pll_type == PLL_TYPE3) ||
4435 + (pll_type == PLL_TYPE4) ||
4436 + (pll_type == PLL_TYPE7)) {
4437 + m1 = factor6(m1);
4438 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4439 + m2 += CC_F5_BIAS;
4440 + else
4441 + m2 = factor6(m2);
4442 + m3 = factor6(m3);
4443 +
4444 + switch (mc) {
4445 + case CC_MC_BYPASS: return (clock);
4446 + case CC_MC_M1: return (clock / m1);
4447 + case CC_MC_M1M2: return (clock / (m1 * m2));
4448 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4449 + case CC_MC_M1M3: return (clock / (m1 * m3));
4450 + default: return (0);
4451 + }
4452 + } else {
4453 + ASSERT(pll_type == PLL_TYPE2);
4454 +
4455 + m1 += CC_T2_BIAS;
4456 + m2 += CC_T2M2_BIAS;
4457 + m3 += CC_T2_BIAS;
4458 + ASSERT((m1 >= 2) && (m1 <= 7));
4459 + ASSERT((m2 >= 3) && (m2 <= 10));
4460 + ASSERT((m3 >= 2) && (m3 <= 7));
4461 +
4462 + if ((mc & CC_T2MC_M1BYP) == 0)
4463 + clock /= m1;
4464 + if ((mc & CC_T2MC_M2BYP) == 0)
4465 + clock /= m2;
4466 + if ((mc & CC_T2MC_M3BYP) == 0)
4467 + clock /= m3;
4468 +
4469 + return(clock);
4470 + }
4471 +}
4472 +
4473 +/* returns the current speed the SB is running at */
4474 +uint32
4475 +sb_clock(sb_t *sbh)
4476 +{
4477 + sb_info_t *si;
4478 + extifregs_t *eir;
4479 + chipcregs_t *cc;
4480 + uint32 n, m;
4481 + uint idx;
4482 + uint32 pll_type, rate;
4483 + uint intr_val = 0;
4484 +
4485 + si = SB_INFO(sbh);
4486 + idx = si->curidx;
4487 + pll_type = PLL_TYPE1;
4488 +
4489 + INTR_OFF(si, intr_val);
4490 +
4491 + /* switch to extif or chipc core */
4492 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4493 + n = R_REG(&eir->clockcontrol_n);
4494 + m = R_REG(&eir->clockcontrol_sb);
4495 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4496 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4497 + n = R_REG(&cc->clockcontrol_n);
4498 + if (pll_type == PLL_TYPE6)
4499 + m = R_REG(&cc->clockcontrol_mips);
4500 + else if (pll_type == PLL_TYPE3)
4501 + {
4502 + // Added by Chen-I for 5365
4503 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4504 + m = R_REG(&cc->clockcontrol_sb);
4505 + else
4506 + m = R_REG(&cc->clockcontrol_m2);
4507 + }
4508 + else
4509 + m = R_REG(&cc->clockcontrol_sb);
4510 + } else {
4511 + INTR_RESTORE(si, intr_val);
4512 + return 0;
4513 + }
4514 +
4515 + // Added by Chen-I for 5365
4516 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4517 + {
4518 + rate = 100000000;
4519 + }
4520 + else
4521 + {
4522 + /* calculate rate */
4523 + rate = sb_clock_rate(pll_type, n, m);
4524 + if (pll_type == PLL_TYPE3)
4525 + rate = rate / 2;
4526 + }
4527 +
4528 + /* switch back to previous core */
4529 + sb_setcoreidx(sbh, idx);
4530 +
4531 + INTR_RESTORE(si, intr_val);
4532 +
4533 + return rate;
4534 +}
4535 +
4536 +/* change logical "focus" to the gpio core for optimized access */
4537 +void*
4538 +sb_gpiosetcore(sb_t *sbh)
4539 +{
4540 + sb_info_t *si;
4541 +
4542 + si = SB_INFO(sbh);
4543 +
4544 + return (sb_setcoreidx(sbh, si->gpioidx));
4545 +}
4546 +
4547 +/* mask&set gpiocontrol bits */
4548 +uint32
4549 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4550 +{
4551 + sb_info_t *si;
4552 + uint regoff;
4553 +
4554 + si = SB_INFO(sbh);
4555 + regoff = 0;
4556 +
4557 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4558 +
4559 + /* gpios could be shared on router platforms */
4560 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4561 + mask = priority ? (sb_gpioreservation & mask) :
4562 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4563 + val &= mask;
4564 + }
4565 +
4566 + switch (si->gpioid) {
4567 + case SB_CC:
4568 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4569 + break;
4570 +
4571 + case SB_PCI:
4572 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4573 + break;
4574 +
4575 + case SB_EXTIF:
4576 + return (0);
4577 + }
4578 +
4579 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4580 +}
4581 +
4582 +/* mask&set gpio output enable bits */
4583 +uint32
4584 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4585 +{
4586 + sb_info_t *si;
4587 + uint regoff;
4588 +
4589 + si = SB_INFO(sbh);
4590 + regoff = 0;
4591 +
4592 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4593 +
4594 + /* gpios could be shared on router platforms */
4595 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4596 + mask = priority ? (sb_gpioreservation & mask) :
4597 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4598 + val &= mask;
4599 + }
4600 +
4601 + switch (si->gpioid) {
4602 + case SB_CC:
4603 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4604 + break;
4605 +
4606 + case SB_PCI:
4607 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4608 + break;
4609 +
4610 + case SB_EXTIF:
4611 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4612 + break;
4613 + }
4614 +
4615 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4616 +}
4617 +
4618 +/* mask&set gpio output bits */
4619 +uint32
4620 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4621 +{
4622 + sb_info_t *si;
4623 + uint regoff;
4624 +
4625 + si = SB_INFO(sbh);
4626 + regoff = 0;
4627 +
4628 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4629 +
4630 + /* gpios could be shared on router platforms */
4631 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4632 + mask = priority ? (sb_gpioreservation & mask) :
4633 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4634 + val &= mask;
4635 + }
4636 +
4637 + switch (si->gpioid) {
4638 + case SB_CC:
4639 + regoff = OFFSETOF(chipcregs_t, gpioout);
4640 + break;
4641 +
4642 + case SB_PCI:
4643 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4644 + break;
4645 +
4646 + case SB_EXTIF:
4647 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4648 + break;
4649 + }
4650 +
4651 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4652 +}
4653 +
4654 +/* reserve one gpio */
4655 +uint32
4656 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4657 +{
4658 + sb_info_t *si;
4659 +
4660 + si = SB_INFO(sbh);
4661 +
4662 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4663 +
4664 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4665 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4666 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4667 + return -1;
4668 + }
4669 + /* make sure only one bit is set */
4670 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4671 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4672 + return -1;
4673 + }
4674 +
4675 + /* already reserved */
4676 + if (sb_gpioreservation & gpio_bitmask)
4677 + return -1;
4678 + /* set reservation */
4679 + sb_gpioreservation |= gpio_bitmask;
4680 +
4681 + return sb_gpioreservation;
4682 +}
4683 +
4684 +/* release one gpio */
4685 +/*
4686 + * releasing the gpio doesn't change the current value on the GPIO last write value
4687 + * persists till some one overwrites it
4688 +*/
4689 +
4690 +uint32
4691 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4692 +{
4693 + sb_info_t *si;
4694 +
4695 + si = SB_INFO(sbh);
4696 +
4697 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4698 +
4699 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4700 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4701 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4702 + return -1;
4703 + }
4704 + /* make sure only one bit is set */
4705 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4706 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4707 + return -1;
4708 + }
4709 +
4710 + /* already released */
4711 + if (!(sb_gpioreservation & gpio_bitmask))
4712 + return -1;
4713 +
4714 + /* clear reservation */
4715 + sb_gpioreservation &= ~gpio_bitmask;
4716 +
4717 + return sb_gpioreservation;
4718 +}
4719 +
4720 +/* return the current gpioin register value */
4721 +uint32
4722 +sb_gpioin(sb_t *sbh)
4723 +{
4724 + sb_info_t *si;
4725 + uint regoff;
4726 +
4727 + si = SB_INFO(sbh);
4728 + regoff = 0;
4729 +
4730 + switch (si->gpioid) {
4731 + case SB_CC:
4732 + regoff = OFFSETOF(chipcregs_t, gpioin);
4733 + break;
4734 +
4735 + case SB_PCI:
4736 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4737 + break;
4738 +
4739 + case SB_EXTIF:
4740 + regoff = OFFSETOF(extifregs_t, gpioin);
4741 + break;
4742 + }
4743 +
4744 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4745 +}
4746 +
4747 +/* mask&set gpio interrupt polarity bits */
4748 +uint32
4749 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4750 +{
4751 + sb_info_t *si;
4752 + uint regoff;
4753 +
4754 + si = SB_INFO(sbh);
4755 + regoff = 0;
4756 +
4757 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4758 +
4759 + /* gpios could be shared on router platforms */
4760 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4761 + mask = priority ? (sb_gpioreservation & mask) :
4762 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4763 + val &= mask;
4764 + }
4765 +
4766 + switch (si->gpioid) {
4767 + case SB_CC:
4768 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4769 + break;
4770 +
4771 + case SB_PCI:
4772 + /* pci gpio implementation does not support interrupt polarity */
4773 + ASSERT(0);
4774 + break;
4775 +
4776 + case SB_EXTIF:
4777 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4778 + break;
4779 + }
4780 +
4781 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4782 +}
4783 +
4784 +/* mask&set gpio interrupt mask bits */
4785 +uint32
4786 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4787 +{
4788 + sb_info_t *si;
4789 + uint regoff;
4790 +
4791 + si = SB_INFO(sbh);
4792 + regoff = 0;
4793 +
4794 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4795 +
4796 + /* gpios could be shared on router platforms */
4797 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4798 + mask = priority ? (sb_gpioreservation & mask) :
4799 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4800 + val &= mask;
4801 + }
4802 +
4803 + switch (si->gpioid) {
4804 + case SB_CC:
4805 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4806 + break;
4807 +
4808 + case SB_PCI:
4809 + /* pci gpio implementation does not support interrupt mask */
4810 + ASSERT(0);
4811 + break;
4812 +
4813 + case SB_EXTIF:
4814 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4815 + break;
4816 + }
4817 +
4818 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4819 +}
4820 +
4821 +/* assign the gpio to an led */
4822 +uint32
4823 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4824 +{
4825 + sb_info_t *si;
4826 +
4827 + si = SB_INFO(sbh);
4828 + if (si->sb.ccrev < 16)
4829 + return -1;
4830 +
4831 + /* gpio led powersave reg */
4832 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4833 +}
4834 +
4835 +/* mask&set gpio timer val */
4836 +uint32
4837 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4838 +{
4839 + sb_info_t *si;
4840 + si = SB_INFO(sbh);
4841 +
4842 + if (si->sb.ccrev < 16)
4843 + return -1;
4844 +
4845 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4846 +}
4847 +
4848 +
4849 +/* return the slow clock source - LPO, XTAL, or PCI */
4850 +static uint
4851 +sb_slowclk_src(sb_info_t *si)
4852 +{
4853 + chipcregs_t *cc;
4854 +
4855 +
4856 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4857 +
4858 + if (si->sb.ccrev < 6) {
4859 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4860 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4861 + return (SCC_SS_PCI);
4862 + else
4863 + return (SCC_SS_XTAL);
4864 + } else if (si->sb.ccrev < 10) {
4865 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4866 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4867 + } else /* Insta-clock */
4868 + return (SCC_SS_XTAL);
4869 +}
4870 +
4871 +/* return the ILP (slowclock) min or max frequency */
4872 +static uint
4873 +sb_slowclk_freq(sb_info_t *si, bool max)
4874 +{
4875 + chipcregs_t *cc;
4876 + uint32 slowclk;
4877 + uint div;
4878 +
4879 +
4880 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4881 +
4882 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4883 +
4884 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4885 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4886 +
4887 + slowclk = sb_slowclk_src(si);
4888 + if (si->sb.ccrev < 6) {
4889 + if (slowclk == SCC_SS_PCI)
4890 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4891 + else
4892 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4893 + } else if (si->sb.ccrev < 10) {
4894 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4895 + if (slowclk == SCC_SS_LPO)
4896 + return (max? LPOMAXFREQ : LPOMINFREQ);
4897 + else if (slowclk == SCC_SS_XTAL)
4898 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4899 + else if (slowclk == SCC_SS_PCI)
4900 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4901 + else
4902 + ASSERT(0);
4903 + } else {
4904 + /* Chipc rev 10 is InstaClock */
4905 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4906 + div = 4 * (div + 1);
4907 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4908 + }
4909 + return (0);
4910 +}
4911 +
4912 +static void
4913 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4914 +{
4915 + chipcregs_t * cc;
4916 + uint slowmaxfreq, pll_delay, slowclk;
4917 + uint pll_on_delay, fref_sel_delay;
4918 +
4919 + pll_delay = PLL_DELAY;
4920 +
4921 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4922 + * since the xtal will also be powered down by dynamic clk control logic.
4923 + */
4924 + slowclk = sb_slowclk_src(si);
4925 + if (slowclk != SCC_SS_XTAL)
4926 + pll_delay += XTAL_ON_DELAY;
4927 +
4928 + /* Starting with 4318 it is ILP that is used for the delays */
4929 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4930 +
4931 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4932 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4933 +
4934 + cc = (chipcregs_t *)chipcregs;
4935 + W_REG(&cc->pll_on_delay, pll_on_delay);
4936 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4937 +}
4938 +
4939 +int
4940 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4941 +{
4942 + sb_info_t *si;
4943 + uint origidx;
4944 + chipcregs_t *cc;
4945 + uint intr_val = 0;
4946 + uint err = 0;
4947 +
4948 + si = SB_INFO(sbh);
4949 +
4950 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4951 + if (si->sb.ccrev < 6)
4952 + return 1;
4953 +
4954 + /* chipcommon cores rev10 are a whole new ball game */
4955 + if (si->sb.ccrev >= 10)
4956 + return 1;
4957 +
4958 + if (set && ((*div % 4) || (*div < 4)))
4959 + return 2;
4960 +
4961 + INTR_OFF(si, intr_val);
4962 + origidx = si->curidx;
4963 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4964 + ASSERT(cc != NULL);
4965 +
4966 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
4967 + err = 3;
4968 + goto done;
4969 + }
4970 +
4971 + if (set) {
4972 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
4973 + sb_clkctl_setdelay(sbh, (void *)cc);
4974 + } else
4975 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4976 +
4977 +done:
4978 + sb_setcoreidx(sbh, origidx);
4979 + INTR_RESTORE(si, intr_val);
4980 + return err;
4981 +}
4982 +
4983 +/* initialize power control delay registers */
4984 +void sb_clkctl_init(sb_t *sbh)
4985 +{
4986 + sb_info_t *si;
4987 + uint origidx;
4988 + chipcregs_t *cc;
4989 +
4990 + si = SB_INFO(sbh);
4991 +
4992 + origidx = si->curidx;
4993 +
4994 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
4995 + return;
4996 +
4997 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
4998 + goto done;
4999 +
5000 + /* set all Instaclk chip ILP to 1 MHz */
5001 + if (si->sb.ccrev >= 10)
5002 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5003 +
5004 + sb_clkctl_setdelay(si, (void *)cc);
5005 +
5006 +done:
5007 + sb_setcoreidx(sbh, origidx);
5008 +}
5009 +void sb_pwrctl_init(sb_t *sbh)
5010 +{
5011 +sb_clkctl_init(sbh);
5012 +}
5013 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5014 +uint16
5015 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5016 +{
5017 + sb_info_t *si;
5018 + uint origidx;
5019 + chipcregs_t *cc;
5020 + uint slowminfreq;
5021 + uint16 fpdelay;
5022 + uint intr_val = 0;
5023 +
5024 + si = SB_INFO(sbh);
5025 + fpdelay = 0;
5026 + origidx = si->curidx;
5027 +
5028 + INTR_OFF(si, intr_val);
5029 +
5030 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5031 + goto done;
5032 +
5033 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5034 + goto done;
5035 +
5036 + slowminfreq = sb_slowclk_freq(si, FALSE);
5037 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5038 +
5039 +done:
5040 + sb_setcoreidx(sbh, origidx);
5041 + INTR_RESTORE(si, intr_val);
5042 + return (fpdelay);
5043 +}
5044 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5045 +{
5046 +return sb_clkctl_fast_pwrup_delay(sbh);
5047 +}
5048 +/* turn primary xtal and/or pll off/on */
5049 +int
5050 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5051 +{
5052 + sb_info_t *si;
5053 + uint32 in, out, outen;
5054 +
5055 + si = SB_INFO(sbh);
5056 +
5057 + switch (BUSTYPE(si->sb.bustype)) {
5058 + case PCI_BUS:
5059 +
5060 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5061 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5062 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5063 +
5064 + /*
5065 + * Avoid glitching the clock if GPRS is already using it.
5066 + * We can't actually read the state of the PLLPD so we infer it
5067 + * by the value of XTAL_PU which *is* readable via gpioin.
5068 + */
5069 + if (on && (in & PCI_CFG_GPIO_XTAL))
5070 + return (0);
5071 +
5072 + if (what & XTAL)
5073 + outen |= PCI_CFG_GPIO_XTAL;
5074 + if (what & PLL)
5075 + outen |= PCI_CFG_GPIO_PLL;
5076 +
5077 + if (on) {
5078 + /* turn primary xtal on */
5079 + if (what & XTAL) {
5080 + out |= PCI_CFG_GPIO_XTAL;
5081 + if (what & PLL)
5082 + out |= PCI_CFG_GPIO_PLL;
5083 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5084 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5085 + OSL_DELAY(XTAL_ON_DELAY);
5086 + }
5087 +
5088 + /* turn pll on */
5089 + if (what & PLL) {
5090 + out &= ~PCI_CFG_GPIO_PLL;
5091 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5092 + OSL_DELAY(2000);
5093 + }
5094 + } else {
5095 + if (what & XTAL)
5096 + out &= ~PCI_CFG_GPIO_XTAL;
5097 + if (what & PLL)
5098 + out |= PCI_CFG_GPIO_PLL;
5099 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5100 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5101 + }
5102 +
5103 + default:
5104 + return (-1);
5105 + }
5106 +
5107 + return (0);
5108 +}
5109 +
5110 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5111 +{
5112 +return sb_clkctl_xtal(sbh,what,on);
5113 +}
5114 +
5115 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5116 +/* returns true if ignore pll off is set and false if it is not */
5117 +bool
5118 +sb_clkctl_clk(sb_t *sbh, uint mode)
5119 +{
5120 + sb_info_t *si;
5121 + uint origidx;
5122 + chipcregs_t *cc;
5123 + uint32 scc;
5124 + bool forcefastclk=FALSE;
5125 + uint intr_val = 0;
5126 +
5127 + si = SB_INFO(sbh);
5128 +
5129 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5130 + if (si->sb.ccrev < 6)
5131 + return (FALSE);
5132 +
5133 + /* chipcommon cores rev10 are a whole new ball game */
5134 + if (si->sb.ccrev >= 10)
5135 + return (FALSE);
5136 +
5137 + INTR_OFF(si, intr_val);
5138 +
5139 + origidx = si->curidx;
5140 +
5141 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5142 + ASSERT(cc != NULL);
5143 +
5144 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5145 + goto done;
5146 +
5147 + switch (mode) {
5148 + case CLK_FAST: /* force fast (pll) clock */
5149 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5150 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5151 +
5152 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5153 + break;
5154 +
5155 + case CLK_DYNAMIC: /* enable dynamic clock control */
5156 + scc = R_REG(&cc->slow_clk_ctl);
5157 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5158 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5159 + scc |= SCC_XC;
5160 + W_REG(&cc->slow_clk_ctl, scc);
5161 +
5162 + /* for dynamic control, we have to release our xtal_pu "force on" */
5163 + if (scc & SCC_XC)
5164 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5165 + break;
5166 +
5167 + default:
5168 + ASSERT(0);
5169 + }
5170 +
5171 + /* Is the h/w forcing the use of the fast clk */
5172 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5173 +
5174 +done:
5175 + sb_setcoreidx(sbh, origidx);
5176 + INTR_RESTORE(si, intr_val);
5177 + return (forcefastclk);
5178 +}
5179 +
5180 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5181 +{
5182 +return sb_clkctl_clk(sbh, mode);
5183 +}
5184 +/* register driver interrupt disabling and restoring callback functions */
5185 +void
5186 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5187 +{
5188 + sb_info_t *si;
5189 +
5190 + si = SB_INFO(sbh);
5191 + si->intr_arg = intr_arg;
5192 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5193 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5194 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5195 + /* save current core id. when this function called, the current core
5196 + * must be the core which provides driver functions(il, et, wl, etc.)
5197 + */
5198 + si->dev_coreid = si->coreid[si->curidx];
5199 +}
5200 +
5201 +
5202 +void
5203 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5204 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5205 +{
5206 + uint vendor, core, unit;
5207 + uint chip, chippkg;
5208 + char varname[8];
5209 + uint8 class, subclass, progif;
5210 +
5211 + vendor = sb_corevendor(sbh);
5212 + core = sb_coreid(sbh);
5213 + unit = sb_coreunit(sbh);
5214 +
5215 + chip = BCMINIT(sb_chip)(sbh);
5216 + chippkg = BCMINIT(sb_chippkg)(sbh);
5217 +
5218 + progif = 0;
5219 +
5220 + /* Known vendor translations */
5221 + switch (vendor) {
5222 + case SB_VEND_BCM:
5223 + vendor = VENDOR_BROADCOM;
5224 + break;
5225 + }
5226 +
5227 + /* Determine class based on known core codes */
5228 + switch (core) {
5229 + case SB_ILINE20:
5230 + class = PCI_CLASS_NET;
5231 + subclass = PCI_NET_ETHER;
5232 + core = BCM47XX_ILINE_ID;
5233 + break;
5234 + case SB_ENET:
5235 + class = PCI_CLASS_NET;
5236 + subclass = PCI_NET_ETHER;
5237 + core = BCM47XX_ENET_ID;
5238 + break;
5239 + case SB_SDRAM:
5240 + case SB_MEMC:
5241 + class = PCI_CLASS_MEMORY;
5242 + subclass = PCI_MEMORY_RAM;
5243 + break;
5244 + case SB_PCI:
5245 + class = PCI_CLASS_BRIDGE;
5246 + subclass = PCI_BRIDGE_PCI;
5247 + break;
5248 + case SB_MIPS:
5249 + case SB_MIPS33:
5250 + class = PCI_CLASS_CPU;
5251 + subclass = PCI_CPU_MIPS;
5252 + break;
5253 + case SB_CODEC:
5254 + class = PCI_CLASS_COMM;
5255 + subclass = PCI_COMM_MODEM;
5256 + core = BCM47XX_V90_ID;
5257 + break;
5258 + case SB_USB:
5259 + class = PCI_CLASS_SERIAL;
5260 + subclass = PCI_SERIAL_USB;
5261 + progif = 0x10; /* OHCI */
5262 + core = BCM47XX_USB_ID;
5263 + break;
5264 + case SB_USB11H:
5265 + class = PCI_CLASS_SERIAL;
5266 + subclass = PCI_SERIAL_USB;
5267 + progif = 0x10; /* OHCI */
5268 + core = BCM47XX_USBH_ID;
5269 + break;
5270 + case SB_USB11D:
5271 + class = PCI_CLASS_SERIAL;
5272 + subclass = PCI_SERIAL_USB;
5273 + core = BCM47XX_USBD_ID;
5274 + break;
5275 + case SB_IPSEC:
5276 + class = PCI_CLASS_CRYPT;
5277 + subclass = PCI_CRYPT_NETWORK;
5278 + core = BCM47XX_IPSEC_ID;
5279 + break;
5280 + case SB_ROBO:
5281 + class = PCI_CLASS_NET;
5282 + subclass = PCI_NET_OTHER;
5283 + core = BCM47XX_ROBO_ID;
5284 + break;
5285 + case SB_EXTIF:
5286 + case SB_CC:
5287 + class = PCI_CLASS_MEMORY;
5288 + subclass = PCI_MEMORY_FLASH;
5289 + break;
5290 + case SB_D11:
5291 + class = PCI_CLASS_NET;
5292 + subclass = PCI_NET_OTHER;
5293 + /* Let an nvram variable override this */
5294 + sprintf(varname, "wl%did", unit);
5295 + if ((core = getintvar(NULL, varname)) == 0) {
5296 + if (chip == BCM4712_DEVICE_ID) {
5297 + if (chippkg == BCM4712SMALL_PKG_ID)
5298 + core = BCM4306_D11G_ID;
5299 + else
5300 + core = BCM4306_D11DUAL_ID;
5301 + }
5302 + }
5303 + break;
5304 +
5305 + default:
5306 + class = subclass = progif = 0xff;
5307 + break;
5308 + }
5309 +
5310 + *pcivendor = (uint16)vendor;
5311 + *pcidevice = (uint16)core;
5312 + *pciclass = class;
5313 + *pcisubclass = subclass;
5314 + *pciprogif = progif;
5315 +}
5316 +
5317 +/* Fix chip's configuration. The current core may be changed upon return */
5318 +static int
5319 +sb_pci_fixcfg(sb_info_t *si)
5320 +{
5321 + uint origidx, pciidx;
5322 + sbpciregs_t *pciregs;
5323 + uint16 val16, *reg16;
5324 +
5325 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5326 +
5327 + /* Fix PCI(e) SROM shadow area */
5328 + /* save the current index */
5329 + origidx = sb_coreidx(&si->sb);
5330 +
5331 + if (si->sb.buscoretype == SB_PCI) {
5332 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5333 + ASSERT(pciregs);
5334 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5335 + }
5336 + else {
5337 + ASSERT(0);
5338 + return -1;
5339 + }
5340 + pciidx = sb_coreidx(&si->sb);
5341 + val16 = R_REG(reg16);
5342 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5343 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5344 + W_REG(reg16, val16);
5345 + }
5346 +
5347 + /* restore the original index */
5348 + sb_setcoreidx(&si->sb, origidx);
5349 +
5350 + return 0;
5351 +}
5352 +
5353 +EXPORT_SYMBOL(sb_boardtype);
5354 +EXPORT_SYMBOL(sb_boardvendor);
5355 +EXPORT_SYMBOL(sb_gpiocontrol);
5356 +EXPORT_SYMBOL(sb_gpioin);
5357 +EXPORT_SYMBOL(sb_gpiointmask);
5358 +EXPORT_SYMBOL(sb_gpiointpolarity);
5359 +EXPORT_SYMBOL(sb_gpioled);
5360 +EXPORT_SYMBOL(sb_gpioout);
5361 +EXPORT_SYMBOL(sb_gpioouten);
5362 +EXPORT_SYMBOL(sb_gpiorelease);
5363 +EXPORT_SYMBOL(sb_gpioreserve);
5364 +EXPORT_SYMBOL(sb_gpiosetcore);
5365 +EXPORT_SYMBOL(sb_gpiotimerval);
5366 +EXPORT_SYMBOL(sb_watchdog);
5367 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sflash.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sflash.c
5368 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5369 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sflash.c 2006-06-18 15:29:23.000000000 +0200
5370 @@ -0,0 +1,418 @@
5371 +/*
5372 + * Broadcom SiliconBackplane chipcommon serial flash interface
5373 + *
5374 + * Copyright 2005, Broadcom Corporation
5375 + * All Rights Reserved.
5376 + *
5377 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5378 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5379 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5380 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5381 + *
5382 + * $Id$
5383 + */
5384 +
5385 +#include <osl.h>
5386 +#include <typedefs.h>
5387 +#include <sbconfig.h>
5388 +#include <sbchipc.h>
5389 +#include <mipsinc.h>
5390 +#include <bcmutils.h>
5391 +#include <bcmdevs.h>
5392 +#include <sflash.h>
5393 +
5394 +/* Private global state */
5395 +static struct sflash sflash;
5396 +
5397 +/* Issue a serial flash command */
5398 +static INLINE void
5399 +sflash_cmd(chipcregs_t *cc, uint opcode)
5400 +{
5401 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5402 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5403 +}
5404 +
5405 +/* Initialize serial flash access */
5406 +struct sflash *
5407 +sflash_init(chipcregs_t *cc)
5408 +{
5409 + uint32 id, id2;
5410 +
5411 + bzero(&sflash, sizeof(sflash));
5412 +
5413 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5414 +
5415 + switch (sflash.type) {
5416 + case SFLASH_ST:
5417 + /* Probe for ST chips */
5418 + sflash_cmd(cc, SFLASH_ST_DP);
5419 + sflash_cmd(cc, SFLASH_ST_RES);
5420 + id = R_REG(&cc->flashdata);
5421 + switch (id) {
5422 + case 0x11:
5423 + /* ST M25P20 2 Mbit Serial Flash */
5424 + sflash.blocksize = 64 * 1024;
5425 + sflash.numblocks = 4;
5426 + break;
5427 + case 0x12:
5428 + /* ST M25P40 4 Mbit Serial Flash */
5429 + sflash.blocksize = 64 * 1024;
5430 + sflash.numblocks = 8;
5431 + break;
5432 + case 0x13:
5433 + /* ST M25P80 8 Mbit Serial Flash */
5434 + sflash.blocksize = 64 * 1024;
5435 + sflash.numblocks = 16;
5436 + break;
5437 + case 0x14:
5438 + /* ST M25P16 16 Mbit Serial Flash */
5439 + sflash.blocksize = 64 * 1024;
5440 + sflash.numblocks = 32;
5441 + break;
5442 + case 0x15:
5443 + /* ST M25P32 32 Mbit Serial Flash */
5444 + sflash.blocksize = 64 * 1024;
5445 + sflash.numblocks = 64;
5446 + break;
5447 + case 0xbf:
5448 + W_REG(&cc->flashaddress, 1);
5449 + sflash_cmd(cc, SFLASH_ST_RES);
5450 + id2 = R_REG(&cc->flashdata);
5451 + if (id2 == 0x44) {
5452 + /* SST M25VF80 4 Mbit Serial Flash */
5453 + sflash.blocksize = 64 * 1024;
5454 + sflash.numblocks = 8;
5455 + }
5456 + break;
5457 + }
5458 + break;
5459 +
5460 + case SFLASH_AT:
5461 + /* Probe for Atmel chips */
5462 + sflash_cmd(cc, SFLASH_AT_STATUS);
5463 + id = R_REG(&cc->flashdata) & 0x3c;
5464 + switch (id) {
5465 + case 0xc:
5466 + /* Atmel AT45DB011 1Mbit Serial Flash */
5467 + sflash.blocksize = 256;
5468 + sflash.numblocks = 512;
5469 + break;
5470 + case 0x14:
5471 + /* Atmel AT45DB021 2Mbit Serial Flash */
5472 + sflash.blocksize = 256;
5473 + sflash.numblocks = 1024;
5474 + break;
5475 + case 0x1c:
5476 + /* Atmel AT45DB041 4Mbit Serial Flash */
5477 + sflash.blocksize = 256;
5478 + sflash.numblocks = 2048;
5479 + break;
5480 + case 0x24:
5481 + /* Atmel AT45DB081 8Mbit Serial Flash */
5482 + sflash.blocksize = 256;
5483 + sflash.numblocks = 4096;
5484 + break;
5485 + case 0x2c:
5486 + /* Atmel AT45DB161 16Mbit Serial Flash */
5487 + sflash.blocksize = 512;
5488 + sflash.numblocks = 4096;
5489 + break;
5490 + case 0x34:
5491 + /* Atmel AT45DB321 32Mbit Serial Flash */
5492 + sflash.blocksize = 512;
5493 + sflash.numblocks = 8192;
5494 + break;
5495 + case 0x3c:
5496 + /* Atmel AT45DB642 64Mbit Serial Flash */
5497 + sflash.blocksize = 1024;
5498 + sflash.numblocks = 8192;
5499 + break;
5500 + }
5501 + break;
5502 + }
5503 +
5504 + sflash.size = sflash.blocksize * sflash.numblocks;
5505 + return sflash.size ? &sflash : NULL;
5506 +}
5507 +
5508 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5509 +int
5510 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5511 +{
5512 + int cnt;
5513 + uint32 *from, *to;
5514 +
5515 + if (!len)
5516 + return 0;
5517 +
5518 + if ((offset + len) > sflash.size)
5519 + return -22;
5520 +
5521 + if ((len >= 4) && (offset & 3))
5522 + cnt = 4 - (offset & 3);
5523 + else if ((len >= 4) && ((uint32)buf & 3))
5524 + cnt = 4 - ((uint32)buf & 3);
5525 + else
5526 + cnt = len;
5527 +
5528 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5529 + to = (uint32 *)buf;
5530 +
5531 + if (cnt < 4) {
5532 + bcopy(from, to, cnt);
5533 + return cnt;
5534 + }
5535 +
5536 + while (cnt >= 4) {
5537 + *to++ = *from++;
5538 + cnt -= 4;
5539 + }
5540 +
5541 + return (len - cnt);
5542 +}
5543 +
5544 +/* Poll for command completion. Returns zero when complete. */
5545 +int
5546 +sflash_poll(chipcregs_t *cc, uint offset)
5547 +{
5548 + if (offset >= sflash.size)
5549 + return -22;
5550 +
5551 + switch (sflash.type) {
5552 + case SFLASH_ST:
5553 + /* Check for ST Write In Progress bit */
5554 + sflash_cmd(cc, SFLASH_ST_RDSR);
5555 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5556 + case SFLASH_AT:
5557 + /* Check for Atmel Ready bit */
5558 + sflash_cmd(cc, SFLASH_AT_STATUS);
5559 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5560 + }
5561 +
5562 + return 0;
5563 +}
5564 +
5565 +/* Write len bytes starting at offset into buf. Returns number of bytes
5566 + * written. Caller should poll for completion.
5567 + */
5568 +int
5569 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5570 +{
5571 + struct sflash *sfl;
5572 + int ret = 0;
5573 + bool is4712b0;
5574 + uint32 page, byte, mask;
5575 +
5576 + if (!len)
5577 + return 0;
5578 +
5579 + if ((offset + len) > sflash.size)
5580 + return -22;
5581 +
5582 + sfl = &sflash;
5583 + switch (sfl->type) {
5584 + case SFLASH_ST:
5585 + mask = R_REG(&cc->chipid);
5586 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5587 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5588 + /* Enable writes */
5589 + sflash_cmd(cc, SFLASH_ST_WREN);
5590 + if (is4712b0) {
5591 + mask = 1 << 14;
5592 + W_REG(&cc->flashaddress, offset);
5593 + W_REG(&cc->flashdata, *buf++);
5594 + /* Set chip select */
5595 + OR_REG(&cc->gpioout, mask);
5596 + /* Issue a page program with the first byte */
5597 + sflash_cmd(cc, SFLASH_ST_PP);
5598 + ret = 1;
5599 + offset++;
5600 + len--;
5601 + while (len > 0) {
5602 + if ((offset & 255) == 0) {
5603 + /* Page boundary, drop cs and return */
5604 + AND_REG(&cc->gpioout, ~mask);
5605 + if (!sflash_poll(cc, offset)) {
5606 + /* Flash rejected command */
5607 + return -11;
5608 + }
5609 + return ret;
5610 + } else {
5611 + /* Write single byte */
5612 + sflash_cmd(cc, *buf++);
5613 + }
5614 + ret++;
5615 + offset++;
5616 + len--;
5617 + }
5618 + /* All done, drop cs if needed */
5619 + if ((offset & 255) != 1) {
5620 + /* Drop cs */
5621 + AND_REG(&cc->gpioout, ~mask);
5622 + if (!sflash_poll(cc, offset)) {
5623 + /* Flash rejected command */
5624 + return -12;
5625 + }
5626 + }
5627 + } else {
5628 + ret = 1;
5629 + W_REG(&cc->flashaddress, offset);
5630 + W_REG(&cc->flashdata, *buf);
5631 + /* Page program */
5632 + sflash_cmd(cc, SFLASH_ST_PP);
5633 + }
5634 + break;
5635 + case SFLASH_AT:
5636 + mask = sfl->blocksize - 1;
5637 + page = (offset & ~mask) << 1;
5638 + byte = offset & mask;
5639 + /* Read main memory page into buffer 1 */
5640 + if (byte || len < sfl->blocksize) {
5641 + W_REG(&cc->flashaddress, page);
5642 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5643 + /* 250 us for AT45DB321B */
5644 + SPINWAIT(sflash_poll(cc, offset), 1000);
5645 + ASSERT(!sflash_poll(cc, offset));
5646 + }
5647 + /* Write into buffer 1 */
5648 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5649 + W_REG(&cc->flashaddress, byte++);
5650 + W_REG(&cc->flashdata, *buf++);
5651 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5652 + }
5653 + /* Write buffer 1 into main memory page */
5654 + W_REG(&cc->flashaddress, page);
5655 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5656 + break;
5657 + }
5658 +
5659 + return ret;
5660 +}
5661 +
5662 +/* Erase a region. Returns number of bytes scheduled for erasure.
5663 + * Caller should poll for completion.
5664 + */
5665 +int
5666 +sflash_erase(chipcregs_t *cc, uint offset)
5667 +{
5668 + struct sflash *sfl;
5669 +
5670 + if (offset >= sflash.size)
5671 + return -22;
5672 +
5673 + sfl = &sflash;
5674 + switch (sfl->type) {
5675 + case SFLASH_ST:
5676 + sflash_cmd(cc, SFLASH_ST_WREN);
5677 + W_REG(&cc->flashaddress, offset);
5678 + sflash_cmd(cc, SFLASH_ST_SE);
5679 + return sfl->blocksize;
5680 + case SFLASH_AT:
5681 + W_REG(&cc->flashaddress, offset << 1);
5682 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5683 + return sfl->blocksize;
5684 + }
5685 +
5686 + return 0;
5687 +}
5688 +
5689 +/*
5690 + * writes the appropriate range of flash, a NULL buf simply erases
5691 + * the region of flash
5692 + */
5693 +int
5694 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5695 +{
5696 + struct sflash *sfl;
5697 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5698 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5699 + uint blk_offset, blk_len, copied;
5700 + int bytes, ret = 0;
5701 +
5702 + /* Check address range */
5703 + if (len <= 0)
5704 + return 0;
5705 +
5706 + sfl = &sflash;
5707 + if ((offset + len) > sfl->size)
5708 + return -1;
5709 +
5710 + blocksize = sfl->blocksize;
5711 + mask = blocksize - 1;
5712 +
5713 + /* Allocate a block of mem */
5714 + if (!(block = MALLOC(NULL, blocksize)))
5715 + return -1;
5716 +
5717 + while (len) {
5718 + /* Align offset */
5719 + cur_offset = offset & ~mask;
5720 + cur_length = blocksize;
5721 + cur_ptr = block;
5722 +
5723 + remainder = blocksize - (offset & mask);
5724 + if (len < remainder)
5725 + cur_retlen = len;
5726 + else
5727 + cur_retlen = remainder;
5728 +
5729 + /* buf == NULL means erase only */
5730 + if (buf) {
5731 + /* Copy existing data into holding block if necessary */
5732 + if ((offset & mask) || (len < blocksize)) {
5733 + blk_offset = cur_offset;
5734 + blk_len = cur_length;
5735 + blk_ptr = cur_ptr;
5736 +
5737 + /* Copy entire block */
5738 + while(blk_len) {
5739 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5740 + blk_offset += copied;
5741 + blk_len -= copied;
5742 + blk_ptr += copied;
5743 + }
5744 + }
5745 +
5746 + /* Copy input data into holding block */
5747 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5748 + }
5749 +
5750 + /* Erase block */
5751 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5752 + goto done;
5753 + while (sflash_poll(cc, (uint) cur_offset));
5754 +
5755 + /* buf == NULL means erase only */
5756 + if (!buf) {
5757 + offset += cur_retlen;
5758 + len -= cur_retlen;
5759 + continue;
5760 + }
5761 +
5762 + /* Write holding block */
5763 + while (cur_length > 0) {
5764 + if ((bytes = sflash_write(cc,
5765 + (uint) cur_offset,
5766 + (uint) cur_length,
5767 + (uchar *) cur_ptr)) < 0) {
5768 + ret = bytes;
5769 + goto done;
5770 + }
5771 + while (sflash_poll(cc, (uint) cur_offset));
5772 + cur_offset += bytes;
5773 + cur_length -= bytes;
5774 + cur_ptr += bytes;
5775 + }
5776 +
5777 + offset += cur_retlen;
5778 + len -= cur_retlen;
5779 + buf += cur_retlen;
5780 + }
5781 +
5782 + ret = len;
5783 +done:
5784 + if (block)
5785 + MFREE(NULL, block, blocksize);
5786 + return ret;
5787 +}
5788 +
5789 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bcmdevs.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmdevs.h
5790 --- linux-2.6.17/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5791 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmdevs.h 2006-06-18 15:29:23.000000000 +0200
5792 @@ -0,0 +1,391 @@
5793 +/*
5794 + * Broadcom device-specific manifest constants.
5795 + *
5796 + * Copyright 2005, Broadcom Corporation
5797 + * All Rights Reserved.
5798 + *
5799 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5800 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5801 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5802 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5803 + * $Id$
5804 + */
5805 +
5806 +#ifndef _BCMDEVS_H
5807 +#define _BCMDEVS_H
5808 +
5809 +
5810 +/* Known PCI vendor Id's */
5811 +#define VENDOR_EPIGRAM 0xfeda
5812 +#define VENDOR_BROADCOM 0x14e4
5813 +#define VENDOR_3COM 0x10b7
5814 +#define VENDOR_NETGEAR 0x1385
5815 +#define VENDOR_DIAMOND 0x1092
5816 +#define VENDOR_DELL 0x1028
5817 +#define VENDOR_HP 0x0e11
5818 +#define VENDOR_APPLE 0x106b
5819 +
5820 +/* PCI Device Id's */
5821 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5822 +#define BCM4211_DEVICE_ID 0x4211
5823 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5824 +#define BCM4231_DEVICE_ID 0x4231
5825 +
5826 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5827 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5828 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5829 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5830 +
5831 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5832 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5833 +
5834 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5835 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5836 +
5837 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5838 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5839 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5840 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5841 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5842 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5843 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5844 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5845 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5846 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5847 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5848 +
5849 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5850 +
5851 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5852 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5853 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5854 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5855 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5856 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5857 +
5858 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5859 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5860 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5861 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5862 +
5863 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5864 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5865 +
5866 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5867 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5868 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5869 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5870 +
5871 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5872 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5873 +#define BCM4306_D11G_ID2 0x4325
5874 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5875 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5876 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5877 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5878 +
5879 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5880 +
5881 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5882 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5883 +
5884 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5885 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5886 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5887 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5888 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5889 +
5890 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5891 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5892 +
5893 +
5894 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5895 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5896 +
5897 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5898 +
5899 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5900 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5901 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5902 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5903 +
5904 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5905 +
5906 +/* Address map */
5907 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5908 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5909 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5910 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5911 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5912 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5913 +
5914 +/* Core register space */
5915 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5916 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5917 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5918 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5919 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5920 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5921 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5922 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5923 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5924 +
5925 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5926 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5927 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5928 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5929 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5930 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5931 +
5932 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5933 +
5934 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5935 +
5936 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5937 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5938 +
5939 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5940 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5941 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5942 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5943 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5944 +
5945 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5946 +
5947 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5948 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5949 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5950 +
5951 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
5952 +
5953 +/* PCMCIA vendor Id's */
5954 +
5955 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
5956 +
5957 +/* SDIO vendor Id's */
5958 +#define VENDOR_BROADCOM_SDIO 0x00BF
5959 +
5960 +
5961 +/* boardflags */
5962 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
5963 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
5964 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
5965 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
5966 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
5967 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
5968 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
5969 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
5970 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
5971 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
5972 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
5973 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
5974 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
5975 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
5976 +
5977 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
5978 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
5979 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
5980 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
5981 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
5982 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
5983 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
5984 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
5985 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
5986 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5987 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5988 +
5989 +/* Bus types */
5990 +#define SB_BUS 0 /* Silicon Backplane */
5991 +#define PCI_BUS 1 /* PCI target */
5992 +#define PCMCIA_BUS 2 /* PCMCIA target */
5993 +#define SDIO_BUS 3 /* SDIO target */
5994 +#define JTAG_BUS 4 /* JTAG */
5995 +
5996 +/* Allows optimization for single-bus support */
5997 +#ifdef BCMBUSTYPE
5998 +#define BUSTYPE(bus) (BCMBUSTYPE)
5999 +#else
6000 +#define BUSTYPE(bus) (bus)
6001 +#endif
6002 +
6003 +/* power control defines */
6004 +#define PLL_DELAY 150 /* us pll on delay */
6005 +#define FREF_DELAY 200 /* us fref change delay */
6006 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6007 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6008 +
6009 +/* Reference Board Types */
6010 +
6011 +#define BU4710_BOARD 0x0400
6012 +#define VSIM4710_BOARD 0x0401
6013 +#define QT4710_BOARD 0x0402
6014 +
6015 +#define BU4610_BOARD 0x0403
6016 +#define VSIM4610_BOARD 0x0404
6017 +
6018 +#define BU4307_BOARD 0x0405
6019 +#define BCM94301CB_BOARD 0x0406
6020 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6021 +#define BCM94301MP_BOARD 0x0407
6022 +#define BCM94307MP_BOARD 0x0408
6023 +#define BCMAP4307_BOARD 0x0409
6024 +
6025 +#define BU4309_BOARD 0x040a
6026 +#define BCM94309CB_BOARD 0x040b
6027 +#define BCM94309MP_BOARD 0x040c
6028 +#define BCM4309AP_BOARD 0x040d
6029 +
6030 +#define BCM94302MP_BOARD 0x040e
6031 +
6032 +#define VSIM4310_BOARD 0x040f
6033 +#define BU4711_BOARD 0x0410
6034 +#define BCM94310U_BOARD 0x0411
6035 +#define BCM94310AP_BOARD 0x0412
6036 +#define BCM94310MP_BOARD 0x0414
6037 +
6038 +#define BU4306_BOARD 0x0416
6039 +#define BCM94306CB_BOARD 0x0417
6040 +#define BCM94306MP_BOARD 0x0418
6041 +
6042 +#define BCM94710D_BOARD 0x041a
6043 +#define BCM94710R1_BOARD 0x041b
6044 +#define BCM94710R4_BOARD 0x041c
6045 +#define BCM94710AP_BOARD 0x041d
6046 +
6047 +
6048 +#define BU2050_BOARD 0x041f
6049 +
6050 +
6051 +#define BCM94309G_BOARD 0x0421
6052 +
6053 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6054 +
6055 +#define BU4704_BOARD 0x0423
6056 +#define BU4702_BOARD 0x0424
6057 +
6058 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6059 +
6060 +#define BU4317_BOARD 0x0426
6061 +
6062 +
6063 +#define BCM94702MN_BOARD 0x0428
6064 +
6065 +/* BCM4702 1U CompactPCI Board */
6066 +#define BCM94702CPCI_BOARD 0x0429
6067 +
6068 +/* BCM4702 with BCM95380 VLAN Router */
6069 +#define BCM95380RR_BOARD 0x042a
6070 +
6071 +/* cb4306 with SiGe PA */
6072 +#define BCM94306CBSG_BOARD 0x042b
6073 +
6074 +/* mp4301 with 2050 radio */
6075 +#define BCM94301MPL_BOARD 0x042c
6076 +
6077 +/* cb4306 with SiGe PA */
6078 +#define PCSG94306_BOARD 0x042d
6079 +
6080 +/* bu4704 with sdram */
6081 +#define BU4704SD_BOARD 0x042e
6082 +
6083 +/* Dual 11a/11g Router */
6084 +#define BCM94704AGR_BOARD 0x042f
6085 +
6086 +/* 11a-only minipci */
6087 +#define BCM94308MP_BOARD 0x0430
6088 +
6089 +
6090 +
6091 +/* BCM94317 boards */
6092 +#define BCM94317CB_BOARD 0x0440
6093 +#define BCM94317MP_BOARD 0x0441
6094 +#define BCM94317PCMCIA_BOARD 0x0442
6095 +#define BCM94317SDIO_BOARD 0x0443
6096 +
6097 +#define BU4712_BOARD 0x0444
6098 +#define BU4712SD_BOARD 0x045d
6099 +#define BU4712L_BOARD 0x045f
6100 +
6101 +/* BCM4712 boards */
6102 +#define BCM94712AP_BOARD 0x0445
6103 +#define BCM94712P_BOARD 0x0446
6104 +
6105 +/* BCM4318 boards */
6106 +#define BU4318_BOARD 0x0447
6107 +#define CB4318_BOARD 0x0448
6108 +#define MPG4318_BOARD 0x0449
6109 +#define MP4318_BOARD 0x044a
6110 +#define SD4318_BOARD 0x044b
6111 +
6112 +/* BCM63XX boards */
6113 +#define BCM96338_BOARD 0x6338
6114 +#define BCM96345_BOARD 0x6345
6115 +#define BCM96348_BOARD 0x6348
6116 +
6117 +/* Another mp4306 with SiGe */
6118 +#define BCM94306P_BOARD 0x044c
6119 +
6120 +/* CF-like 4317 modules */
6121 +#define BCM94317CF_BOARD 0x044d
6122 +
6123 +/* mp4303 */
6124 +#define BCM94303MP_BOARD 0x044e
6125 +
6126 +/* mpsgh4306 */
6127 +#define BCM94306MPSGH_BOARD 0x044f
6128 +
6129 +/* BRCM 4306 w/ Front End Modules */
6130 +#define BCM94306MPM 0x0450
6131 +#define BCM94306MPL 0x0453
6132 +
6133 +/* 4712agr */
6134 +#define BCM94712AGR_BOARD 0x0451
6135 +
6136 +/* The real CF 4317 board */
6137 +#define CFI4317_BOARD 0x0452
6138 +
6139 +/* pcmcia 4303 */
6140 +#define PC4303_BOARD 0x0454
6141 +
6142 +/* 5350K */
6143 +#define BCM95350K_BOARD 0x0455
6144 +
6145 +/* 5350R */
6146 +#define BCM95350R_BOARD 0x0456
6147 +
6148 +/* 4306mplna */
6149 +#define BCM94306MPLNA_BOARD 0x0457
6150 +
6151 +/* 4320 boards */
6152 +#define BU4320_BOARD 0x0458
6153 +#define BU4320S_BOARD 0x0459
6154 +#define BCM94320PH_BOARD 0x045a
6155 +
6156 +/* 4306mph */
6157 +#define BCM94306MPH_BOARD 0x045b
6158 +
6159 +/* 4306pciv */
6160 +#define BCM94306PCIV_BOARD 0x045c
6161 +
6162 +#define BU4712SD_BOARD 0x045d
6163 +
6164 +#define BCM94320PFLSH_BOARD 0x045e
6165 +
6166 +#define BU4712L_BOARD 0x045f
6167 +#define BCM94712LGR_BOARD 0x0460
6168 +#define BCM94320R_BOARD 0x0461
6169 +
6170 +#define BU5352_BOARD 0x0462
6171 +
6172 +#define BCM94318MPGH_BOARD 0x0463
6173 +
6174 +
6175 +#define BCM95352GR_BOARD 0x0467
6176 +
6177 +/* bcm95351agr */
6178 +#define BCM95351AGR_BOARD 0x0470
6179 +
6180 +/* # of GPIO pins */
6181 +#define GPIO_NUMPINS 16
6182 +
6183 +#endif /* _BCMDEVS_H */
6184 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bcmendian.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmendian.h
6185 --- linux-2.6.17/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6186 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmendian.h 2006-06-18 15:29:23.000000000 +0200
6187 @@ -0,0 +1,152 @@
6188 +/*
6189 + * local version of endian.h - byte order defines
6190 + *
6191 + * Copyright 2005, Broadcom Corporation
6192 + * All Rights Reserved.
6193 + *
6194 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6195 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6196 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6197 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6198 + *
6199 + * $Id$
6200 +*/
6201 +
6202 +#ifndef _BCMENDIAN_H_
6203 +#define _BCMENDIAN_H_
6204 +
6205 +#include <typedefs.h>
6206 +
6207 +/* Byte swap a 16 bit value */
6208 +#define BCMSWAP16(val) \
6209 + ((uint16)( \
6210 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6211 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6212 +
6213 +/* Byte swap a 32 bit value */
6214 +#define BCMSWAP32(val) \
6215 + ((uint32)( \
6216 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6217 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6218 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6219 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6220 +
6221 +/* 2 Byte swap a 32 bit value */
6222 +#define BCMSWAP32BY16(val) \
6223 + ((uint32)( \
6224 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6225 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6226 +
6227 +
6228 +static INLINE uint16
6229 +bcmswap16(uint16 val)
6230 +{
6231 + return BCMSWAP16(val);
6232 +}
6233 +
6234 +static INLINE uint32
6235 +bcmswap32(uint32 val)
6236 +{
6237 + return BCMSWAP32(val);
6238 +}
6239 +
6240 +static INLINE uint32
6241 +bcmswap32by16(uint32 val)
6242 +{
6243 + return BCMSWAP32BY16(val);
6244 +}
6245 +
6246 +/* buf - start of buffer of shorts to swap */
6247 +/* len - byte length of buffer */
6248 +static INLINE void
6249 +bcmswap16_buf(uint16 *buf, uint len)
6250 +{
6251 + len = len/2;
6252 +
6253 + while(len--){
6254 + *buf = bcmswap16(*buf);
6255 + buf++;
6256 + }
6257 +}
6258 +
6259 +#ifndef hton16
6260 +#ifndef IL_BIGENDIAN
6261 +#define HTON16(i) BCMSWAP16(i)
6262 +#define hton16(i) bcmswap16(i)
6263 +#define hton32(i) bcmswap32(i)
6264 +#define ntoh16(i) bcmswap16(i)
6265 +#define ntoh32(i) bcmswap32(i)
6266 +#define ltoh16(i) (i)
6267 +#define ltoh32(i) (i)
6268 +#define htol16(i) (i)
6269 +#define htol32(i) (i)
6270 +#else
6271 +#define HTON16(i) (i)
6272 +#define hton16(i) (i)
6273 +#define hton32(i) (i)
6274 +#define ntoh16(i) (i)
6275 +#define ntoh32(i) (i)
6276 +#define ltoh16(i) bcmswap16(i)
6277 +#define ltoh32(i) bcmswap32(i)
6278 +#define htol16(i) bcmswap16(i)
6279 +#define htol32(i) bcmswap32(i)
6280 +#endif
6281 +#endif
6282 +
6283 +#ifndef IL_BIGENDIAN
6284 +#define ltoh16_buf(buf, i)
6285 +#define htol16_buf(buf, i)
6286 +#else
6287 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6288 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6289 +#endif
6290 +
6291 +/*
6292 +* load 16-bit value from unaligned little endian byte array.
6293 +*/
6294 +static INLINE uint16
6295 +ltoh16_ua(uint8 *bytes)
6296 +{
6297 + return (bytes[1]<<8)+bytes[0];
6298 +}
6299 +
6300 +/*
6301 +* load 32-bit value from unaligned little endian byte array.
6302 +*/
6303 +static INLINE uint32
6304 +ltoh32_ua(uint8 *bytes)
6305 +{
6306 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6307 +}
6308 +
6309 +/*
6310 +* load 16-bit value from unaligned big(network) endian byte array.
6311 +*/
6312 +static INLINE uint16
6313 +ntoh16_ua(uint8 *bytes)
6314 +{
6315 + return (bytes[0]<<8)+bytes[1];
6316 +}
6317 +
6318 +/*
6319 +* load 32-bit value from unaligned big(network) endian byte array.
6320 +*/
6321 +static INLINE uint32
6322 +ntoh32_ua(uint8 *bytes)
6323 +{
6324 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6325 +}
6326 +
6327 +#define ltoh_ua(ptr) ( \
6328 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6329 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6330 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6331 +)
6332 +
6333 +#define ntoh_ua(ptr) ( \
6334 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6335 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6336 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6337 +)
6338 +
6339 +#endif /* _BCMENDIAN_H_ */
6340 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bcmnvram.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmnvram.h
6341 --- linux-2.6.17/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6342 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmnvram.h 2006-06-18 15:29:23.000000000 +0200
6343 @@ -0,0 +1,95 @@
6344 +/*
6345 + * NVRAM variable manipulation
6346 + *
6347 + * Copyright 2005, Broadcom Corporation
6348 + * All Rights Reserved.
6349 + *
6350 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6351 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6352 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6353 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6354 + *
6355 + * $Id$
6356 + */
6357 +
6358 +#ifndef _bcmnvram_h_
6359 +#define _bcmnvram_h_
6360 +
6361 +#ifndef _LANGUAGE_ASSEMBLY
6362 +
6363 +#include <typedefs.h>
6364 +
6365 +struct nvram_header {
6366 + uint32 magic;
6367 + uint32 len;
6368 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6369 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6370 + uint32 config_ncdl; /* ncdl values for memc */
6371 +};
6372 +
6373 +struct nvram_tuple {
6374 + char *name;
6375 + char *value;
6376 + struct nvram_tuple *next;
6377 +};
6378 +
6379 +/*
6380 + * Get the value of an NVRAM variable. The pointer returned may be
6381 + * invalid after a set.
6382 + * @param name name of variable to get
6383 + * @return value of variable or NULL if undefined
6384 + */
6385 +extern char * __init early_nvram_get(const char *name);
6386 +
6387 +/*
6388 + * Get the value of an NVRAM variable. The pointer returned may be
6389 + * invalid after a set.
6390 + * @param name name of variable to get
6391 + * @return value of variable or NULL if undefined
6392 + */
6393 +extern char *nvram_get(const char *name);
6394 +
6395 +/*
6396 + * Get the value of an NVRAM variable.
6397 + * @param name name of variable to get
6398 + * @return value of variable or NUL if undefined
6399 + */
6400 +#define nvram_safe_get(name) (BCMINIT(early_nvram_get)(name) ? : "")
6401 +
6402 +/*
6403 + * Match an NVRAM variable.
6404 + * @param name name of variable to match
6405 + * @param match value to compare against value of variable
6406 + * @return TRUE if variable is defined and its value is string equal
6407 + * to match or FALSE otherwise
6408 + */
6409 +static inline int
6410 +nvram_match(char *name, char *match) {
6411 + const char *value = BCMINIT(early_nvram_get)(name);
6412 + return (value && !strcmp(value, match));
6413 +}
6414 +
6415 +/*
6416 + * Inversely match an NVRAM variable.
6417 + * @param name name of variable to match
6418 + * @param match value to compare against value of variable
6419 + * @return TRUE if variable is defined and its value is not string
6420 + * equal to invmatch or FALSE otherwise
6421 + */
6422 +static inline int
6423 +nvram_invmatch(char *name, char *invmatch) {
6424 + const char *value = BCMINIT(early_nvram_get)(name);
6425 + return (value && strcmp(value, invmatch));
6426 +}
6427 +
6428 +#endif /* _LANGUAGE_ASSEMBLY */
6429 +
6430 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6431 +#define NVRAM_VERSION 1
6432 +#define NVRAM_HEADER_SIZE 20
6433 +#define NVRAM_SPACE 0x8000
6434 +
6435 +#define NVRAM_MAX_VALUE_LEN 255
6436 +#define NVRAM_MAX_PARAM_LEN 64
6437 +
6438 +#endif /* _bcmnvram_h_ */
6439 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bcmsrom.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmsrom.h
6440 --- linux-2.6.17/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6441 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmsrom.h 2006-06-18 15:29:23.000000000 +0200
6442 @@ -0,0 +1,23 @@
6443 +/*
6444 + * Misc useful routines to access NIC local SROM/OTP .
6445 + *
6446 + * Copyright 2005, Broadcom Corporation
6447 + * All Rights Reserved.
6448 + *
6449 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6450 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6451 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6452 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6453 + *
6454 + * $Id$
6455 + */
6456 +
6457 +#ifndef _bcmsrom_h_
6458 +#define _bcmsrom_h_
6459 +
6460 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6461 +
6462 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6463 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6464 +
6465 +#endif /* _bcmsrom_h_ */
6466 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bcmutils.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmutils.h
6467 --- linux-2.6.17/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6468 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bcmutils.h 2006-06-18 15:29:23.000000000 +0200
6469 @@ -0,0 +1,308 @@
6470 +/*
6471 + * Misc useful os-independent macros and functions.
6472 + *
6473 + * Copyright 2005, Broadcom Corporation
6474 + * All Rights Reserved.
6475 + *
6476 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6477 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6478 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6479 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6480 + * $Id$
6481 + */
6482 +
6483 +#ifndef _bcmutils_h_
6484 +#define _bcmutils_h_
6485 +
6486 +/*** driver-only section ***/
6487 +#include <osl.h>
6488 +
6489 +#define _BCM_U 0x01 /* upper */
6490 +#define _BCM_L 0x02 /* lower */
6491 +#define _BCM_D 0x04 /* digit */
6492 +#define _BCM_C 0x08 /* cntrl */
6493 +#define _BCM_P 0x10 /* punct */
6494 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6495 +#define _BCM_X 0x40 /* hex digit */
6496 +#define _BCM_SP 0x80 /* hard space (0x20) */
6497 +
6498 +#define GPIO_PIN_NOTDEFINED 0x20
6499 +
6500 +extern unsigned char bcm_ctype[];
6501 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6502 +
6503 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6504 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6505 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6506 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6507 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6508 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6509 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6510 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6511 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6512 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6513 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6514 +
6515 +/*
6516 + * Spin at most 'us' microseconds while 'exp' is true.
6517 + * Caller should explicitly test 'exp' when this completes
6518 + * and take appropriate error action if 'exp' is still true.
6519 + */
6520 +#define SPINWAIT(exp, us) { \
6521 + uint countdown = (us) + 9; \
6522 + while ((exp) && (countdown >= 10)) {\
6523 + OSL_DELAY(10); \
6524 + countdown -= 10; \
6525 + } \
6526 +}
6527 +
6528 +/* generic osl packet queue */
6529 +struct pktq {
6530 + void *head; /* first packet to dequeue */
6531 + void *tail; /* last packet to dequeue */
6532 + uint len; /* number of queued packets */
6533 + uint maxlen; /* maximum number of queued packets */
6534 + bool priority; /* enqueue by packet priority */
6535 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6536 +};
6537 +#define DEFAULT_QLEN 128
6538 +
6539 +#define pktq_len(q) ((q)->len)
6540 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6541 +#define pktq_head(q) ((q)->head)
6542 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6543 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6544 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6545 +
6546 +/* externs */
6547 +/* packet */
6548 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6549 +extern uint pkttotlen(osl_t *osh, void *);
6550 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6551 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6552 +extern void *pktdeq(struct pktq *q);
6553 +extern void *pktdeqtail(struct pktq *q);
6554 +/* string */
6555 +extern uint bcm_atoi(char *s);
6556 +extern uchar bcm_toupper(uchar c);
6557 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6558 +extern char *bcmstrstr(char *haystack, char *needle);
6559 +extern char *bcmstrcat(char *dest, const char *src);
6560 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6561 +/* ethernet address */
6562 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6563 +extern int bcm_ether_atoe(char *p, char *ea);
6564 +/* delay */
6565 +extern void bcm_mdelay(uint ms);
6566 +/* variable access */
6567 +extern char *getvar(char *vars, char *name);
6568 +extern int getintvar(char *vars, char *name);
6569 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6570 +#define bcmlog(fmt, a1, a2)
6571 +#define bcmdumplog(buf, size) *buf = '\0'
6572 +#define bcmdumplogent(buf, idx) -1
6573 +
6574 +/*** driver/apps-shared section ***/
6575 +
6576 +#define BCME_STRLEN 64
6577 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6578 +
6579 +
6580 +/*
6581 + * error codes could be added but the defined ones shouldn't be changed/deleted
6582 + * these error codes are exposed to the user code
6583 + * when ever a new error code is added to this list
6584 + * please update errorstring table with the related error string and
6585 + * update osl files with os specific errorcode map
6586 +*/
6587 +
6588 +#define BCME_ERROR -1 /* Error generic */
6589 +#define BCME_BADARG -2 /* Bad Argument */
6590 +#define BCME_BADOPTION -3 /* Bad option */
6591 +#define BCME_NOTUP -4 /* Not up */
6592 +#define BCME_NOTDOWN -5 /* Not down */
6593 +#define BCME_NOTAP -6 /* Not AP */
6594 +#define BCME_NOTSTA -7 /* Not STA */
6595 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6596 +#define BCME_RADIOOFF -9 /* Radio Off */
6597 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6598 +#define BCME_NOCLK -11 /* No Clock*/
6599 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6600 +#define BCME_BADBAND -13 /* BAD Band */
6601 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6602 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6603 +#define BCME_BUSY -16 /* Busy*/
6604 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6605 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6606 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6607 +#define BCME_BADCHAN -20 /* BAD Channel */
6608 +#define BCME_BADADDR -21 /* BAD Address*/
6609 +#define BCME_NORESOURCE -22 /* No resources*/
6610 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6611 +#define BCME_BADLEN -24 /* Bad Length*/
6612 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6613 +#define BCME_EPERM -26 /* Not Permitted */
6614 +#define BCME_NOMEM -27 /* No Memory */
6615 +#define BCME_ASSOCIATED -28 /* Associated */
6616 +#define BCME_RANGE -29 /* Range Error*/
6617 +#define BCME_NOTFOUND -30 /* Not found */
6618 +#define BCME_LAST BCME_NOTFOUND
6619 +
6620 +#ifndef ABS
6621 +#define ABS(a) (((a)<0)?-(a):(a))
6622 +#endif
6623 +
6624 +#ifndef MIN
6625 +#define MIN(a, b) (((a)<(b))?(a):(b))
6626 +#endif
6627 +
6628 +#ifndef MAX
6629 +#define MAX(a, b) (((a)>(b))?(a):(b))
6630 +#endif
6631 +
6632 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6633 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6634 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6635 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6636 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6637 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6638 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6639 +
6640 +/* bit map related macros */
6641 +#ifndef setbit
6642 +#define NBBY 8 /* 8 bits per byte */
6643 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6644 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6645 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6646 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6647 +#endif
6648 +
6649 +#define NBITS(type) (sizeof(type) * 8)
6650 +#define NBITVAL(bits) (1 << (bits))
6651 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6652 +
6653 +/* crc defines */
6654 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6655 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6656 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6657 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6658 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6659 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6660 +
6661 +/* bcm_format_flags() bit description structure */
6662 +typedef struct bcm_bit_desc {
6663 + uint32 bit;
6664 + char* name;
6665 +} bcm_bit_desc_t;
6666 +
6667 +/* tag_ID/length/value_buffer tuple */
6668 +typedef struct bcm_tlv {
6669 + uint8 id;
6670 + uint8 len;
6671 + uint8 data[1];
6672 +} bcm_tlv_t;
6673 +
6674 +/* Check that bcm_tlv_t fits into the given buflen */
6675 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6676 +
6677 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6678 +#define ETHER_ADDR_STR_LEN 18
6679 +
6680 +/* unaligned load and store macros */
6681 +#ifdef IL_BIGENDIAN
6682 +static INLINE uint32
6683 +load32_ua(uint8 *a)
6684 +{
6685 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6686 +}
6687 +
6688 +static INLINE void
6689 +store32_ua(uint8 *a, uint32 v)
6690 +{
6691 + a[0] = (v >> 24) & 0xff;
6692 + a[1] = (v >> 16) & 0xff;
6693 + a[2] = (v >> 8) & 0xff;
6694 + a[3] = v & 0xff;
6695 +}
6696 +
6697 +static INLINE uint16
6698 +load16_ua(uint8 *a)
6699 +{
6700 + return ((a[0] << 8) | a[1]);
6701 +}
6702 +
6703 +static INLINE void
6704 +store16_ua(uint8 *a, uint16 v)
6705 +{
6706 + a[0] = (v >> 8) & 0xff;
6707 + a[1] = v & 0xff;
6708 +}
6709 +
6710 +#else
6711 +
6712 +static INLINE uint32
6713 +load32_ua(uint8 *a)
6714 +{
6715 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6716 +}
6717 +
6718 +static INLINE void
6719 +store32_ua(uint8 *a, uint32 v)
6720 +{
6721 + a[3] = (v >> 24) & 0xff;
6722 + a[2] = (v >> 16) & 0xff;
6723 + a[1] = (v >> 8) & 0xff;
6724 + a[0] = v & 0xff;
6725 +}
6726 +
6727 +static INLINE uint16
6728 +load16_ua(uint8 *a)
6729 +{
6730 + return ((a[1] << 8) | a[0]);
6731 +}
6732 +
6733 +static INLINE void
6734 +store16_ua(uint8 *a, uint16 v)
6735 +{
6736 + a[1] = (v >> 8) & 0xff;
6737 + a[0] = v & 0xff;
6738 +}
6739 +
6740 +#endif
6741 +
6742 +/* externs */
6743 +/* crc */
6744 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6745 +/* format/print */
6746 +/* IE parsing */
6747 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6748 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6749 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6750 +
6751 +/* bcmerror*/
6752 +extern const char *bcmerrorstr(int bcmerror);
6753 +
6754 +/* multi-bool data type: set of bools, mbool is true if any is set */
6755 +typedef uint32 mbool;
6756 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6757 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6758 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6759 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6760 +
6761 +/* power conversion */
6762 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6763 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6764 +
6765 +/* generic datastruct to help dump routines */
6766 +struct fielddesc {
6767 + char *nameandfmt;
6768 + uint32 offset;
6769 + uint32 len;
6770 +};
6771 +
6772 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6773 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6774 +
6775 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6776 +
6777 +#endif /* _bcmutils_h_ */
6778 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/bitfuncs.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/bitfuncs.h
6779 --- linux-2.6.17/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6780 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/bitfuncs.h 2006-06-18 15:29:23.000000000 +0200
6781 @@ -0,0 +1,85 @@
6782 +/*
6783 + * bit manipulation utility functions
6784 + *
6785 + * Copyright 2005, Broadcom Corporation
6786 + * All Rights Reserved.
6787 + *
6788 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6789 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6790 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6791 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6792 + * $Id$
6793 + */
6794 +
6795 +#ifndef _BITFUNCS_H
6796 +#define _BITFUNCS_H
6797 +
6798 +#include <typedefs.h>
6799 +
6800 +/* local prototypes */
6801 +static INLINE uint32 find_msbit(uint32 x);
6802 +
6803 +
6804 +/*
6805 + * find_msbit: returns index of most significant set bit in x, with index
6806 + * range defined as 0-31. NOTE: returns zero if input is zero.
6807 + */
6808 +
6809 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6810 +
6811 +/*
6812 + * Implementation for Pentium processors and gcc. Note that this
6813 + * instruction is actually very slow on some processors (e.g., family 5,
6814 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6815 + * implementation instead.
6816 + */
6817 +static INLINE uint32 find_msbit(uint32 x)
6818 +{
6819 + uint msbit;
6820 + __asm__("bsrl %1,%0"
6821 + :"=r" (msbit)
6822 + :"r" (x));
6823 + return msbit;
6824 +}
6825 +
6826 +#else
6827 +
6828 +/*
6829 + * Generic Implementation
6830 + */
6831 +
6832 +#define DB_POW_MASK16 0xffff0000
6833 +#define DB_POW_MASK8 0x0000ff00
6834 +#define DB_POW_MASK4 0x000000f0
6835 +#define DB_POW_MASK2 0x0000000c
6836 +#define DB_POW_MASK1 0x00000002
6837 +
6838 +static INLINE uint32 find_msbit(uint32 x)
6839 +{
6840 + uint32 temp_x = x;
6841 + uint msbit = 0;
6842 + if (temp_x & DB_POW_MASK16) {
6843 + temp_x >>= 16;
6844 + msbit = 16;
6845 + }
6846 + if (temp_x & DB_POW_MASK8) {
6847 + temp_x >>= 8;
6848 + msbit += 8;
6849 + }
6850 + if (temp_x & DB_POW_MASK4) {
6851 + temp_x >>= 4;
6852 + msbit += 4;
6853 + }
6854 + if (temp_x & DB_POW_MASK2) {
6855 + temp_x >>= 2;
6856 + msbit += 2;
6857 + }
6858 + if (temp_x & DB_POW_MASK1) {
6859 + msbit += 1;
6860 + }
6861 + return(msbit);
6862 +}
6863 +
6864 +#endif
6865 +
6866 +#endif /* _BITFUNCS_H */
6867 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/flash.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/flash.h
6868 --- linux-2.6.17/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6869 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/flash.h 2006-06-18 15:29:23.000000000 +0200
6870 @@ -0,0 +1,188 @@
6871 +/*
6872 + * flash.h: Common definitions for flash access.
6873 + *
6874 + * Copyright 2005, Broadcom Corporation
6875 + * All Rights Reserved.
6876 + *
6877 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6878 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6879 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6880 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6881 + *
6882 + * $Id$
6883 + */
6884 +
6885 +/* Types of flashes we know about */
6886 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6887 +
6888 +/* Commands to write/erase the flases */
6889 +typedef struct _flash_cmds{
6890 + flash_type_t type;
6891 + bool need_unlock;
6892 + uint16 pre_erase;
6893 + uint16 erase_block;
6894 + uint16 erase_chip;
6895 + uint16 write_word;
6896 + uint16 write_buf;
6897 + uint16 clear_csr;
6898 + uint16 read_csr;
6899 + uint16 read_id;
6900 + uint16 confirm;
6901 + uint16 read_array;
6902 +} flash_cmds_t;
6903 +
6904 +#define UNLOCK_CMD_WORDS 2
6905 +
6906 +typedef struct _unlock_cmd {
6907 + uint addr[UNLOCK_CMD_WORDS];
6908 + uint16 cmd[UNLOCK_CMD_WORDS];
6909 +} unlock_cmd_t;
6910 +
6911 +/* Flash descriptors */
6912 +typedef struct _flash_desc {
6913 + uint16 mfgid; /* Manufacturer Id */
6914 + uint16 devid; /* Device Id */
6915 + uint size; /* Total size in bytes */
6916 + uint width; /* Device width in bytes */
6917 + flash_type_t type; /* Device type old, S, J */
6918 + uint bsize; /* Block size */
6919 + uint nb; /* Number of blocks */
6920 + uint ff; /* First full block */
6921 + uint lf; /* Last full block */
6922 + uint nsub; /* Number of subblocks */
6923 + uint *subblocks; /* Offsets for subblocks */
6924 + char *desc; /* Description */
6925 +} flash_desc_t;
6926 +
6927 +
6928 +#ifdef DECLARE_FLASHES
6929 +flash_cmds_t sflash_cmd_t =
6930 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6931 +
6932 +flash_cmds_t flash_cmds[] = {
6933 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6934 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6935 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6936 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6937 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6938 + { 0 }
6939 +};
6940 +
6941 +unlock_cmd_t unlock_cmd_amd = {
6942 +#ifdef MIPSEB
6943 +/* addr: */ { 0x0aa8, 0x0556},
6944 +#else
6945 +/* addr: */ { 0x0aaa, 0x0554},
6946 +#endif
6947 +/* data: */ { 0xaa, 0x55}
6948 +};
6949 +
6950 +unlock_cmd_t unlock_cmd_sst = {
6951 +#ifdef MIPSEB
6952 +/* addr: */ { 0xaaa8, 0x5556},
6953 +#else
6954 +/* addr: */ { 0xaaaa, 0x5554},
6955 +#endif
6956 +/* data: */ { 0xaa, 0x55}
6957 +};
6958 +
6959 +#define AMD_CMD 0xaaa
6960 +#define SST_CMD 0xaaaa
6961 +
6962 +/* intel unlock block cmds */
6963 +#define INTEL_UNLOCK1 0x60
6964 +#define INTEL_UNLOCK2 0xD0
6965 +
6966 +/* Just eight blocks of 8KB byte each */
6967 +
6968 +uint blk8x8k[] = { 0x00000000,
6969 + 0x00002000,
6970 + 0x00004000,
6971 + 0x00006000,
6972 + 0x00008000,
6973 + 0x0000a000,
6974 + 0x0000c000,
6975 + 0x0000e000,
6976 + 0x00010000
6977 +};
6978 +
6979 +/* Funky AMD arrangement for 29xx800's */
6980 +uint amd800[] = { 0x00000000, /* 16KB */
6981 + 0x00004000, /* 32KB */
6982 + 0x0000c000, /* 8KB */
6983 + 0x0000e000, /* 8KB */
6984 + 0x00010000, /* 8KB */
6985 + 0x00012000, /* 8KB */
6986 + 0x00014000, /* 32KB */
6987 + 0x0001c000, /* 16KB */
6988 + 0x00020000
6989 +};
6990 +
6991 +/* AMD arrangement for 29xx160's */
6992 +uint amd4112[] = { 0x00000000, /* 32KB */
6993 + 0x00008000, /* 8KB */
6994 + 0x0000a000, /* 8KB */
6995 + 0x0000c000, /* 16KB */
6996 + 0x00010000
6997 +};
6998 +uint amd2114[] = { 0x00000000, /* 16KB */
6999 + 0x00004000, /* 8KB */
7000 + 0x00006000, /* 8KB */
7001 + 0x00008000, /* 32KB */
7002 + 0x00010000
7003 +};
7004 +
7005 +
7006 +flash_desc_t sflash_desc =
7007 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7008 +
7009 +flash_desc_t flashes[] = {
7010 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7011 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7012 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7013 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7014 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7015 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7016 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7017 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7018 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7019 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7020 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7021 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7022 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7023 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7024 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7025 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7026 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7027 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7028 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7029 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7030 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7031 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7032 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7033 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7034 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7035 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7036 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7037 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7038 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7039 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7040 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7041 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7042 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7043 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7044 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7045 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7046 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7047 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7048 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7049 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7050 +};
7051 +
7052 +#else
7053 +
7054 +extern flash_cmds_t flash_cmds[];
7055 +extern unlock_cmd_t unlock_cmd;
7056 +extern flash_desc_t flashes[];
7057 +
7058 +#endif
7059 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/flashutl.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/flashutl.h
7060 --- linux-2.6.17/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7061 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/flashutl.h 2006-06-18 15:29:23.000000000 +0200
7062 @@ -0,0 +1,27 @@
7063 +/*
7064 + * BCM47XX FLASH driver interface
7065 + *
7066 + * Copyright 2005, Broadcom Corporation
7067 + * All Rights Reserved.
7068 + *
7069 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7070 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7071 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7072 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7073 + * $Id$
7074 + */
7075 +
7076 +#ifndef _flashutl_h_
7077 +#define _flashutl_h_
7078 +
7079 +
7080 +#ifndef _LANGUAGE_ASSEMBLY
7081 +
7082 +int sysFlashInit(char *flash_str);
7083 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7084 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7085 +void nvWrite(unsigned short *data, unsigned int len);
7086 +
7087 +#endif /* _LANGUAGE_ASSEMBLY */
7088 +
7089 +#endif /* _flashutl_h_ */
7090 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/hndmips.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/hndmips.h
7091 --- linux-2.6.17/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7092 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/hndmips.h 2006-06-18 15:29:23.000000000 +0200
7093 @@ -0,0 +1,16 @@
7094 +/*
7095 + * Alternate include file for HND sbmips.h since CFE also ships with
7096 + * a sbmips.h.
7097 + *
7098 + * Copyright 2005, Broadcom Corporation
7099 + * All Rights Reserved.
7100 + *
7101 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7102 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7103 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7104 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7105 + *
7106 + * $Id$
7107 + */
7108 +
7109 +#include "sbmips.h"
7110 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/linux_osl.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/linux_osl.h
7111 --- linux-2.6.17/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7112 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/linux_osl.h 2006-06-18 15:29:23.000000000 +0200
7113 @@ -0,0 +1,331 @@
7114 +/*
7115 + * Linux OS Independent Layer
7116 + *
7117 + * Copyright 2005, Broadcom Corporation
7118 + * All Rights Reserved.
7119 + *
7120 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7121 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7122 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7123 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7124 + *
7125 + * $Id$
7126 + */
7127 +
7128 +#ifndef _linux_osl_h_
7129 +#define _linux_osl_h_
7130 +
7131 +#include <typedefs.h>
7132 +
7133 +/* use current 2.4.x calling conventions */
7134 +#include <linuxver.h>
7135 +
7136 +/* assert and panic */
7137 +#ifdef __GNUC__
7138 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7139 +#if GCC_VERSION > 30100
7140 +#define ASSERT(exp) do {} while (0)
7141 +#else
7142 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7143 +#define ASSERT(exp)
7144 +#endif
7145 +#endif
7146 +
7147 +/* microsecond delay */
7148 +#define OSL_DELAY(usec) osl_delay(usec)
7149 +extern void osl_delay(uint usec);
7150 +
7151 +/* PCI configuration space access macros */
7152 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7153 + osl_pci_read_config((osh), (offset), (size))
7154 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7155 + osl_pci_write_config((osh), (offset), (size), (val))
7156 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7157 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7158 +
7159 +/* PCI device bus # and slot # */
7160 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7161 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7162 +extern uint osl_pci_bus(osl_t *osh);
7163 +extern uint osl_pci_slot(osl_t *osh);
7164 +
7165 +/* OSL initialization */
7166 +extern osl_t *osl_attach(void *pdev);
7167 +extern void osl_detach(osl_t *osh);
7168 +
7169 +/* host/bus architecture-specific byte swap */
7170 +#define BUS_SWAP32(v) (v)
7171 +
7172 +/* general purpose memory allocation */
7173 +
7174 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7175 +#define MFREE(osh, addr, size) kfree(addr);
7176 +
7177 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7178 +
7179 +extern void *osl_malloc(osl_t *osh, uint size);
7180 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7181 +extern uint osl_malloced(osl_t *osh);
7182 +extern uint osl_malloc_failed(osl_t *osh);
7183 +
7184 +/* allocate/free shared (dma-able) consistent memory */
7185 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7186 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7187 + osl_dma_alloc_consistent((osh), (size), (pap))
7188 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7189 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7190 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7191 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7192 +
7193 +/* map/unmap direction */
7194 +#define DMA_TX 1
7195 +#define DMA_RX 2
7196 +
7197 +/* register access macros */
7198 +#if defined(BCMJTAG)
7199 +#include <bcmjtag.h>
7200 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7201 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7202 +#endif
7203 +
7204 +/*
7205 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7206 + * Macros expand to calls to functions defined in linux_osl.c .
7207 + */
7208 +#ifndef BINOSL
7209 +
7210 +/* string library, kernel mode */
7211 +#define printf(fmt, args...) printk(fmt, ## args)
7212 +#include <linux/kernel.h>
7213 +#include <linux/string.h>
7214 +
7215 +/* register access macros */
7216 +#if !defined(BCMJTAG)
7217 +#ifndef IL_BIGENDIAN
7218 +#define R_REG(r) ( \
7219 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7220 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7221 + readl((volatile uint32*)(r)) \
7222 +)
7223 +#define W_REG(r, v) do { \
7224 + switch (sizeof(*(r))) { \
7225 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7226 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7227 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7228 + } \
7229 +} while (0)
7230 +#else /* IL_BIGENDIAN */
7231 +#define R_REG(r) ({ \
7232 + __typeof(*(r)) __osl_v; \
7233 + switch (sizeof(*(r))) { \
7234 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7235 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7236 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7237 + } \
7238 + __osl_v; \
7239 +})
7240 +#define W_REG(r, v) do { \
7241 + switch (sizeof(*(r))) { \
7242 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7243 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7244 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7245 + } \
7246 +} while (0)
7247 +#endif
7248 +#endif
7249 +
7250 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7251 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7252 +
7253 +/* bcopy, bcmp, and bzero */
7254 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7255 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7256 +#define bzero(b, len) memset((b), '\0', (len))
7257 +
7258 +/* uncached virtual address */
7259 +#ifdef mips
7260 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7261 +#include <asm/addrspace.h>
7262 +#else
7263 +#define OSL_UNCACHED(va) (va)
7264 +#endif
7265 +
7266 +/* get processor cycle count */
7267 +#if defined(mips)
7268 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7269 +#elif defined(__i386__)
7270 +#define OSL_GETCYCLES(x) rdtscl((x))
7271 +#else
7272 +#define OSL_GETCYCLES(x) ((x) = 0)
7273 +#endif
7274 +
7275 +/* dereference an address that may cause a bus exception */
7276 +#ifdef mips
7277 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7278 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7279 +#else
7280 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7281 +#include <asm/paccess.h>
7282 +#endif
7283 +#else
7284 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7285 +#endif
7286 +
7287 +/* map/unmap physical to virtual I/O */
7288 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7289 +#define REG_UNMAP(va) iounmap((void *)(va))
7290 +
7291 +/* shared (dma-able) memory access macros */
7292 +#define R_SM(r) *(r)
7293 +#define W_SM(r, v) (*(r) = (v))
7294 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7295 +
7296 +/* packet primitives */
7297 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7298 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7299 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7300 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7301 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7302 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7303 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7304 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7305 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7306 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7307 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7308 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7309 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7310 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7311 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7312 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7313 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7314 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7315 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7316 +extern void osl_pktfree(void *skb);
7317 +
7318 +#else /* BINOSL */
7319 +
7320 +/* string library */
7321 +#ifndef LINUX_OSL
7322 +#undef printf
7323 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7324 +#undef sprintf
7325 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7326 +#undef strcmp
7327 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7328 +#undef strncmp
7329 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7330 +#undef strlen
7331 +#define strlen(s) osl_strlen((s))
7332 +#undef strcpy
7333 +#define strcpy(d, s) osl_strcpy((d), (s))
7334 +#undef strncpy
7335 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7336 +#endif
7337 +extern int osl_printf(const char *format, ...);
7338 +extern int osl_sprintf(char *buf, const char *format, ...);
7339 +extern int osl_strcmp(const char *s1, const char *s2);
7340 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7341 +extern int osl_strlen(const char *s);
7342 +extern char* osl_strcpy(char *d, const char *s);
7343 +extern char* osl_strncpy(char *d, const char *s, uint n);
7344 +
7345 +/* register access macros */
7346 +#if !defined(BCMJTAG)
7347 +#define R_REG(r) ( \
7348 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7349 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7350 + osl_readl((volatile uint32*)(r)) \
7351 +)
7352 +#define W_REG(r, v) do { \
7353 + switch (sizeof(*(r))) { \
7354 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7355 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7356 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7357 + } \
7358 +} while (0)
7359 +#endif
7360 +
7361 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7362 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7363 +extern uint8 osl_readb(volatile uint8 *r);
7364 +extern uint16 osl_readw(volatile uint16 *r);
7365 +extern uint32 osl_readl(volatile uint32 *r);
7366 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7367 +extern void osl_writew(uint16 v, volatile uint16 *r);
7368 +extern void osl_writel(uint32 v, volatile uint32 *r);
7369 +
7370 +/* bcopy, bcmp, and bzero */
7371 +extern void bcopy(const void *src, void *dst, int len);
7372 +extern int bcmp(const void *b1, const void *b2, int len);
7373 +extern void bzero(void *b, int len);
7374 +
7375 +/* uncached virtual address */
7376 +#define OSL_UNCACHED(va) osl_uncached((va))
7377 +extern void *osl_uncached(void *va);
7378 +
7379 +/* get processor cycle count */
7380 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7381 +extern uint osl_getcycles(void);
7382 +
7383 +/* dereference an address that may target abort */
7384 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7385 +extern int osl_busprobe(uint32 *val, uint32 addr);
7386 +
7387 +/* map/unmap physical to virtual */
7388 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7389 +#define REG_UNMAP(va) osl_reg_unmap((va))
7390 +extern void *osl_reg_map(uint32 pa, uint size);
7391 +extern void osl_reg_unmap(void *va);
7392 +
7393 +/* shared (dma-able) memory access macros */
7394 +#define R_SM(r) *(r)
7395 +#define W_SM(r, v) (*(r) = (v))
7396 +#define BZERO_SM(r, len) bzero((r), (len))
7397 +
7398 +/* packet primitives */
7399 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7400 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7401 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7402 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7403 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7404 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7405 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7406 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7407 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7408 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7409 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7410 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7411 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7412 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7413 +#define PKTLINK(skb) osl_pktlink((skb))
7414 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7415 +#define PKTPRIO(skb) osl_pktprio((skb))
7416 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7417 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7418 +extern void osl_pktfree(void *skb);
7419 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7420 +extern uint osl_pktlen(osl_t *osh, void *skb);
7421 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7422 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7423 +extern void *osl_pktnext(osl_t *osh, void *skb);
7424 +extern void osl_pktsetnext(void *skb, void *x);
7425 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7426 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7427 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7428 +extern void *osl_pktdup(osl_t *osh, void *skb);
7429 +extern void *osl_pktcookie(void *skb);
7430 +extern void osl_pktsetcookie(void *skb, void *x);
7431 +extern void *osl_pktlink(void *skb);
7432 +extern void osl_pktsetlink(void *skb, void *x);
7433 +extern uint osl_pktprio(void *skb);
7434 +extern void osl_pktsetprio(void *skb, uint x);
7435 +
7436 +#endif /* BINOSL */
7437 +
7438 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7439 +extern int osl_error(int bcmerror);
7440 +
7441 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7442 +#define PKTBUFSZ 2048
7443 +
7444 +#endif /* _linux_osl_h_ */
7445 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/linuxver.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/linuxver.h
7446 --- linux-2.6.17/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7447 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/linuxver.h 2006-06-18 15:29:23.000000000 +0200
7448 @@ -0,0 +1,389 @@
7449 +/*
7450 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7451 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7452 + *
7453 + * Copyright 2005, Broadcom Corporation
7454 + * All Rights Reserved.
7455 + *
7456 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7457 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7458 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7459 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7460 + *
7461 + * $Id$
7462 + */
7463 +
7464 +#ifndef _linuxver_h_
7465 +#define _linuxver_h_
7466 +
7467 +#include <linux/config.h>
7468 +#include <linux/version.h>
7469 +
7470 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7471 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7472 +#ifdef __UNDEF_NO_VERSION__
7473 +#undef __NO_VERSION__
7474 +#else
7475 +#define __NO_VERSION__
7476 +#endif
7477 +#endif
7478 +
7479 +#if defined(MODULE) && defined(MODVERSIONS)
7480 +#include <linux/modversions.h>
7481 +#endif
7482 +
7483 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7484 +#include <linux/moduleparam.h>
7485 +#endif
7486 +
7487 +
7488 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7489 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7490 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7491 +#endif
7492 +
7493 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7494 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7495 +#include <linux/malloc.h>
7496 +#else
7497 +#include <linux/slab.h>
7498 +#endif
7499 +
7500 +#include <linux/types.h>
7501 +#include <linux/init.h>
7502 +#include <linux/mm.h>
7503 +#include <linux/string.h>
7504 +#include <linux/pci.h>
7505 +#include <linux/interrupt.h>
7506 +#include <linux/netdevice.h>
7507 +#include <asm/io.h>
7508 +
7509 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7510 +#include <linux/workqueue.h>
7511 +#else
7512 +#include <linux/tqueue.h>
7513 +#ifndef work_struct
7514 +#define work_struct tq_struct
7515 +#endif
7516 +#ifndef INIT_WORK
7517 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7518 +#endif
7519 +#ifndef schedule_work
7520 +#define schedule_work(_work) schedule_task((_work))
7521 +#endif
7522 +#ifndef flush_scheduled_work
7523 +#define flush_scheduled_work() flush_scheduled_tasks()
7524 +#endif
7525 +#endif
7526 +
7527 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7528 +/* Some distributions have their own 2.6.x compatibility layers */
7529 +#ifndef IRQ_NONE
7530 +typedef void irqreturn_t;
7531 +#define IRQ_NONE
7532 +#define IRQ_HANDLED
7533 +#define IRQ_RETVAL(x)
7534 +#endif
7535 +#else
7536 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7537 +#endif
7538 +
7539 +#ifndef __exit
7540 +#define __exit
7541 +#endif
7542 +#ifndef __devexit
7543 +#define __devexit
7544 +#endif
7545 +#ifndef __devinit
7546 +#define __devinit __init
7547 +#endif
7548 +#ifndef __devinitdata
7549 +#define __devinitdata
7550 +#endif
7551 +#ifndef __devexit_p
7552 +#define __devexit_p(x) x
7553 +#endif
7554 +
7555 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7556 +
7557 +#define pci_get_drvdata(dev) (dev)->sysdata
7558 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7559 +
7560 +/*
7561 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7562 + */
7563 +
7564 +struct pci_device_id {
7565 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7566 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7567 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7568 + unsigned long driver_data; /* Data private to the driver */
7569 +};
7570 +
7571 +struct pci_driver {
7572 + struct list_head node;
7573 + char *name;
7574 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7575 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7576 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7577 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7578 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7579 +};
7580 +
7581 +#define MODULE_DEVICE_TABLE(type, name)
7582 +#define PCI_ANY_ID (~0)
7583 +
7584 +/* compatpci.c */
7585 +#define pci_module_init pci_register_driver
7586 +extern int pci_register_driver(struct pci_driver *drv);
7587 +extern void pci_unregister_driver(struct pci_driver *drv);
7588 +
7589 +#endif /* PCI registration */
7590 +
7591 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7592 +#ifdef MODULE
7593 +#define module_init(x) int init_module(void) { return x(); }
7594 +#define module_exit(x) void cleanup_module(void) { x(); }
7595 +#else
7596 +#define module_init(x) __initcall(x);
7597 +#define module_exit(x) __exitcall(x);
7598 +#endif
7599 +#endif
7600 +
7601 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7602 +#define list_for_each(pos, head) \
7603 + for (pos = (head)->next; pos != (head); pos = pos->next)
7604 +#endif
7605 +
7606 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7607 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7608 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7609 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7610 +#endif
7611 +
7612 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7613 +#define pci_enable_device(dev) do { } while (0)
7614 +#endif
7615 +
7616 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7617 +#define net_device device
7618 +#endif
7619 +
7620 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7621 +
7622 +/*
7623 + * DMA mapping
7624 + *
7625 + * See linux/Documentation/DMA-mapping.txt
7626 + */
7627 +
7628 +#ifndef PCI_DMA_TODEVICE
7629 +#define PCI_DMA_TODEVICE 1
7630 +#define PCI_DMA_FROMDEVICE 2
7631 +#endif
7632 +
7633 +typedef u32 dma_addr_t;
7634 +
7635 +/* Pure 2^n version of get_order */
7636 +static inline int get_order(unsigned long size)
7637 +{
7638 + int order;
7639 +
7640 + size = (size-1) >> (PAGE_SHIFT-1);
7641 + order = -1;
7642 + do {
7643 + size >>= 1;
7644 + order++;
7645 + } while (size);
7646 + return order;
7647 +}
7648 +
7649 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7650 + dma_addr_t *dma_handle)
7651 +{
7652 + void *ret;
7653 + int gfp = GFP_ATOMIC | GFP_DMA;
7654 +
7655 + ret = (void *)__get_free_pages(gfp, get_order(size));
7656 +
7657 + if (ret != NULL) {
7658 + memset(ret, 0, size);
7659 + *dma_handle = virt_to_bus(ret);
7660 + }
7661 + return ret;
7662 +}
7663 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7664 + void *vaddr, dma_addr_t dma_handle)
7665 +{
7666 + free_pages((unsigned long)vaddr, get_order(size));
7667 +}
7668 +#ifdef ILSIM
7669 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7670 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7671 +#else
7672 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7673 +#define pci_unmap_single(cookie, address, size, dir)
7674 +#endif
7675 +
7676 +#endif /* DMA mapping */
7677 +
7678 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7679 +
7680 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7681 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7682 +
7683 +/* pcmcia-cs provides its own netdevice compatibility layer */
7684 +#ifndef _COMPAT_NETDEVICE_H
7685 +
7686 +/*
7687 + * SoftNet
7688 + *
7689 + * For pre-softnet kernels we need to tell the upper layer not to
7690 + * re-enter start_xmit() while we are in there. However softnet
7691 + * guarantees not to enter while we are in there so there is no need
7692 + * to do the netif_stop_queue() dance unless the transmit queue really
7693 + * gets stuck. This should also improve performance according to tests
7694 + * done by Aman Singla.
7695 + */
7696 +
7697 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7698 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7699 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7700 +
7701 +static inline void netif_start_queue(struct net_device *dev)
7702 +{
7703 + dev->tbusy = 0;
7704 + dev->interrupt = 0;
7705 + dev->start = 1;
7706 +}
7707 +
7708 +#define netif_queue_stopped(dev) (dev)->tbusy
7709 +#define netif_running(dev) (dev)->start
7710 +
7711 +#endif /* _COMPAT_NETDEVICE_H */
7712 +
7713 +#define netif_device_attach(dev) netif_start_queue(dev)
7714 +#define netif_device_detach(dev) netif_stop_queue(dev)
7715 +
7716 +/* 2.4.x renamed bottom halves to tasklets */
7717 +#define tasklet_struct tq_struct
7718 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7719 +{
7720 + queue_task(tasklet, &tq_immediate);
7721 + mark_bh(IMMEDIATE_BH);
7722 +}
7723 +
7724 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7725 + void (*func)(unsigned long),
7726 + unsigned long data)
7727 +{
7728 + tasklet->next = NULL;
7729 + tasklet->sync = 0;
7730 + tasklet->routine = (void (*)(void *))func;
7731 + tasklet->data = (void *)data;
7732 +}
7733 +#define tasklet_kill(tasklet) {do{} while(0);}
7734 +
7735 +/* 2.4.x introduced del_timer_sync() */
7736 +#define del_timer_sync(timer) del_timer(timer)
7737 +
7738 +#else
7739 +
7740 +#define netif_down(dev)
7741 +
7742 +#endif /* SoftNet */
7743 +
7744 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7745 +
7746 +/*
7747 + * Emit code to initialise a tq_struct's routine and data pointers
7748 + */
7749 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7750 + do { \
7751 + (_tq)->routine = _routine; \
7752 + (_tq)->data = _data; \
7753 + } while (0)
7754 +
7755 +/*
7756 + * Emit code to initialise all of a tq_struct
7757 + */
7758 +#define INIT_TQUEUE(_tq, _routine, _data) \
7759 + do { \
7760 + INIT_LIST_HEAD(&(_tq)->list); \
7761 + (_tq)->sync = 0; \
7762 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7763 + } while (0)
7764 +
7765 +#endif
7766 +
7767 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7768 +
7769 +/* Power management related routines */
7770 +
7771 +static inline int
7772 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7773 +{
7774 + int i;
7775 + if (buffer) {
7776 + for (i = 0; i < 16; i++)
7777 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7778 + }
7779 + return 0;
7780 +}
7781 +
7782 +static inline int
7783 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7784 +{
7785 + int i;
7786 +
7787 + if (buffer) {
7788 + for (i = 0; i < 16; i++)
7789 + pci_write_config_dword(dev,i * 4, buffer[i]);
7790 + }
7791 + /*
7792 + * otherwise, write the context information we know from bootup.
7793 + * This works around a problem where warm-booting from Windows
7794 + * combined with a D3(hot)->D0 transition causes PCI config
7795 + * header data to be forgotten.
7796 + */
7797 + else {
7798 + for (i = 0; i < 6; i ++)
7799 + pci_write_config_dword(dev,
7800 + PCI_BASE_ADDRESS_0 + (i * 4),
7801 + pci_resource_start(dev, i));
7802 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7803 + }
7804 + return 0;
7805 +}
7806 +
7807 +#endif /* PCI power management */
7808 +
7809 +/* Old cp0 access macros deprecated in 2.4.19 */
7810 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7811 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7812 +#endif
7813 +
7814 +/* Module refcount handled internally in 2.6.x */
7815 +#ifndef SET_MODULE_OWNER
7816 +#define SET_MODULE_OWNER(dev) do {} while (0)
7817 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7818 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7819 +#else
7820 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7821 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7822 +#endif
7823 +
7824 +#ifndef SET_NETDEV_DEV
7825 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7826 +#endif
7827 +
7828 +#ifndef HAVE_FREE_NETDEV
7829 +#define free_netdev(dev) kfree(dev)
7830 +#endif
7831 +
7832 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7833 +/* struct packet_type redefined in 2.6.x */
7834 +#define af_packet_priv data
7835 +#endif
7836 +
7837 +#endif /* _linuxver_h_ */
7838 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/mipsinc.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/mipsinc.h
7839 --- linux-2.6.17/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7840 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/mipsinc.h 2006-06-18 15:29:23.000000000 +0200
7841 @@ -0,0 +1,552 @@
7842 +/*
7843 + * HND Run Time Environment for standalone MIPS programs.
7844 + *
7845 + * Copyright 2005, Broadcom Corporation
7846 + * All Rights Reserved.
7847 + *
7848 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7849 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7850 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7851 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7852 + *
7853 + * $Id$
7854 + */
7855 +
7856 +#ifndef _MISPINC_H
7857 +#define _MISPINC_H
7858 +
7859 +
7860 +/* MIPS defines */
7861 +
7862 +#ifdef _LANGUAGE_ASSEMBLY
7863 +
7864 +/*
7865 + * Symbolic register names for 32 bit ABI
7866 + */
7867 +#define zero $0 /* wired zero */
7868 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7869 +#define v0 $2 /* return value */
7870 +#define v1 $3
7871 +#define a0 $4 /* argument registers */
7872 +#define a1 $5
7873 +#define a2 $6
7874 +#define a3 $7
7875 +#define t0 $8 /* caller saved */
7876 +#define t1 $9
7877 +#define t2 $10
7878 +#define t3 $11
7879 +#define t4 $12
7880 +#define t5 $13
7881 +#define t6 $14
7882 +#define t7 $15
7883 +#define s0 $16 /* callee saved */
7884 +#define s1 $17
7885 +#define s2 $18
7886 +#define s3 $19
7887 +#define s4 $20
7888 +#define s5 $21
7889 +#define s6 $22
7890 +#define s7 $23
7891 +#define t8 $24 /* caller saved */
7892 +#define t9 $25
7893 +#define jp $25 /* PIC jump register */
7894 +#define k0 $26 /* kernel scratch */
7895 +#define k1 $27
7896 +#define gp $28 /* global pointer */
7897 +#define sp $29 /* stack pointer */
7898 +#define fp $30 /* frame pointer */
7899 +#define s8 $30 /* same like fp! */
7900 +#define ra $31 /* return address */
7901 +
7902 +
7903 +/*
7904 + * CP0 Registers
7905 + */
7906 +
7907 +#define C0_INX $0
7908 +#define C0_RAND $1
7909 +#define C0_TLBLO0 $2
7910 +#define C0_TLBLO C0_TLBLO0
7911 +#define C0_TLBLO1 $3
7912 +#define C0_CTEXT $4
7913 +#define C0_PGMASK $5
7914 +#define C0_WIRED $6
7915 +#define C0_BADVADDR $8
7916 +#define C0_COUNT $9
7917 +#define C0_TLBHI $10
7918 +#define C0_COMPARE $11
7919 +#define C0_SR $12
7920 +#define C0_STATUS C0_SR
7921 +#define C0_CAUSE $13
7922 +#define C0_EPC $14
7923 +#define C0_PRID $15
7924 +#define C0_CONFIG $16
7925 +#define C0_LLADDR $17
7926 +#define C0_WATCHLO $18
7927 +#define C0_WATCHHI $19
7928 +#define C0_XCTEXT $20
7929 +#define C0_DIAGNOSTIC $22
7930 +#define C0_BROADCOM C0_DIAGNOSTIC
7931 +#define C0_PERFORMANCE $25
7932 +#define C0_ECC $26
7933 +#define C0_CACHEERR $27
7934 +#define C0_TAGLO $28
7935 +#define C0_TAGHI $29
7936 +#define C0_ERREPC $30
7937 +#define C0_DESAVE $31
7938 +
7939 +/*
7940 + * LEAF - declare leaf routine
7941 + */
7942 +#define LEAF(symbol) \
7943 + .globl symbol; \
7944 + .align 2; \
7945 + .type symbol,@function; \
7946 + .ent symbol,0; \
7947 +symbol: .frame sp,0,ra
7948 +
7949 +/*
7950 + * END - mark end of function
7951 + */
7952 +#define END(function) \
7953 + .end function; \
7954 + .size function,.-function
7955 +
7956 +#define _ULCAST_
7957 +
7958 +#else
7959 +
7960 +/*
7961 + * The following macros are especially useful for __asm__
7962 + * inline assembler.
7963 + */
7964 +#ifndef __STR
7965 +#define __STR(x) #x
7966 +#endif
7967 +#ifndef STR
7968 +#define STR(x) __STR(x)
7969 +#endif
7970 +
7971 +#define _ULCAST_ (unsigned long)
7972 +
7973 +
7974 +/*
7975 + * CP0 Registers
7976 + */
7977 +
7978 +#define C0_INX 0 /* CP0: TLB Index */
7979 +#define C0_RAND 1 /* CP0: TLB Random */
7980 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
7981 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
7982 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
7983 +#define C0_CTEXT 4 /* CP0: Context */
7984 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
7985 +#define C0_WIRED 6 /* CP0: TLB Wired */
7986 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
7987 +#define C0_COUNT 9 /* CP0: Count */
7988 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
7989 +#define C0_COMPARE 11 /* CP0: Compare */
7990 +#define C0_SR 12 /* CP0: Processor Status */
7991 +#define C0_STATUS C0_SR /* CP0: Processor Status */
7992 +#define C0_CAUSE 13 /* CP0: Exception Cause */
7993 +#define C0_EPC 14 /* CP0: Exception PC */
7994 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
7995 +#define C0_CONFIG 16 /* CP0: Config */
7996 +#define C0_LLADDR 17 /* CP0: LLAddr */
7997 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
7998 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
7999 +#define C0_XCTEXT 20 /* CP0: XContext */
8000 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
8001 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
8002 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
8003 +#define C0_ECC 26 /* CP0: ECC */
8004 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8005 +#define C0_TAGLO 28 /* CP0: TagLo */
8006 +#define C0_TAGHI 29 /* CP0: TagHi */
8007 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8008 +#define C0_DESAVE 31 /* CP0: DebugSave */
8009 +
8010 +#endif /* _LANGUAGE_ASSEMBLY */
8011 +
8012 +/*
8013 + * Memory segments (32bit kernel mode addresses)
8014 + */
8015 +#undef KUSEG
8016 +#undef KSEG0
8017 +#undef KSEG1
8018 +#undef KSEG2
8019 +#undef KSEG3
8020 +#define KUSEG 0x00000000
8021 +#define KSEG0 0x80000000
8022 +#define KSEG1 0xa0000000
8023 +#define KSEG2 0xc0000000
8024 +#define KSEG3 0xe0000000
8025 +#define PHYSADDR_MASK 0x1fffffff
8026 +
8027 +/*
8028 + * Map an address to a certain kernel segment
8029 + */
8030 +#undef PHYSADDR
8031 +#undef KSEG0ADDR
8032 +#undef KSEG1ADDR
8033 +#undef KSEG2ADDR
8034 +#undef KSEG3ADDR
8035 +
8036 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8037 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8038 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8039 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8040 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8041 +
8042 +
8043 +#ifndef Index_Invalidate_I
8044 +/*
8045 + * Cache Operations
8046 + */
8047 +#define Index_Invalidate_I 0x00
8048 +#define Index_Writeback_Inv_D 0x01
8049 +#define Index_Invalidate_SI 0x02
8050 +#define Index_Writeback_Inv_SD 0x03
8051 +#define Index_Load_Tag_I 0x04
8052 +#define Index_Load_Tag_D 0x05
8053 +#define Index_Load_Tag_SI 0x06
8054 +#define Index_Load_Tag_SD 0x07
8055 +#define Index_Store_Tag_I 0x08
8056 +#define Index_Store_Tag_D 0x09
8057 +#define Index_Store_Tag_SI 0x0A
8058 +#define Index_Store_Tag_SD 0x0B
8059 +#define Create_Dirty_Excl_D 0x0d
8060 +#define Create_Dirty_Excl_SD 0x0f
8061 +#define Hit_Invalidate_I 0x10
8062 +#define Hit_Invalidate_D 0x11
8063 +#define Hit_Invalidate_SI 0x12
8064 +#define Hit_Invalidate_SD 0x13
8065 +#define Fill_I 0x14
8066 +#define Hit_Writeback_Inv_D 0x15
8067 + /* 0x16 is unused */
8068 +#define Hit_Writeback_Inv_SD 0x17
8069 +#define R5K_Page_Invalidate_S 0x17
8070 +#define Hit_Writeback_I 0x18
8071 +#define Hit_Writeback_D 0x19
8072 + /* 0x1a is unused */
8073 +#define Hit_Writeback_SD 0x1b
8074 + /* 0x1c is unused */
8075 + /* 0x1e is unused */
8076 +#define Hit_Set_Virtual_SI 0x1e
8077 +#define Hit_Set_Virtual_SD 0x1f
8078 +#endif
8079 +
8080 +
8081 +/*
8082 + * R4x00 interrupt enable / cause bits
8083 + */
8084 +#define IE_SW0 (_ULCAST_(1) << 8)
8085 +#define IE_SW1 (_ULCAST_(1) << 9)
8086 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8087 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8088 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8089 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8090 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8091 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8092 +
8093 +#ifndef ST0_UM
8094 +/*
8095 + * Bitfields in the mips32 cp0 status register
8096 + */
8097 +#define ST0_IE 0x00000001
8098 +#define ST0_EXL 0x00000002
8099 +#define ST0_ERL 0x00000004
8100 +#define ST0_UM 0x00000010
8101 +#define ST0_SWINT0 0x00000100
8102 +#define ST0_SWINT1 0x00000200
8103 +#define ST0_HWINT0 0x00000400
8104 +#define ST0_HWINT1 0x00000800
8105 +#define ST0_HWINT2 0x00001000
8106 +#define ST0_HWINT3 0x00002000
8107 +#define ST0_HWINT4 0x00004000
8108 +#define ST0_HWINT5 0x00008000
8109 +#define ST0_IM 0x0000ff00
8110 +#define ST0_NMI 0x00080000
8111 +#define ST0_SR 0x00100000
8112 +#define ST0_TS 0x00200000
8113 +#define ST0_BEV 0x00400000
8114 +#define ST0_RE 0x02000000
8115 +#define ST0_RP 0x08000000
8116 +#define ST0_CU 0xf0000000
8117 +#define ST0_CU0 0x10000000
8118 +#define ST0_CU1 0x20000000
8119 +#define ST0_CU2 0x40000000
8120 +#define ST0_CU3 0x80000000
8121 +#endif
8122 +
8123 +
8124 +/*
8125 + * Bitfields in the mips32 cp0 cause register
8126 + */
8127 +#define C_EXC 0x0000007c
8128 +#define C_EXC_SHIFT 2
8129 +#define C_INT 0x0000ff00
8130 +#define C_INT_SHIFT 8
8131 +#define C_SW0 (_ULCAST_(1) << 8)
8132 +#define C_SW1 (_ULCAST_(1) << 9)
8133 +#define C_IRQ0 (_ULCAST_(1) << 10)
8134 +#define C_IRQ1 (_ULCAST_(1) << 11)
8135 +#define C_IRQ2 (_ULCAST_(1) << 12)
8136 +#define C_IRQ3 (_ULCAST_(1) << 13)
8137 +#define C_IRQ4 (_ULCAST_(1) << 14)
8138 +#define C_IRQ5 (_ULCAST_(1) << 15)
8139 +#define C_WP 0x00400000
8140 +#define C_IV 0x00800000
8141 +#define C_CE 0x30000000
8142 +#define C_CE_SHIFT 28
8143 +#define C_BD 0x80000000
8144 +
8145 +/* Values in C_EXC */
8146 +#define EXC_INT 0
8147 +#define EXC_TLBM 1
8148 +#define EXC_TLBL 2
8149 +#define EXC_TLBS 3
8150 +#define EXC_AEL 4
8151 +#define EXC_AES 5
8152 +#define EXC_IBE 6
8153 +#define EXC_DBE 7
8154 +#define EXC_SYS 8
8155 +#define EXC_BPT 9
8156 +#define EXC_RI 10
8157 +#define EXC_CU 11
8158 +#define EXC_OV 12
8159 +#define EXC_TR 13
8160 +#define EXC_WATCH 23
8161 +#define EXC_MCHK 24
8162 +
8163 +
8164 +/*
8165 + * Bits in the cp0 config register.
8166 + */
8167 +#define CONF_CM_CACHABLE_NO_WA 0
8168 +#define CONF_CM_CACHABLE_WA 1
8169 +#define CONF_CM_UNCACHED 2
8170 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8171 +#define CONF_CM_CACHABLE_CE 4
8172 +#define CONF_CM_CACHABLE_COW 5
8173 +#define CONF_CM_CACHABLE_CUW 6
8174 +#define CONF_CM_CACHABLE_ACCELERATED 7
8175 +#define CONF_CM_CMASK 7
8176 +#define CONF_CU (_ULCAST_(1) << 3)
8177 +#define CONF_DB (_ULCAST_(1) << 4)
8178 +#define CONF_IB (_ULCAST_(1) << 5)
8179 +#define CONF_SE (_ULCAST_(1) << 12)
8180 +#define CONF_SC (_ULCAST_(1) << 17)
8181 +#define CONF_AC (_ULCAST_(1) << 23)
8182 +#define CONF_HALT (_ULCAST_(1) << 25)
8183 +
8184 +
8185 +/*
8186 + * Bits in the cp0 config register select 1.
8187 + */
8188 +#define CONF1_FP 0x00000001 /* FPU present */
8189 +#define CONF1_EP 0x00000002 /* EJTAG present */
8190 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8191 +#define CONF1_WR 0x00000008 /* Watch registers present */
8192 +#define CONF1_PC 0x00000010 /* Performance counters present */
8193 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8194 +#define CONF1_DA_MASK 0x00000380
8195 +#define CONF1_DA_BASE 1
8196 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8197 +#define CONF1_DL_MASK 0x00001c00
8198 +#define CONF1_DL_BASE 2
8199 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8200 +#define CONF1_DS_MASK 0x0000e000
8201 +#define CONF1_DS_BASE 64
8202 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8203 +#define CONF1_IA_MASK 0x00070000
8204 +#define CONF1_IA_BASE 1
8205 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8206 +#define CONF1_IL_MASK 0x00380000
8207 +#define CONF1_IL_BASE 2
8208 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8209 +#define CONF1_IS_MASK 0x01c00000
8210 +#define CONF1_IS_BASE 64
8211 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8212 +#define CONF1_MS_SHIFT 25
8213 +
8214 +/* PRID register */
8215 +#define PRID_COPT_MASK 0xff000000
8216 +#define PRID_COMP_MASK 0x00ff0000
8217 +#define PRID_IMP_MASK 0x0000ff00
8218 +#define PRID_REV_MASK 0x000000ff
8219 +
8220 +#define PRID_COMP_LEGACY 0x000000
8221 +#define PRID_COMP_MIPS 0x010000
8222 +#define PRID_COMP_BROADCOM 0x020000
8223 +#define PRID_COMP_ALCHEMY 0x030000
8224 +#define PRID_COMP_SIBYTE 0x040000
8225 +#define PRID_IMP_BCM4710 0x4000
8226 +#define PRID_IMP_BCM3302 0x9000
8227 +#define PRID_IMP_BCM3303 0x9100
8228 +
8229 +#define PRID_IMP_UNKNOWN 0xff00
8230 +
8231 +#define BCM330X(id) \
8232 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8233 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8234 +
8235 +/* Bits in C0_BROADCOM */
8236 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8237 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8238 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8239 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8240 +
8241 +/* PreFetch Cache aka Read Ahead Cache */
8242 +
8243 +#define PFC_CR0 0xff400000 /* control reg 0 */
8244 +#define PFC_CR1 0xff400004 /* control reg 1 */
8245 +
8246 +/* PFC operations */
8247 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8248 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8249 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8250 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8251 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8252 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8253 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8254 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8255 +#define PFC_BRR 0x40000000 /* Bus error indication */
8256 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8257 +
8258 +/* Handy defaults */
8259 +#define PFC_DISABLED 0
8260 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8261 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8262 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8263 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8264 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8265 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8266 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8267 +
8268 +
8269 +/*
8270 + * These are the UART port assignments, expressed as offsets from the base
8271 + * register. These assignments should hold for any serial port based on
8272 + * a 8250, 16450, or 16550(A).
8273 + */
8274 +
8275 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8276 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8277 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8278 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8279 +#define UART_LCR 3 /* Out: Line Control Register */
8280 +#define UART_MCR 4 /* Out: Modem Control Register */
8281 +#define UART_LSR 5 /* In: Line Status Register */
8282 +#define UART_MSR 6 /* In: Modem Status Register */
8283 +#define UART_SCR 7 /* I/O: Scratch Register */
8284 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8285 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8286 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8287 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8288 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8289 +
8290 +
8291 +#ifndef _LANGUAGE_ASSEMBLY
8292 +
8293 +/*
8294 + * Macros to access the system control coprocessor
8295 + */
8296 +
8297 +#define MFC0(source, sel) \
8298 +({ \
8299 + int __res; \
8300 + __asm__ __volatile__( \
8301 + ".set\tnoreorder\n\t" \
8302 + ".set\tnoat\n\t" \
8303 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8304 + "move\t%0,$1\n\t" \
8305 + ".set\tat\n\t" \
8306 + ".set\treorder" \
8307 + :"=r" (__res) \
8308 + : \
8309 + :"$1"); \
8310 + __res; \
8311 +})
8312 +
8313 +#define MTC0(source, sel, value) \
8314 +do { \
8315 + __asm__ __volatile__( \
8316 + ".set\tnoreorder\n\t" \
8317 + ".set\tnoat\n\t" \
8318 + "move\t$1,%z0\n\t" \
8319 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8320 + ".set\tat\n\t" \
8321 + ".set\treorder" \
8322 + : \
8323 + :"jr" (value) \
8324 + :"$1"); \
8325 +} while (0)
8326 +
8327 +#define get_c0_count() \
8328 +({ \
8329 + int __res; \
8330 + __asm__ __volatile__( \
8331 + ".set\tnoreorder\n\t" \
8332 + ".set\tnoat\n\t" \
8333 + "mfc0\t%0,$9\n\t" \
8334 + ".set\tat\n\t" \
8335 + ".set\treorder" \
8336 + :"=r" (__res)); \
8337 + __res; \
8338 +})
8339 +
8340 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8341 +{
8342 + uint lsz, sets, ways;
8343 +
8344 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8345 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8346 + lsz = CONF1_IL_BASE << lsz;
8347 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8348 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8349 + *size = lsz * sets * ways;
8350 + *lsize = lsz;
8351 +}
8352 +
8353 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8354 +{
8355 + uint lsz, sets, ways;
8356 +
8357 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8358 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8359 + lsz = CONF1_DL_BASE << lsz;
8360 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8361 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8362 + *size = lsz * sets * ways;
8363 + *lsize = lsz;
8364 +}
8365 +
8366 +#define cache_op(base, op) \
8367 + __asm__ __volatile__(" \
8368 + .set noreorder; \
8369 + .set mips3; \
8370 + cache %1, (%0); \
8371 + .set mips0; \
8372 + .set reorder" \
8373 + : \
8374 + : "r" (base), \
8375 + "i" (op));
8376 +
8377 +#define cache_unroll4(base, delta, op) \
8378 + __asm__ __volatile__(" \
8379 + .set noreorder; \
8380 + .set mips3; \
8381 + cache %1,0(%0); \
8382 + cache %1,delta(%0); \
8383 + cache %1,(2 * delta)(%0); \
8384 + cache %1,(3 * delta)(%0); \
8385 + .set mips0; \
8386 + .set reorder" \
8387 + : \
8388 + : "r" (base), \
8389 + "i" (op));
8390 +
8391 +#endif /* !_LANGUAGE_ASSEMBLY */
8392 +
8393 +#endif /* _MISPINC_H */
8394 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/osl.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/osl.h
8395 --- linux-2.6.17/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8396 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/osl.h 2006-06-18 15:29:23.000000000 +0200
8397 @@ -0,0 +1,42 @@
8398 +/*
8399 + * OS Abstraction Layer
8400 + *
8401 + * Copyright 2005, Broadcom Corporation
8402 + * All Rights Reserved.
8403 + *
8404 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8405 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8406 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8407 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8408 + * $Id$
8409 + */
8410 +
8411 +#ifndef _osl_h_
8412 +#define _osl_h_
8413 +
8414 +/* osl handle type forward declaration */
8415 +typedef struct os_handle osl_t;
8416 +
8417 +#if defined(linux)
8418 +#include <linux_osl.h>
8419 +#elif defined(NDIS)
8420 +#include <ndis_osl.h>
8421 +#elif defined(_CFE_)
8422 +#include <cfe_osl.h>
8423 +#elif defined(_HNDRTE_)
8424 +#include <hndrte_osl.h>
8425 +#elif defined(_MINOSL_)
8426 +#include <min_osl.h>
8427 +#elif PMON
8428 +#include <pmon_osl.h>
8429 +#elif defined(MACOSX)
8430 +#include <macosx_osl.h>
8431 +#else
8432 +#error "Unsupported OSL requested"
8433 +#endif
8434 +
8435 +/* handy */
8436 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8437 +#define MAXPRIO 7 /* 0-7 */
8438 +
8439 +#endif /* _osl_h_ */
8440 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/pcicfg.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/pcicfg.h
8441 --- linux-2.6.17/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8442 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/pcicfg.h 2006-06-18 15:29:23.000000000 +0200
8443 @@ -0,0 +1,398 @@
8444 +/*
8445 + * pcicfg.h: PCI configuration constants and structures.
8446 + *
8447 + * Copyright 2005, Broadcom Corporation
8448 + * All Rights Reserved.
8449 + *
8450 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8451 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8452 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8453 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8454 + *
8455 + * $Id$
8456 + */
8457 +
8458 +#ifndef _h_pci_
8459 +#define _h_pci_
8460 +
8461 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8462 +#ifndef PCI_MAX_BUS
8463 +#define PCI_MAX_BUS 0x100
8464 +#endif
8465 +#ifndef PCI_MAX_DEVICES
8466 +#define PCI_MAX_DEVICES 0x20
8467 +#endif
8468 +#ifndef PCI_MAX_FUNCTION
8469 +#define PCI_MAX_FUNCTION 0x8
8470 +#endif
8471 +
8472 +#ifndef PCI_INVALID_VENDORID
8473 +#define PCI_INVALID_VENDORID 0xffff
8474 +#endif
8475 +#ifndef PCI_INVALID_DEVICEID
8476 +#define PCI_INVALID_DEVICEID 0xffff
8477 +#endif
8478 +
8479 +
8480 +/* Convert between bus-slot-function-register and config addresses */
8481 +
8482 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8483 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8484 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8485 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8486 +
8487 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8488 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8489 +#define PCICFG_FUN_MASK 7 /* Function mask */
8490 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8491 +
8492 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8493 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8494 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8495 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8496 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8497 +
8498 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8499 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8500 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8501 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8502 +
8503 +/* The actual config space */
8504 +
8505 +#define PCI_BAR_MAX 6
8506 +
8507 +#define PCI_ROM_BAR 8
8508 +
8509 +#define PCR_RSVDA_MAX 2
8510 +
8511 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8512 +
8513 +#define PCI_CAPPTR_PRESENT 0x0010
8514 +
8515 +typedef struct _pci_config_regs {
8516 + unsigned short vendor;
8517 + unsigned short device;
8518 + unsigned short command;
8519 + unsigned short status;
8520 + unsigned char rev_id;
8521 + unsigned char prog_if;
8522 + unsigned char sub_class;
8523 + unsigned char base_class;
8524 + unsigned char cache_line_size;
8525 + unsigned char latency_timer;
8526 + unsigned char header_type;
8527 + unsigned char bist;
8528 + unsigned long base[PCI_BAR_MAX];
8529 + unsigned long cardbus_cis;
8530 + unsigned short subsys_vendor;
8531 + unsigned short subsys_id;
8532 + unsigned long baserom;
8533 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8534 + unsigned char int_line;
8535 + unsigned char int_pin;
8536 + unsigned char min_gnt;
8537 + unsigned char max_lat;
8538 + unsigned char dev_dep[192];
8539 +} pci_config_regs;
8540 +
8541 +#define SZPCR (sizeof (pci_config_regs))
8542 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8543 +
8544 +/* A structure for the config registers is nice, but in most
8545 + * systems the config space is not memory mapped, so we need
8546 + * filed offsetts. :-(
8547 + */
8548 +#define PCI_CFG_VID 0
8549 +#define PCI_CFG_DID 2
8550 +#define PCI_CFG_CMD 4
8551 +#define PCI_CFG_STAT 6
8552 +#define PCI_CFG_REV 8
8553 +#define PCI_CFG_PROGIF 9
8554 +#define PCI_CFG_SUBCL 0xa
8555 +#define PCI_CFG_BASECL 0xb
8556 +#define PCI_CFG_CLSZ 0xc
8557 +#define PCI_CFG_LATTIM 0xd
8558 +#define PCI_CFG_HDR 0xe
8559 +#define PCI_CFG_BIST 0xf
8560 +#define PCI_CFG_BAR0 0x10
8561 +#define PCI_CFG_BAR1 0x14
8562 +#define PCI_CFG_BAR2 0x18
8563 +#define PCI_CFG_BAR3 0x1c
8564 +#define PCI_CFG_BAR4 0x20
8565 +#define PCI_CFG_BAR5 0x24
8566 +#define PCI_CFG_CIS 0x28
8567 +#define PCI_CFG_SVID 0x2c
8568 +#define PCI_CFG_SSID 0x2e
8569 +#define PCI_CFG_ROMBAR 0x30
8570 +#define PCI_CFG_CAPPTR 0x34
8571 +#define PCI_CFG_INT 0x3c
8572 +#define PCI_CFG_PIN 0x3d
8573 +#define PCI_CFG_MINGNT 0x3e
8574 +#define PCI_CFG_MAXLAT 0x3f
8575 +
8576 +/* Classes and subclasses */
8577 +
8578 +typedef enum {
8579 + PCI_CLASS_OLD = 0,
8580 + PCI_CLASS_DASDI,
8581 + PCI_CLASS_NET,
8582 + PCI_CLASS_DISPLAY,
8583 + PCI_CLASS_MMEDIA,
8584 + PCI_CLASS_MEMORY,
8585 + PCI_CLASS_BRIDGE,
8586 + PCI_CLASS_COMM,
8587 + PCI_CLASS_BASE,
8588 + PCI_CLASS_INPUT,
8589 + PCI_CLASS_DOCK,
8590 + PCI_CLASS_CPU,
8591 + PCI_CLASS_SERIAL,
8592 + PCI_CLASS_INTELLIGENT = 0xe,
8593 + PCI_CLASS_SATELLITE,
8594 + PCI_CLASS_CRYPT,
8595 + PCI_CLASS_DSP,
8596 + PCI_CLASS_MAX
8597 +} pci_classes;
8598 +
8599 +typedef enum {
8600 + PCI_DASDI_SCSI,
8601 + PCI_DASDI_IDE,
8602 + PCI_DASDI_FLOPPY,
8603 + PCI_DASDI_IPI,
8604 + PCI_DASDI_RAID,
8605 + PCI_DASDI_OTHER = 0x80
8606 +} pci_dasdi_subclasses;
8607 +
8608 +typedef enum {
8609 + PCI_NET_ETHER,
8610 + PCI_NET_TOKEN,
8611 + PCI_NET_FDDI,
8612 + PCI_NET_ATM,
8613 + PCI_NET_OTHER = 0x80
8614 +} pci_net_subclasses;
8615 +
8616 +typedef enum {
8617 + PCI_DISPLAY_VGA,
8618 + PCI_DISPLAY_XGA,
8619 + PCI_DISPLAY_3D,
8620 + PCI_DISPLAY_OTHER = 0x80
8621 +} pci_display_subclasses;
8622 +
8623 +typedef enum {
8624 + PCI_MMEDIA_VIDEO,
8625 + PCI_MMEDIA_AUDIO,
8626 + PCI_MMEDIA_PHONE,
8627 + PCI_MEDIA_OTHER = 0x80
8628 +} pci_mmedia_subclasses;
8629 +
8630 +typedef enum {
8631 + PCI_MEMORY_RAM,
8632 + PCI_MEMORY_FLASH,
8633 + PCI_MEMORY_OTHER = 0x80
8634 +} pci_memory_subclasses;
8635 +
8636 +typedef enum {
8637 + PCI_BRIDGE_HOST,
8638 + PCI_BRIDGE_ISA,
8639 + PCI_BRIDGE_EISA,
8640 + PCI_BRIDGE_MC,
8641 + PCI_BRIDGE_PCI,
8642 + PCI_BRIDGE_PCMCIA,
8643 + PCI_BRIDGE_NUBUS,
8644 + PCI_BRIDGE_CARDBUS,
8645 + PCI_BRIDGE_RACEWAY,
8646 + PCI_BRIDGE_OTHER = 0x80
8647 +} pci_bridge_subclasses;
8648 +
8649 +typedef enum {
8650 + PCI_COMM_UART,
8651 + PCI_COMM_PARALLEL,
8652 + PCI_COMM_MULTIUART,
8653 + PCI_COMM_MODEM,
8654 + PCI_COMM_OTHER = 0x80
8655 +} pci_comm_subclasses;
8656 +
8657 +typedef enum {
8658 + PCI_BASE_PIC,
8659 + PCI_BASE_DMA,
8660 + PCI_BASE_TIMER,
8661 + PCI_BASE_RTC,
8662 + PCI_BASE_PCI_HOTPLUG,
8663 + PCI_BASE_OTHER = 0x80
8664 +} pci_base_subclasses;
8665 +
8666 +typedef enum {
8667 + PCI_INPUT_KBD,
8668 + PCI_INPUT_PEN,
8669 + PCI_INPUT_MOUSE,
8670 + PCI_INPUT_SCANNER,
8671 + PCI_INPUT_GAMEPORT,
8672 + PCI_INPUT_OTHER = 0x80
8673 +} pci_input_subclasses;
8674 +
8675 +typedef enum {
8676 + PCI_DOCK_GENERIC,
8677 + PCI_DOCK_OTHER = 0x80
8678 +} pci_dock_subclasses;
8679 +
8680 +typedef enum {
8681 + PCI_CPU_386,
8682 + PCI_CPU_486,
8683 + PCI_CPU_PENTIUM,
8684 + PCI_CPU_ALPHA = 0x10,
8685 + PCI_CPU_POWERPC = 0x20,
8686 + PCI_CPU_MIPS = 0x30,
8687 + PCI_CPU_COPROC = 0x40,
8688 + PCI_CPU_OTHER = 0x80
8689 +} pci_cpu_subclasses;
8690 +
8691 +typedef enum {
8692 + PCI_SERIAL_IEEE1394,
8693 + PCI_SERIAL_ACCESS,
8694 + PCI_SERIAL_SSA,
8695 + PCI_SERIAL_USB,
8696 + PCI_SERIAL_FIBER,
8697 + PCI_SERIAL_SMBUS,
8698 + PCI_SERIAL_OTHER = 0x80
8699 +} pci_serial_subclasses;
8700 +
8701 +typedef enum {
8702 + PCI_INTELLIGENT_I2O,
8703 +} pci_intelligent_subclasses;
8704 +
8705 +typedef enum {
8706 + PCI_SATELLITE_TV,
8707 + PCI_SATELLITE_AUDIO,
8708 + PCI_SATELLITE_VOICE,
8709 + PCI_SATELLITE_DATA,
8710 + PCI_SATELLITE_OTHER = 0x80
8711 +} pci_satellite_subclasses;
8712 +
8713 +typedef enum {
8714 + PCI_CRYPT_NETWORK,
8715 + PCI_CRYPT_ENTERTAINMENT,
8716 + PCI_CRYPT_OTHER = 0x80
8717 +} pci_crypt_subclasses;
8718 +
8719 +typedef enum {
8720 + PCI_DSP_DPIO,
8721 + PCI_DSP_OTHER = 0x80
8722 +} pci_dsp_subclasses;
8723 +
8724 +/* Header types */
8725 +typedef enum {
8726 + PCI_HEADER_NORMAL,
8727 + PCI_HEADER_BRIDGE,
8728 + PCI_HEADER_CARDBUS
8729 +} pci_header_types;
8730 +
8731 +
8732 +/* Overlay for a PCI-to-PCI bridge */
8733 +
8734 +#define PPB_RSVDA_MAX 2
8735 +#define PPB_RSVDD_MAX 8
8736 +
8737 +typedef struct _ppb_config_regs {
8738 + unsigned short vendor;
8739 + unsigned short device;
8740 + unsigned short command;
8741 + unsigned short status;
8742 + unsigned char rev_id;
8743 + unsigned char prog_if;
8744 + unsigned char sub_class;
8745 + unsigned char base_class;
8746 + unsigned char cache_line_size;
8747 + unsigned char latency_timer;
8748 + unsigned char header_type;
8749 + unsigned char bist;
8750 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8751 + unsigned char prim_bus;
8752 + unsigned char sec_bus;
8753 + unsigned char sub_bus;
8754 + unsigned char sec_lat;
8755 + unsigned char io_base;
8756 + unsigned char io_lim;
8757 + unsigned short sec_status;
8758 + unsigned short mem_base;
8759 + unsigned short mem_lim;
8760 + unsigned short pf_mem_base;
8761 + unsigned short pf_mem_lim;
8762 + unsigned long pf_mem_base_hi;
8763 + unsigned long pf_mem_lim_hi;
8764 + unsigned short io_base_hi;
8765 + unsigned short io_lim_hi;
8766 + unsigned short subsys_vendor;
8767 + unsigned short subsys_id;
8768 + unsigned long rsvd_b;
8769 + unsigned char rsvd_c;
8770 + unsigned char int_pin;
8771 + unsigned short bridge_ctrl;
8772 + unsigned char chip_ctrl;
8773 + unsigned char diag_ctrl;
8774 + unsigned short arb_ctrl;
8775 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8776 + unsigned char dev_dep[192];
8777 +} ppb_config_regs;
8778 +
8779 +
8780 +/* PCI CAPABILITY DEFINES */
8781 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8782 +#define PCI_CAP_MSICAP_ID 0x05
8783 +
8784 +/* Data structure to define the Message Signalled Interrupt facility
8785 + * Valid for PCI and PCIE configurations */
8786 +typedef struct _pciconfig_cap_msi {
8787 + unsigned char capID;
8788 + unsigned char nextptr;
8789 + unsigned short msgctrl;
8790 + unsigned int msgaddr;
8791 +} pciconfig_cap_msi;
8792 +
8793 +/* Data structure to define the Power managment facility
8794 + * Valid for PCI and PCIE configurations */
8795 +typedef struct _pciconfig_cap_pwrmgmt {
8796 + unsigned char capID;
8797 + unsigned char nextptr;
8798 + unsigned short pme_cap;
8799 + unsigned short pme_sts_ctrl;
8800 + unsigned char pme_bridge_ext;
8801 + unsigned char data;
8802 +} pciconfig_cap_pwrmgmt;
8803 +
8804 +/* Everything below is BRCM HND proprietary */
8805 +
8806 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8807 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8808 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8809 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8810 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8811 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8812 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8813 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8814 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8815 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8816 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8817 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8818 +
8819 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8820 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8821 +
8822 +/* PCI_INT_STATUS */
8823 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8824 +
8825 +/* PCI_INT_MASK */
8826 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8827 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8828 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8829 +
8830 +/* PCI_SPROM_CONTROL */
8831 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8832 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8833 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8834 +
8835 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8836 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8837 +
8838 +/* PCI_CFG_CMD_STAT */
8839 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8840 +
8841 +#endif
8842 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/proto/ethernet.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/proto/ethernet.h
8843 --- linux-2.6.17/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8844 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/proto/ethernet.h 2006-06-18 15:29:23.000000000 +0200
8845 @@ -0,0 +1,145 @@
8846 +/*******************************************************************************
8847 + * $Id$
8848 + * Copyright 2001-2003, Broadcom Corporation
8849 + * All Rights Reserved.
8850 + *
8851 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8852 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8853 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8854 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8855 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8856 + ******************************************************************************/
8857 +
8858 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8859 +#define _NET_ETHERNET_H_
8860 +
8861 +#ifndef _TYPEDEFS_H_
8862 +#include "typedefs.h"
8863 +#endif
8864 +
8865 +#if defined(__GNUC__)
8866 +#define PACKED __attribute__((packed))
8867 +#else
8868 +#define PACKED
8869 +#endif
8870 +
8871 +/*
8872 + * The number of bytes in an ethernet (MAC) address.
8873 + */
8874 +#define ETHER_ADDR_LEN 6
8875 +
8876 +/*
8877 + * The number of bytes in the type field.
8878 + */
8879 +#define ETHER_TYPE_LEN 2
8880 +
8881 +/*
8882 + * The number of bytes in the trailing CRC field.
8883 + */
8884 +#define ETHER_CRC_LEN 4
8885 +
8886 +/*
8887 + * The length of the combined header.
8888 + */
8889 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8890 +
8891 +/*
8892 + * The minimum packet length.
8893 + */
8894 +#define ETHER_MIN_LEN 64
8895 +
8896 +/*
8897 + * The minimum packet user data length.
8898 + */
8899 +#define ETHER_MIN_DATA 46
8900 +
8901 +/*
8902 + * The maximum packet length.
8903 + */
8904 +#define ETHER_MAX_LEN 1518
8905 +
8906 +/*
8907 + * The maximum packet user data length.
8908 + */
8909 +#define ETHER_MAX_DATA 1500
8910 +
8911 +/*
8912 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8913 + */
8914 +#define VLAN_TAG 0x8100
8915 +
8916 +/*
8917 + * Located after dest & src address in ether header.
8918 + */
8919 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8920 +
8921 +/*
8922 + * 4 bytes of vlan field info.
8923 + */
8924 +#define VLAN_FIELDS_SIZE 4
8925 +
8926 +/* location of pri bits in 16-bit vlan fields */
8927 +#define VLAN_PRI_SHIFT 13
8928 +
8929 +/* 3 bits of priority */
8930 +#define VLAN_PRI_MASK 7
8931 +
8932 +/* 802.1X ethertype */
8933 +#define ETHER_TYPE_802_1X 0x888e
8934 +
8935 +/*
8936 + * A macro to validate a length with
8937 + */
8938 +#define ETHER_IS_VALID_LEN(foo) \
8939 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8940 +
8941 +
8942 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8943 +/*
8944 + * Structure of a 10Mb/s Ethernet header.
8945 + */
8946 +struct ether_header {
8947 + uint8 ether_dhost[ETHER_ADDR_LEN];
8948 + uint8 ether_shost[ETHER_ADDR_LEN];
8949 + uint16 ether_type;
8950 +} PACKED ;
8951 +
8952 +/*
8953 + * Structure of a 48-bit Ethernet address.
8954 + */
8955 +struct ether_addr {
8956 + uint8 octet[ETHER_ADDR_LEN];
8957 +} PACKED ;
8958 +#endif
8959 +
8960 +/*
8961 + * Takes a pointer, returns true if a 48-bit multicast address
8962 + * (including broadcast, since it is all ones)
8963 + */
8964 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
8965 +
8966 +/*
8967 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
8968 + */
8969 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
8970 + ((uint8 *)(ea))[1] & \
8971 + ((uint8 *)(ea))[2] & \
8972 + ((uint8 *)(ea))[3] & \
8973 + ((uint8 *)(ea))[4] & \
8974 + ((uint8 *)(ea))[5]) == 0xff)
8975 +
8976 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
8977 +
8978 +/*
8979 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
8980 + */
8981 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
8982 + ((uint8 *)(ea))[1] | \
8983 + ((uint8 *)(ea))[2] | \
8984 + ((uint8 *)(ea))[3] | \
8985 + ((uint8 *)(ea))[4] | \
8986 + ((uint8 *)(ea))[5]) == 0)
8987 +
8988 +#undef PACKED
8989 +
8990 +#endif /* _NET_ETHERNET_H_ */
8991 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/s5.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/s5.h
8992 --- linux-2.6.17/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
8993 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/s5.h 2006-06-18 15:29:23.000000000 +0200
8994 @@ -0,0 +1,103 @@
8995 +#ifndef _S5_H_
8996 +#define _S5_H_
8997 +/*
8998 + * Copyright 2003, Broadcom Corporation
8999 + * All Rights Reserved.
9000 + *
9001 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9002 + * and MIPS3301 (R4K) System Address Space
9003 + *
9004 + * This program is free software; you can redistribute it and/or
9005 + * modify it under the terms of the GNU General Public License as
9006 + * published by the Free Software Foundation, located in the file
9007 + * LICENSE.
9008 + *
9009 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9010 + *
9011 + */
9012 +
9013 +/* BCM5365 Address map */
9014 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9015 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9016 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9017 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9018 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9019 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9020 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9021 +
9022 +/* BCM5365 Core register space */
9023 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9024 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9025 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9026 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9027 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9028 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9029 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9030 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9031 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9032 +
9033 +/* COM Ports 1/2 */
9034 +#define BCM5365_UART (BCM5365_REG_UARTS)
9035 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9036 +
9037 +/* Registers common to MIPS33 Core used in 5365 */
9038 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9039 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9040 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9041 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9042 +
9043 +/* Internal Core Sonics Backplane Devices */
9044 +#define INTERNAL_UART_COM1 BCM5365_UART
9045 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9046 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9047 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9048 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9049 +#define SB_REG_USB BCM5365_REG_USB
9050 +#define SB_REG_PCI BCM5365_REG_PCI
9051 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9052 +#define SB_REG_MEMC BCM5365_REG_MEMC
9053 +#define SB_REG_MEMC_OFF 0x6000
9054 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9055 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9056 +
9057 +/*
9058 + * XXX
9059 + * 5365-specific backplane interrupt flag numbers. This should be done
9060 + * dynamically instead.
9061 + */
9062 +#define SBFLAG_PCI 0
9063 +#define SBFLAG_ENET0 1
9064 +#define SBFLAG_ILINE20 2
9065 +#define SBFLAG_CODEC 3
9066 +#define SBFLAG_USB 4
9067 +#define SBFLAG_EXTIF 5
9068 +#define SBFLAG_ENET1 6
9069 +
9070 +/* BCM95365 Local Bus devices */
9071 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9072 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9073 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9074 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9075 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9076 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9077 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9078 +
9079 +/* Write to DLR2416 VFD Display character RAM */
9080 +#define LED_REG(x) \
9081 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9082 +
9083 +#ifdef CONFIG_VSIM
9084 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9085 + } while (0)
9086 +#else
9087 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9088 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9089 + *((int *)0xa0002ff8) = (trval); } while (0)
9090 +#endif
9091 +
9092 +/* BCM9536R Local Bus devices */
9093 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9094 +
9095 +
9096 +
9097 +#endif /*!_S5_H_ */
9098 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbchipc.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbchipc.h
9099 --- linux-2.6.17/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9100 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbchipc.h 2006-06-18 15:29:23.000000000 +0200
9101 @@ -0,0 +1,440 @@
9102 +/*
9103 + * SiliconBackplane Chipcommon core hardware definitions.
9104 + *
9105 + * The chipcommon core provides chip identification, SB control,
9106 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9107 + * gpio interface, extbus, and support for serial and parallel flashes.
9108 + *
9109 + * $Id$
9110 + * Copyright 2005, Broadcom Corporation
9111 + * All Rights Reserved.
9112 + *
9113 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9114 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9115 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9116 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9117 + *
9118 + */
9119 +
9120 +#ifndef _SBCHIPC_H
9121 +#define _SBCHIPC_H
9122 +
9123 +
9124 +#ifndef _LANGUAGE_ASSEMBLY
9125 +
9126 +/* cpp contortions to concatenate w/arg prescan */
9127 +#ifndef PAD
9128 +#define _PADLINE(line) pad ## line
9129 +#define _XSTR(line) _PADLINE(line)
9130 +#define PAD _XSTR(__LINE__)
9131 +#endif /* PAD */
9132 +
9133 +typedef volatile struct {
9134 + uint32 chipid; /* 0x0 */
9135 + uint32 capabilities;
9136 + uint32 corecontrol; /* corerev >= 1 */
9137 + uint32 bist;
9138 +
9139 + /* OTP */
9140 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9141 + uint32 otpcontrol;
9142 + uint32 otpprog;
9143 + uint32 PAD;
9144 +
9145 + /* Interrupt control */
9146 + uint32 intstatus; /* 0x20 */
9147 + uint32 intmask;
9148 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9149 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9150 +
9151 + /* Jtag Master */
9152 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9153 + uint32 jtagir;
9154 + uint32 jtagdr;
9155 + uint32 jtagctrl;
9156 +
9157 + /* serial flash interface registers */
9158 + uint32 flashcontrol; /* 0x40 */
9159 + uint32 flashaddress;
9160 + uint32 flashdata;
9161 + uint32 PAD[1];
9162 +
9163 + /* Silicon backplane configuration broadcast control */
9164 + uint32 broadcastaddress; /* 0x50 */
9165 + uint32 broadcastdata;
9166 + uint32 PAD[2];
9167 +
9168 + /* gpio - cleared only by power-on-reset */
9169 + uint32 gpioin; /* 0x60 */
9170 + uint32 gpioout;
9171 + uint32 gpioouten;
9172 + uint32 gpiocontrol;
9173 + uint32 gpiointpolarity;
9174 + uint32 gpiointmask;
9175 + uint32 PAD[2];
9176 +
9177 + /* Watchdog timer */
9178 + uint32 watchdog; /* 0x80 */
9179 + uint32 PAD[1];
9180 +
9181 + /*GPIO based LED powersave registers corerev >= 16*/
9182 + uint32 gpiotimerval; /*0x88 */
9183 + uint32 gpiotimeroutmask;
9184 +
9185 + /* clock control */
9186 + uint32 clockcontrol_n; /* 0x90 */
9187 + uint32 clockcontrol_sb; /* aka m0 */
9188 + uint32 clockcontrol_pci; /* aka m1 */
9189 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9190 + uint32 clockcontrol_mips; /* aka m3 */
9191 + uint32 clkdiv; /* corerev >= 3 */
9192 + uint32 PAD[2];
9193 +
9194 + /* pll delay registers (corerev >= 4) */
9195 + uint32 pll_on_delay; /* 0xb0 */
9196 + uint32 fref_sel_delay;
9197 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9198 + uint32 PAD[1];
9199 +
9200 + /* Instaclock registers (corerev >= 10) */
9201 + uint32 system_clk_ctl; /* 0xc0 */
9202 + uint32 clkstatestretch;
9203 + uint32 PAD[14];
9204 +
9205 + /* ExtBus control registers (corerev >= 3) */
9206 + uint32 pcmcia_config; /* 0x100 */
9207 + uint32 pcmcia_memwait;
9208 + uint32 pcmcia_attrwait;
9209 + uint32 pcmcia_iowait;
9210 + uint32 ide_config;
9211 + uint32 ide_memwait;
9212 + uint32 ide_attrwait;
9213 + uint32 ide_iowait;
9214 + uint32 prog_config;
9215 + uint32 prog_waitcount;
9216 + uint32 flash_config;
9217 + uint32 flash_waitcount;
9218 + uint32 PAD[116];
9219 +
9220 + /* uarts */
9221 + uint8 uart0data; /* 0x300 */
9222 + uint8 uart0imr;
9223 + uint8 uart0fcr;
9224 + uint8 uart0lcr;
9225 + uint8 uart0mcr;
9226 + uint8 uart0lsr;
9227 + uint8 uart0msr;
9228 + uint8 uart0scratch;
9229 + uint8 PAD[248]; /* corerev >= 1 */
9230 +
9231 + uint8 uart1data; /* 0x400 */
9232 + uint8 uart1imr;
9233 + uint8 uart1fcr;
9234 + uint8 uart1lcr;
9235 + uint8 uart1mcr;
9236 + uint8 uart1lsr;
9237 + uint8 uart1msr;
9238 + uint8 uart1scratch;
9239 +} chipcregs_t;
9240 +
9241 +#endif /* _LANGUAGE_ASSEMBLY */
9242 +
9243 +#define CC_CHIPID 0
9244 +#define CC_CAPABILITIES 4
9245 +#define CC_JTAGCMD 0x30
9246 +#define CC_JTAGIR 0x34
9247 +#define CC_JTAGDR 0x38
9248 +#define CC_JTAGCTRL 0x3c
9249 +#define CC_WATCHDOG 0x80
9250 +#define CC_CLKC_N 0x90
9251 +#define CC_CLKC_M0 0x94
9252 +#define CC_CLKC_M1 0x98
9253 +#define CC_CLKC_M2 0x9c
9254 +#define CC_CLKC_M3 0xa0
9255 +#define CC_CLKDIV 0xa4
9256 +#define CC_SYS_CLK_CTL 0xc0
9257 +#define CC_OTP 0x800
9258 +
9259 +/* chipid */
9260 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9261 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9262 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9263 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9264 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9265 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9266 +#define CID_CC_SHIFT 24
9267 +
9268 +/* capabilities */
9269 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9270 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9271 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9272 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9273 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9274 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9275 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9276 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9277 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9278 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9279 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9280 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9281 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9282 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9283 +
9284 +/* PLL type */
9285 +#define PLL_NONE 0x00000000
9286 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9287 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9288 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9289 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9290 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9291 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9292 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9293 +
9294 +/* corecontrol */
9295 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9296 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9297 +
9298 +/* Fields in the otpstatus register */
9299 +#define OTPS_PROGFAIL 0x80000000
9300 +#define OTPS_PROTECT 0x00000007
9301 +#define OTPS_HW_PROTECT 0x00000001
9302 +#define OTPS_SW_PROTECT 0x00000002
9303 +#define OTPS_CID_PROTECT 0x00000004
9304 +
9305 +/* Fields in the otpcontrol register */
9306 +#define OTPC_RECWAIT 0xff000000
9307 +#define OTPC_PROGWAIT 0x00ffff00
9308 +#define OTPC_PRW_SHIFT 8
9309 +#define OTPC_MAXFAIL 0x00000038
9310 +#define OTPC_VSEL 0x00000006
9311 +#define OTPC_SELVL 0x00000001
9312 +
9313 +/* Fields in otpprog */
9314 +#define OTPP_COL_MASK 0x000000ff
9315 +#define OTPP_ROW_MASK 0x0000ff00
9316 +#define OTPP_ROW_SHIFT 8
9317 +#define OTPP_READERR 0x10000000
9318 +#define OTPP_VALUE 0x20000000
9319 +#define OTPP_VALUE_SHIFT 29
9320 +#define OTPP_READ 0x40000000
9321 +#define OTPP_START 0x80000000
9322 +#define OTPP_BUSY 0x80000000
9323 +
9324 +/* jtagcmd */
9325 +#define JCMD_START 0x80000000
9326 +#define JCMD_BUSY 0x80000000
9327 +#define JCMD_PAUSE 0x40000000
9328 +#define JCMD0_ACC_MASK 0x0000f000
9329 +#define JCMD0_ACC_IRDR 0x00000000
9330 +#define JCMD0_ACC_DR 0x00001000
9331 +#define JCMD0_ACC_IR 0x00002000
9332 +#define JCMD0_ACC_RESET 0x00003000
9333 +#define JCMD0_ACC_IRPDR 0x00004000
9334 +#define JCMD0_ACC_PDR 0x00005000
9335 +#define JCMD0_IRW_MASK 0x00000f00
9336 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9337 +#define JCMD_ACC_IRDR 0x00000000
9338 +#define JCMD_ACC_DR 0x00010000
9339 +#define JCMD_ACC_IR 0x00020000
9340 +#define JCMD_ACC_RESET 0x00030000
9341 +#define JCMD_ACC_IRPDR 0x00040000
9342 +#define JCMD_ACC_PDR 0x00050000
9343 +#define JCMD_IRW_MASK 0x00001f00
9344 +#define JCMD_IRW_SHIFT 8
9345 +#define JCMD_DRW_MASK 0x0000003f
9346 +
9347 +/* jtagctrl */
9348 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9349 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9350 +#define JCTRL_EN 1 /* Enable Jtag master */
9351 +
9352 +/* Fields in clkdiv */
9353 +#define CLKD_SFLASH 0x0f000000
9354 +#define CLKD_SFLASH_SHIFT 24
9355 +#define CLKD_OTP 0x000f0000
9356 +#define CLKD_OTP_SHIFT 16
9357 +#define CLKD_JTAG 0x00000f00
9358 +#define CLKD_JTAG_SHIFT 8
9359 +#define CLKD_UART 0x000000ff
9360 +
9361 +/* intstatus/intmask */
9362 +#define CI_GPIO 0x00000001 /* gpio intr */
9363 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9364 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9365 +
9366 +/* slow_clk_ctl */
9367 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9368 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9369 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9370 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9371 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9372 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9373 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9374 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9375 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9376 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9377 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9378 +#define SCC_CD_SHIFT 16
9379 +
9380 +/* system_clk_ctl */
9381 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9382 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9383 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9384 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9385 +#define SYCC_HR 0x00000010 /* Force HT */
9386 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9387 +#define SYCC_CD_SHIFT 16
9388 +
9389 +/* gpiotimerval*/
9390 +#define GPIO_ONTIME_SHIFT 16
9391 +
9392 +/* clockcontrol_n */
9393 +#define CN_N1_MASK 0x3f /* n1 control */
9394 +#define CN_N2_MASK 0x3f00 /* n2 control */
9395 +#define CN_N2_SHIFT 8
9396 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9397 +#define CN_PLLC_SHIFT 16
9398 +
9399 +/* clockcontrol_sb/pci/uart */
9400 +#define CC_M1_MASK 0x3f /* m1 control */
9401 +#define CC_M2_MASK 0x3f00 /* m2 control */
9402 +#define CC_M2_SHIFT 8
9403 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9404 +#define CC_M3_SHIFT 16
9405 +#define CC_MC_MASK 0x1f000000 /* mux control */
9406 +#define CC_MC_SHIFT 24
9407 +
9408 +/* N3M Clock control magic field values */
9409 +#define CC_F6_2 0x02 /* A factor of 2 in */
9410 +#define CC_F6_3 0x03 /* 6-bit fields like */
9411 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9412 +#define CC_F6_5 0x09
9413 +#define CC_F6_6 0x11
9414 +#define CC_F6_7 0x21
9415 +
9416 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9417 +
9418 +#define CC_MC_BYPASS 0x08
9419 +#define CC_MC_M1 0x04
9420 +#define CC_MC_M1M2 0x02
9421 +#define CC_MC_M1M2M3 0x01
9422 +#define CC_MC_M1M3 0x11
9423 +
9424 +/* Type 2 Clock control magic field values */
9425 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9426 +#define CC_T2M2_BIAS 3 /* m2 bias */
9427 +
9428 +#define CC_T2MC_M1BYP 1
9429 +#define CC_T2MC_M2BYP 2
9430 +#define CC_T2MC_M3BYP 4
9431 +
9432 +/* Type 6 Clock control magic field values */
9433 +#define CC_T6_MMASK 1 /* bits of interest in m */
9434 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9435 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9436 +#define SB2MIPS_T6(sb) (2 * (sb))
9437 +
9438 +/* Common clock base */
9439 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9440 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9441 +
9442 +/* Clock control values for 200Mhz in 5350 */
9443 +#define CLKC_5350_N 0x0311
9444 +#define CLKC_5350_M 0x04020009
9445 +
9446 +/* Flash types in the chipcommon capabilities register */
9447 +#define FLASH_NONE 0x000 /* No flash */
9448 +#define SFLASH_ST 0x100 /* ST serial flash */
9449 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9450 +#define PFLASH 0x700 /* Parallel flash */
9451 +
9452 +/* Bits in the config registers */
9453 +#define CC_CFG_EN 0x0001 /* Enable */
9454 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9455 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9456 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9457 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9458 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9459 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9460 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9461 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9462 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9463 +
9464 +/* Start/busy bit in flashcontrol */
9465 +#define SFLASH_START 0x80000000
9466 +#define SFLASH_BUSY SFLASH_START
9467 +
9468 +/* flashcontrol opcodes for ST flashes */
9469 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9470 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9471 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9472 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9473 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9474 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9475 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9476 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9477 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9478 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9479 +
9480 +/* Status register bits for ST flashes */
9481 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9482 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9483 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9484 +#define SFLASH_ST_BP_SHIFT 2
9485 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9486 +
9487 +/* flashcontrol opcodes for Atmel flashes */
9488 +#define SFLASH_AT_READ 0x07e8
9489 +#define SFLASH_AT_PAGE_READ 0x07d2
9490 +#define SFLASH_AT_BUF1_READ
9491 +#define SFLASH_AT_BUF2_READ
9492 +#define SFLASH_AT_STATUS 0x01d7
9493 +#define SFLASH_AT_BUF1_WRITE 0x0384
9494 +#define SFLASH_AT_BUF2_WRITE 0x0387
9495 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9496 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9497 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9498 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9499 +#define SFLASH_AT_PAGE_ERASE 0x0281
9500 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9501 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9502 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9503 +#define SFLASH_AT_BUF1_LOAD 0x0253
9504 +#define SFLASH_AT_BUF2_LOAD 0x0255
9505 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9506 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9507 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9508 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9509 +
9510 +/* Status register bits for Atmel flashes */
9511 +#define SFLASH_AT_READY 0x80
9512 +#define SFLASH_AT_MISMATCH 0x40
9513 +#define SFLASH_AT_ID_MASK 0x38
9514 +#define SFLASH_AT_ID_SHIFT 3
9515 +
9516 +/* OTP regions */
9517 +#define OTP_HW_REGION OTPS_HW_PROTECT
9518 +#define OTP_SW_REGION OTPS_SW_PROTECT
9519 +#define OTP_CID_REGION OTPS_CID_PROTECT
9520 +
9521 +/* OTP regions (Byte offsets from otp size) */
9522 +#define OTP_SWLIM_OFF (-8)
9523 +#define OTP_CIDBASE_OFF 0
9524 +#define OTP_CIDLIM_OFF 8
9525 +
9526 +/* Predefined OTP words (Word offset from otp size) */
9527 +#define OTP_BOUNDARY_OFF (-4)
9528 +#define OTP_HWSIGN_OFF (-3)
9529 +#define OTP_SWSIGN_OFF (-2)
9530 +#define OTP_CIDSIGN_OFF (-1)
9531 +
9532 +#define OTP_CID_OFF 0
9533 +#define OTP_PKG_OFF 1
9534 +#define OTP_FID_OFF 2
9535 +#define OTP_RSV_OFF 3
9536 +#define OTP_LIM_OFF 4
9537 +
9538 +#define OTP_SIGNATURE 0x578a
9539 +#define OTP_MAGIC 0x4e56
9540 +
9541 +#endif /* _SBCHIPC_H */
9542 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbconfig.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbconfig.h
9543 --- linux-2.6.17/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9544 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbconfig.h 2006-06-18 15:29:23.000000000 +0200
9545 @@ -0,0 +1,342 @@
9546 +/*
9547 + * Broadcom SiliconBackplane hardware register definitions.
9548 + *
9549 + * Copyright 2005, Broadcom Corporation
9550 + * All Rights Reserved.
9551 + *
9552 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9553 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9554 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9555 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9556 + * $Id$
9557 + */
9558 +
9559 +#ifndef _SBCONFIG_H
9560 +#define _SBCONFIG_H
9561 +
9562 +/* cpp contortions to concatenate w/arg prescan */
9563 +#ifndef PAD
9564 +#define _PADLINE(line) pad ## line
9565 +#define _XSTR(line) _PADLINE(line)
9566 +#define PAD _XSTR(__LINE__)
9567 +#endif
9568 +
9569 +/*
9570 + * SiliconBackplane Address Map.
9571 + * All regions may not exist on all chips.
9572 + */
9573 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9574 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9575 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9576 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9577 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9578 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9579 +
9580 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9581 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9582 +
9583 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9584 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9585 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9586 +
9587 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9588 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9589 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9590 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9591 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9592 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9593 +
9594 +
9595 +/* enumeration space related defs */
9596 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9597 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9598 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9599 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9600 +
9601 +/* mips address */
9602 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9603 +
9604 +/*
9605 + * Sonics Configuration Space Registers.
9606 + */
9607 +#define SBIPSFLAG 0x08
9608 +#define SBTPSFLAG 0x18
9609 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9610 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9611 +#define SBADMATCH3 0x60
9612 +#define SBADMATCH2 0x68
9613 +#define SBADMATCH1 0x70
9614 +#define SBIMSTATE 0x90
9615 +#define SBINTVEC 0x94
9616 +#define SBTMSTATELOW 0x98
9617 +#define SBTMSTATEHIGH 0x9c
9618 +#define SBBWA0 0xa0
9619 +#define SBIMCONFIGLOW 0xa8
9620 +#define SBIMCONFIGHIGH 0xac
9621 +#define SBADMATCH0 0xb0
9622 +#define SBTMCONFIGLOW 0xb8
9623 +#define SBTMCONFIGHIGH 0xbc
9624 +#define SBBCONFIG 0xc0
9625 +#define SBBSTATE 0xc8
9626 +#define SBACTCNFG 0xd8
9627 +#define SBFLAGST 0xe8
9628 +#define SBIDLOW 0xf8
9629 +#define SBIDHIGH 0xfc
9630 +
9631 +#ifndef _LANGUAGE_ASSEMBLY
9632 +
9633 +typedef volatile struct _sbconfig {
9634 + uint32 PAD[2];
9635 + uint32 sbipsflag; /* initiator port ocp slave flag */
9636 + uint32 PAD[3];
9637 + uint32 sbtpsflag; /* target port ocp slave flag */
9638 + uint32 PAD[11];
9639 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9640 + uint32 PAD;
9641 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9642 + uint32 PAD[3];
9643 + uint32 sbadmatch3; /* address match3 */
9644 + uint32 PAD;
9645 + uint32 sbadmatch2; /* address match2 */
9646 + uint32 PAD;
9647 + uint32 sbadmatch1; /* address match1 */
9648 + uint32 PAD[7];
9649 + uint32 sbimstate; /* initiator agent state */
9650 + uint32 sbintvec; /* interrupt mask */
9651 + uint32 sbtmstatelow; /* target state */
9652 + uint32 sbtmstatehigh; /* target state */
9653 + uint32 sbbwa0; /* bandwidth allocation table0 */
9654 + uint32 PAD;
9655 + uint32 sbimconfiglow; /* initiator configuration */
9656 + uint32 sbimconfighigh; /* initiator configuration */
9657 + uint32 sbadmatch0; /* address match0 */
9658 + uint32 PAD;
9659 + uint32 sbtmconfiglow; /* target configuration */
9660 + uint32 sbtmconfighigh; /* target configuration */
9661 + uint32 sbbconfig; /* broadcast configuration */
9662 + uint32 PAD;
9663 + uint32 sbbstate; /* broadcast state */
9664 + uint32 PAD[3];
9665 + uint32 sbactcnfg; /* activate configuration */
9666 + uint32 PAD[3];
9667 + uint32 sbflagst; /* current sbflags */
9668 + uint32 PAD[3];
9669 + uint32 sbidlow; /* identification */
9670 + uint32 sbidhigh; /* identification */
9671 +} sbconfig_t;
9672 +
9673 +#endif /* _LANGUAGE_ASSEMBLY */
9674 +
9675 +/* sbipsflag */
9676 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9677 +#define SBIPS_INT1_SHIFT 0
9678 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9679 +#define SBIPS_INT2_SHIFT 8
9680 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9681 +#define SBIPS_INT3_SHIFT 16
9682 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9683 +#define SBIPS_INT4_SHIFT 24
9684 +
9685 +/* sbtpsflag */
9686 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9687 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9688 +
9689 +/* sbtmerrlog */
9690 +#define SBTMEL_CM 0x00000007 /* command */
9691 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9692 +#define SBTMEL_EC 0x0f000000 /* error code */
9693 +#define SBTMEL_ME 0x80000000 /* multiple error */
9694 +
9695 +/* sbimstate */
9696 +#define SBIM_PC 0xf /* pipecount */
9697 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9698 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9699 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9700 +#define SBIM_AP_TK 0x20 /* use token only */
9701 +#define SBIM_AP_RSV 0x30 /* reserved */
9702 +#define SBIM_IBE 0x20000 /* inbanderror */
9703 +#define SBIM_TO 0x40000 /* timeout */
9704 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9705 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9706 +
9707 +/* sbtmstatelow */
9708 +#define SBTML_RESET 0x1 /* reset */
9709 +#define SBTML_REJ_MASK 0x6 /* reject */
9710 +#define SBTML_REJ_SHIFT 1
9711 +#define SBTML_CLK 0x10000 /* clock enable */
9712 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9713 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9714 +#define SBTML_PE 0x40000000 /* pme enable */
9715 +#define SBTML_BE 0x80000000 /* bist enable */
9716 +
9717 +/* sbtmstatehigh */
9718 +#define SBTMH_SERR 0x1 /* serror */
9719 +#define SBTMH_INT 0x2 /* interrupt */
9720 +#define SBTMH_BUSY 0x4 /* busy */
9721 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9722 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9723 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9724 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9725 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9726 +#define SBTMH_BISTD 0x80000000 /* bist done */
9727 +
9728 +
9729 +/* sbbwa0 */
9730 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9731 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9732 +#define SBBWA_TAB1_SHIFT 16
9733 +
9734 +/* sbimconfiglow */
9735 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9736 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9737 +#define SBIMCL_RTO_SHIFT 4
9738 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9739 +#define SBIMCL_CID_SHIFT 16
9740 +
9741 +/* sbimconfighigh */
9742 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9743 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9744 +#define SBIMCH_TEM_SHIFT 4
9745 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9746 +#define SBIMCH_BEM_SHIFT 6
9747 +
9748 +/* sbadmatch0 */
9749 +#define SBAM_TYPE_MASK 0x3 /* address type */
9750 +#define SBAM_AD64 0x4 /* reserved */
9751 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9752 +#define SBAM_ADINT0_SHIFT 3
9753 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9754 +#define SBAM_ADINT1_SHIFT 3
9755 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9756 +#define SBAM_ADINT2_SHIFT 3
9757 +#define SBAM_ADEN 0x400 /* enable */
9758 +#define SBAM_ADNEG 0x800 /* negative decode */
9759 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9760 +#define SBAM_BASE0_SHIFT 8
9761 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9762 +#define SBAM_BASE1_SHIFT 12
9763 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9764 +#define SBAM_BASE2_SHIFT 16
9765 +
9766 +/* sbtmconfiglow */
9767 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9768 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9769 +#define SBTMCL_CO_SHIFT 11
9770 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9771 +#define SBTMCL_IF_SHIFT 18
9772 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9773 +#define SBTMCL_IM_SHIFT 24
9774 +
9775 +/* sbtmconfighigh */
9776 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9777 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9778 +#define SBTMCH_RM_SHIFT 2
9779 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9780 +#define SBTMCH_SM_SHIFT 4
9781 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9782 +#define SBTMCH_EM_SHIFT 8
9783 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9784 +#define SBTMCH_IM_SHIFT 10
9785 +
9786 +/* sbbconfig */
9787 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9788 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9789 +#define SBBC_MAX0_SHIFT 16
9790 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9791 +#define SBBC_MAX1_SHIFT 20
9792 +
9793 +/* sbbstate */
9794 +#define SBBS_SRD 0x1 /* st reg disable */
9795 +#define SBBS_HRD 0x2 /* hold reg disable */
9796 +
9797 +/* sbidlow */
9798 +#define SBIDL_CS_MASK 0x3 /* config space */
9799 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9800 +#define SBIDL_AR_SHIFT 3
9801 +#define SBIDL_SYNCH 0x40 /* sync */
9802 +#define SBIDL_INIT 0x80 /* initiator */
9803 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9804 +#define SBIDL_MINLAT_SHIFT 8
9805 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9806 +#define SBIDL_MAXLAT_SHIFT 12
9807 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9808 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9809 +#define SBIDL_CW_SHIFT 18
9810 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9811 +#define SBIDL_TP_SHIFT 20
9812 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9813 +#define SBIDL_IP_SHIFT 24
9814 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9815 +#define SBIDL_RV_SHIFT 28
9816 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9817 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9818 +
9819 +/* sbidhigh */
9820 +#define SBIDH_RC_MASK 0x000f /* revision code */
9821 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9822 +#define SBIDH_RCE_SHIFT 8
9823 +#define SBCOREREV(sbidh) \
9824 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9825 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9826 +#define SBIDH_CC_SHIFT 4
9827 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9828 +#define SBIDH_VC_SHIFT 16
9829 +
9830 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9831 +
9832 +/* vendor codes */
9833 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9834 +
9835 +/* core codes */
9836 +#define SB_CC 0x800 /* chipcommon core */
9837 +#define SB_ILINE20 0x801 /* iline20 core */
9838 +#define SB_SDRAM 0x803 /* sdram core */
9839 +#define SB_PCI 0x804 /* pci core */
9840 +#define SB_MIPS 0x805 /* mips core */
9841 +#define SB_ENET 0x806 /* enet mac core */
9842 +#define SB_CODEC 0x807 /* v90 codec core */
9843 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9844 +#define SB_ADSL 0x809 /* ADSL core */
9845 +#define SB_ILINE100 0x80a /* iline100 core */
9846 +#define SB_IPSEC 0x80b /* ipsec core */
9847 +#define SB_PCMCIA 0x80d /* pcmcia core */
9848 +#define SB_SOCRAM 0x80e /* internal memory core */
9849 +#define SB_MEMC 0x80f /* memc sdram core */
9850 +#define SB_EXTIF 0x811 /* external interface core */
9851 +#define SB_D11 0x812 /* 802.11 MAC core */
9852 +#define SB_MIPS33 0x816 /* mips3302 core */
9853 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9854 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9855 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9856 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9857 +#define SB_SDIOH 0x81b /* sdio host core */
9858 +#define SB_ROBO 0x81c /* roboswitch core */
9859 +#define SB_ATA100 0x81d /* parallel ATA core */
9860 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9861 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9862 +#define SB_PCIE 0x820 /* pci express core */
9863 +#define SB_SRAMC 0x822 /* SRAM controller core */
9864 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9865 +
9866 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9867 +
9868 +/* Not really related to Silicon Backplane, but a couple of software
9869 + * conventions for the use the flash space:
9870 + */
9871 +
9872 +/* Minumum amount of flash we support */
9873 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9874 +
9875 +/* A boot/binary may have an embedded block that describes its size */
9876 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9877 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9878 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9879 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9880 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9881 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9882 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9883 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9884 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9885 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9886 +
9887 +#endif /* _SBCONFIG_H */
9888 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbextif.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbextif.h
9889 --- linux-2.6.17/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9890 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbextif.h 2006-06-18 15:29:23.000000000 +0200
9891 @@ -0,0 +1,242 @@
9892 +/*
9893 + * Hardware-specific External Interface I/O core definitions
9894 + * for the BCM47xx family of SiliconBackplane-based chips.
9895 + *
9896 + * The External Interface core supports a total of three external chip selects
9897 + * supporting external interfaces. One of the external chip selects is
9898 + * used for Flash, one is used for PCMCIA, and the other may be
9899 + * programmed to support either a synchronous interface or an
9900 + * asynchronous interface. The asynchronous interface can be used to
9901 + * support external devices such as UARTs and the BCM2019 Bluetooth
9902 + * baseband processor.
9903 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9904 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9905 + *
9906 + * Copyright 2005, Broadcom Corporation
9907 + * All Rights Reserved.
9908 + *
9909 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9910 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9911 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9912 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9913 + * $Id$
9914 + */
9915 +
9916 +#ifndef _SBEXTIF_H
9917 +#define _SBEXTIF_H
9918 +
9919 +/* external interface address space */
9920 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9921 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9922 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9923 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9924 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9925 +
9926 +/* cpp contortions to concatenate w/arg prescan */
9927 +#ifndef PAD
9928 +#define _PADLINE(line) pad ## line
9929 +#define _XSTR(line) _PADLINE(line)
9930 +#define PAD _XSTR(__LINE__)
9931 +#endif /* PAD */
9932 +
9933 +/*
9934 + * The multiple instances of output and output enable registers
9935 + * are present to allow driver software for multiple cores to control
9936 + * gpio outputs without needing to share a single register pair.
9937 + */
9938 +struct gpiouser {
9939 + uint32 out;
9940 + uint32 outen;
9941 +};
9942 +#define NGPIOUSER 5
9943 +
9944 +typedef volatile struct {
9945 + uint32 corecontrol;
9946 + uint32 extstatus;
9947 + uint32 PAD[2];
9948 +
9949 + /* pcmcia control registers */
9950 + uint32 pcmcia_config;
9951 + uint32 pcmcia_memwait;
9952 + uint32 pcmcia_attrwait;
9953 + uint32 pcmcia_iowait;
9954 +
9955 + /* programmable interface control registers */
9956 + uint32 prog_config;
9957 + uint32 prog_waitcount;
9958 +
9959 + /* flash control registers */
9960 + uint32 flash_config;
9961 + uint32 flash_waitcount;
9962 + uint32 PAD[4];
9963 +
9964 + uint32 watchdog;
9965 +
9966 + /* clock control */
9967 + uint32 clockcontrol_n;
9968 + uint32 clockcontrol_sb;
9969 + uint32 clockcontrol_pci;
9970 + uint32 clockcontrol_mii;
9971 + uint32 PAD[3];
9972 +
9973 + /* gpio */
9974 + uint32 gpioin;
9975 + struct gpiouser gpio[NGPIOUSER];
9976 + uint32 PAD;
9977 + uint32 ejtagouten;
9978 + uint32 gpiointpolarity;
9979 + uint32 gpiointmask;
9980 + uint32 PAD[153];
9981 +
9982 + uint8 uartdata;
9983 + uint8 PAD[3];
9984 + uint8 uartimer;
9985 + uint8 PAD[3];
9986 + uint8 uartfcr;
9987 + uint8 PAD[3];
9988 + uint8 uartlcr;
9989 + uint8 PAD[3];
9990 + uint8 uartmcr;
9991 + uint8 PAD[3];
9992 + uint8 uartlsr;
9993 + uint8 PAD[3];
9994 + uint8 uartmsr;
9995 + uint8 PAD[3];
9996 + uint8 uartscratch;
9997 + uint8 PAD[3];
9998 +} extifregs_t;
9999 +
10000 +/* corecontrol */
10001 +#define CC_UE (1 << 0) /* uart enable */
10002 +
10003 +/* extstatus */
10004 +#define ES_EM (1 << 0) /* endian mode (ro) */
10005 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10006 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10007 +
10008 +/* gpio bit mask */
10009 +#define GPIO_BIT0 (1 << 0)
10010 +#define GPIO_BIT1 (1 << 1)
10011 +#define GPIO_BIT2 (1 << 2)
10012 +#define GPIO_BIT3 (1 << 3)
10013 +#define GPIO_BIT4 (1 << 4)
10014 +#define GPIO_BIT5 (1 << 5)
10015 +#define GPIO_BIT6 (1 << 6)
10016 +#define GPIO_BIT7 (1 << 7)
10017 +
10018 +
10019 +/* pcmcia/prog/flash_config */
10020 +#define CF_EN (1 << 0) /* enable */
10021 +#define CF_EM_MASK 0xe /* mode */
10022 +#define CF_EM_SHIFT 1
10023 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10024 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10025 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10026 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10027 +#define CF_BS (1 << 5) /* byteswap */
10028 +#define CF_CD_MASK 0xc0 /* clock divider */
10029 +#define CF_CD_SHIFT 6
10030 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10031 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10032 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10033 +#define CF_CE (1 << 8) /* clock enable */
10034 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10035 +
10036 +/* pcmcia_memwait */
10037 +#define PM_W0_MASK 0x3f /* waitcount0 */
10038 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10039 +#define PM_W1_SHIFT 8
10040 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10041 +#define PM_W2_SHIFT 16
10042 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10043 +#define PM_W3_SHIFT 24
10044 +
10045 +/* pcmcia_attrwait */
10046 +#define PA_W0_MASK 0x3f /* waitcount0 */
10047 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10048 +#define PA_W1_SHIFT 8
10049 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10050 +#define PA_W2_SHIFT 16
10051 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10052 +#define PA_W3_SHIFT 24
10053 +
10054 +/* pcmcia_iowait */
10055 +#define PI_W0_MASK 0x3f /* waitcount0 */
10056 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10057 +#define PI_W1_SHIFT 8
10058 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10059 +#define PI_W2_SHIFT 16
10060 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10061 +#define PI_W3_SHIFT 24
10062 +
10063 +/* prog_waitcount */
10064 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10065 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10066 +#define PW_W1_SHIFT 8
10067 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10068 +#define PW_W2_SHIFT 16
10069 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10070 +#define PW_W3_SHIFT 24
10071 +
10072 +#define PW_W0 0x0000000c
10073 +#define PW_W1 0x00000a00
10074 +#define PW_W2 0x00020000
10075 +#define PW_W3 0x01000000
10076 +
10077 +/* flash_waitcount */
10078 +#define FW_W0_MASK 0x1f /* waitcount0 */
10079 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10080 +#define FW_W1_SHIFT 8
10081 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10082 +#define FW_W2_SHIFT 16
10083 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10084 +#define FW_W3_SHIFT 24
10085 +
10086 +/* watchdog */
10087 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10088 +
10089 +/* clockcontrol_n */
10090 +#define CN_N1_MASK 0x3f /* n1 control */
10091 +#define CN_N2_MASK 0x3f00 /* n2 control */
10092 +#define CN_N2_SHIFT 8
10093 +
10094 +/* clockcontrol_sb/pci/mii */
10095 +#define CC_M1_MASK 0x3f /* m1 control */
10096 +#define CC_M2_MASK 0x3f00 /* m2 control */
10097 +#define CC_M2_SHIFT 8
10098 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10099 +#define CC_M3_SHIFT 16
10100 +#define CC_MC_MASK 0x1f000000 /* mux control */
10101 +#define CC_MC_SHIFT 24
10102 +
10103 +/* Clock control default values */
10104 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10105 +#define CC_DEF_100 0x04020011
10106 +#define CC_DEF_33 0x11030011
10107 +#define CC_DEF_25 0x11050011
10108 +
10109 +/* Clock control values for 125Mhz */
10110 +#define CC_125_N 0x0802
10111 +#define CC_125_M 0x04020009
10112 +#define CC_125_M25 0x11090009
10113 +#define CC_125_M33 0x11090005
10114 +
10115 +/* Clock control magic field values */
10116 +#define CC_F6_2 0x02 /* A factor of 2 in */
10117 +#define CC_F6_3 0x03 /* 6-bit fields like */
10118 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10119 +#define CC_F6_5 0x09
10120 +#define CC_F6_6 0x11
10121 +#define CC_F6_7 0x21
10122 +
10123 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10124 +
10125 +#define CC_MC_BYPASS 0x08
10126 +#define CC_MC_M1 0x04
10127 +#define CC_MC_M1M2 0x02
10128 +#define CC_MC_M1M2M3 0x01
10129 +#define CC_MC_M1M3 0x11
10130 +
10131 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10132 +
10133 +#endif /* _SBEXTIF_H */
10134 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbmemc.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbmemc.h
10135 --- linux-2.6.17/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10136 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbmemc.h 2006-06-18 15:29:23.000000000 +0200
10137 @@ -0,0 +1,148 @@
10138 +/*
10139 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10140 + *
10141 + * Copyright 2005, Broadcom Corporation
10142 + * All Rights Reserved.
10143 + *
10144 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10145 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10146 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10147 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10148 + *
10149 + * $Id$
10150 + */
10151 +
10152 +#ifndef _SBMEMC_H
10153 +#define _SBMEMC_H
10154 +
10155 +#ifdef _LANGUAGE_ASSEMBLY
10156 +
10157 +#define MEMC_CONTROL 0x00
10158 +#define MEMC_CONFIG 0x04
10159 +#define MEMC_REFRESH 0x08
10160 +#define MEMC_BISTSTAT 0x0c
10161 +#define MEMC_MODEBUF 0x10
10162 +#define MEMC_BKCLS 0x14
10163 +#define MEMC_PRIORINV 0x18
10164 +#define MEMC_DRAMTIM 0x1c
10165 +#define MEMC_INTSTAT 0x20
10166 +#define MEMC_INTMASK 0x24
10167 +#define MEMC_INTINFO 0x28
10168 +#define MEMC_NCDLCTL 0x30
10169 +#define MEMC_RDNCDLCOR 0x34
10170 +#define MEMC_WRNCDLCOR 0x38
10171 +#define MEMC_MISCDLYCTL 0x3c
10172 +#define MEMC_DQSGATENCDL 0x40
10173 +#define MEMC_SPARE 0x44
10174 +#define MEMC_TPADDR 0x48
10175 +#define MEMC_TPDATA 0x4c
10176 +#define MEMC_BARRIER 0x50
10177 +#define MEMC_CORE 0x54
10178 +
10179 +
10180 +#else
10181 +
10182 +/* Sonics side: MEMC core registers */
10183 +typedef volatile struct sbmemcregs {
10184 + uint32 control;
10185 + uint32 config;
10186 + uint32 refresh;
10187 + uint32 biststat;
10188 + uint32 modebuf;
10189 + uint32 bkcls;
10190 + uint32 priorinv;
10191 + uint32 dramtim;
10192 + uint32 intstat;
10193 + uint32 intmask;
10194 + uint32 intinfo;
10195 + uint32 reserved1;
10196 + uint32 ncdlctl;
10197 + uint32 rdncdlcor;
10198 + uint32 wrncdlcor;
10199 + uint32 miscdlyctl;
10200 + uint32 dqsgatencdl;
10201 + uint32 spare;
10202 + uint32 tpaddr;
10203 + uint32 tpdata;
10204 + uint32 barrier;
10205 + uint32 core;
10206 +} sbmemcregs_t;
10207 +
10208 +#endif
10209 +
10210 +/* MEMC Core Init values (OCP ID 0x80f) */
10211 +
10212 +/* For sdr: */
10213 +#define MEMC_SD_CONFIG_INIT 0x00048000
10214 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10215 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10216 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10217 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10218 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10219 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10220 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10221 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10222 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10223 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10224 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10225 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10226 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10227 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10228 +
10229 +
10230 +/* This is for SDRM8X8X4 */
10231 +#define MEMC_SDR_INIT 0x0008
10232 +#define MEMC_SDR_MODE 0x32
10233 +#define MEMC_SDR_NCDL 0x00020032
10234 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10235 +
10236 +/* For ddr: */
10237 +#define MEMC_CONFIG_INIT 0x00048000
10238 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10239 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10240 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10241 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10242 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10243 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10244 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10245 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10246 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10247 +#define MEMC_NCDLCTL_INIT 0x00002001
10248 +#define MEMC_CONTROL_INIT0 0x00000002
10249 +#define MEMC_CONTROL_INIT1 0x00000008
10250 +#define MEMC_MODEBUF_INIT0 0x00004000
10251 +#define MEMC_CONTROL_INIT2 0x00000010
10252 +#define MEMC_MODEBUF_INIT1 0x00000100
10253 +#define MEMC_CONTROL_INIT3 0x00000010
10254 +#define MEMC_CONTROL_INIT4 0x00000008
10255 +#define MEMC_REFRESH_INIT 0x0000840f
10256 +#define MEMC_CONTROL_INIT5 0x00000004
10257 +#define MEMC_MODEBUF_INIT2 0x00000000
10258 +#define MEMC_CONTROL_INIT6 0x00000010
10259 +#define MEMC_CONTROL_INIT7 0x00000001
10260 +
10261 +
10262 +/* This is for DDRM16X16X2 */
10263 +#define MEMC_DDR_INIT 0x0009
10264 +#define MEMC_DDR_MODE 0x62
10265 +#define MEMC_DDR_NCDL 0x0005050a
10266 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10267 +
10268 +/* mask for sdr/ddr calibration registers */
10269 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10270 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10271 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10272 +
10273 +/* masks for miscdlyctl registers */
10274 +#define MEMC_MISC_SM_MASK 0x30000000
10275 +#define MEMC_MISC_SM_SHIFT 28
10276 +#define MEMC_MISC_SD_MASK 0x0f000000
10277 +#define MEMC_MISC_SD_SHIFT 24
10278 +
10279 +/* hw threshhold for calculating wr/rd for sdr memc */
10280 +#define MEMC_CD_THRESHOLD 128
10281 +
10282 +/* Low bit of init register says if memc is ddr or sdr */
10283 +#define MEMC_CONFIG_DDR 0x00000001
10284 +
10285 +#endif /* _SBMEMC_H */
10286 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbmips.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbmips.h
10287 --- linux-2.6.17/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10288 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbmips.h 2006-06-18 15:29:23.000000000 +0200
10289 @@ -0,0 +1,62 @@
10290 +/*
10291 + * Broadcom SiliconBackplane MIPS definitions
10292 + *
10293 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10294 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10295 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10296 + * interface. The core revision is stored in the SB ID register in SB
10297 + * configuration space.
10298 + *
10299 + * Copyright 2005, Broadcom Corporation
10300 + * All Rights Reserved.
10301 + *
10302 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10303 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10304 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10305 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10306 + *
10307 + * $Id$
10308 + */
10309 +
10310 +#ifndef _SBMIPS_H
10311 +#define _SBMIPS_H
10312 +
10313 +#include <mipsinc.h>
10314 +
10315 +#ifndef _LANGUAGE_ASSEMBLY
10316 +
10317 +/* cpp contortions to concatenate w/arg prescan */
10318 +#ifndef PAD
10319 +#define _PADLINE(line) pad ## line
10320 +#define _XSTR(line) _PADLINE(line)
10321 +#define PAD _XSTR(__LINE__)
10322 +#endif /* PAD */
10323 +
10324 +typedef volatile struct {
10325 + uint32 corecontrol;
10326 + uint32 PAD[2];
10327 + uint32 biststatus;
10328 + uint32 PAD[4];
10329 + uint32 intstatus;
10330 + uint32 intmask;
10331 + uint32 timer;
10332 +} mipsregs_t;
10333 +
10334 +extern uint32 sb_flag(sb_t *sbh);
10335 +extern uint sb_irq(sb_t *sbh);
10336 +
10337 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10338 +
10339 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10340 +extern void sb_jtagm_disable(void *h);
10341 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10342 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10343 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10344 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10345 +extern void BCMINIT(enable_pfc)(uint32 mode);
10346 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10347 +
10348 +
10349 +#endif /* _LANGUAGE_ASSEMBLY */
10350 +
10351 +#endif /* _SBMIPS_H */
10352 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbpci.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbpci.h
10353 --- linux-2.6.17/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10354 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbpci.h 2006-06-18 15:29:23.000000000 +0200
10355 @@ -0,0 +1,122 @@
10356 +/*
10357 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10358 + *
10359 + * $Id$
10360 + * Copyright 2005, Broadcom Corporation
10361 + * All Rights Reserved.
10362 + *
10363 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10364 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10365 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10366 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10367 + */
10368 +
10369 +#ifndef _SBPCI_H
10370 +#define _SBPCI_H
10371 +
10372 +/* cpp contortions to concatenate w/arg prescan */
10373 +#ifndef PAD
10374 +#define _PADLINE(line) pad ## line
10375 +#define _XSTR(line) _PADLINE(line)
10376 +#define PAD _XSTR(__LINE__)
10377 +#endif
10378 +
10379 +/* Sonics side: PCI core and host control registers */
10380 +typedef struct sbpciregs {
10381 + uint32 control; /* PCI control */
10382 + uint32 PAD[3];
10383 + uint32 arbcontrol; /* PCI arbiter control */
10384 + uint32 PAD[3];
10385 + uint32 intstatus; /* Interrupt status */
10386 + uint32 intmask; /* Interrupt mask */
10387 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10388 + uint32 PAD[9];
10389 + uint32 bcastaddr; /* Sonics broadcast address */
10390 + uint32 bcastdata; /* Sonics broadcast data */
10391 + uint32 PAD[2];
10392 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10393 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10394 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10395 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10396 + uint32 PAD[36];
10397 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10398 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10399 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10400 + uint32 PAD[445];
10401 + uint16 sprom[36]; /* SPROM shadow Area */
10402 + uint32 PAD[46];
10403 +} sbpciregs_t;
10404 +
10405 +/* PCI control */
10406 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10407 +#define PCI_RST 0x02 /* Value driven out to pin */
10408 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10409 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10410 +
10411 +/* PCI arbiter control */
10412 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10413 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10414 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10415 +#define PCI_PARKID_SHIFT 1
10416 +#define PCI_PARKID_LAST 0 /* Last requestor */
10417 +#define PCI_PARKID_4710 1 /* 4710 */
10418 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10419 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10420 +
10421 +/* Interrupt status/mask */
10422 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10423 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10424 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10425 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10426 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10427 +
10428 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10429 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10430 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10431 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10432 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10433 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10434 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10435 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10436 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10437 +
10438 +/* Sonics broadcast address */
10439 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10440 +
10441 +/* Sonics to PCI translation types */
10442 +#define SBTOPCI0_MASK 0xfc000000
10443 +#define SBTOPCI1_MASK 0xfc000000
10444 +#define SBTOPCI2_MASK 0xc0000000
10445 +#define SBTOPCI_MEM 0
10446 +#define SBTOPCI_IO 1
10447 +#define SBTOPCI_CFG0 2
10448 +#define SBTOPCI_CFG1 3
10449 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10450 +#define SBTOPCI_BURST 0x8 /* burst enable */
10451 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10452 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10453 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10454 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10455 +
10456 +/* PCI core index in SROM shadow area */
10457 +#define SRSH_PI_OFFSET 0 /* first word */
10458 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10459 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10460 +
10461 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10462 +#define cap_list rsvd_a[0]
10463 +#define bar0_window dev_dep[0x80 - 0x40]
10464 +#define bar1_window dev_dep[0x84 - 0x40]
10465 +#define sprom_control dev_dep[0x88 - 0x40]
10466 +
10467 +#ifndef _LANGUAGE_ASSEMBLY
10468 +
10469 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10470 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10471 +extern void sbpci_ban(uint16 core);
10472 +extern int sbpci_init(sb_t *sbh);
10473 +extern void sbpci_check(sb_t *sbh);
10474 +
10475 +#endif /* !_LANGUAGE_ASSEMBLY */
10476 +
10477 +#endif /* _SBPCI_H */
10478 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbsdram.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbsdram.h
10479 --- linux-2.6.17/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10480 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbsdram.h 2006-06-18 15:29:23.000000000 +0200
10481 @@ -0,0 +1,75 @@
10482 +/*
10483 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10484 + *
10485 + * Copyright 2005, Broadcom Corporation
10486 + * All Rights Reserved.
10487 + *
10488 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10489 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10490 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10491 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10492 + * $Id$
10493 + */
10494 +
10495 +#ifndef _SBSDRAM_H
10496 +#define _SBSDRAM_H
10497 +
10498 +#ifndef _LANGUAGE_ASSEMBLY
10499 +
10500 +/* Sonics side: SDRAM core registers */
10501 +typedef volatile struct sbsdramregs {
10502 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10503 + uint32 config; /* Initializes external SDRAM mode register */
10504 + uint32 refresh; /* Controls external SDRAM refresh rate */
10505 + uint32 pad1;
10506 + uint32 pad2;
10507 +} sbsdramregs_t;
10508 +
10509 +#endif
10510 +
10511 +/* SDRAM initialization control (initcontrol) register bits */
10512 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10513 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10514 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10515 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10516 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10517 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10518 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10519 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10520 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10521 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10522 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10523 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10524 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10525 +
10526 +/* SDRAM configuration (config) register bits */
10527 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10528 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10529 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10530 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10531 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10532 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10533 +
10534 +/* SDRAM refresh control (refresh) register bits */
10535 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10536 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10537 +
10538 +/* SDRAM Core default Init values (OCP ID 0x803) */
10539 +#define SDRAM_INIT MEM4MX16X2
10540 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10541 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10542 +
10543 +#define MEM1MX16 0x009 /* 2 MB */
10544 +#define MEM1MX16X2 0x409 /* 4 MB */
10545 +#define MEM2MX8X2 0x809 /* 4 MB */
10546 +#define MEM2MX8X4 0xc09 /* 8 MB */
10547 +#define MEM2MX32 0x439 /* 8 MB */
10548 +#define MEM4MX16 0x019 /* 8 MB */
10549 +#define MEM4MX16X2 0x419 /* 16 MB */
10550 +#define MEM8MX8X2 0x819 /* 16 MB */
10551 +#define MEM8MX16 0x829 /* 16 MB */
10552 +#define MEM4MX32 0x429 /* 16 MB */
10553 +#define MEM8MX8X4 0xc19 /* 32 MB */
10554 +#define MEM8MX16X2 0xc29 /* 32 MB */
10555 +
10556 +#endif /* _SBSDRAM_H */
10557 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sbutils.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbutils.h
10558 --- linux-2.6.17/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10559 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sbutils.h 2006-06-18 15:29:23.000000000 +0200
10560 @@ -0,0 +1,136 @@
10561 +/*
10562 + * Misc utility routines for accessing chip-specific features
10563 + * of Broadcom HNBU SiliconBackplane-based chips.
10564 + *
10565 + * Copyright 2005, Broadcom Corporation
10566 + * All Rights Reserved.
10567 + *
10568 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10569 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10570 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10571 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10572 + *
10573 + * $Id$
10574 + */
10575 +
10576 +#ifndef _sbutils_h_
10577 +#define _sbutils_h_
10578 +
10579 +/*
10580 + * Datastructure to export all chip specific common variables
10581 + * public (read-only) portion of sbutils handle returned by
10582 + * sb_attach()/sb_kattach()
10583 +*/
10584 +
10585 +struct sb_pub {
10586 +
10587 + uint bustype; /* SB_BUS, PCI_BUS */
10588 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10589 + uint buscorerev; /* buscore rev */
10590 + uint buscoreidx; /* buscore index */
10591 + int ccrev; /* chip common core rev */
10592 + uint boardtype; /* board type */
10593 + uint boardvendor; /* board vendor */
10594 + uint chip; /* chip number */
10595 + uint chiprev; /* chip revision */
10596 + uint chippkg; /* chip package option */
10597 + uint sonicsrev; /* sonics backplane rev */
10598 +};
10599 +
10600 +typedef const struct sb_pub sb_t;
10601 +
10602 +/*
10603 + * Many of the routines below take an 'sbh' handle as their first arg.
10604 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10605 + * At any one time, the sbh is logically focused on one particular sb core
10606 + * (the "current core").
10607 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10608 + */
10609 +
10610 +/* exported externs */
10611 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10612 +extern sb_t * BCMINIT(sb_kattach)(void);
10613 +extern void sb_detach(sb_t *sbh);
10614 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10615 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10616 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10617 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10618 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10619 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10620 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10621 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10622 +extern uint sb_bus(sb_t *sbh);
10623 +extern uint sb_buscoretype(sb_t *sbh);
10624 +extern uint sb_buscorerev(sb_t *sbh);
10625 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10626 +extern uint sb_coreid(sb_t *sbh);
10627 +extern uint sb_coreidx(sb_t *sbh);
10628 +extern uint sb_coreunit(sb_t *sbh);
10629 +extern uint sb_corevendor(sb_t *sbh);
10630 +extern uint sb_corerev(sb_t *sbh);
10631 +extern void *sb_osh(sb_t *sbh);
10632 +extern void *sb_coreregs(sb_t *sbh);
10633 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10634 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10635 +extern bool sb_iscoreup(sb_t *sbh);
10636 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10637 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10638 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10639 +extern void sb_commit(sb_t *sbh);
10640 +extern uint32 sb_base(uint32 admatch);
10641 +extern uint32 sb_size(uint32 admatch);
10642 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10643 +extern void sb_core_tofixup(sb_t *sbh);
10644 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10645 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10646 +extern uint32 sb_clock(sb_t *sbh);
10647 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10648 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10649 +extern void *sb_gpiosetcore(sb_t *sbh);
10650 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10651 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10652 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10653 +extern uint32 sb_gpioin(sb_t *sbh);
10654 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10655 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10656 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10657 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10658 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10659 +
10660 +extern void sb_clkctl_init(sb_t *sbh);
10661 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10662 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10663 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10664 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10665 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10666 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10667 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10668 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10669 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10670 +
10671 +
10672 +
10673 +/*
10674 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10675 +* The returned path is NULL terminated and has trailing '/'.
10676 +* Return 0 on success, nonzero otherwise.
10677 +*/
10678 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10679 +
10680 +/* clkctl xtal what flags */
10681 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10682 +#define PLL 0x2 /* main chip pll */
10683 +
10684 +/* clkctl clk mode */
10685 +#define CLK_FAST 0 /* force fast (pll) clock */
10686 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10687 +
10688 +
10689 +/* GPIO usage priorities */
10690 +#define GPIO_DRV_PRIORITY 0
10691 +#define GPIO_APP_PRIORITY 1
10692 +
10693 +/* device path */
10694 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10695 +
10696 +#endif /* _sbutils_h_ */
10697 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/sflash.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/sflash.h
10698 --- linux-2.6.17/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10699 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/sflash.h 2006-06-18 15:29:23.000000000 +0200
10700 @@ -0,0 +1,36 @@
10701 +/*
10702 + * Broadcom SiliconBackplane chipcommon serial flash interface
10703 + *
10704 + * Copyright 2005, Broadcom Corporation
10705 + * All Rights Reserved.
10706 + *
10707 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10708 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10709 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10710 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10711 + *
10712 + * $Id$
10713 + */
10714 +
10715 +#ifndef _sflash_h_
10716 +#define _sflash_h_
10717 +
10718 +#include <typedefs.h>
10719 +#include <sbchipc.h>
10720 +
10721 +struct sflash {
10722 + uint blocksize; /* Block size */
10723 + uint numblocks; /* Number of blocks */
10724 + uint32 type; /* Type */
10725 + uint size; /* Total size in bytes */
10726 +};
10727 +
10728 +/* Utility functions */
10729 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10730 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10731 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10732 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10733 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10734 +extern struct sflash * sflash_init(chipcregs_t *cc);
10735 +
10736 +#endif /* _sflash_h_ */
10737 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/trxhdr.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/trxhdr.h
10738 --- linux-2.6.17/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10739 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/trxhdr.h 2006-06-18 15:29:23.000000000 +0200
10740 @@ -0,0 +1,33 @@
10741 +/*
10742 + * TRX image file header format.
10743 + *
10744 + * Copyright 2005, Broadcom Corporation
10745 + * All Rights Reserved.
10746 + *
10747 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10748 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10749 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10750 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10751 + *
10752 + * $Id$
10753 + */
10754 +
10755 +#include <typedefs.h>
10756 +
10757 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10758 +#define TRX_VERSION 1
10759 +#define TRX_MAX_LEN 0x3A0000
10760 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10761 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10762 +#define TRX_MAX_OFFSET 3
10763 +
10764 +struct trx_header {
10765 + uint32 magic; /* "HDR0" */
10766 + uint32 len; /* Length of file including header */
10767 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10768 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10769 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10770 +};
10771 +
10772 +/* Compatibility */
10773 +typedef struct trx_header TRXHDR, *PTRXHDR;
10774 diff -Nur linux-2.6.17/arch/mips/bcm947xx/include/typedefs.h linux-2.6.17-owrt/arch/mips/bcm947xx/include/typedefs.h
10775 --- linux-2.6.17/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10776 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/include/typedefs.h 2006-06-18 15:29:23.000000000 +0200
10777 @@ -0,0 +1,326 @@
10778 +/*
10779 + * Copyright 2005, Broadcom Corporation
10780 + * All Rights Reserved.
10781 + *
10782 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10783 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10784 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10785 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10786 + * $Id$
10787 + */
10788 +
10789 +#ifndef _TYPEDEFS_H_
10790 +#define _TYPEDEFS_H_
10791 +
10792 +
10793 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10794 + * typedef file "site_typedefs.h".
10795 + *
10796 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10797 + * section of this file makes inferences about the compile environment
10798 + * based on defined symbols and possibly compiler pragmas.
10799 + *
10800 + * Following these two sections is the "Default Typedefs"
10801 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10802 + * defined. This section has a default set of typedefs and a few
10803 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10804 + */
10805 +
10806 +#ifdef SITE_TYPEDEFS
10807 +
10808 +/*******************************************************************************
10809 + * Site Specific Typedefs
10810 + *******************************************************************************/
10811 +
10812 +#include "site_typedefs.h"
10813 +
10814 +#else
10815 +
10816 +/*******************************************************************************
10817 + * Inferred Typedefs
10818 + *******************************************************************************/
10819 +
10820 +/* Infer the compile environment based on preprocessor symbols and pramas.
10821 + * Override type definitions as needed, and include configuration dependent
10822 + * header files to define types.
10823 + */
10824 +
10825 +#ifdef __cplusplus
10826 +
10827 +#define TYPEDEF_BOOL
10828 +#ifndef FALSE
10829 +#define FALSE false
10830 +#endif
10831 +#ifndef TRUE
10832 +#define TRUE true
10833 +#endif
10834 +
10835 +#else /* ! __cplusplus */
10836 +
10837 +#if defined(_WIN32)
10838 +
10839 +#define TYPEDEF_BOOL
10840 +typedef unsigned char bool; /* consistent w/BOOL */
10841 +
10842 +#endif /* _WIN32 */
10843 +
10844 +#endif /* ! __cplusplus */
10845 +
10846 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10847 +#if defined(_WIN64)
10848 +#include <basetsd.h>
10849 +#define TYPEDEF_UINTPTR
10850 +typedef ULONG_PTR uintptr;
10851 +#endif
10852 +
10853 +#ifdef _HNDRTE_
10854 +typedef long unsigned int size_t;
10855 +#endif
10856 +
10857 +#ifdef _MSC_VER /* Microsoft C */
10858 +#define TYPEDEF_INT64
10859 +#define TYPEDEF_UINT64
10860 +typedef signed __int64 int64;
10861 +typedef unsigned __int64 uint64;
10862 +#endif
10863 +
10864 +#if defined(MACOSX) && defined(KERNEL)
10865 +#define TYPEDEF_BOOL
10866 +#endif
10867 +
10868 +
10869 +#if defined(linux)
10870 +#define TYPEDEF_UINT
10871 +#define TYPEDEF_USHORT
10872 +#define TYPEDEF_ULONG
10873 +#endif
10874 +
10875 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10876 +#define TYPEDEF_UINT
10877 +#define TYPEDEF_USHORT
10878 +#endif
10879 +
10880 +
10881 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10882 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10883 +#define TYPEDEF_INT64
10884 +#define TYPEDEF_UINT64
10885 +#endif
10886 +
10887 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10888 + * for singned or unsigned */
10889 +#if defined(__ICL)
10890 +
10891 +#define TYPEDEF_INT64
10892 +
10893 +#if defined(__STDC__)
10894 +#define TYPEDEF_UINT64
10895 +#endif
10896 +
10897 +#endif /* __ICL */
10898 +
10899 +
10900 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10901 +
10902 +/* pick up ushort & uint from standard types.h */
10903 +#if defined(linux) && defined(__KERNEL__)
10904 +
10905 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10906 +
10907 +#else
10908 +
10909 +#include <sys/types.h>
10910 +
10911 +#endif
10912 +
10913 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10914 +
10915 +#if defined(MACOSX) && defined(KERNEL)
10916 +#include <IOKit/IOTypes.h>
10917 +#endif
10918 +
10919 +
10920 +/* use the default typedefs in the next section of this file */
10921 +#define USE_TYPEDEF_DEFAULTS
10922 +
10923 +#endif /* SITE_TYPEDEFS */
10924 +
10925 +
10926 +/*******************************************************************************
10927 + * Default Typedefs
10928 + *******************************************************************************/
10929 +
10930 +#ifdef USE_TYPEDEF_DEFAULTS
10931 +#undef USE_TYPEDEF_DEFAULTS
10932 +
10933 +#ifndef TYPEDEF_BOOL
10934 +typedef /*@abstract@*/ unsigned char bool;
10935 +#endif
10936 +
10937 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10938 +
10939 +#ifndef TYPEDEF_UCHAR
10940 +typedef unsigned char uchar;
10941 +#endif
10942 +
10943 +#ifndef TYPEDEF_USHORT
10944 +typedef unsigned short ushort;
10945 +#endif
10946 +
10947 +#ifndef TYPEDEF_UINT
10948 +typedef unsigned int uint;
10949 +#endif
10950 +
10951 +#ifndef TYPEDEF_ULONG
10952 +typedef unsigned long ulong;
10953 +#endif
10954 +
10955 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
10956 +
10957 +#ifndef TYPEDEF_UINT8
10958 +typedef unsigned char uint8;
10959 +#endif
10960 +
10961 +#ifndef TYPEDEF_UINT16
10962 +typedef unsigned short uint16;
10963 +#endif
10964 +
10965 +#ifndef TYPEDEF_UINT32
10966 +typedef unsigned int uint32;
10967 +#endif
10968 +
10969 +#ifndef TYPEDEF_UINT64
10970 +typedef unsigned long long uint64;
10971 +#endif
10972 +
10973 +#ifndef TYPEDEF_UINTPTR
10974 +typedef unsigned int uintptr;
10975 +#endif
10976 +
10977 +#ifndef TYPEDEF_INT8
10978 +typedef signed char int8;
10979 +#endif
10980 +
10981 +#ifndef TYPEDEF_INT16
10982 +typedef signed short int16;
10983 +#endif
10984 +
10985 +#ifndef TYPEDEF_INT32
10986 +typedef signed int int32;
10987 +#endif
10988 +
10989 +#ifndef TYPEDEF_INT64
10990 +typedef signed long long int64;
10991 +#endif
10992 +
10993 +/*----------------------- define float32/64, float_t -----------------------*/
10994 +
10995 +#ifndef TYPEDEF_FLOAT32
10996 +typedef float float32;
10997 +#endif
10998 +
10999 +#ifndef TYPEDEF_FLOAT64
11000 +typedef double float64;
11001 +#endif
11002 +
11003 +/*
11004 + * abstracted floating point type allows for compile time selection of
11005 + * single or double precision arithmetic. Compiling with -DFLOAT32
11006 + * selects single precision; the default is double precision.
11007 + */
11008 +
11009 +#ifndef TYPEDEF_FLOAT_T
11010 +
11011 +#if defined(FLOAT32)
11012 +typedef float32 float_t;
11013 +#else /* default to double precision floating point */
11014 +typedef float64 float_t;
11015 +#endif
11016 +
11017 +#endif /* TYPEDEF_FLOAT_T */
11018 +
11019 +/*----------------------- define macro values -----------------------------*/
11020 +
11021 +#ifndef FALSE
11022 +#define FALSE 0
11023 +#endif
11024 +
11025 +#ifndef TRUE
11026 +#define TRUE 1
11027 +#endif
11028 +
11029 +#ifndef NULL
11030 +#define NULL 0
11031 +#endif
11032 +
11033 +#ifndef OFF
11034 +#define OFF 0
11035 +#endif
11036 +
11037 +#ifndef ON
11038 +#define ON 1
11039 +#endif
11040 +
11041 +#define AUTO (-1)
11042 +
11043 +/* Reclaiming text and data :
11044 + The following macros specify special linker sections that can be reclaimed
11045 + after a system is considered 'up'.
11046 + */
11047 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11048 +extern bool bcmreclaimed;
11049 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11050 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11051 +#define BCMINIT(_id) _id##_ini
11052 +#else
11053 +#define BCMINITDATA(_data) _data
11054 +#define BCMINITFN(_fn) _fn
11055 +#define BCMINIT(_id) _id
11056 +#define bcmreclaimed 0
11057 +#endif
11058 +
11059 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11060 +
11061 +#ifndef PTRSZ
11062 +#define PTRSZ sizeof (char*)
11063 +#endif
11064 +
11065 +#ifndef INLINE
11066 +
11067 +#ifdef _MSC_VER
11068 +
11069 +#define INLINE __inline
11070 +
11071 +#elif __GNUC__
11072 +
11073 +#define INLINE __inline__
11074 +
11075 +#else
11076 +
11077 +#define INLINE
11078 +
11079 +#endif /* _MSC_VER */
11080 +
11081 +#endif /* INLINE */
11082 +
11083 +#undef TYPEDEF_BOOL
11084 +#undef TYPEDEF_UCHAR
11085 +#undef TYPEDEF_USHORT
11086 +#undef TYPEDEF_UINT
11087 +#undef TYPEDEF_ULONG
11088 +#undef TYPEDEF_UINT8
11089 +#undef TYPEDEF_UINT16
11090 +#undef TYPEDEF_UINT32
11091 +#undef TYPEDEF_UINT64
11092 +#undef TYPEDEF_UINTPTR
11093 +#undef TYPEDEF_INT8
11094 +#undef TYPEDEF_INT16
11095 +#undef TYPEDEF_INT32
11096 +#undef TYPEDEF_INT64
11097 +#undef TYPEDEF_FLOAT32
11098 +#undef TYPEDEF_FLOAT64
11099 +#undef TYPEDEF_FLOAT_T
11100 +
11101 +#endif /* USE_TYPEDEF_DEFAULTS */
11102 +
11103 +#endif /* _TYPEDEFS_H_ */
11104 diff -Nur linux-2.6.17/arch/mips/bcm947xx/irq.c linux-2.6.17-owrt/arch/mips/bcm947xx/irq.c
11105 --- linux-2.6.17/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11106 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/irq.c 2006-06-18 15:32:25.000000000 +0200
11107 @@ -0,0 +1,64 @@
11108 +/*
11109 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11110 + *
11111 + * This program is free software; you can redistribute it and/or modify it
11112 + * under the terms of the GNU General Public License as published by the
11113 + * Free Software Foundation; either version 2 of the License, or (at your
11114 + * option) any later version.
11115 + *
11116 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11117 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11118 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11119 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11120 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11121 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11122 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11123 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11124 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11125 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11126 + *
11127 + * You should have received a copy of the GNU General Public License along
11128 + * with this program; if not, write to the Free Software Foundation, Inc.,
11129 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11130 + */
11131 +
11132 +#include <linux/config.h>
11133 +#include <linux/errno.h>
11134 +#include <linux/init.h>
11135 +#include <linux/interrupt.h>
11136 +#include <linux/irq.h>
11137 +#include <linux/module.h>
11138 +#include <linux/smp.h>
11139 +#include <linux/types.h>
11140 +
11141 +#include <asm/cpu.h>
11142 +#include <asm/io.h>
11143 +#include <asm/irq.h>
11144 +#include <asm/irq_cpu.h>
11145 +
11146 +void plat_irq_dispatch(struct pt_regs *regs)
11147 +{
11148 + u32 cause;
11149 +
11150 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11151 +
11152 + clear_c0_status(cause);
11153 +
11154 + if (cause & CAUSEF_IP7)
11155 + do_IRQ(7, regs);
11156 + if (cause & CAUSEF_IP2)
11157 + do_IRQ(2, regs);
11158 + if (cause & CAUSEF_IP3)
11159 + do_IRQ(3, regs);
11160 + if (cause & CAUSEF_IP4)
11161 + do_IRQ(4, regs);
11162 + if (cause & CAUSEF_IP5)
11163 + do_IRQ(5, regs);
11164 + if (cause & CAUSEF_IP6)
11165 + do_IRQ(6, regs);
11166 +}
11167 +
11168 +void __init arch_init_irq(void)
11169 +{
11170 + mips_cpu_irq_init(0);
11171 +}
11172 diff -Nur linux-2.6.17/arch/mips/bcm947xx/Makefile linux-2.6.17-owrt/arch/mips/bcm947xx/Makefile
11173 --- linux-2.6.17/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
11174 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/Makefile 2006-06-18 15:33:03.000000000 +0200
11175 @@ -0,0 +1,6 @@
11176 +#
11177 +# Makefile for the BCM47xx specific kernel interface routines
11178 +# under Linux.
11179 +#
11180 +
11181 +obj-y := irq.o prom.o setup.o time.o pci.o
11182 diff -Nur linux-2.6.17/arch/mips/bcm947xx/pci.c linux-2.6.17-owrt/arch/mips/bcm947xx/pci.c
11183 --- linux-2.6.17/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11184 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/pci.c 2006-06-18 15:29:23.000000000 +0200
11185 @@ -0,0 +1,215 @@
11186 +#include <linux/kernel.h>
11187 +#include <linux/init.h>
11188 +#include <linux/pci.h>
11189 +#include <linux/types.h>
11190 +
11191 +#include <asm/cpu.h>
11192 +#include <asm/io.h>
11193 +
11194 +#include <typedefs.h>
11195 +#include <osl.h>
11196 +#include <sbutils.h>
11197 +#include <sbmips.h>
11198 +#include <sbconfig.h>
11199 +#include <sbpci.h>
11200 +#include <bcmdevs.h>
11201 +#include <pcicfg.h>
11202 +
11203 +extern sb_t *sbh;
11204 +extern spinlock_t sbh_lock;
11205 +
11206 +
11207 +static int
11208 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11209 + int reg, int size, u32 *val)
11210 +{
11211 + int ret;
11212 + unsigned long flags;
11213 +
11214 + spin_lock_irqsave(&sbh_lock, flags);
11215 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11216 + spin_unlock_irqrestore(&sbh_lock, flags);
11217 +
11218 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11219 +}
11220 +
11221 +static int
11222 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11223 + int reg, int size, u32 val)
11224 +{
11225 + int ret;
11226 + unsigned long flags;
11227 +
11228 + spin_lock_irqsave(&sbh_lock, flags);
11229 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11230 + spin_unlock_irqrestore(&sbh_lock, flags);
11231 +
11232 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11233 +}
11234 +
11235 +
11236 +static struct pci_ops sb_pci_ops = {
11237 + .read = sb_pci_read_config,
11238 + .write = sb_pci_write_config,
11239 +};
11240 +
11241 +static struct resource sb_pci_mem_resource = {
11242 + .name = "SB PCI Memory resources",
11243 + .start = SB_ENUM_BASE,
11244 + .end = SB_ENUM_LIM - 1,
11245 + .flags = IORESOURCE_MEM,
11246 +};
11247 +
11248 +static struct resource sb_pci_io_resource = {
11249 + .name = "SB PCI I/O resources",
11250 + .start = 0x000,
11251 + .end = 0x0FF,
11252 + .flags = IORESOURCE_IO,
11253 +};
11254 +
11255 +static struct pci_controller bcm47xx_sb_pci_controller = {
11256 + .pci_ops = &sb_pci_ops,
11257 + .mem_resource = &sb_pci_mem_resource,
11258 + .io_resource = &sb_pci_io_resource,
11259 +};
11260 +
11261 +static struct resource ext_pci_mem_resource = {
11262 + .name = "Ext PCI Memory resources",
11263 + .start = 0x40000000,
11264 + .end = 0x7fffffff,
11265 + .flags = IORESOURCE_MEM,
11266 +};
11267 +
11268 +static struct resource ext_pci_io_resource = {
11269 + .name = "Ext PCI I/O resources",
11270 + .start = 0x100,
11271 + .end = 0x1FF,
11272 + .flags = IORESOURCE_IO,
11273 +};
11274 +
11275 +static struct pci_controller bcm47xx_ext_pci_controller = {
11276 + .pci_ops = &sb_pci_ops,
11277 + .io_resource = &ext_pci_io_resource,
11278 + .mem_resource = &ext_pci_mem_resource,
11279 + .mem_offset = 0x24000000,
11280 +};
11281 +
11282 +void bcm47xx_pci_init(void)
11283 +{
11284 + unsigned long flags;
11285 +
11286 + spin_lock_irqsave(&sbh_lock, flags);
11287 + sbpci_init(sbh);
11288 + spin_unlock_irqrestore(&sbh_lock, flags);
11289 +
11290 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11291 +
11292 + register_pci_controller(&bcm47xx_sb_pci_controller);
11293 + register_pci_controller(&bcm47xx_ext_pci_controller);
11294 +}
11295 +
11296 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11297 +{
11298 + u8 irq;
11299 +
11300 + if (dev->bus->number == 1)
11301 + return 2;
11302 +
11303 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11304 + return irq + 2;
11305 +}
11306 +
11307 +u32 pci_iobase = 0x100;
11308 +u32 pci_membase = SB_PCI_DMA;
11309 +
11310 +static void bcm47xx_fixup_device(struct pci_dev *d)
11311 +{
11312 + struct resource *res;
11313 + int pos, size;
11314 + u32 *base;
11315 +
11316 + if (d->bus->number == 0)
11317 + return;
11318 +
11319 + printk("PCI: Fixing up device %s\n", pci_name(d));
11320 +
11321 + /* Fix up resource bases */
11322 + for (pos = 0; pos < 6; pos++) {
11323 + res = &d->resource[pos];
11324 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11325 + if (res->end) {
11326 + size = res->end - res->start + 1;
11327 + if (*base & (size - 1))
11328 + *base = (*base + size) & ~(size - 1);
11329 + res->start = *base;
11330 + res->end = res->start + size - 1;
11331 + *base += size;
11332 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11333 + }
11334 + /* Fix up PCI bridge BAR0 only */
11335 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11336 + break;
11337 + }
11338 + /* Fix up interrupt lines */
11339 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11340 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11341 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11342 +}
11343 +
11344 +
11345 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11346 +{
11347 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11348 + return;
11349 +
11350 + printk("PCI: fixing up bridge\n");
11351 +
11352 + /* Enable PCI bridge bus mastering and memory space */
11353 + pci_set_master(dev);
11354 + pcibios_enable_device(dev, ~0);
11355 +
11356 + /* Enable PCI bridge BAR1 prefetch and burst */
11357 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11358 +}
11359 +
11360 +/* Do platform specific device initialization at pci_enable_device() time */
11361 +int pcibios_plat_dev_init(struct pci_dev *dev)
11362 +{
11363 + uint coreidx;
11364 + unsigned long flags;
11365 +
11366 + bcm47xx_fixup_device(dev);
11367 +
11368 + /* These cores come out of reset enabled */
11369 + if ((dev->bus->number != 0) ||
11370 + (dev->device == SB_MIPS) ||
11371 + (dev->device == SB_MIPS33) ||
11372 + (dev->device == SB_EXTIF) ||
11373 + (dev->device == SB_CC))
11374 + return 0;
11375 +
11376 + /* Do a core reset */
11377 + spin_lock_irqsave(&sbh_lock, flags);
11378 + coreidx = sb_coreidx(sbh);
11379 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11380 + /*
11381 + * The USB core requires a special bit to be set during core
11382 + * reset to enable host (OHCI) mode. Resetting the SB core in
11383 + * pcibios_enable_device() is a hack for compatibility with
11384 + * vanilla usb-ohci so that it does not have to know about
11385 + * SB. A driver that wants to use the USB core in device mode
11386 + * should know about SB and should reset the bit back to 0
11387 + * after calling pcibios_enable_device().
11388 + */
11389 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11390 + sb_core_reset(sbh, 1 << 29);
11391 + } else {
11392 + sb_core_reset(sbh, 0);
11393 + }
11394 + sb_setcoreidx(sbh, coreidx);
11395 + spin_unlock_irqrestore(&sbh_lock, flags);
11396 +
11397 + return 0;
11398 +}
11399 +
11400 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11401 diff -Nur linux-2.6.17/arch/mips/bcm947xx/prom.c linux-2.6.17-owrt/arch/mips/bcm947xx/prom.c
11402 --- linux-2.6.17/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11403 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/prom.c 2006-06-18 15:29:23.000000000 +0200
11404 @@ -0,0 +1,59 @@
11405 +/*
11406 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11407 + *
11408 + * This program is free software; you can redistribute it and/or modify it
11409 + * under the terms of the GNU General Public License as published by the
11410 + * Free Software Foundation; either version 2 of the License, or (at your
11411 + * option) any later version.
11412 + *
11413 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11414 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11415 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11416 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11417 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11418 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11419 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11420 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11421 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11422 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11423 + *
11424 + * You should have received a copy of the GNU General Public License along
11425 + * with this program; if not, write to the Free Software Foundation, Inc.,
11426 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11427 + */
11428 +
11429 +#include <linux/init.h>
11430 +#include <linux/mm.h>
11431 +#include <linux/sched.h>
11432 +#include <linux/bootmem.h>
11433 +
11434 +#include <asm/addrspace.h>
11435 +#include <asm/bootinfo.h>
11436 +#include <asm/pmon.h>
11437 +
11438 +const char *get_system_type(void)
11439 +{
11440 + return "Broadcom BCM47xx";
11441 +}
11442 +
11443 +void __init prom_init(void)
11444 +{
11445 + unsigned long mem;
11446 +
11447 + mips_machgroup = MACH_GROUP_BRCM;
11448 + mips_machtype = MACH_BCM47XX;
11449 +
11450 + /* Figure out memory size by finding aliases */
11451 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11452 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11453 + *(unsigned long *)(prom_init))
11454 + break;
11455 + }
11456 +
11457 + add_memory_region(0, mem, BOOT_MEM_RAM);
11458 +}
11459 +
11460 +unsigned long __init prom_free_prom_memory(void)
11461 +{
11462 + return 0;
11463 +}
11464 diff -Nur linux-2.6.17/arch/mips/bcm947xx/setup.c linux-2.6.17-owrt/arch/mips/bcm947xx/setup.c
11465 --- linux-2.6.17/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11466 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/setup.c 2006-06-18 15:29:23.000000000 +0200
11467 @@ -0,0 +1,158 @@
11468 +/*
11469 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11470 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11471 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11472 + *
11473 + * This program is free software; you can redistribute it and/or modify it
11474 + * under the terms of the GNU General Public License as published by the
11475 + * Free Software Foundation; either version 2 of the License, or (at your
11476 + * option) any later version.
11477 + *
11478 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11479 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11480 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11481 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11482 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11483 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11484 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11485 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11486 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11487 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11488 + *
11489 + * You should have received a copy of the GNU General Public License along
11490 + * with this program; if not, write to the Free Software Foundation, Inc.,
11491 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11492 + */
11493 +
11494 +#include <linux/init.h>
11495 +#include <linux/types.h>
11496 +#include <linux/tty.h>
11497 +#include <linux/serial.h>
11498 +#include <linux/serial_core.h>
11499 +#include <linux/serial_reg.h>
11500 +#include <asm/bootinfo.h>
11501 +#include <asm/time.h>
11502 +#include <asm/reboot.h>
11503 +#include <linux/pm.h>
11504 +
11505 +#include <typedefs.h>
11506 +#include <osl.h>
11507 +#include <sbutils.h>
11508 +#include <sbmips.h>
11509 +#include <sbpci.h>
11510 +#include <sbconfig.h>
11511 +#include <bcmdevs.h>
11512 +#include <bcmutils.h>
11513 +#include <bcmnvram.h>
11514 +
11515 +extern void bcm47xx_pci_init(void);
11516 +extern void bcm47xx_time_init(void);
11517 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11518 +void *sbh;
11519 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11520 +int boardflags;
11521 +
11522 +static int ser_line = 0;
11523 +
11524 +typedef struct {
11525 + void *regs;
11526 + uint irq;
11527 + uint baud_base;
11528 + uint reg_shift;
11529 +} serial_port;
11530 +
11531 +static serial_port ports[4];
11532 +static int num_ports = 0;
11533 +
11534 +static void
11535 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11536 +{
11537 + ports[num_ports].regs = regs;
11538 + ports[num_ports].irq = irq;
11539 + ports[num_ports].baud_base = baud_base;
11540 + ports[num_ports].reg_shift = reg_shift;
11541 + num_ports++;
11542 +}
11543 +
11544 +static void
11545 +do_serial_add(serial_port *port)
11546 +{
11547 + void *regs;
11548 + uint irq;
11549 + uint baud_base;
11550 + uint reg_shift;
11551 + struct uart_port s;
11552 +
11553 + regs = port->regs;
11554 + irq = port->irq;
11555 + baud_base = port->baud_base;
11556 + reg_shift = port->reg_shift;
11557 +
11558 + memset(&s, 0, sizeof(s));
11559 +
11560 + s.line = ser_line++;
11561 + s.membase = regs;
11562 + s.irq = irq + 2;
11563 + s.uartclk = baud_base;
11564 + s.flags = ASYNC_BOOT_AUTOCONF;
11565 + s.iotype = SERIAL_IO_MEM;
11566 + s.regshift = reg_shift;
11567 +
11568 + if (early_serial_setup(&s) != 0) {
11569 + printk(KERN_ERR "Serial setup failed!\n");
11570 + }
11571 +}
11572 +
11573 +static void bcm47xx_machine_restart(char *command)
11574 +{
11575 + printk("Please stand by while rebooting the system...\n");
11576 +
11577 + /* Set the watchdog timer to reset immediately */
11578 + local_irq_disable();
11579 + sb_watchdog(sbh, 1);
11580 + while (1);
11581 +}
11582 +
11583 +static void bcm47xx_machine_halt(void)
11584 +{
11585 + /* Disable interrupts and watchdog and spin forever */
11586 + local_irq_disable();
11587 + sb_watchdog(sbh, 0);
11588 + while (1);
11589 +}
11590 +
11591 +void __init plat_setup(void)
11592 +{
11593 + char *s;
11594 + int i;
11595 +
11596 + sbh = (void *) sb_kattach();
11597 + sb_mips_init(sbh);
11598 +
11599 + bcm47xx_pci_init();
11600 +
11601 + sb_serial_init(sbh, serial_add);
11602 + boardflags = getintvar(NULL, "boardflags");
11603 +
11604 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11605 + s = early_nvram_get("kernel_args");
11606 + if (!s) s = "";
11607 + if (!strncmp(s, "console=ttyS1", 13)) {
11608 + for (i = num_ports; i; i--)
11609 + do_serial_add(&ports[i - 1]);
11610 + } else {
11611 + for (i = 0; i < num_ports; i++)
11612 + do_serial_add(&ports[i]);
11613 + }
11614 +
11615 + _machine_restart = bcm47xx_machine_restart;
11616 + _machine_halt = bcm47xx_machine_halt;
11617 + pm_power_off = bcm47xx_machine_halt;
11618 +
11619 + board_time_init = bcm47xx_time_init;
11620 + board_timer_setup = bcm47xx_timer_setup;
11621 +}
11622 +
11623 +EXPORT_SYMBOL(sbh);
11624 +EXPORT_SYMBOL(sbh_lock);
11625 +EXPORT_SYMBOL(boardflags);
11626 diff -Nur linux-2.6.17/arch/mips/bcm947xx/time.c linux-2.6.17-owrt/arch/mips/bcm947xx/time.c
11627 --- linux-2.6.17/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11628 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/time.c 2006-06-18 15:29:23.000000000 +0200
11629 @@ -0,0 +1,59 @@
11630 +/*
11631 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11632 + *
11633 + * This program is free software; you can redistribute it and/or modify it
11634 + * under the terms of the GNU General Public License as published by the
11635 + * Free Software Foundation; either version 2 of the License, or (at your
11636 + * option) any later version.
11637 + *
11638 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11639 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11640 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11641 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11642 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11643 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11644 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11645 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11646 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11647 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11648 + *
11649 + * You should have received a copy of the GNU General Public License along
11650 + * with this program; if not, write to the Free Software Foundation, Inc.,
11651 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11652 + */
11653 +
11654 +#include <linux/config.h>
11655 +#include <linux/init.h>
11656 +#include <linux/kernel.h>
11657 +#include <linux/sched.h>
11658 +#include <linux/serial_reg.h>
11659 +#include <linux/interrupt.h>
11660 +#include <asm/addrspace.h>
11661 +#include <asm/io.h>
11662 +#include <asm/time.h>
11663 +
11664 +void __init
11665 +bcm47xx_time_init(void)
11666 +{
11667 + unsigned int hz;
11668 +
11669 + /*
11670 + * Use deterministic values for initial counter interrupt
11671 + * so that calibrate delay avoids encountering a counter wrap.
11672 + */
11673 + write_c0_count(0);
11674 + write_c0_compare(0xffff);
11675 +
11676 + hz = 200 * 1000 * 1000;
11677 +
11678 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11679 + mips_hpt_frequency = hz / 2;
11680 +
11681 +}
11682 +
11683 +void __init
11684 +bcm47xx_timer_setup(struct irqaction *irq)
11685 +{
11686 + /* Enable the timer interrupt */
11687 + setup_irq(7, irq);
11688 +}
11689 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
11690 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
11691 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 15:29:23.000000000 +0200
11692 @@ -245,6 +245,17 @@
11693 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
11694 Olivetti M700-10 workstations.
11695
11696 +config BCM947XX
11697 + bool "Support for BCM947xx based boards"
11698 + select DMA_NONCOHERENT
11699 + select HW_HAS_PCI
11700 + select IRQ_CPU
11701 + select SYS_HAS_CPU_MIPS32_R1
11702 + select SYS_SUPPORTS_32BIT_KERNEL
11703 + select SYS_SUPPORTS_LITTLE_ENDIAN
11704 + help
11705 + Support for BCM947xx based boards
11706 +
11707 config LASAT
11708 bool "LASAT Networks platforms"
11709 select DMA_NONCOHERENT
11710 diff -Nur linux-2.6.17/arch/mips/kernel/cpu-probe.c linux-2.6.17-owrt/arch/mips/kernel/cpu-probe.c
11711 --- linux-2.6.17/arch/mips/kernel/cpu-probe.c 2006-06-18 03:49:35.000000000 +0200
11712 +++ linux-2.6.17-owrt/arch/mips/kernel/cpu-probe.c 2006-06-18 15:29:23.000000000 +0200
11713 @@ -691,6 +691,28 @@
11714 }
11715
11716
11717 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11718 +{
11719 + decode_config1(c);
11720 + switch (c->processor_id & 0xff00) {
11721 + case PRID_IMP_BCM3302:
11722 + c->cputype = CPU_BCM3302;
11723 + c->isa_level = MIPS_CPU_ISA_M32R1;
11724 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11725 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11726 + break;
11727 + case PRID_IMP_BCM4710:
11728 + c->cputype = CPU_BCM4710;
11729 + c->isa_level = MIPS_CPU_ISA_M32R1;
11730 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11731 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11732 + break;
11733 + default:
11734 + c->cputype = CPU_UNKNOWN;
11735 + break;
11736 + }
11737 +}
11738 +
11739 __init void cpu_probe(void)
11740 {
11741 struct cpuinfo_mips *c = &current_cpu_data;
11742 @@ -713,6 +735,9 @@
11743 case PRID_COMP_SIBYTE:
11744 cpu_probe_sibyte(c);
11745 break;
11746 + case PRID_COMP_BROADCOM:
11747 + cpu_probe_broadcom(c);
11748 + break;
11749 case PRID_COMP_SANDCRAFT:
11750 cpu_probe_sandcraft(c);
11751 break;
11752 diff -Nur linux-2.6.17/arch/mips/kernel/head.S linux-2.6.17-owrt/arch/mips/kernel/head.S
11753 --- linux-2.6.17/arch/mips/kernel/head.S 2006-06-18 12:54:51.000000000 +0200
11754 +++ linux-2.6.17-owrt/arch/mips/kernel/head.S 2006-06-18 15:29:23.000000000 +0200
11755 @@ -133,6 +133,11 @@
11756 j kernel_entry
11757 nop
11758
11759 +#ifdef CONFIG_BCM4710
11760 +#undef eret
11761 +#define eret nop; nop; eret
11762 +#endif
11763 +
11764 /*
11765 * Reserved space for exception handlers.
11766 * Necessary for machines which link their kernels at KSEG0.
11767 diff -Nur linux-2.6.17/arch/mips/kernel/proc.c linux-2.6.17-owrt/arch/mips/kernel/proc.c
11768 --- linux-2.6.17/arch/mips/kernel/proc.c 2006-06-18 03:49:35.000000000 +0200
11769 +++ linux-2.6.17-owrt/arch/mips/kernel/proc.c 2006-06-18 15:29:23.000000000 +0200
11770 @@ -84,6 +84,8 @@
11771 [CPU_VR4181] = "NEC VR4181",
11772 [CPU_VR4181A] = "NEC VR4181A",
11773 [CPU_SR71000] = "Sandcraft SR71000",
11774 + [CPU_BCM3302] = "Broadcom BCM3302",
11775 + [CPU_BCM4710] = "Broadcom BCM4710",
11776 [CPU_PR4450] = "Philips PR4450",
11777 };
11778
11779 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
11780 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
11781 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 15:29:23.000000000 +0200
11782 @@ -565,6 +565,13 @@
11783 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
11784
11785 #
11786 +# Broadcom BCM47XX boards
11787 +#
11788 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
11789 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
11790 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
11791 +
11792 +#
11793 # SNI RM200 PCI
11794 #
11795 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
11796 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
11797 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
11798 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 15:29:23.000000000 +0200
11799 @@ -882,6 +882,8 @@
11800 case CPU_4KSC:
11801 case CPU_20KC:
11802 case CPU_25KF:
11803 + case CPU_BCM3302:
11804 + case CPU_BCM4710:
11805 tlbw(p);
11806 break;
11807
11808 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
11809 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
11810 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 15:29:23.000000000 +0200
11811 @@ -218,6 +218,12 @@
11812 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11813 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11814
11815 +/*
11816 + * Valid machtype for group Broadcom
11817 + */
11818 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11819 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11820 +
11821 #define CL_SIZE COMMAND_LINE_SIZE
11822
11823 const char *get_system_type(void);
11824 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
11825 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
11826 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 15:30:53.000000000 +0200
11827 @@ -104,6 +104,13 @@
11828 #define PRID_IMP_SR71000 0x0400
11829
11830 /*
11831 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11832 + */
11833 +
11834 +#define PRID_IMP_BCM4710 0x4000
11835 +#define PRID_IMP_BCM3302 0x9000
11836 +
11837 +/*
11838 * Definitions for 7:0 on legacy processors
11839 */
11840
11841 @@ -200,7 +207,9 @@
11842 #define CPU_SB1A 62
11843 #define CPU_74K 63
11844 #define CPU_R14000 64
11845 -#define CPU_LAST 64
11846 +#define CPU_BCM3302 65
11847 +#define CPU_BCM4710 66
11848 +#define CPU_LAST 66
11849
11850 /*
11851 * ISA Level encodings
11852 diff -Nur linux-2.6.17/include/linux/pci_ids.h linux-2.6.17-owrt/include/linux/pci_ids.h
11853 --- linux-2.6.17/include/linux/pci_ids.h 2006-06-18 03:49:35.000000000 +0200
11854 +++ linux-2.6.17-owrt/include/linux/pci_ids.h 2006-06-18 15:29:23.000000000 +0200
11855 @@ -1906,6 +1906,7 @@
11856 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11857 #define PCI_DEVICE_ID_BCM4401 0x4401
11858 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11859 +#define PCI_DEVICE_ID_BCM4713 0x4713
11860
11861 #define PCI_VENDOR_ID_TOPIC 0x151f
11862 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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