package/ltq-dsl/src/ifxmips_atm_fw_regs_ar9.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_fw_regs_ar9.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM (ADSL)
   6 **
   7 ** DATE         : 1 AUG 2005
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM Driver (Firmware Registers)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 **  4 AUG 2005  Xu Liang        Initiate Version
  22 ** 23 OCT 2006  Xu Liang        Add GPL header.
  23 **  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)
  24 *******************************************************************************/
  25
  26
  27
  28 #ifndef IFXMIPS_ATM_FW_REGS_AR9_H
  29 #define IFXMIPS_ATM_FW_REGS_AR9_H
  30
  31
  32
  33 /*
  34  *  Host-PPE Communication Data Address Mapping
  35  */
  36 #define FW_VER_ID                       ((volatile struct fw_ver_id *)      SB_BUFFER(0x2001))
  37 #define CFG_WRX_HTUTS                   SB_BUFFER(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */
  38 #define CFG_WRX_QNUM                    SB_BUFFER(0x2401)   /*  WAN RX Queue Number */
  39 #define CFG_WRX_DCHNUM                  SB_BUFFER(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */
  40 #define CFG_WTX_DCHNUM                  SB_BUFFER(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */
  41 #define CFG_WRDES_DELAY                 SB_BUFFER(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */
  42 #define WRX_DMACH_ON                    SB_BUFFER(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */
  43 #define WTX_DMACH_ON                    SB_BUFFER(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */
  44 #define WRX_HUNT_BITTH                  SB_BUFFER(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */
  45 #define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)         SB_BUFFER(0x2500 + (i) * 20))
  46 #define WRX_QUEUE_CONTEXT(i)            ((struct wrx_queue_context*)        SB_BUFFER(0x2504 + (i) * 20))
  47 #define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)   SB_BUFFER(0x2640 + (i) * 7))
  48 #define WRX_DESC_CONTEXT(i)             ((struct wrx_desc_context*)         SB_BUFFER(0x2643 + (i) * 7))
  49 #define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)          SB_BUFFER(0x2440 + (i)))
  50 #define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)         SB_BUFFER(0x3800 + (i) * 27))
  51 #define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)   SB_BUFFER(0x3801 + (i) * 27))
  52 #define WAN_MIB_TABLE                   ((struct wan_mib_table*)            SB_BUFFER(0x2410))
  53 #define HTU_ENTRY(i)                    ((struct htu_entry*)                SB_BUFFER(0x2010 + (i)))
  54 #define HTU_MASK(i)                     ((struct htu_mask*)                 SB_BUFFER(0x2030 + (i)))
  55 #define HTU_RESULT(i)                   ((struct htu_result*)               SB_BUFFER(0x2050 + (i)))
  56
  57 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
  58
  59   #define RETX_MODE_CFG                     ((volatile struct Retx_mode_cfg *)      SB_BUFFER(0x2408))
  60   #define RETX_TSYNC_CFG                    ((volatile struct Retx_Tsync_cfg *)     SB_BUFFER(0x2409))
  61   #define RETX_TD_CFG                       ((volatile struct Retx_Td_cfg *)        SB_BUFFER(0x240A))
  62   #define RETX_MIB_TIMER_CFG                ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B))
  63   #define RETX_PLAYOUT_BUFFER_BASE          SB_BUFFER(0x240D)
  64   #define RETX_SERVICE_HEADER_CFG           SB_BUFFER(0x240E)
  65   #define RETX_MASK_HEADER_CFG              SB_BUFFER(0x240F)
  66
  67   #define RETX_ADSL_PPE_INTF                ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78))
  68   #define BAD_REC_RETX_ADSL_PPE_INTF        ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC))
  69   #define FIRST_BAD_REC_RETX_ADSL_PPE_INTF  ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE))
  70
  71   #define PB_BUFFER_USAGE                   SB_BUFFER(0x2100)
  72   #define DTU_STAT_INFO                     ((volatile struct DTU_stat_info *)      SB_BUFFER(0x2180))
  73   #define DTU_VLD_STAT                      SB_BUFFER(0x2380)
  74
  75
  76   //=====================================================================
  77   // retx firmware mib, for debug purpose
  78   //      address : 0x2388 - 0x238F
  79   //      size    : 8
  80   //=====================================================================
  81   #define URETX_RX_TOTAL_DTU                    SB_BUFFER(0x2388)
  82   #define URETX_RX_BAD_DTU                      SB_BUFFER(0x2389)
  83   #define URETX_RX_GOOD_DTU                     SB_BUFFER(0x238A)
  84   #define URETX_RX_CORRECTED_DTU                SB_BUFFER(0x238B)
  85   #define URETX_RX_OUTOFDATE_DTU                SB_BUFFER(0x238C)
  86   #define URETX_RX_DUPLICATE_DTU                SB_BUFFER(0x238D)
  87   #define URETX_RX_TIMEOUT_DTU                  SB_BUFFER(0x238E)
  88
  89   #define URETX_ALPHA_SWITCH_TO_HUNT_TIMES      SB_BUFFER(0x238F)
  90
  91   // cell counter for debug purpose
  92   #define WRX_BC0_CELL_NUM                      SB_BUFFER(0x23E0)
  93   #define WRX_BC0_DROP_CELL_NUM                 SB_BUFFER(0x23E1)
  94   #define WRX_BC0_NONRETX_CELL_NUM              SB_BUFFER(0x23E2)
  95   #define WRX_BC0_RETX_CELL_NUM                 SB_BUFFER(0x23E3)
  96   #define WRX_BC0_OUTOFDATE_CELL_NUM            SB_BUFFER(0x23E4)
  97   #define WRX_BC0_DIRECTUP_NUM                  SB_BUFFER(0x23E5)
  98   #define WRX_BC0_PBW_TOTAL_NUM                 SB_BUFFER(0x23E6)
  99   #define WRX_BC0_PBW_SUCC_NUM                  SB_BUFFER(0x23E7)
 100   #define WRX_BC0_PBW_FAIL_NUM                  SB_BUFFER(0x23E8)
 101   #define WRX_BC1_CELL_NUM                      SB_BUFFER(0x23E9)
 102
 103   // debug info (interface)
 104
 105   #define DBG_DTU_INTF_WRPTR                    SB_BUFFER(0x2390)
 106   #define DBG_INTF_FCW_DUP_CNT                  SB_BUFFER(0x2391)
 107   #define DBG_INTF_SID_CHANGE_IN_DTU_CNT        SB_BUFFER(0x2392)
 108   #define DBG_INTF_LCW_DUP_CNT                  SB_BUFFER(0x2393)
 109
 110   #define DBG_RFBI_DONE_INT_CNT                 SB_BUFFER(0x2394)
 111   #define DBG_DREG_BEG_END                      SB_BUFFER(0x2395)
 112   #define DBG_RFBI_BC0_INVALID_CNT              SB_BUFFER(0x2396)
 113   #define DBG_RFBI_LAST_T                       SB_BUFFER(0x2397)
 114
 115   #define DBG_RFBI_INTV0                        SB_BUFFER(0x23EE)
 116   #define DBG_RFBI_INTV1                        SB_BUFFER(0x23EF)
 117
 118   #define DBG_INTF_INFO(i)                      ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i))
 119
 120   // Internal status
 121   #define URetx_curr_time                       SB_BUFFER(0x2398)
 122   #define URetx_sec_counter                     SB_BUFFER(0x2399)
 123   #define RxCURR_EFB                            SB_BUFFER(0x239A)
 124   #define RxDTURetransmittedCNT                 SB_BUFFER(0x239B)
 125
 126   //=====================================================================
 127   // standardized MIB counter
 128   //      address : 0x239C - 0x239F
 129   //      size    : 4
 130   //=====================================================================
 131   #define RxLastEFBCNT                          SB_BUFFER(0x239C)
 132   #define RxDTUCorrectedCNT                     SB_BUFFER(0x239D)
 133   #define RxDTUCorruptedCNT                     SB_BUFFER(0x239E)
 134   #define RxRetxDTUUncorrectedCNT               SB_BUFFER(0x239F)
 135
 136
 137   //=====================================================================
 138   // General URetx Context
 139   //      address : 0x23A0 - 0x23AF
 140   //      size    : 16
 141   //=====================================================================
 142   #define NEXT_DTU_SID_OUT                      SB_BUFFER(0x23A0)
 143   #define LAST_DTU_SID_IN                       SB_BUFFER(0x23A1)
 144   #define NEXT_CELL_SID_OUT                     SB_BUFFER(0x23A2)
 145   #define ISR_CELL_ID                           SB_BUFFER(0x23A3)
 146   #define PB_CELL_SEARCH_IDX                    SB_BUFFER(0x23A4)
 147   #define PB_READ_PEND_FLAG                     SB_BUFFER(0x23A5)
 148   #define RFBI_FIRST_CW                         SB_BUFFER(0x23A6)
 149   #define RFBI_BAD_CW                           SB_BUFFER(0x23A7)
 150   #define RFBI_INVALID_CW                       SB_BUFFER(0x23A8)
 151   #define RFBI_RETX_CW                          SB_BUFFER(0x23A9)
 152   #define RFBI_CHK_DTU_STATUS                   SB_BUFFER(0x23AA)
 153
 154   //=====================================================================
 155   // per PVC counter for RX error_pdu and correct_pdu
 156   //      address : 0x23B0 - 0x23CF
 157   //      size    : 32
 158   //=====================================================================
 159   #define WRX_PER_PVC_CORRECT_PDU_BASE          SB_BUFFER(0x23B0)
 160   #define WRX_PER_PVC_ERROR_PDU_BASE            SB_BUFFER(0x23C0)
 161
 162   #define __WRXCTXT_L2_RdPtr(i)                 SB_BUFFER(0x2422 + (i))
 163   #define __WRXCTXT_L2Pages(i)                  SB_BUFFER(0x2424 + (i))
 164
 165   #define __WTXCTXT_TC_WRPTR(i)                 SB_BUFFER(0x2450 + (i))
 166   #define __WRXCTXT_PortState(i)                SB_BUFFER(0x242A + (i))
 167
 168 #endif
 169
 170
 171
 172 #endif  //  IFXMIPS_ATM_FW_REGS_AR9_H