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[adm5120] add support for GPIO IRQs
[openwrt.git] / target / linux / ar7 / files / drivers / net / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 OpenWrt.org
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <asm/gpio.h>
40 #include <asm/atomic.h>
41
42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44 MODULE_LICENSE("GPL");
45
46 static int debug_level = 8;
47 static int dumb_switch;
48
49 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
50 module_param(debug_level, int, 0444);
51 module_param(dumb_switch, int, 0444);
52
53 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
54 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
55
56 #define CPMAC_VERSION "0.5.0"
57 /* stolen from net/ieee80211.h */
58 #ifndef MAC_FMT
59 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
60 #define MAC_ARG(x) ((u8*)(x))[0], ((u8*)(x))[1], ((u8*)(x))[2], \
61 ((u8*)(x))[3], ((u8*)(x))[4], ((u8*)(x))[5]
62 #endif
63 /* frame size + 802.1q tag */
64 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
65 #define CPMAC_QUEUES 8
66
67 /* Ethernet registers */
68 #define CPMAC_TX_CONTROL 0x0004
69 #define CPMAC_TX_TEARDOWN 0x0008
70 #define CPMAC_RX_CONTROL 0x0014
71 #define CPMAC_RX_TEARDOWN 0x0018
72 #define CPMAC_MBP 0x0100
73 # define MBP_RXPASSCRC 0x40000000
74 # define MBP_RXQOS 0x20000000
75 # define MBP_RXNOCHAIN 0x10000000
76 # define MBP_RXCMF 0x01000000
77 # define MBP_RXSHORT 0x00800000
78 # define MBP_RXCEF 0x00400000
79 # define MBP_RXPROMISC 0x00200000
80 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
81 # define MBP_RXBCAST 0x00002000
82 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
83 # define MBP_RXMCAST 0x00000020
84 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
85 #define CPMAC_UNICAST_ENABLE 0x0104
86 #define CPMAC_UNICAST_CLEAR 0x0108
87 #define CPMAC_MAX_LENGTH 0x010c
88 #define CPMAC_BUFFER_OFFSET 0x0110
89 #define CPMAC_MAC_CONTROL 0x0160
90 # define MAC_TXPTYPE 0x00000200
91 # define MAC_TXPACE 0x00000040
92 # define MAC_MII 0x00000020
93 # define MAC_TXFLOW 0x00000010
94 # define MAC_RXFLOW 0x00000008
95 # define MAC_MTEST 0x00000004
96 # define MAC_LOOPBACK 0x00000002
97 # define MAC_FDX 0x00000001
98 #define CPMAC_MAC_STATUS 0x0164
99 # define MAC_STATUS_QOS 0x00000004
100 # define MAC_STATUS_RXFLOW 0x00000002
101 # define MAC_STATUS_TXFLOW 0x00000001
102 #define CPMAC_TX_INT_ENABLE 0x0178
103 #define CPMAC_TX_INT_CLEAR 0x017c
104 #define CPMAC_MAC_INT_VECTOR 0x0180
105 # define MAC_INT_STATUS 0x00080000
106 # define MAC_INT_HOST 0x00040000
107 # define MAC_INT_RX 0x00020000
108 # define MAC_INT_TX 0x00010000
109 #define CPMAC_MAC_EOI_VECTOR 0x0184
110 #define CPMAC_RX_INT_ENABLE 0x0198
111 #define CPMAC_RX_INT_CLEAR 0x019c
112 #define CPMAC_MAC_INT_ENABLE 0x01a8
113 #define CPMAC_MAC_INT_CLEAR 0x01ac
114 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
115 #define CPMAC_MAC_ADDR_MID 0x01d0
116 #define CPMAC_MAC_ADDR_HI 0x01d4
117 #define CPMAC_MAC_HASH_LO 0x01d8
118 #define CPMAC_MAC_HASH_HI 0x01dc
119 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
120 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
121 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
122 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
123 #define CPMAC_REG_END 0x0680
124 /*
125 * Rx/Tx statistics
126 * TODO: use some of them to fill stats in cpmac_stats()
127 */
128 #define CPMAC_STATS_RX_GOOD 0x0200
129 #define CPMAC_STATS_RX_BCAST 0x0204
130 #define CPMAC_STATS_RX_MCAST 0x0208
131 #define CPMAC_STATS_RX_PAUSE 0x020c
132 #define CPMAC_STATS_RX_CRC 0x0210
133 #define CPMAC_STATS_RX_ALIGN 0x0214
134 #define CPMAC_STATS_RX_OVER 0x0218
135 #define CPMAC_STATS_RX_JABBER 0x021c
136 #define CPMAC_STATS_RX_UNDER 0x0220
137 #define CPMAC_STATS_RX_FRAG 0x0224
138 #define CPMAC_STATS_RX_FILTER 0x0228
139 #define CPMAC_STATS_RX_QOSFILTER 0x022c
140 #define CPMAC_STATS_RX_OCTETS 0x0230
141
142 #define CPMAC_STATS_TX_GOOD 0x0234
143 #define CPMAC_STATS_TX_BCAST 0x0238
144 #define CPMAC_STATS_TX_MCAST 0x023c
145 #define CPMAC_STATS_TX_PAUSE 0x0240
146 #define CPMAC_STATS_TX_DEFER 0x0244
147 #define CPMAC_STATS_TX_COLLISION 0x0248
148 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
149 #define CPMAC_STATS_TX_MULTICOLL 0x0250
150 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
151 #define CPMAC_STATS_TX_LATECOLL 0x0258
152 #define CPMAC_STATS_TX_UNDERRUN 0x025c
153 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
154 #define CPMAC_STATS_TX_OCTETS 0x0264
155
156 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
157 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
158 (reg)))
159
160 /* MDIO bus */
161 #define CPMAC_MDIO_VERSION 0x0000
162 #define CPMAC_MDIO_CONTROL 0x0004
163 # define MDIOC_IDLE 0x80000000
164 # define MDIOC_ENABLE 0x40000000
165 # define MDIOC_PREAMBLE 0x00100000
166 # define MDIOC_FAULT 0x00080000
167 # define MDIOC_FAULTDETECT 0x00040000
168 # define MDIOC_INTTEST 0x00020000
169 # define MDIOC_CLKDIV(div) ((div) & 0xff)
170 #define CPMAC_MDIO_ALIVE 0x0008
171 #define CPMAC_MDIO_LINK 0x000c
172 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
173 # define MDIO_BUSY 0x80000000
174 # define MDIO_WRITE 0x40000000
175 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
176 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
177 # define MDIO_DATA(data) ((data) & 0xffff)
178 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
179 # define PHYSEL_LINKSEL 0x00000040
180 # define PHYSEL_LINKINT 0x00000020
181
182 struct cpmac_desc {
183 u32 hw_next;
184 u32 hw_data;
185 u16 buflen;
186 u16 bufflags;
187 u16 datalen;
188 u16 dataflags;
189 #define CPMAC_SOP 0x8000
190 #define CPMAC_EOP 0x4000
191 #define CPMAC_OWN 0x2000
192 #define CPMAC_EOQ 0x1000
193 struct sk_buff *skb;
194 struct cpmac_desc *next;
195 struct cpmac_desc *prev;
196 dma_addr_t mapping;
197 dma_addr_t data_mapping;
198 };
199
200 struct cpmac_priv {
201 spinlock_t lock;
202 spinlock_t rx_lock;
203 struct cpmac_desc *rx_head;
204 int ring_size;
205 struct cpmac_desc *desc_ring;
206 dma_addr_t dma_ring;
207 void __iomem *regs;
208 struct mii_bus *mii_bus;
209 struct phy_device *phy;
210 char phy_name[BUS_ID_SIZE];
211 int oldlink, oldspeed, oldduplex;
212 u32 msg_enable;
213 struct net_device *dev;
214 struct work_struct reset_work;
215 struct platform_device *pdev;
216 atomic_t reset_pending;
217 };
218
219 static irqreturn_t cpmac_irq(int, void *);
220 static void cpmac_hw_start(struct net_device *dev);
221 static void cpmac_hw_stop(struct net_device *dev);
222 static int cpmac_stop(struct net_device *dev);
223 static int cpmac_open(struct net_device *dev);
224
225 static void cpmac_dump_regs(struct net_device *dev)
226 {
227 int i;
228 struct cpmac_priv *priv = netdev_priv(dev);
229 for (i = 0; i < CPMAC_REG_END; i += 4) {
230 if (i % 16 == 0) {
231 if (i)
232 printk("\n");
233 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
234 priv->regs + i);
235 }
236 printk(" %08x", cpmac_read(priv->regs, i));
237 }
238 printk("\n");
239 }
240
241 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
242 {
243 int i;
244 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
245 for (i = 0; i < sizeof(*desc) / 4; i++)
246 printk(" %08x", ((u32 *)desc)[i]);
247 printk("\n");
248 }
249
250 static void cpmac_dump_all_desc(struct net_device *dev)
251 {
252 struct cpmac_priv *priv = netdev_priv(dev);
253 struct cpmac_desc *dump = priv->rx_head;
254 do {
255 cpmac_dump_desc(dev, dump);
256 dump = dump->next;
257 } while (dump != priv->rx_head);
258 }
259
260 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
261 {
262 int i;
263 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
264 for (i = 0; i < skb->len; i++) {
265 if (i % 16 == 0) {
266 if (i)
267 printk("\n");
268 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
269 skb->data + i);
270 }
271 printk(" %02x", ((u8 *)skb->data)[i]);
272 }
273 printk("\n");
274 }
275
276 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
277 {
278 u32 val;
279
280 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
281 cpu_relax();
282 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
283 MDIO_PHY(phy_id));
284 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
285 cpu_relax();
286 return MDIO_DATA(val);
287 }
288
289 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
290 int reg, u16 val)
291 {
292 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
293 cpu_relax();
294 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
295 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
296 return 0;
297 }
298
299 static int cpmac_mdio_reset(struct mii_bus *bus)
300 {
301 ar7_device_reset(AR7_RESET_BIT_MDIO);
302 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
303 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
304 return 0;
305 }
306
307 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
308
309 static struct mii_bus cpmac_mii = {
310 .name = "cpmac-mii",
311 .read = cpmac_mdio_read,
312 .write = cpmac_mdio_write,
313 .reset = cpmac_mdio_reset,
314 .irq = mii_irqs,
315 };
316
317 static int cpmac_config(struct net_device *dev, struct ifmap *map)
318 {
319 if (dev->flags & IFF_UP)
320 return -EBUSY;
321
322 /* Don't allow changing the I/O address */
323 if (map->base_addr != dev->base_addr)
324 return -EOPNOTSUPP;
325
326 /* ignore other fields */
327 return 0;
328 }
329
330 static void cpmac_set_multicast_list(struct net_device *dev)
331 {
332 struct dev_mc_list *iter;
333 int i;
334 u8 tmp;
335 u32 mbp, bit, hash[2] = { 0, };
336 struct cpmac_priv *priv = netdev_priv(dev);
337
338 mbp = cpmac_read(priv->regs, CPMAC_MBP);
339 if (dev->flags & IFF_PROMISC) {
340 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
341 MBP_RXPROMISC);
342 } else {
343 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
344 if (dev->flags & IFF_ALLMULTI) {
345 /* enable all multicast mode */
346 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
347 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
348 } else {
349 /*
350 * cpmac uses some strange mac address hashing
351 * (not crc32)
352 */
353 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
354 i++, iter = iter->next) {
355 bit = 0;
356 tmp = iter->dmi_addr[0];
357 bit ^= (tmp >> 2) ^ (tmp << 4);
358 tmp = iter->dmi_addr[1];
359 bit ^= (tmp >> 4) ^ (tmp << 2);
360 tmp = iter->dmi_addr[2];
361 bit ^= (tmp >> 6) ^ tmp;
362 tmp = iter->dmi_addr[3];
363 bit ^= (tmp >> 2) ^ (tmp << 4);
364 tmp = iter->dmi_addr[4];
365 bit ^= (tmp >> 4) ^ (tmp << 2);
366 tmp = iter->dmi_addr[5];
367 bit ^= (tmp >> 6) ^ tmp;
368 bit &= 0x3f;
369 hash[bit / 32] |= 1 << (bit % 32);
370 }
371
372 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
373 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
374 }
375 }
376 }
377
378 static struct sk_buff *cpmac_rx_one(struct net_device *dev,
379 struct cpmac_priv *priv,
380 struct cpmac_desc *desc)
381 {
382 struct sk_buff *skb, *result = NULL;
383
384 if (unlikely(netif_msg_hw(priv)))
385 cpmac_dump_desc(dev, desc);
386 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
387 if (unlikely(!desc->datalen)) {
388 if (netif_msg_rx_err(priv) && net_ratelimit())
389 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
390 dev->name);
391 return NULL;
392 }
393
394 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
395 if (likely(skb)) {
396 skb_reserve(skb, 2);
397 skb_put(desc->skb, desc->datalen);
398 desc->skb->protocol = eth_type_trans(desc->skb, dev);
399 desc->skb->ip_summed = CHECKSUM_NONE;
400 dev->stats.rx_packets++;
401 dev->stats.rx_bytes += desc->datalen;
402 result = desc->skb;
403 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
404 DMA_FROM_DEVICE);
405 desc->skb = skb;
406 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
407 CPMAC_SKB_SIZE,
408 DMA_FROM_DEVICE);
409 desc->hw_data = (u32)desc->data_mapping;
410 if (unlikely(netif_msg_pktdata(priv))) {
411 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
412 cpmac_dump_skb(dev, result);
413 }
414 } else {
415 if (netif_msg_rx_err(priv) && net_ratelimit())
416 printk(KERN_WARNING
417 "%s: low on skbs, dropping packet\n", dev->name);
418 dev->stats.rx_dropped++;
419 }
420
421 desc->buflen = CPMAC_SKB_SIZE;
422 desc->dataflags = CPMAC_OWN;
423
424 return result;
425 }
426
427 static int cpmac_poll(struct net_device *dev, int *budget)
428 {
429 struct sk_buff *skb;
430 struct cpmac_desc *desc, *restart;
431 int received = 0, processed = 0, quota = min(dev->quota, *budget);
432 struct cpmac_priv *priv = netdev_priv(dev);
433
434 spin_lock(&priv->rx_lock);
435 if (unlikely(!priv->rx_head)) {
436 if (netif_msg_rx_err(priv) && net_ratelimit())
437 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
438 dev->name);
439 spin_unlock(&priv->rx_lock);
440 netif_rx_complete(dev);
441 return 0;
442 }
443
444 desc = priv->rx_head;
445 restart = NULL;
446 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
447 processed++;
448
449 if ((desc->dataflags & CPMAC_EOQ) != 0) {
450 /* The last update to eoq->hw_next didn't happen soon enough, and the
451 * receiver stopped here. Remember this descriptor so we can restart
452 * the receiver after freeing some space.
453 */
454 if (unlikely(restart)) {
455 if (netif_msg_rx_err(priv))
456 printk(KERN_ERR "%s: poll found a duplicate EOQ: %p and %p\n",
457 dev->name, restart, desc);
458 goto fatal_error;
459 }
460
461 restart = desc->next;
462 }
463
464 skb = cpmac_rx_one(dev, priv, desc);
465 if (likely(skb)) {
466 netif_receive_skb(skb);
467 received++;
468 }
469 desc = desc->next;
470 }
471
472 if (desc != priv->rx_head) {
473 /* We freed some buffers, but not the whole ring, add what we did free to the rx list */
474 desc->prev->hw_next = (u32)0;
475 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
476 }
477
478 /* Optimization: If we did not actually process an EOQ (perhaps because of
479 * quota limits), check to see if the tail of the queue has EOQ set. We
480 * should immediately restart in that case so that the receiver can restart
481 * and run in parallel with more packet processing. This lets us handle slightly
482 * larger bursts before running out of ring space (assuming dev->weight < ring_size)
483 */
484 if (!restart &&
485 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ)) == CPMAC_EOQ &&
486 (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
487 /* reset EOQ so the poll loop (above) doesn't try to restart this when it
488 * eventually gets to this descriptor.
489 */
490 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
491 restart = priv->rx_head;
492 }
493
494 if (restart) {
495 dev->stats.rx_errors++;
496 dev->stats.rx_fifo_errors++;
497 if (netif_msg_rx_err(priv) && net_ratelimit())
498 printk(KERN_WARNING "%s: rx dma ring overrun\n", dev->name);
499
500 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
501 if (netif_msg_drv(priv))
502 printk(KERN_ERR "%s: cpmac_poll is trying to restart rx from a descriptor that's not free: %p\n",
503 dev->name, restart);
504 goto fatal_error;
505 }
506
507 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
508 }
509
510 priv->rx_head = desc;
511 spin_unlock(&priv->rx_lock);
512 *budget -= received;
513 dev->quota -= received;
514 if (unlikely(netif_msg_rx_status(priv)))
515 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
516 received);
517
518 if (processed == 0) {
519 /* we ran out of packets to read, revert to interrupt-driven mode */
520 netif_rx_complete(dev);
521 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
522 return 0;
523 }
524
525 return 1;
526
527 fatal_error:
528 /* Something went horribly wrong. Reset hardware to try to recover rather than wedging. */
529
530 if (netif_msg_drv(priv)) {
531 printk(KERN_ERR "%s: cpmac_poll is confused. Resetting hardware\n", dev->name);
532 cpmac_dump_all_desc(dev);
533 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
534 dev->name,
535 cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
536 cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
537 }
538
539 spin_unlock(&priv->rx_lock);
540 netif_rx_complete(dev);
541 netif_stop_queue(dev);
542
543 atomic_inc(&priv->reset_pending);
544 cpmac_hw_stop(dev);
545 if (!schedule_work(&priv->reset_work))
546 atomic_dec(&priv->reset_pending);
547 return 0;
548 }
549
550 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
551 {
552 int queue, len;
553 struct cpmac_desc *desc;
554 struct cpmac_priv *priv = netdev_priv(dev);
555
556 if (unlikely(atomic_read(&priv->reset_pending)))
557 return NETDEV_TX_BUSY;
558
559 if (unlikely(skb_padto(skb, ETH_ZLEN)))
560 return NETDEV_TX_OK;
561
562 len = max(skb->len, ETH_ZLEN);
563 queue = skb->queue_mapping;
564 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
565 netif_stop_subqueue(dev, queue);
566 #else
567 netif_stop_queue(dev);
568 #endif
569
570 desc = &priv->desc_ring[queue];
571 if (unlikely(desc->dataflags & CPMAC_OWN)) {
572 if (netif_msg_tx_err(priv) && net_ratelimit())
573 printk(KERN_WARNING "%s: tx dma ring full\n",
574 dev->name);
575 return NETDEV_TX_BUSY;
576 }
577
578 spin_lock(&priv->lock);
579 dev->trans_start = jiffies;
580 spin_unlock(&priv->lock);
581 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
582 desc->skb = skb;
583 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
584 DMA_TO_DEVICE);
585 desc->hw_data = (u32)desc->data_mapping;
586 desc->datalen = len;
587 desc->buflen = len;
588 if (unlikely(netif_msg_tx_queued(priv)))
589 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
590 skb->len);
591 if (unlikely(netif_msg_hw(priv)))
592 cpmac_dump_desc(dev, desc);
593 if (unlikely(netif_msg_pktdata(priv)))
594 cpmac_dump_skb(dev, skb);
595 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
596
597 return NETDEV_TX_OK;
598 }
599
600 static void cpmac_end_xmit(struct net_device *dev, int queue)
601 {
602 struct cpmac_desc *desc;
603 struct cpmac_priv *priv = netdev_priv(dev);
604
605 desc = &priv->desc_ring[queue];
606 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
607 if (likely(desc->skb)) {
608 spin_lock(&priv->lock);
609 dev->stats.tx_packets++;
610 dev->stats.tx_bytes += desc->skb->len;
611 spin_unlock(&priv->lock);
612 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
613 DMA_TO_DEVICE);
614
615 if (unlikely(netif_msg_tx_done(priv)))
616 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
617 desc->skb, desc->skb->len);
618
619 dev_kfree_skb_irq(desc->skb);
620 desc->skb = NULL;
621 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
622 if (netif_subqueue_stopped(dev, queue))
623 netif_wake_subqueue(dev, queue);
624 #else
625 if (netif_queue_stopped(dev))
626 netif_wake_queue(dev);
627 #endif
628 } else {
629 if (netif_msg_tx_err(priv) && net_ratelimit())
630 printk(KERN_WARNING
631 "%s: end_xmit: spurious interrupt\n", dev->name);
632 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
633 if (netif_subqueue_stopped(dev, queue))
634 netif_wake_subqueue(dev, queue);
635 #else
636 if (netif_queue_stopped(dev))
637 netif_wake_queue(dev);
638 #endif
639 }
640 }
641
642 static void cpmac_hw_stop(struct net_device *dev)
643 {
644 int i;
645 struct cpmac_priv *priv = netdev_priv(dev);
646 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
647
648 ar7_device_reset(pdata->reset_bit);
649 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
650 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
651 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
652 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
653 for (i = 0; i < 8; i++) {
654 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
655 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
656 }
657 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
658 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
659 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
660 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
661 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
662 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
663 }
664
665 static void cpmac_hw_start(struct net_device *dev)
666 {
667 int i;
668 struct cpmac_priv *priv = netdev_priv(dev);
669 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
670
671 ar7_device_reset(pdata->reset_bit);
672 for (i = 0; i < 8; i++) {
673 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
674 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
675 }
676 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
677
678 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
679 MBP_RXMCAST);
680 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
681 for (i = 0; i < 8; i++)
682 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
683 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
684 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
685 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
686 (dev->dev_addr[3] << 24));
687 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
688 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
689 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
690 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
691 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
692 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
693 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
694 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
695 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
696
697 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
698 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
699 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
700 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
701 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
702 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
703 MAC_FDX);
704 }
705
706 static void cpmac_clear_rx(struct net_device *dev)
707 {
708 struct cpmac_priv *priv = netdev_priv(dev);
709 struct cpmac_desc *desc;
710 int i;
711 if (unlikely(!priv->rx_head))
712 return;
713 desc = priv->rx_head;
714 for (i = 0; i < priv->ring_size; i++) {
715 if ((desc->dataflags & CPMAC_OWN) == 0) {
716 if (netif_msg_rx_err(priv) && net_ratelimit())
717 printk(KERN_WARNING "%s: packet dropped\n",
718 dev->name);
719 if (unlikely(netif_msg_hw(priv)))
720 cpmac_dump_desc(dev, desc);
721 desc->dataflags = CPMAC_OWN;
722 dev->stats.rx_dropped++;
723 }
724 desc->hw_next = desc->next->mapping;
725 desc = desc->next;
726 }
727
728 priv->rx_head->prev->hw_next = 0;
729 }
730
731 static void cpmac_clear_tx(struct net_device *dev)
732 {
733 struct cpmac_priv *priv = netdev_priv(dev);
734 int i;
735 if (unlikely(!priv->desc_ring))
736 return;
737 for (i = 0; i < CPMAC_QUEUES; i++) {
738 priv->desc_ring[i].dataflags = 0;
739 if (priv->desc_ring[i].skb) {
740 dev_kfree_skb_any(priv->desc_ring[i].skb);
741 priv->desc_ring[i].skb = NULL;
742 }
743 }
744 }
745
746 static void cpmac_hw_error(struct work_struct *work)
747 {
748 int i;
749 struct cpmac_priv *priv =
750 container_of(work, struct cpmac_priv, reset_work);
751
752 spin_lock(&priv->rx_lock);
753 cpmac_clear_rx(priv->dev);
754 spin_unlock(&priv->rx_lock);
755 cpmac_clear_tx(priv->dev);
756 cpmac_hw_start(priv->dev);
757 barrier();
758 atomic_dec(&priv->reset_pending);
759
760 for (i = 0; i < CPMAC_QUEUES; i++) {
761 netif_wake_subqueue(priv->dev, i);
762 }
763 netif_wake_queue(priv->dev);
764 }
765
766 static void cpmac_check_status(struct net_device *dev)
767 {
768 struct cpmac_priv *priv = netdev_priv(dev);
769
770 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
771 int rx_channel = (macstatus >> 8) & 7;
772 int rx_code = (macstatus >> 12) & 15;
773 int tx_channel = (macstatus >> 16) & 7;
774 int tx_code = (macstatus >> 20) & 15;
775
776 if (rx_code || tx_code) {
777 if (netif_msg_drv(priv) && net_ratelimit()) {
778 /* Can't find any documentation on what these error codes actually are.
779 * So just log them and hope..
780 */
781 if (rx_code)
782 printk(KERN_WARNING "%s: host error %d on rx channel %d (macstatus %08x), resetting\n",
783 dev->name, rx_code, rx_channel, macstatus);
784 if (tx_code)
785 printk(KERN_WARNING "%s: host error %d on tx channel %d (macstatus %08x), resetting\n",
786 dev->name, tx_code, tx_channel, macstatus);
787 }
788
789 netif_stop_queue(dev);
790 cpmac_hw_stop(dev);
791 if (schedule_work(&priv->reset_work))
792 atomic_inc(&priv->reset_pending);
793 if (unlikely(netif_msg_hw(priv)))
794 cpmac_dump_regs(dev);
795 }
796 }
797
798 static irqreturn_t cpmac_irq(int irq, void *dev_id)
799 {
800 struct net_device *dev = dev_id;
801 struct cpmac_priv *priv;
802 int queue;
803 u32 status;
804
805 if (!dev)
806 return IRQ_NONE;
807
808 priv = netdev_priv(dev);
809
810 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
811
812 if (unlikely(netif_msg_intr(priv)))
813 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
814 status);
815
816 if (status & MAC_INT_TX)
817 cpmac_end_xmit(dev, (status & 7));
818
819 if (status & MAC_INT_RX) {
820 queue = (status >> 8) & 7;
821 netif_rx_schedule(dev);
822 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
823 }
824
825 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
826
827 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
828 cpmac_check_status(dev);
829
830 return IRQ_HANDLED;
831 }
832
833 static void cpmac_tx_timeout(struct net_device *dev)
834 {
835 int i;
836 struct cpmac_priv *priv = netdev_priv(dev);
837
838 spin_lock(&priv->lock);
839 dev->stats.tx_errors++;
840 spin_unlock(&priv->lock);
841 if (netif_msg_tx_err(priv) && net_ratelimit())
842 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
843
844 atomic_inc(&priv->reset_pending);
845 barrier();
846 cpmac_clear_tx(dev);
847 barrier();
848 atomic_dec(&priv->reset_pending);
849
850 netif_wake_queue(priv->dev);
851 for (i = 0; i < CPMAC_QUEUES; i++) {
852 netif_wake_subqueue(dev, i);
853 }
854 }
855
856 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
857 {
858 struct cpmac_priv *priv = netdev_priv(dev);
859 if (!(netif_running(dev)))
860 return -EINVAL;
861 if (!priv->phy)
862 return -EINVAL;
863 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
864 (cmd == SIOCSMIIREG))
865 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
866
867 return -EOPNOTSUPP;
868 }
869
870 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
871 {
872 struct cpmac_priv *priv = netdev_priv(dev);
873
874 if (priv->phy)
875 return phy_ethtool_gset(priv->phy, cmd);
876
877 return -EINVAL;
878 }
879
880 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
881 {
882 struct cpmac_priv *priv = netdev_priv(dev);
883
884 if (!capable(CAP_NET_ADMIN))
885 return -EPERM;
886
887 if (priv->phy)
888 return phy_ethtool_sset(priv->phy, cmd);
889
890 return -EINVAL;
891 }
892
893 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
894 {
895 struct cpmac_priv *priv = netdev_priv(dev);
896
897 ring->rx_max_pending = 1024;
898 ring->rx_mini_max_pending = 1;
899 ring->rx_jumbo_max_pending = 1;
900 ring->tx_max_pending = 1;
901
902 ring->rx_pending = priv->ring_size;
903 ring->rx_mini_pending = 1;
904 ring->rx_jumbo_pending = 1;
905 ring->tx_pending = 1;
906 }
907
908 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
909 {
910 struct cpmac_priv *priv = netdev_priv(dev);
911
912 if (netif_running(dev))
913 return -EBUSY;
914 priv->ring_size = ring->rx_pending;
915 return 0;
916 }
917
918 static void cpmac_get_drvinfo(struct net_device *dev,
919 struct ethtool_drvinfo *info)
920 {
921 strcpy(info->driver, "cpmac");
922 strcpy(info->version, CPMAC_VERSION);
923 info->fw_version[0] = '\0';
924 sprintf(info->bus_info, "%s", "cpmac");
925 info->regdump_len = 0;
926 }
927
928 static const struct ethtool_ops cpmac_ethtool_ops = {
929 .get_settings = cpmac_get_settings,
930 .set_settings = cpmac_set_settings,
931 .get_drvinfo = cpmac_get_drvinfo,
932 .get_link = ethtool_op_get_link,
933 .get_ringparam = cpmac_get_ringparam,
934 .set_ringparam = cpmac_set_ringparam,
935 };
936
937 static void cpmac_adjust_link(struct net_device *dev)
938 {
939 struct cpmac_priv *priv = netdev_priv(dev);
940 int new_state = 0;
941
942 spin_lock(&priv->lock);
943 if (priv->phy->link) {
944 netif_start_queue(dev);
945 if (priv->phy->duplex != priv->oldduplex) {
946 new_state = 1;
947 priv->oldduplex = priv->phy->duplex;
948 }
949
950 if (priv->phy->speed != priv->oldspeed) {
951 new_state = 1;
952 priv->oldspeed = priv->phy->speed;
953 }
954
955 if (!priv->oldlink) {
956 new_state = 1;
957 priv->oldlink = 1;
958 netif_schedule(dev);
959 }
960 } else if (priv->oldlink) {
961 netif_stop_queue(dev);
962 new_state = 1;
963 priv->oldlink = 0;
964 priv->oldspeed = 0;
965 priv->oldduplex = -1;
966 }
967
968 if (new_state && netif_msg_link(priv) && net_ratelimit())
969 phy_print_status(priv->phy);
970
971 spin_unlock(&priv->lock);
972 }
973
974 static int cpmac_open(struct net_device *dev)
975 {
976 int i, size, res;
977 struct cpmac_priv *priv = netdev_priv(dev);
978 struct resource *mem;
979 struct cpmac_desc *desc;
980 struct sk_buff *skb;
981
982 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
983 0, PHY_INTERFACE_MODE_MII);
984 if (IS_ERR(priv->phy)) {
985 if (netif_msg_drv(priv))
986 printk(KERN_ERR "%s: Could not attach to PHY\n",
987 dev->name);
988 return PTR_ERR(priv->phy);
989 }
990
991 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
992 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
993 if (netif_msg_drv(priv))
994 printk(KERN_ERR "%s: failed to request registers\n",
995 dev->name);
996 res = -ENXIO;
997 goto fail_reserve;
998 }
999
1000 priv->regs = ioremap(mem->start, mem->end - mem->start);
1001 if (!priv->regs) {
1002 if (netif_msg_drv(priv))
1003 printk(KERN_ERR "%s: failed to remap registers\n",
1004 dev->name);
1005 res = -ENXIO;
1006 goto fail_remap;
1007 }
1008
1009 size = priv->ring_size + CPMAC_QUEUES;
1010 priv->desc_ring = dma_alloc_coherent(&dev->dev,
1011 sizeof(struct cpmac_desc) * size,
1012 &priv->dma_ring,
1013 GFP_KERNEL);
1014 if (!priv->desc_ring) {
1015 res = -ENOMEM;
1016 goto fail_alloc;
1017 }
1018
1019 for (i = 0; i < size; i++)
1020 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
1021
1022 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1023 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
1024 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
1025 if (unlikely(!skb)) {
1026 res = -ENOMEM;
1027 goto fail_desc;
1028 }
1029 skb_reserve(skb, 2);
1030 desc->skb = skb;
1031 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1032 CPMAC_SKB_SIZE,
1033 DMA_FROM_DEVICE);
1034 desc->hw_data = (u32)desc->data_mapping;
1035 desc->buflen = CPMAC_SKB_SIZE;
1036 desc->dataflags = CPMAC_OWN;
1037 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1038 desc->next->prev = desc;
1039 desc->hw_next = (u32)desc->next->mapping;
1040 }
1041
1042 priv->rx_head->prev->hw_next = (u32)0;
1043
1044 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1045 dev->name, dev))) {
1046 if (netif_msg_drv(priv))
1047 printk(KERN_ERR "%s: failed to obtain irq\n",
1048 dev->name);
1049 goto fail_irq;
1050 }
1051
1052 atomic_set(&priv->reset_pending, 0);
1053 INIT_WORK(&priv->reset_work, cpmac_hw_error);
1054 cpmac_hw_start(dev);
1055
1056 priv->phy->state = PHY_CHANGELINK;
1057 phy_start(priv->phy);
1058
1059 return 0;
1060
1061 fail_irq:
1062 fail_desc:
1063 for (i = 0; i < priv->ring_size; i++) {
1064 if (priv->rx_head[i].skb) {
1065 dma_unmap_single(&dev->dev,
1066 priv->rx_head[i].data_mapping,
1067 CPMAC_SKB_SIZE,
1068 DMA_FROM_DEVICE);
1069 kfree_skb(priv->rx_head[i].skb);
1070 }
1071 }
1072 fail_alloc:
1073 kfree(priv->desc_ring);
1074 iounmap(priv->regs);
1075
1076 fail_remap:
1077 release_mem_region(mem->start, mem->end - mem->start);
1078
1079 fail_reserve:
1080 phy_disconnect(priv->phy);
1081
1082 return res;
1083 }
1084
1085 static int cpmac_stop(struct net_device *dev)
1086 {
1087 int i;
1088 struct cpmac_priv *priv = netdev_priv(dev);
1089 struct resource *mem;
1090
1091 netif_stop_queue(dev);
1092
1093 cancel_work_sync(&priv->reset_work);
1094 phy_stop(priv->phy);
1095 phy_disconnect(priv->phy);
1096 priv->phy = NULL;
1097
1098 cpmac_hw_stop(dev);
1099
1100 for (i = 0; i < 8; i++)
1101 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1102 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1103 cpmac_write(priv->regs, CPMAC_MBP, 0);
1104
1105 free_irq(dev->irq, dev);
1106 iounmap(priv->regs);
1107 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1108 release_mem_region(mem->start, mem->end - mem->start);
1109 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1110 for (i = 0; i < priv->ring_size; i++) {
1111 if (priv->rx_head[i].skb) {
1112 dma_unmap_single(&dev->dev,
1113 priv->rx_head[i].data_mapping,
1114 CPMAC_SKB_SIZE,
1115 DMA_FROM_DEVICE);
1116 kfree_skb(priv->rx_head[i].skb);
1117 }
1118 }
1119
1120 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1121 (CPMAC_QUEUES + priv->ring_size),
1122 priv->desc_ring, priv->dma_ring);
1123 return 0;
1124 }
1125
1126 static int external_switch;
1127
1128 static int __devinit cpmac_probe(struct platform_device *pdev)
1129 {
1130 int rc, phy_id;
1131 struct resource *mem;
1132 struct cpmac_priv *priv;
1133 struct net_device *dev;
1134 struct plat_cpmac_data *pdata;
1135
1136 pdata = pdev->dev.platform_data;
1137
1138 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1139 if (!(pdata->phy_mask & (1 << phy_id)))
1140 continue;
1141 if (!cpmac_mii.phy_map[phy_id])
1142 continue;
1143 break;
1144 }
1145
1146 if (phy_id == PHY_MAX_ADDR) {
1147 if (external_switch || dumb_switch)
1148 phy_id = 0;
1149 else {
1150 printk(KERN_ERR "cpmac: no PHY present\n");
1151 return -ENODEV;
1152 }
1153 }
1154
1155 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1156
1157 if (!dev) {
1158 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1159 return -ENOMEM;
1160 }
1161
1162 platform_set_drvdata(pdev, dev);
1163 priv = netdev_priv(dev);
1164
1165 priv->pdev = pdev;
1166 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1167 if (!mem) {
1168 rc = -ENODEV;
1169 goto fail;
1170 }
1171
1172 dev->irq = platform_get_irq_byname(pdev, "irq");
1173
1174 dev->open = cpmac_open;
1175 dev->stop = cpmac_stop;
1176 dev->set_config = cpmac_config;
1177 dev->hard_start_xmit = cpmac_start_xmit;
1178 dev->do_ioctl = cpmac_ioctl;
1179 dev->set_multicast_list = cpmac_set_multicast_list;
1180 dev->tx_timeout = cpmac_tx_timeout;
1181 dev->ethtool_ops = &cpmac_ethtool_ops;
1182 dev->poll = cpmac_poll;
1183 dev->features |= NETIF_F_MULTI_QUEUE;
1184
1185 spin_lock_init(&priv->lock);
1186 spin_lock_init(&priv->rx_lock);
1187 priv->dev = dev;
1188 priv->ring_size = 64;
1189 dev->weight = max(4, priv->ring_size/4);
1190 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1191 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1192 if (phy_id == 31) {
1193 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1194 cpmac_mii.id, phy_id);
1195 } else
1196 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1197
1198 if ((rc = register_netdev(dev))) {
1199 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1200 dev->name);
1201 goto fail;
1202 }
1203
1204 if (netif_msg_probe(priv)) {
1205 printk(KERN_INFO
1206 "cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: "
1207 MAC_FMT ")\n", dev->name, (void *)mem->start, dev->irq,
1208 priv->phy_name, MAC_ARG(dev->dev_addr));
1209 }
1210 return 0;
1211
1212 fail:
1213 free_netdev(dev);
1214 return rc;
1215 }
1216
1217 static int __devexit cpmac_remove(struct platform_device *pdev)
1218 {
1219 struct net_device *dev = platform_get_drvdata(pdev);
1220 unregister_netdev(dev);
1221 free_netdev(dev);
1222 return 0;
1223 }
1224
1225 static struct platform_driver cpmac_driver = {
1226 .driver.name = "cpmac",
1227 .probe = cpmac_probe,
1228 .remove = __devexit_p(cpmac_remove),
1229 };
1230
1231 int __devinit cpmac_init(void)
1232 {
1233 u32 mask;
1234 int i, res;
1235
1236 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1237
1238 if (!cpmac_mii.priv) {
1239 printk(KERN_ERR "Can't ioremap mdio registers\n");
1240 return -ENXIO;
1241 }
1242
1243 #warning FIXME: unhardcode gpio&reset bits
1244 ar7_gpio_disable(26);
1245 ar7_gpio_disable(27);
1246 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1247 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1248 ar7_device_reset(AR7_RESET_BIT_EPHY);
1249
1250 cpmac_mii.reset(&cpmac_mii);
1251
1252 for (i = 0; i < 300000; i++)
1253 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1254 break;
1255 else
1256 cpu_relax();
1257
1258 mask &= 0x7fffffff;
1259 if (mask & (mask - 1)) {
1260 external_switch = 1;
1261 mask = 0;
1262 }
1263
1264 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1265
1266 res = mdiobus_register(&cpmac_mii);
1267 if (res)
1268 goto fail_mii;
1269
1270 res = platform_driver_register(&cpmac_driver);
1271 if (res)
1272 goto fail_cpmac;
1273
1274 return 0;
1275
1276 fail_cpmac:
1277 mdiobus_unregister(&cpmac_mii);
1278
1279 fail_mii:
1280 iounmap(cpmac_mii.priv);
1281
1282 return res;
1283 }
1284
1285 void __devexit cpmac_exit(void)
1286 {
1287 platform_driver_unregister(&cpmac_driver);
1288 mdiobus_unregister(&cpmac_mii);
1289 iounmap(cpmac_mii.priv);
1290 }
1291
1292 module_init(cpmac_init);
1293 module_exit(cpmac_exit);
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