package/mac80211/patches/552-ath9k_txdesc_optimization.patch

   1 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
   2 +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
   3 @@ -208,77 +208,68 @@ static int ar9002_hw_proc_txdesc(struct
   4                                  struct ath_tx_status *ts)
   5  {
   6         struct ar5416_desc *ads = AR5416DESC(ds);
   7 +       u32 status;
   8
   9 -       if ((ads->ds_txstatus9 & AR_TxDone) == 0)
  10 +       status = ACCESS_ONCE(ads->ds_txstatus9);
  11 +       if ((status & AR_TxDone) == 0)
  12                 return -EINPROGRESS;
  13
  14 -       ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
  15         ts->ts_tstamp = ads->AR_SendTimestamp;
  16         ts->ts_status = 0;
  17         ts->ts_flags = 0;
  18
  19 -       if (ads->ds_txstatus1 & AR_FrmXmitOK)
  20 +       if (status & AR_TxOpExceeded)
  21 +               ts->ts_status |= ATH9K_TXERR_XTXOP;
  22 +       ts->tid = MS(status, AR_TxTid);
  23 +       ts->ts_rateindex = MS(status, AR_FinalTxIdx);
  24 +       ts->ts_seqnum = MS(status, AR_SeqNum);
  25 +
  26 +       status = ACCESS_ONCE(ads->ds_txstatus0);
  27 +       ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
  28 +       ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
  29 +       ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
  30 +       if (status & AR_TxBaStatus) {
  31 +               ts->ts_flags |= ATH9K_TX_BA;
  32 +               ts->ba_low = ads->AR_BaBitmapLow;
  33 +               ts->ba_high = ads->AR_BaBitmapHigh;
  34 +       }
  35 +
  36 +       status = ACCESS_ONCE(ads->ds_txstatus1);
  37 +       if (status & AR_FrmXmitOK)
  38                 ts->ts_status |= ATH9K_TX_ACKED;
  39 -       if (ads->ds_txstatus1 & AR_ExcessiveRetries)
  40 +       if (status & AR_ExcessiveRetries)
  41                 ts->ts_status |= ATH9K_TXERR_XRETRY;
  42 -       if (ads->ds_txstatus1 & AR_Filtered)
  43 +       if (status & AR_Filtered)
  44                 ts->ts_status |= ATH9K_TXERR_FILT;
  45 -       if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
  46 +       if (status & AR_FIFOUnderrun) {
  47                 ts->ts_status |= ATH9K_TXERR_FIFO;
  48                 ath9k_hw_updatetxtriglevel(ah, true);
  49         }
  50 -       if (ads->ds_txstatus9 & AR_TxOpExceeded)
  51 -               ts->ts_status |= ATH9K_TXERR_XTXOP;
  52 -       if (ads->ds_txstatus1 & AR_TxTimerExpired)
  53 +       if (status & AR_TxTimerExpired)
  54                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
  55 -
  56 -       if (ads->ds_txstatus1 & AR_DescCfgErr)
  57 +       if (status & AR_DescCfgErr)
  58                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
  59 -       if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
  60 +       if (status & AR_TxDataUnderrun) {
  61                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
  62                 ath9k_hw_updatetxtriglevel(ah, true);
  63         }
  64 -       if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
  65 +       if (status & AR_TxDelimUnderrun) {
  66                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
  67                 ath9k_hw_updatetxtriglevel(ah, true);
  68         }
  69 -       if (ads->ds_txstatus0 & AR_TxBaStatus) {
  70 -               ts->ts_flags |= ATH9K_TX_BA;
  71 -               ts->ba_low = ads->AR_BaBitmapLow;
  72 -               ts->ba_high = ads->AR_BaBitmapHigh;
  73 -       }
  74 -
  75 -       ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
  76 -       switch (ts->ts_rateindex) {
  77 -       case 0:
  78 -               ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
  79 -               break;
  80 -       case 1:
  81 -               ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
  82 -               break;
  83 -       case 2:
  84 -               ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
  85 -               break;
  86 -       case 3:
  87 -               ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
  88 -               break;
  89 -       }
  90 +       ts->ts_shortretry = MS(status, AR_RTSFailCnt);
  91 +       ts->ts_longretry = MS(status, AR_DataFailCnt);
  92 +       ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
  93 +
  94 +       status = ACCESS_ONCE(ads->ds_txstatus5);
  95 +       ts->ts_rssi = MS(status, AR_TxRSSICombined);
  96 +       ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
  97 +       ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
  98 +       ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
  99
 100 -       ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
 101 -       ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
 102 -       ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
 103 -       ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
 104 -       ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
 105 -       ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
 106 -       ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
 107         ts->evm0 = ads->AR_TxEVM0;
 108         ts->evm1 = ads->AR_TxEVM1;
 109         ts->evm2 = ads->AR_TxEVM2;
 110 -       ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
 111 -       ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
 112 -       ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
 113 -       ts->tid = MS(ads->ds_txstatus9, AR_TxTid);
 114 -       ts->ts_antenna = 0;
 115
 116         return 0;
 117  }
 118 --- a/drivers/net/wireless/ath/ath9k/mac.h
 119 +++ b/drivers/net/wireless/ath/ath9k/mac.h
 120 @@ -104,13 +104,11 @@ struct ath_tx_status {
 121         u32 ts_tstamp;
 122         u16 ts_seqnum;
 123         u8 ts_status;
 124 -       u8 ts_ratecode;
 125         u8 ts_rateindex;
 126         int8_t ts_rssi;
 127         u8 ts_shortretry;
 128         u8 ts_longretry;
 129         u8 ts_virtcol;
 130 -       u8 ts_antenna;
 131         u8 ts_flags;
 132         int8_t ts_rssi_ctl0;
 133         int8_t ts_rssi_ctl1;
 134 @@ -121,7 +119,6 @@ struct ath_tx_status {
 135         u8 qid;
 136         u16 desc_id;
 137         u8 tid;
 138 -       u8 pad[2];
 139         u32 ba_low;
 140         u32 ba_high;
 141         u32 evm0;
 142 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
 143 +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
 144 @@ -237,10 +237,12 @@ static int ar9003_hw_proc_txdesc(struct
 145                                  struct ath_tx_status *ts)
 146  {
 147         struct ar9003_txs *ads;
 148 +       u32 status;
 149
 150         ads = &ah->ts_ring[ah->ts_tail];
 151
 152 -       if ((ads->status8 & AR_TxDone) == 0)
 153 +       status = ACCESS_ONCE(ads->status8);
 154 +       if ((status & AR_TxDone) == 0)
 155                 return -EINPROGRESS;
 156
 157         ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
 158 @@ -253,57 +255,58 @@ static int ar9003_hw_proc_txdesc(struct
 159                 return -EIO;
 160         }
 161
 162 +       if (status & AR_TxOpExceeded)
 163 +               ts->ts_status |= ATH9K_TXERR_XTXOP;
 164 +       ts->ts_rateindex = MS(status, AR_FinalTxIdx);
 165 +       ts->ts_seqnum = MS(status, AR_SeqNum);
 166 +       ts->tid = MS(status, AR_TxTid);
 167 +
 168         ts->qid = MS(ads->ds_info, AR_TxQcuNum);
 169         ts->desc_id = MS(ads->status1, AR_TxDescId);
 170 -       ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
 171         ts->ts_tstamp = ads->status4;
 172         ts->ts_status = 0;
 173         ts->ts_flags  = 0;
 174
 175 -       if (ads->status3 & AR_ExcessiveRetries)
 176 +       status = ACCESS_ONCE(ads->status2);
 177 +       ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
 178 +       ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
 179 +       ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
 180 +       if (status & AR_TxBaStatus) {
 181 +               ts->ts_flags |= ATH9K_TX_BA;
 182 +               ts->ba_low = ads->status5;
 183 +               ts->ba_high = ads->status6;
 184 +       }
 185 +
 186 +       status = ACCESS_ONCE(ads->status3);
 187 +       if (status & AR_ExcessiveRetries)
 188                 ts->ts_status |= ATH9K_TXERR_XRETRY;
 189 -       if (ads->status3 & AR_Filtered)
 190 +       if (status & AR_Filtered)
 191                 ts->ts_status |= ATH9K_TXERR_FILT;
 192 -       if (ads->status3 & AR_FIFOUnderrun) {
 193 +       if (status & AR_FIFOUnderrun) {
 194                 ts->ts_status |= ATH9K_TXERR_FIFO;
 195                 ath9k_hw_updatetxtriglevel(ah, true);
 196         }
 197 -       if (ads->status8 & AR_TxOpExceeded)
 198 -               ts->ts_status |= ATH9K_TXERR_XTXOP;
 199 -       if (ads->status3 & AR_TxTimerExpired)
 200 +       if (status & AR_TxTimerExpired)
 201                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
 202 -
 203 -       if (ads->status3 & AR_DescCfgErr)
 204 +       if (status & AR_DescCfgErr)
 205                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
 206 -       if (ads->status3 & AR_TxDataUnderrun) {
 207 +       if (status & AR_TxDataUnderrun) {
 208                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
 209                 ath9k_hw_updatetxtriglevel(ah, true);
 210         }
 211 -       if (ads->status3 & AR_TxDelimUnderrun) {
 212 +       if (status & AR_TxDelimUnderrun) {
 213                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
 214                 ath9k_hw_updatetxtriglevel(ah, true);
 215         }
 216 -       if (ads->status2 & AR_TxBaStatus) {
 217 -               ts->ts_flags |= ATH9K_TX_BA;
 218 -               ts->ba_low = ads->status5;
 219 -               ts->ba_high = ads->status6;
 220 -       }
 221 -
 222 -       ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
 223 -
 224 -       ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
 225 -       ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
 226 -       ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
 227 -       ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
 228 -       ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
 229 -       ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
 230 -       ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
 231 -       ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
 232 -       ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
 233 -       ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
 234 -       ts->ts_antenna = 0;
 235 -
 236 -       ts->tid = MS(ads->status8, AR_TxTid);
 237 +       ts->ts_shortretry = MS(status, AR_RTSFailCnt);
 238 +       ts->ts_longretry = MS(status, AR_DataFailCnt);
 239 +       ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 240 +
 241 +       status = ACCESS_ONCE(ads->status7);
 242 +       ts->ts_rssi = MS(status, AR_TxRSSICombined);
 243 +       ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
 244 +       ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
 245 +       ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 246
 247         memset(ads, 0, sizeof(*ads));
 248