2 * pcicfg.h: PCI configuration constants and structures.
4 * Copyright 2007, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
17 /* The following inside ifndef's so we don't collide with NTDDK.H */
19 #define PCI_MAX_BUS 0x100
21 #ifndef PCI_MAX_DEVICES
22 #define PCI_MAX_DEVICES 0x20
24 #ifndef PCI_MAX_FUNCTION
25 #define PCI_MAX_FUNCTION 0x8
28 #ifndef PCI_INVALID_VENDORID
29 #define PCI_INVALID_VENDORID 0xffff
31 #ifndef PCI_INVALID_DEVICEID
32 #define PCI_INVALID_DEVICEID 0xffff
36 /* Convert between bus-slot-function-register and config addresses */
38 #define PCICFG_BUS_SHIFT 16 /* Bus shift */
39 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */
40 #define PCICFG_FUN_SHIFT 8 /* Function shift */
41 #define PCICFG_OFF_SHIFT 0 /* Register shift */
43 #define PCICFG_BUS_MASK 0xff /* Bus mask */
44 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */
45 #define PCICFG_FUN_MASK 7 /* Function mask */
46 #define PCICFG_OFF_MASK 0xff /* Bus mask */
48 #define PCI_CONFIG_ADDR(b, s, f, o) \
49 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
50 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
51 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
52 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
54 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
55 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
56 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
57 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
59 /* PCIE Config space accessing MACROS */
61 #define PCIECFG_BUS_SHIFT 24 /* Bus shift */
62 #define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
63 #define PCIECFG_FUN_SHIFT 16 /* Function shift */
64 #define PCIECFG_OFF_SHIFT 0 /* Register shift */
66 #define PCIECFG_BUS_MASK 0xff /* Bus mask */
67 #define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
68 #define PCIECFG_FUN_MASK 7 /* Function mask */
69 #define PCIECFG_OFF_MASK 0x3ff /* Register mask */
71 #define PCIE_CONFIG_ADDR(b, s, f, o) \
72 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
73 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
74 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
75 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
77 #define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
78 #define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
79 #define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
80 #define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
82 /* The actual config space */
88 #define PCR_RSVDA_MAX 2
90 /* Bits in PCI bars' flags */
92 #define PCIBAR_FLAGS 0xf
94 #define PCIBAR_MEM1M 0x2
95 #define PCIBAR_MEM64 0x4
96 #define PCIBAR_PREFETCH 0x8
97 #define PCIBAR_MEM32_MASK 0xFFFFFF80
99 /* pci config status reg has a bit to indicate that capability ptr is present */
101 #define PCI_CAPPTR_PRESENT 0x0010
103 typedef struct _pci_config_regs
{
104 unsigned short vendor
;
105 unsigned short device
;
106 unsigned short command
;
107 unsigned short status
;
108 unsigned char rev_id
;
109 unsigned char prog_if
;
110 unsigned char sub_class
;
111 unsigned char base_class
;
112 unsigned char cache_line_size
;
113 unsigned char latency_timer
;
114 unsigned char header_type
;
116 unsigned long base
[PCI_BAR_MAX
];
117 unsigned long cardbus_cis
;
118 unsigned short subsys_vendor
;
119 unsigned short subsys_id
;
120 unsigned long baserom
;
121 unsigned long rsvd_a
[PCR_RSVDA_MAX
];
122 unsigned char int_line
;
123 unsigned char int_pin
;
124 unsigned char min_gnt
;
125 unsigned char max_lat
;
126 unsigned char dev_dep
[192];
129 #define SZPCR (sizeof (pci_config_regs))
130 #define MINSZPCR 64 /* offsetof (dev_dep[0] */
132 /* A structure for the config registers is nice, but in most
133 * systems the config space is not memory mapped, so we need
134 * filed offsetts. :-(
136 #define PCI_CFG_VID 0
137 #define PCI_CFG_DID 2
138 #define PCI_CFG_CMD 4
139 #define PCI_CFG_STAT 6
140 #define PCI_CFG_REV 8
141 #define PCI_CFG_PROGIF 9
142 #define PCI_CFG_SUBCL 0xa
143 #define PCI_CFG_BASECL 0xb
144 #define PCI_CFG_CLSZ 0xc
145 #define PCI_CFG_LATTIM 0xd
146 #define PCI_CFG_HDR 0xe
147 #define PCI_CFG_BIST 0xf
148 #define PCI_CFG_BAR0 0x10
149 #define PCI_CFG_BAR1 0x14
150 #define PCI_CFG_BAR2 0x18
151 #define PCI_CFG_BAR3 0x1c
152 #define PCI_CFG_BAR4 0x20
153 #define PCI_CFG_BAR5 0x24
154 #define PCI_CFG_CIS 0x28
155 #define PCI_CFG_SVID 0x2c
156 #define PCI_CFG_SSID 0x2e
157 #define PCI_CFG_ROMBAR 0x30
158 #define PCI_CFG_CAPPTR 0x34
159 #define PCI_CFG_INT 0x3c
160 #define PCI_CFG_PIN 0x3d
161 #define PCI_CFG_MINGNT 0x3e
162 #define PCI_CFG_MAXLAT 0x3f
165 #undef PCI_CLASS_DISPLAY
166 #undef PCI_CLASS_MEMORY
167 #undef PCI_CLASS_BRIDGE
168 #undef PCI_CLASS_INPUT
169 #undef PCI_CLASS_DOCK
170 #endif /* __NetBSD__ */
173 #undef PCI_CLASS_BRIDGE
175 #undef PCI_CLASS_DISPLAY
176 #undef PCI_CLASS_SERIAL
177 #undef PCI_CLASS_SATELLITE
180 /* Classes and subclasses */
196 PCI_CLASS_INTELLIGENT
= 0xe,
209 PCI_DASDI_OTHER
= 0x80
210 } pci_dasdi_subclasses
;
218 } pci_net_subclasses
;
224 PCI_DISPLAY_OTHER
= 0x80
225 } pci_display_subclasses
;
231 PCI_MEDIA_OTHER
= 0x80
232 } pci_mmedia_subclasses
;
237 PCI_MEMORY_OTHER
= 0x80
238 } pci_memory_subclasses
;
250 PCI_BRIDGE_OTHER
= 0x80
251 } pci_bridge_subclasses
;
258 PCI_COMM_OTHER
= 0x80
259 } pci_comm_subclasses
;
266 PCI_BASE_PCI_HOTPLUG
,
267 PCI_BASE_OTHER
= 0x80
268 } pci_base_subclasses
;
276 PCI_INPUT_OTHER
= 0x80
277 } pci_input_subclasses
;
281 PCI_DOCK_OTHER
= 0x80
282 } pci_dock_subclasses
;
288 PCI_CPU_ALPHA
= 0x10,
289 PCI_CPU_POWERPC
= 0x20,
291 PCI_CPU_COPROC
= 0x40,
293 } pci_cpu_subclasses
;
302 PCI_SERIAL_OTHER
= 0x80
303 } pci_serial_subclasses
;
307 } pci_intelligent_subclasses
;
314 PCI_SATELLITE_OTHER
= 0x80
315 } pci_satellite_subclasses
;
319 PCI_CRYPT_ENTERTAINMENT
,
320 PCI_CRYPT_OTHER
= 0x80
321 } pci_crypt_subclasses
;
326 } pci_dsp_subclasses
;
331 } pci_xor_subclasses
;
341 /* Overlay for a PCI-to-PCI bridge */
343 #define PPB_RSVDA_MAX 2
344 #define PPB_RSVDD_MAX 8
346 typedef struct _ppb_config_regs
{
347 unsigned short vendor
;
348 unsigned short device
;
349 unsigned short command
;
350 unsigned short status
;
351 unsigned char rev_id
;
352 unsigned char prog_if
;
353 unsigned char sub_class
;
354 unsigned char base_class
;
355 unsigned char cache_line_size
;
356 unsigned char latency_timer
;
357 unsigned char header_type
;
359 unsigned long rsvd_a
[PPB_RSVDA_MAX
];
360 unsigned char prim_bus
;
361 unsigned char sec_bus
;
362 unsigned char sub_bus
;
363 unsigned char sec_lat
;
364 unsigned char io_base
;
365 unsigned char io_lim
;
366 unsigned short sec_status
;
367 unsigned short mem_base
;
368 unsigned short mem_lim
;
369 unsigned short pf_mem_base
;
370 unsigned short pf_mem_lim
;
371 unsigned long pf_mem_base_hi
;
372 unsigned long pf_mem_lim_hi
;
373 unsigned short io_base_hi
;
374 unsigned short io_lim_hi
;
375 unsigned short subsys_vendor
;
376 unsigned short subsys_id
;
377 unsigned long rsvd_b
;
378 unsigned char rsvd_c
;
379 unsigned char int_pin
;
380 unsigned short bridge_ctrl
;
381 unsigned char chip_ctrl
;
382 unsigned char diag_ctrl
;
383 unsigned short arb_ctrl
;
384 unsigned long rsvd_d
[PPB_RSVDD_MAX
];
385 unsigned char dev_dep
[192];
389 /* PCI CAPABILITY DEFINES */
390 #define PCI_CAP_POWERMGMTCAP_ID 0x01
391 #define PCI_CAP_MSICAP_ID 0x05
392 #define PCI_CAP_PCIECAP_ID 0x10
394 /* Data structure to define the Message Signalled Interrupt facility
395 * Valid for PCI and PCIE configurations
397 typedef struct _pciconfig_cap_msi
{
399 unsigned char nextptr
;
400 unsigned short msgctrl
;
401 unsigned int msgaddr
;
404 /* Data structure to define the Power managment facility
405 * Valid for PCI and PCIE configurations
407 typedef struct _pciconfig_cap_pwrmgmt
{
409 unsigned char nextptr
;
410 unsigned short pme_cap
;
411 unsigned short pme_sts_ctrl
;
412 unsigned char pme_bridge_ext
;
414 } pciconfig_cap_pwrmgmt
;
416 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
417 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
418 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
419 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
421 /* Data structure to define the PCIE capability */
422 typedef struct _pciconfig_cap_pcie
{
424 unsigned char nextptr
;
425 unsigned short pcie_cap
;
426 unsigned int dev_cap
;
427 unsigned short dev_ctrl
;
428 unsigned short dev_status
;
429 unsigned int link_cap
;
430 unsigned short link_ctrl
;
431 unsigned short link_status
;
432 } pciconfig_cap_pcie
;
434 /* PCIE Enhanced CAPABILITY DEFINES */
435 #define PCIE_EXTCFG_OFFSET 0x100
436 #define PCIE_ADVERRREP_CAPID 0x0001
437 #define PCIE_VC_CAPID 0x0002
438 #define PCIE_DEVSNUM_CAPID 0x0003
439 #define PCIE_PWRBUDGET_CAPID 0x0004
441 /* Header to define the PCIE specific capabilities in the extended config space */
442 typedef struct _pcie_enhanced_caphdr
{
443 unsigned short capID
;
444 unsigned short cap_ver
: 4;
445 unsigned short next_ptr
: 12;
446 } pcie_enhanced_caphdr
;
449 /* Everything below is BRCM HND proprietary */
452 /* Brcm PCI configuration registers */
453 #define cap_list rsvd_a[0]
454 #define bar0_window dev_dep[0x80 - 0x40]
455 #define bar1_window dev_dep[0x84 - 0x40]
456 #define sprom_control dev_dep[0x88 - 0x40]
458 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
459 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
460 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */
461 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
462 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
463 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
464 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
465 #define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
466 #define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
467 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
468 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
469 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
471 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
472 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
473 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
474 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
475 * 8KB window, so their address is the "regular"
478 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
480 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
481 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
482 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
483 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
486 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
489 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
490 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
491 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
493 /* PCI_SPROM_CONTROL */
494 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
495 #define SPROM_LOCKED 0x08 /* SPROM Locked */
496 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */
497 #define SPROM_WRITEEN 0x10 /* SPROM write enable */
498 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
499 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */
501 #define SPROM_SIZE 256 /* sprom size in 16-bit */
502 #define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
504 /* PCI_CFG_CMD_STAT */
505 #define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
507 #endif /* _h_pcicfg_ */