ar71xx: boost SPI flash read performance
[openwrt.git] / target / linux / lantiq / patches-3.2 / 0013-MIPS-lantiq-fix-STP-gpio-groups.patch
1 From 556ba7f7149a0350a47ecf26185aed99c8d87176 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 27 Oct 2011 20:06:05 +0200
4 Subject: [PATCH 13/70] MIPS: lantiq: fix STP gpio groups
5
6 The STP engine has 3 groups of 8 pins. Only the first was activated by default.
7 This patch activates the 2 missing groups.
8
9 Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 ---
12 arch/mips/lantiq/xway/gpio_stp.c | 7 +++++--
13 1 files changed, 5 insertions(+), 2 deletions(-)
14
15 diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
16 index 2c78660..cb6f170 100644
17 --- a/arch/mips/lantiq/xway/gpio_stp.c
18 +++ b/arch/mips/lantiq/xway/gpio_stp.c
19 @@ -35,6 +35,8 @@
20 #define LTQ_STP_ADSL_SRC (3 << 24)
21
22 #define LTQ_STP_GROUP0 (1 << 0)
23 +#define LTQ_STP_GROUP1 (1 << 1)
24 +#define LTQ_STP_GROUP2 (1 << 2)
25
26 #define LTQ_STP_RISING 0
27 #define LTQ_STP_FALLING (1 << 26)
28 @@ -93,8 +95,9 @@ static int ltq_stp_hw_init(void)
29 /* rising or falling edge */
30 ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
31
32 - /* per default stp 15-0 are set */
33 - ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
34 + /* enable all three led groups */
35 + ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2,
36 + LTQ_STP_CON1);
37
38 /* stp are update periodically by the FPI bus */
39 ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
40 --
41 1.7.7.1
42
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