target/linux/lantiq/patches-3.2/0061-MIPS-clean-up-clock-code.patch

   1 From d23a3c21962bcc3dc18e7916c2499cd3b26feaf0 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 20 Mar 2012 08:26:04 +0100
   4 Subject: [PATCH 61/70] MIPS: clean up clock code
   5
   6 ---
   7  arch/mips/lantiq/clk.c          |   11 +++
   8  arch/mips/lantiq/clk.h          |    3 +-
   9  arch/mips/lantiq/xway/devices.c |    2 +-
  10  arch/mips/lantiq/xway/sysctrl.c |  166 ++++++++++++++++++++++++++++++---------
  11  4 files changed, 143 insertions(+), 39 deletions(-)
  12
  13 diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
  14 index 84a201e..5494b6e 100644
  15 --- a/arch/mips/lantiq/clk.c
  16 +++ b/arch/mips/lantiq/clk.c
  17 @@ -44,6 +44,7 @@ struct clk *clk_get_fpi(void)
  18  {
  19         return &cpu_clk_generic[1];
  20  }
  21 +EXPORT_SYMBOL_GPL(clk_get_fpi);
  22
  23  struct clk *clk_get_io(void)
  24  {
  25 @@ -70,6 +71,16 @@ unsigned long clk_get_rate(struct clk *clk)
  26  }
  27  EXPORT_SYMBOL(clk_get_rate);
  28
  29 +int clk_set_rate(struct clk *clk, unsigned long rate)
  30 +{
  31 +       if (unlikely(!clk_good(clk)))
  32 +               return 0;
  33 +
  34 +       clk->rate = rate;
  35 +       return 0;
  36 +}
  37 +EXPORT_SYMBOL(clk_set_rate);
  38 +
  39  int clk_enable(struct clk *clk)
  40  {
  41         if (unlikely(!clk_good(clk)))
  42 diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
  43 index d047768..b34e675 100644
  44 --- a/arch/mips/lantiq/clk.h
  45 +++ b/arch/mips/lantiq/clk.h
  46 @@ -12,6 +12,7 @@
  47  #include <linux/clkdev.h>
  48
  49  /* clock speeds */
  50 +#define CLOCK_33M      33333333
  51  #define CLOCK_60M      60000000
  52  #define CLOCK_62_5M    62500000
  53  #define CLOCK_83M      83333333
  54 @@ -38,9 +39,9 @@
  55  struct clk {
  56         struct clk_lookup cl;
  57         unsigned long rate;
  58 -       unsigned long (*get_rate) (void);
  59         unsigned int module;
  60         unsigned int bits;
  61 +       unsigned long (*get_rate) (void);
  62         int (*enable) (struct clk *clk);
  63         void (*disable) (struct clk *clk);
  64         int (*activate) (struct clk *clk);
  65 diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
  66 index e6d45bc..5d4650d 100644
  67 --- a/arch/mips/lantiq/xway/devices.c
  68 +++ b/arch/mips/lantiq/xway/devices.c
  69 @@ -59,7 +59,7 @@ static struct resource ltq_stp_resource =
  70
  71  void __init ltq_register_gpio_stp(void)
  72  {
  73 -       platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
  74 +       platform_device_register_simple("ltq_stp", -1, &ltq_stp_resource, 1);
  75  }
  76
  77  /* asc ports - amazon se has its own serial mapping */
  78 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
  79 index ac7383f..9df048c 100644
  80 --- a/arch/mips/lantiq/xway/sysctrl.c
  81 +++ b/arch/mips/lantiq/xway/sysctrl.c
  82 @@ -16,40 +16,57 @@
  83  #include "../devices.h"
  84
  85  /* clock control register */
  86 -#define LTQ_CGU_IFCCR  0x0018
  87 +#define CGU_IFCCR      0x0018
  88  /* system clock register */
  89 -#define LTQ_CGU_SYS     0x0010
  90 -
  91 -/* the enable / disable registers */
  92 -#define LTQ_PMU_PWDCR  0x1C
  93 -#define LTQ_PMU_PWDSR  0x20
  94 -#define LTQ_PMU_PWDCR1 0x24
  95 -#define LTQ_PMU_PWDSR1 0x28
  96 -
  97 -#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
  98 -#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
  99 -
 100 -/* CGU - clock generation unit */
 101 -#define CGU_EPHY               0x10
 102 +#define CGU_SYS                0x0010
 103 +/* pci control register */
 104 +#define CGU_PCICR      0x0034
 105 +/* ephy configuration register */
 106 +#define CGU_EPHY       0x10
 107 +/* power control register */
 108 +#define PMU_PWDCR      0x1C
 109 +/* power status register */
 110 +#define PMU_PWDSR      0x20
 111 +/* power control register */
 112 +#define PMU_PWDCR1     0x24
 113 +/* power status register */
 114 +#define PMU_PWDSR1     0x28
 115 +/* power control register */
 116 +#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
 117 +/* power status register */
 118 +#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
 119
 120  /* PMU - power management unit */
 121 -#define PMU_DMA                        0x0020
 122 -#define PMU_SPI                        0x0100
 123 -#define PMU_EPHY               0x0080
 124 -#define PMU_USB                        0x8041
 125 -#define PMU_STP                        0x0800
 126 -#define PMU_GPT                        0x1000
 127 -#define PMU_PPE                        0x2000
 128 -#define PMU_FPI                        0x4000
 129 -#define PMU_SWITCH             0x10000000
 130 -#define PMU_AHBS               0x2000
 131 -#define PMU_AHBM               0x8000
 132 -#define PMU_PCIE_CLK            0x80000000
 133 -
 134 -#define PMU1_PCIE_PHY          0x0001
 135 -#define PMU1_PCIE_CTL          0x0002
 136 -#define PMU1_PCIE_MSI          0x0020
 137 -#define PMU1_PCIE_PDI          0x0010
 138 +#define PMU_USB0_P     BIT(0)
 139 +#define PMU_PCI                BIT(4)
 140 +#define PMU_DMA                BIT(5)
 141 +#define PMU_USB0       BIT(5)
 142 +#define PMU_SPI                BIT(8)
 143 +#define PMU_EPHY       BIT(7)
 144 +#define PMU_EBU                BIT(10)
 145 +#define PMU_STP                BIT(11)
 146 +#define PMU_GPT                BIT(12)
 147 +#define PMU_PPE                BIT(13)
 148 +#define PMU_AHBS       BIT(13) /* vr9 */
 149 +#define PMU_FPI                BIT(14)
 150 +#define PMU_AHBM       BIT(15)
 151 +#define PMU_PPE_QSB    BIT(18)
 152 +#define PMU_PPE_SLL01  BIT(19)
 153 +#define PMU_PPE_TC     BIT(21)
 154 +#define PMU_PPE_EMA    BIT(22)
 155 +#define PMU_PPE_DPLUM  BIT(23)
 156 +#define PMU_PPE_DPLUS  BIT(24)
 157 +#define PMU_USB1_P     BIT(26)
 158 +#define PMU_USB1       BIT(27)
 159 +#define PMU_SWITCH     BIT(28)
 160 +#define PMU_PPE_TOP    BIT(29)
 161 +#define PMU_GPHY       BIT(30)
 162 +#define PMU_PCIE_CLK   BIT(31)
 163 +
 164 +#define PMU1_PCIE_PHY  BIT(0)
 165 +#define PMU1_PCIE_CTL  BIT(1)
 166 +#define PMU1_PCIE_PDI  BIT(4)
 167 +#define PMU1_PCIE_MSI  BIT(5)
 168
 169  #define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 170  #define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 171 @@ -69,13 +86,13 @@ static void __iomem *ltq_pmu_membase;
 172
 173  static int ltq_cgu_enable(struct clk *clk)
 174  {
 175 -       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
 176 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
 177         return 0;
 178  }
 179
 180  static void ltq_cgu_disable(struct clk *clk)
 181  {
 182 -       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
 183 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
 184  }
 185
 186  static int ltq_pmu_enable(struct clk *clk)
 187 @@ -94,9 +111,49 @@ static int ltq_pmu_enable(struct clk *clk)
 188
 189  static void ltq_pmu_disable(struct clk *clk)
 190  {
 191 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
 192 +       ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits,
 193 +               PWDCR(clk->module));
 194 +}
 195 +
 196 +static int ltq_pci_enable(struct clk *clk)
 197 +{
 198 +       unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
 199 +       /* set clock bus speed */
 200 +       if (ltq_is_ar9()) {
 201 +               ifccr &= ~0x1f00000;
 202 +               if (clk->rate == CLOCK_33M)
 203 +                       ifccr |= 0xe00000;
 204 +               else
 205 +                       ifccr |= 0x700000; /* 62.5M */
 206 +       } else {
 207 +               ifccr &= ~0xf00000;
 208 +               if (clk->rate == CLOCK_33M)
 209 +                       ifccr |= 0x800000;
 210 +               else
 211 +                       ifccr |= 0x400000; /* 62.5M */
 212 +       }
 213 +       ltq_cgu_w32(ifccr, CGU_IFCCR);
 214 +       return 0;
 215 +}
 216 +
 217 +static int ltq_pci_ext_enable(struct clk *clk)
 218 +{
 219 +       /* enable external pci clock */
 220 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
 221 +               CGU_IFCCR);
 222 +       ltq_cgu_w32((1 << 30), CGU_PCICR);
 223 +       return 0;
 224 +}
 225 +
 226 +static void ltq_pci_ext_disable(struct clk *clk)
 227 +{
 228 +       /* enable external pci clock */
 229 +       ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
 230 +               CGU_IFCCR);
 231 +       ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
 232  }
 233
 234 +/* manage the clock gates via PMU */
 235  static inline void clkdev_add_pmu(const char *dev, const char *con,
 236                                         unsigned int module, unsigned int bits)
 237  {
 238 @@ -112,6 +169,7 @@ static inline void clkdev_add_pmu(const char *dev, const char *con,
 239         clkdev_add(&clk->cl);
 240  }
 241
 242 +/* manage the clock generator */
 243  static inline void clkdev_add_cgu(const char *dev, const char *con,
 244                                         unsigned int bits)
 245  {
 246 @@ -126,6 +184,33 @@ static inline void clkdev_add_cgu(const char *dev, const char *con,
 247         clkdev_add(&clk->cl);
 248  }
 249
 250 +/* pci needs its own enable function */
 251 +static inline void clkdev_add_pci(void)
 252 +{
 253 +       struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 254 +       struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 255 +
 256 +       /* main pci clock */
 257 +       clk->cl.dev_id = "ltq_pci";
 258 +       clk->cl.con_id = NULL;
 259 +       clk->cl.clk = clk;
 260 +       clk->rate = CLOCK_33M;
 261 +       clk->enable = ltq_pci_enable;
 262 +       clk->disable = ltq_pmu_disable;
 263 +       clk->module = 0;
 264 +       clk->bits = PMU_PCI;
 265 +       clkdev_add(&clk->cl);
 266 +
 267 +       /* use internal/external bus clock */
 268 +       clk_ext->cl.dev_id = "ltq_pci";
 269 +       clk_ext->cl.con_id = "external";
 270 +       clk_ext->cl.clk = clk_ext;
 271 +       clk_ext->enable = ltq_pci_ext_enable;
 272 +       clk_ext->disable = ltq_pci_ext_disable;
 273 +       clkdev_add(&clk_ext->cl);
 274 +
 275 +}
 276 +
 277  void __init ltq_soc_init(void)
 278  {
 279         ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
 280 @@ -144,14 +229,16 @@ void __init ltq_soc_init(void)
 281         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 282
 283         /* add our clocks */
 284 +       clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI);
 285         clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
 286         clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
 287         clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
 288          clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
 289 +        clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
 290         if (!ltq_is_vr9())
 291                 clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
 292         if (ltq_is_ase()) {
 293 -               if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
 294 +               if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 295                         clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
 296                 else
 297                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
 298 @@ -166,11 +253,16 @@ void __init ltq_soc_init(void)
 299                 clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
 300                 clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
 301                 clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
 302 -               clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1);
 303 -               clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27));
 304 +               clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P);
 305 +               clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P);
 306 +               clkdev_add_pmu("ltq_vrx200", NULL, 0,
 307 +                       PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 308 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 309 +                       PMU_PPE_QSB);
 310         } else {
 311                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 312                                         ltq_danube_io_region_clock());
 313 +               clkdev_add_pci();
 314                 if (ltq_is_ar9())
 315                         clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
 316         }
 317 --
 318 1.7.7.1
 319