target/linux/lantiq/patches-3.2/0065-MIPS-adds-dsl-clocks.patch

   1 From a840d623b6a70428e8b698f0116fecc38e16e668 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Tue, 20 Mar 2012 13:05:11 +0100
   4 Subject: [PATCH 65/70] MIPS: adds dsl clocks
   5
   6 ---
   7  arch/mips/lantiq/xway/sysctrl.c |   15 +++++++++++++--
   8  1 files changed, 13 insertions(+), 2 deletions(-)
   9
  10 diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
  11 index 6771a7e..3672fc6 100644
  12 --- a/arch/mips/lantiq/xway/sysctrl.c
  13 +++ b/arch/mips/lantiq/xway/sysctrl.c
  14 @@ -41,8 +41,9 @@
  15  #define PMU_PCI                BIT(4)
  16  #define PMU_DMA                BIT(5)
  17  #define PMU_USB0       BIT(5)
  18 +#define PMU_EPHY       BIT(7)  /* ase */
  19  #define PMU_SPI                BIT(8)
  20 -#define PMU_EPHY       BIT(7)
  21 +#define PMU_DFE                BIT(9)
  22  #define PMU_EBU                BIT(10)
  23  #define PMU_STP                BIT(11)
  24  #define PMU_GPT                BIT(12)
  25 @@ -147,7 +148,7 @@ static int ltq_pci_ext_enable(struct clk *clk)
  26
  27  static void ltq_pci_ext_disable(struct clk *clk)
  28  {
  29 -       /* enable external pci clock */
  30 +       /* disable external pci clock (internal) */
  31         ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
  32                 CGU_IFCCR);
  33         ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
  34 @@ -246,6 +247,9 @@ void __init ltq_soc_init(void)
  35                         clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
  36                 clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY),
  37                 clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY);
  38 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  39 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  40 +                       PMU_AHBS | PMU_DFE);
  41         } else if (ltq_is_vr9()) {
  42                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
  43                         ltq_vr9_fpi_hz());
  44 @@ -261,12 +265,19 @@ void __init ltq_soc_init(void)
  45                         PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
  46                         PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  47                         PMU_PPE_QSB);
  48 +               clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS);
  49         } else if (ltq_is_ar9()) {
  50                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
  51                         ltq_ar9_fpi_hz());
  52                 clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
  53 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  54 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  55 +                       PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
  56         } else {
  57                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
  58                         ltq_danube_io_region_clock());
  59 +               clkdev_add_pmu("ltq_dsl", NULL, 0,
  60 +                       PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
  61 +                       PMU_PPE_QSB | PMU_AHBS | PMU_DFE);
  62         }
  63  }
  64 --
  65 1.7.7.1
  66