target/linux/lantiq/patches-3.2/100-falcon_bsp_header.patch

   1 --- /dev/null
   2 +++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
   3 @@ -0,0 +1,376 @@
   4 +/******************************************************************************
   5 +
   6 +                               Copyright (c) 2010
   7 +                            Lantiq Deutschland GmbH
   8 +
   9 +  For licensing information, see the file 'LICENSE' in the root folder of
  10 +  this software module.
  11 +
  12 +******************************************************************************/
  13 +
  14 +#ifndef _gpon_reg_base_h
  15 +#define _gpon_reg_base_h
  16 +
  17 +/** \addtogroup GPON_BASE
  18 +   @{
  19 +*/
  20 +
  21 +#ifndef KSEG1
  22 +#define KSEG1 0xA0000000
  23 +#endif
  24 +
  25 +/** address range for ebu
  26 +    0x18000000--0x180000FF */
  27 +#define GPON_EBU_BASE          (KSEG1 | 0x18000000)
  28 +#define GPON_EBU_END           (KSEG1 | 0x180000FF)
  29 +#define GPON_EBU_SIZE          0x00000100
  30 +/** address range for gpearb
  31 +    0x1D400100--0x1D4001FF */
  32 +#define GPON_GPEARB_BASE               (KSEG1 | 0x1D400100)
  33 +#define GPON_GPEARB_END                (KSEG1 | 0x1D4001FF)
  34 +#define GPON_GPEARB_SIZE               0x00000100
  35 +/** address range for tmu
  36 +    0x1D404000--0x1D404FFF */
  37 +#define GPON_TMU_BASE          (KSEG1 | 0x1D404000)
  38 +#define GPON_TMU_END           (KSEG1 | 0x1D404FFF)
  39 +#define GPON_TMU_SIZE          0x00001000
  40 +/** address range for iqm
  41 +    0x1D410000--0x1D41FFFF */
  42 +#define GPON_IQM_BASE          (KSEG1 | 0x1D410000)
  43 +#define GPON_IQM_END           (KSEG1 | 0x1D41FFFF)
  44 +#define GPON_IQM_SIZE          0x00010000
  45 +/** address range for octrlg
  46 +    0x1D420000--0x1D42FFFF */
  47 +#define GPON_OCTRLG_BASE               (KSEG1 | 0x1D420000)
  48 +#define GPON_OCTRLG_END                (KSEG1 | 0x1D42FFFF)
  49 +#define GPON_OCTRLG_SIZE               0x00010000
  50 +/** address range for octrll0
  51 +    0x1D440000--0x1D4400FF */
  52 +#define GPON_OCTRLL0_BASE              (KSEG1 | 0x1D440000)
  53 +#define GPON_OCTRLL0_END               (KSEG1 | 0x1D4400FF)
  54 +#define GPON_OCTRLL0_SIZE              0x00000100
  55 +/** address range for octrll1
  56 +    0x1D440100--0x1D4401FF */
  57 +#define GPON_OCTRLL1_BASE              (KSEG1 | 0x1D440100)
  58 +#define GPON_OCTRLL1_END               (KSEG1 | 0x1D4401FF)
  59 +#define GPON_OCTRLL1_SIZE              0x00000100
  60 +/** address range for octrll2
  61 +    0x1D440200--0x1D4402FF */
  62 +#define GPON_OCTRLL2_BASE              (KSEG1 | 0x1D440200)
  63 +#define GPON_OCTRLL2_END               (KSEG1 | 0x1D4402FF)
  64 +#define GPON_OCTRLL2_SIZE              0x00000100
  65 +/** address range for octrll3
  66 +    0x1D440300--0x1D4403FF */
  67 +#define GPON_OCTRLL3_BASE              (KSEG1 | 0x1D440300)
  68 +#define GPON_OCTRLL3_END               (KSEG1 | 0x1D4403FF)
  69 +#define GPON_OCTRLL3_SIZE              0x00000100
  70 +/** address range for octrlc
  71 +    0x1D441000--0x1D4410FF */
  72 +#define GPON_OCTRLC_BASE               (KSEG1 | 0x1D441000)
  73 +#define GPON_OCTRLC_END                (KSEG1 | 0x1D4410FF)
  74 +#define GPON_OCTRLC_SIZE               0x00000100
  75 +/** address range for ictrlg
  76 +    0x1D450000--0x1D45FFFF */
  77 +#define GPON_ICTRLG_BASE               (KSEG1 | 0x1D450000)
  78 +#define GPON_ICTRLG_END                (KSEG1 | 0x1D45FFFF)
  79 +#define GPON_ICTRLG_SIZE               0x00010000
  80 +/** address range for ictrll0
  81 +    0x1D460000--0x1D4601FF */
  82 +#define GPON_ICTRLL0_BASE              (KSEG1 | 0x1D460000)
  83 +#define GPON_ICTRLL0_END               (KSEG1 | 0x1D4601FF)
  84 +#define GPON_ICTRLL0_SIZE              0x00000200
  85 +/** address range for ictrll1
  86 +    0x1D460200--0x1D4603FF */
  87 +#define GPON_ICTRLL1_BASE              (KSEG1 | 0x1D460200)
  88 +#define GPON_ICTRLL1_END               (KSEG1 | 0x1D4603FF)
  89 +#define GPON_ICTRLL1_SIZE              0x00000200
  90 +/** address range for ictrll2
  91 +    0x1D460400--0x1D4605FF */
  92 +#define GPON_ICTRLL2_BASE              (KSEG1 | 0x1D460400)
  93 +#define GPON_ICTRLL2_END               (KSEG1 | 0x1D4605FF)
  94 +#define GPON_ICTRLL2_SIZE              0x00000200
  95 +/** address range for ictrll3
  96 +    0x1D460600--0x1D4607FF */
  97 +#define GPON_ICTRLL3_BASE              (KSEG1 | 0x1D460600)
  98 +#define GPON_ICTRLL3_END               (KSEG1 | 0x1D4607FF)
  99 +#define GPON_ICTRLL3_SIZE              0x00000200
 100 +/** address range for ictrlc0
 101 +    0x1D461000--0x1D4610FF */
 102 +#define GPON_ICTRLC0_BASE              (KSEG1 | 0x1D461000)
 103 +#define GPON_ICTRLC0_END               (KSEG1 | 0x1D4610FF)
 104 +#define GPON_ICTRLC0_SIZE              0x00000100
 105 +/** address range for ictrlc1
 106 +    0x1D461100--0x1D4611FF */
 107 +#define GPON_ICTRLC1_BASE              (KSEG1 | 0x1D461100)
 108 +#define GPON_ICTRLC1_END               (KSEG1 | 0x1D4611FF)
 109 +#define GPON_ICTRLC1_SIZE              0x00000100
 110 +/** address range for fsqm
 111 +    0x1D500000--0x1D5FFFFF */
 112 +#define GPON_FSQM_BASE         (KSEG1 | 0x1D500000)
 113 +#define GPON_FSQM_END          (KSEG1 | 0x1D5FFFFF)
 114 +#define GPON_FSQM_SIZE         0x00100000
 115 +/** address range for pctrl
 116 +    0x1D600000--0x1D6001FF */
 117 +#define GPON_PCTRL_BASE                (KSEG1 | 0x1D600000)
 118 +#define GPON_PCTRL_END         (KSEG1 | 0x1D6001FF)
 119 +#define GPON_PCTRL_SIZE                0x00000200
 120 +/** address range for link0
 121 +    0x1D600200--0x1D6002FF */
 122 +#define GPON_LINK0_BASE                (KSEG1 | 0x1D600200)
 123 +#define GPON_LINK0_END         (KSEG1 | 0x1D6002FF)
 124 +#define GPON_LINK0_SIZE                0x00000100
 125 +/** address range for link1
 126 +    0x1D600300--0x1D6003FF */
 127 +#define GPON_LINK1_BASE                (KSEG1 | 0x1D600300)
 128 +#define GPON_LINK1_END         (KSEG1 | 0x1D6003FF)
 129 +#define GPON_LINK1_SIZE                0x00000100
 130 +/** address range for link2
 131 +    0x1D600400--0x1D6004FF */
 132 +#define GPON_LINK2_BASE                (KSEG1 | 0x1D600400)
 133 +#define GPON_LINK2_END         (KSEG1 | 0x1D6004FF)
 134 +#define GPON_LINK2_SIZE                0x00000100
 135 +/** address range for disp
 136 +    0x1D600500--0x1D6005FF */
 137 +#define GPON_DISP_BASE         (KSEG1 | 0x1D600500)
 138 +#define GPON_DISP_END          (KSEG1 | 0x1D6005FF)
 139 +#define GPON_DISP_SIZE         0x00000100
 140 +/** address range for merge
 141 +    0x1D600600--0x1D6006FF */
 142 +#define GPON_MERGE_BASE                (KSEG1 | 0x1D600600)
 143 +#define GPON_MERGE_END         (KSEG1 | 0x1D6006FF)
 144 +#define GPON_MERGE_SIZE                0x00000100
 145 +/** address range for tbm
 146 +    0x1D600700--0x1D6007FF */
 147 +#define GPON_TBM_BASE          (KSEG1 | 0x1D600700)
 148 +#define GPON_TBM_END           (KSEG1 | 0x1D6007FF)
 149 +#define GPON_TBM_SIZE          0x00000100
 150 +/** address range for pe0
 151 +    0x1D610000--0x1D61FFFF */
 152 +#define GPON_PE0_BASE          (KSEG1 | 0x1D610000)
 153 +#define GPON_PE0_END           (KSEG1 | 0x1D61FFFF)
 154 +#define GPON_PE0_SIZE          0x00010000
 155 +/** address range for pe1
 156 +    0x1D620000--0x1D62FFFF */
 157 +#define GPON_PE1_BASE          (KSEG1 | 0x1D620000)
 158 +#define GPON_PE1_END           (KSEG1 | 0x1D62FFFF)
 159 +#define GPON_PE1_SIZE          0x00010000
 160 +/** address range for pe2
 161 +    0x1D630000--0x1D63FFFF */
 162 +#define GPON_PE2_BASE          (KSEG1 | 0x1D630000)
 163 +#define GPON_PE2_END           (KSEG1 | 0x1D63FFFF)
 164 +#define GPON_PE2_SIZE          0x00010000
 165 +/** address range for pe3
 166 +    0x1D640000--0x1D64FFFF */
 167 +#define GPON_PE3_BASE          (KSEG1 | 0x1D640000)
 168 +#define GPON_PE3_END           (KSEG1 | 0x1D64FFFF)
 169 +#define GPON_PE3_SIZE          0x00010000
 170 +/** address range for pe4
 171 +    0x1D650000--0x1D65FFFF */
 172 +#define GPON_PE4_BASE          (KSEG1 | 0x1D650000)
 173 +#define GPON_PE4_END           (KSEG1 | 0x1D65FFFF)
 174 +#define GPON_PE4_SIZE          0x00010000
 175 +/** address range for pe5
 176 +    0x1D660000--0x1D66FFFF */
 177 +#define GPON_PE5_BASE          (KSEG1 | 0x1D660000)
 178 +#define GPON_PE5_END           (KSEG1 | 0x1D66FFFF)
 179 +#define GPON_PE5_SIZE          0x00010000
 180 +/** address range for sys_gpe
 181 +    0x1D700000--0x1D7000FF */
 182 +#define GPON_SYS_GPE_BASE              (KSEG1 | 0x1D700000)
 183 +#define GPON_SYS_GPE_END               (KSEG1 | 0x1D7000FF)
 184 +#define GPON_SYS_GPE_SIZE              0x00000100
 185 +/** address range for eim
 186 +    0x1D800000--0x1D800FFF */
 187 +#define GPON_EIM_BASE          (KSEG1 | 0x1D800000)
 188 +#define GPON_EIM_END           (KSEG1 | 0x1D800FFF)
 189 +#define GPON_EIM_SIZE          0x00001000
 190 +/** address range for sxgmii
 191 +    0x1D808800--0x1D8088FF */
 192 +#define GPON_SXGMII_BASE               (KSEG1 | 0x1D808800)
 193 +#define GPON_SXGMII_END                (KSEG1 | 0x1D8088FF)
 194 +#define GPON_SXGMII_SIZE               0x00000100
 195 +/** address range for sgmii
 196 +    0x1D808C00--0x1D808CFF */
 197 +#define GPON_SGMII_BASE                (KSEG1 | 0x1D808C00)
 198 +#define GPON_SGMII_END         (KSEG1 | 0x1D808CFF)
 199 +#define GPON_SGMII_SIZE                0x00000100
 200 +/** address range for gpio0
 201 +    0x1D810000--0x1D81007F */
 202 +#define GPON_GPIO0_BASE                (KSEG1 | 0x1D810000)
 203 +#define GPON_GPIO0_END         (KSEG1 | 0x1D81007F)
 204 +#define GPON_GPIO0_SIZE                0x00000080
 205 +/** address range for gpio2
 206 +    0x1D810100--0x1D81017F */
 207 +#define GPON_GPIO2_BASE                (KSEG1 | 0x1D810100)
 208 +#define GPON_GPIO2_END         (KSEG1 | 0x1D81017F)
 209 +#define GPON_GPIO2_SIZE                0x00000080
 210 +/** address range for sys_eth
 211 +    0x1DB00000--0x1DB000FF */
 212 +#define GPON_SYS_ETH_BASE              (KSEG1 | 0x1DB00000)
 213 +#define GPON_SYS_ETH_END               (KSEG1 | 0x1DB000FF)
 214 +#define GPON_SYS_ETH_SIZE              0x00000100
 215 +/** address range for padctrl0
 216 +    0x1DB01000--0x1DB010FF */
 217 +#define GPON_PADCTRL0_BASE             (KSEG1 | 0x1DB01000)
 218 +#define GPON_PADCTRL0_END              (KSEG1 | 0x1DB010FF)
 219 +#define GPON_PADCTRL0_SIZE             0x00000100
 220 +/** address range for padctrl2
 221 +    0x1DB02000--0x1DB020FF */
 222 +#define GPON_PADCTRL2_BASE             (KSEG1 | 0x1DB02000)
 223 +#define GPON_PADCTRL2_END              (KSEG1 | 0x1DB020FF)
 224 +#define GPON_PADCTRL2_SIZE             0x00000100
 225 +/** address range for gtc
 226 +    0x1DC05000--0x1DC052D4 */
 227 +#define GPON_GTC_BASE          (KSEG1 | 0x1DC05000)
 228 +#define GPON_GTC_END           (KSEG1 | 0x1DC052D4)
 229 +#define GPON_GTC_SIZE          0x000002D5
 230 +/** address range for pma
 231 +    0x1DD00000--0x1DD003FF */
 232 +#define GPON_PMA_BASE          (KSEG1 | 0x1DD00000)
 233 +#define GPON_PMA_END           (KSEG1 | 0x1DD003FF)
 234 +#define GPON_PMA_SIZE          0x00000400
 235 +/** address range for fcsic
 236 +    0x1DD00600--0x1DD0061F */
 237 +#define GPON_FCSIC_BASE                (KSEG1 | 0x1DD00600)
 238 +#define GPON_FCSIC_END         (KSEG1 | 0x1DD0061F)
 239 +#define GPON_FCSIC_SIZE                0x00000020
 240 +/** address range for pma_int200
 241 +    0x1DD00700--0x1DD0070F */
 242 +#define GPON_PMA_INT200_BASE           (KSEG1 | 0x1DD00700)
 243 +#define GPON_PMA_INT200_END            (KSEG1 | 0x1DD0070F)
 244 +#define GPON_PMA_INT200_SIZE           0x00000010
 245 +/** address range for pma_inttx
 246 +    0x1DD00720--0x1DD0072F */
 247 +#define GPON_PMA_INTTX_BASE            (KSEG1 | 0x1DD00720)
 248 +#define GPON_PMA_INTTX_END             (KSEG1 | 0x1DD0072F)
 249 +#define GPON_PMA_INTTX_SIZE            0x00000010
 250 +/** address range for pma_intrx
 251 +    0x1DD00740--0x1DD0074F */
 252 +#define GPON_PMA_INTRX_BASE            (KSEG1 | 0x1DD00740)
 253 +#define GPON_PMA_INTRX_END             (KSEG1 | 0x1DD0074F)
 254 +#define GPON_PMA_INTRX_SIZE            0x00000010
 255 +/** address range for gtc_pma
 256 +    0x1DEFFF00--0x1DEFFFFF */
 257 +#define GPON_GTC_PMA_BASE              (KSEG1 | 0x1DEFFF00)
 258 +#define GPON_GTC_PMA_END               (KSEG1 | 0x1DEFFFFF)
 259 +#define GPON_GTC_PMA_SIZE              0x00000100
 260 +/** address range for sys
 261 +    0x1DF00000--0x1DF000FF */
 262 +#define GPON_SYS_BASE          (KSEG1 | 0x1DF00000)
 263 +#define GPON_SYS_END           (KSEG1 | 0x1DF000FF)
 264 +#define GPON_SYS_SIZE          0x00000100
 265 +/** address range for asc1
 266 +    0x1E100B00--0x1E100BFF */
 267 +#define GPON_ASC1_BASE         (KSEG1 | 0x1E100B00)
 268 +#define GPON_ASC1_END          (KSEG1 | 0x1E100BFF)
 269 +#define GPON_ASC1_SIZE         0x00000100
 270 +/** address range for asc0
 271 +    0x1E100C00--0x1E100CFF */
 272 +#define GPON_ASC0_BASE         (KSEG1 | 0x1E100C00)
 273 +#define GPON_ASC0_END          (KSEG1 | 0x1E100CFF)
 274 +#define GPON_ASC0_SIZE         0x00000100
 275 +/** address range for i2c
 276 +    0x1E200000--0x1E20FFFF */
 277 +#define GPON_I2C_BASE          (KSEG1 | 0x1E200000)
 278 +#define GPON_I2C_END           (KSEG1 | 0x1E20FFFF)
 279 +#define GPON_I2C_SIZE          0x00010000
 280 +/** address range for gpio1
 281 +    0x1E800100--0x1E80017F */
 282 +#define GPON_GPIO1_BASE                (KSEG1 | 0x1E800100)
 283 +#define GPON_GPIO1_END         (KSEG1 | 0x1E80017F)
 284 +#define GPON_GPIO1_SIZE                0x00000080
 285 +/** address range for gpio3
 286 +    0x1E800200--0x1E80027F */
 287 +#define GPON_GPIO3_BASE                (KSEG1 | 0x1E800200)
 288 +#define GPON_GPIO3_END         (KSEG1 | 0x1E80027F)
 289 +#define GPON_GPIO3_SIZE                0x00000080
 290 +/** address range for gpio4
 291 +    0x1E800300--0x1E80037F */
 292 +#define GPON_GPIO4_BASE                (KSEG1 | 0x1E800300)
 293 +#define GPON_GPIO4_END         (KSEG1 | 0x1E80037F)
 294 +#define GPON_GPIO4_SIZE                0x00000080
 295 +/** address range for padctrl1
 296 +    0x1E800400--0x1E8004FF */
 297 +#define GPON_PADCTRL1_BASE             (KSEG1 | 0x1E800400)
 298 +#define GPON_PADCTRL1_END              (KSEG1 | 0x1E8004FF)
 299 +#define GPON_PADCTRL1_SIZE             0x00000100
 300 +/** address range for padctrl3
 301 +    0x1E800500--0x1E8005FF */
 302 +#define GPON_PADCTRL3_BASE             (KSEG1 | 0x1E800500)
 303 +#define GPON_PADCTRL3_END              (KSEG1 | 0x1E8005FF)
 304 +#define GPON_PADCTRL3_SIZE             0x00000100
 305 +/** address range for padctrl4
 306 +    0x1E800600--0x1E8006FF */
 307 +#define GPON_PADCTRL4_BASE             (KSEG1 | 0x1E800600)
 308 +#define GPON_PADCTRL4_END              (KSEG1 | 0x1E8006FF)
 309 +#define GPON_PADCTRL4_SIZE             0x00000100
 310 +/** address range for status
 311 +    0x1E802000--0x1E80207F */
 312 +#define GPON_STATUS_BASE               (KSEG1 | 0x1E802000)
 313 +#define GPON_STATUS_END                (KSEG1 | 0x1E80207F)
 314 +#define GPON_STATUS_SIZE               0x00000080
 315 +/** address range for dcdc_1v0
 316 +    0x1E803000--0x1E8033FF */
 317 +#define GPON_DCDC_1V0_BASE             (KSEG1 | 0x1E803000)
 318 +#define GPON_DCDC_1V0_END              (KSEG1 | 0x1E8033FF)
 319 +#define GPON_DCDC_1V0_SIZE             0x00000400
 320 +/** address range for dcdc_ddr
 321 +    0x1E804000--0x1E8043FF */
 322 +#define GPON_DCDC_DDR_BASE             (KSEG1 | 0x1E804000)
 323 +#define GPON_DCDC_DDR_END              (KSEG1 | 0x1E8043FF)
 324 +#define GPON_DCDC_DDR_SIZE             0x00000400
 325 +/** address range for dcdc_apd
 326 +    0x1E805000--0x1E8053FF */
 327 +#define GPON_DCDC_APD_BASE             (KSEG1 | 0x1E805000)
 328 +#define GPON_DCDC_APD_END              (KSEG1 | 0x1E8053FF)
 329 +#define GPON_DCDC_APD_SIZE             0x00000400
 330 +/** address range for sys1
 331 +    0x1EF00000--0x1EF000FF */
 332 +#define GPON_SYS1_BASE         (KSEG1 | 0x1EF00000)
 333 +#define GPON_SYS1_END          (KSEG1 | 0x1EF000FF)
 334 +#define GPON_SYS1_SIZE         0x00000100
 335 +/** address range for sbs0ctrl
 336 +    0x1F080000--0x1F0801FF */
 337 +#define GPON_SBS0CTRL_BASE             (KSEG1 | 0x1F080000)
 338 +#define GPON_SBS0CTRL_END              (KSEG1 | 0x1F0801FF)
 339 +#define GPON_SBS0CTRL_SIZE             0x00000200
 340 +/** address range for sbs0red
 341 +    0x1F080200--0x1F08027F */
 342 +#define GPON_SBS0RED_BASE              (KSEG1 | 0x1F080200)
 343 +#define GPON_SBS0RED_END               (KSEG1 | 0x1F08027F)
 344 +#define GPON_SBS0RED_SIZE              0x00000080
 345 +/** address range for sbs0ram
 346 +    0x1F200000--0x1F32FFFF */
 347 +#define GPON_SBS0RAM_BASE              (KSEG1 | 0x1F200000)
 348 +#define GPON_SBS0RAM_END               (KSEG1 | 0x1F32FFFF)
 349 +#define GPON_SBS0RAM_SIZE              0x00130000
 350 +/** address range for ddrdb
 351 +    0x1F701000--0x1F701FFF */
 352 +#define GPON_DDRDB_BASE                (KSEG1 | 0x1F701000)
 353 +#define GPON_DDRDB_END         (KSEG1 | 0x1F701FFF)
 354 +#define GPON_DDRDB_SIZE                0x00001000
 355 +/** address range for sbiu
 356 +    0x1F880000--0x1F8800FF */
 357 +#define GPON_SBIU_BASE         (KSEG1 | 0x1F880000)
 358 +#define GPON_SBIU_END          (KSEG1 | 0x1F8800FF)
 359 +#define GPON_SBIU_SIZE         0x00000100
 360 +/** address range for icu0
 361 +    0x1F880200--0x1F8802DF */
 362 +#define GPON_ICU0_BASE         (KSEG1 | 0x1F880200)
 363 +#define GPON_ICU0_END          (KSEG1 | 0x1F8802DF)
 364 +#define GPON_ICU0_SIZE         0x000000E0
 365 +/** address range for icu1
 366 +    0x1F880300--0x1F8803DF */
 367 +#define GPON_ICU1_BASE         (KSEG1 | 0x1F880300)
 368 +#define GPON_ICU1_END          (KSEG1 | 0x1F8803DF)
 369 +#define GPON_ICU1_SIZE         0x000000E0
 370 +/** address range for wdt
 371 +    0x1F8803F0--0x1F8803FF */
 372 +#define GPON_WDT_BASE          (KSEG1 | 0x1F8803F0)
 373 +#define GPON_WDT_END           (KSEG1 | 0x1F8803FF)
 374 +#define GPON_WDT_SIZE          0x00000010
 375 +
 376 +/*! @} */ /* GPON_BASE */
 377 +
 378 +#endif /* _gpon_reg_base_h */
 379 +
 380 --- /dev/null
 381 +++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h
 382 @@ -0,0 +1,830 @@
 383 +/******************************************************************************
 384 +
 385 +                               Copyright (c) 2010
 386 +                            Lantiq Deutschland GmbH
 387 +
 388 +  For licensing information, see the file 'LICENSE' in the root folder of
 389 +  this software module.
 390 +
 391 +******************************************************************************/
 392 +
 393 +#ifndef _i2c_reg_h
 394 +#define _i2c_reg_h
 395 +
 396 +/** \addtogroup I2C_REGISTER
 397 +   @{
 398 +*/
 399 +/* access macros */
 400 +#define i2c_r32(reg) reg_r32(&i2c->reg)
 401 +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
 402 +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
 403 +#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx)
 404 +#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx)
 405 +#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx)
 406 +#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx)
 407 +
 408 +
 409 +/** I2C register structure */
 410 +struct gpon_reg_i2c
 411 +{
 412 +   /** I2C Kernel Clock Control Register */
 413 +   unsigned int clc; /* 0x00000000 */
 414 +   /** Reserved */
 415 +   unsigned int res_0; /* 0x00000004 */
 416 +   /** I2C Identification Register */
 417 +   unsigned int id; /* 0x00000008 */
 418 +   /** Reserved */
 419 +   unsigned int res_1; /* 0x0000000C */
 420 +   /** I2C RUN Control Register
 421 +       This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */
 422 +   unsigned int run_ctrl; /* 0x00000010 */
 423 +   /** I2C End Data Control Register
 424 +       This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */
 425 +   unsigned int endd_ctrl; /* 0x00000014 */
 426 +   /** I2C Fractional Divider Configuration Register
 427 +       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */
 428 +   unsigned int fdiv_cfg; /* 0x00000018 */
 429 +   /** I2C Fractional Divider (highspeed mode) Configuration Register
 430 +       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */
 431 +   unsigned int fdiv_high_cfg; /* 0x0000001C */
 432 +   /** I2C Address Configuration Register */
 433 +   unsigned int addr_cfg; /* 0x00000020 */
 434 +   /** I2C Bus Status Register
 435 +       This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */
 436 +   unsigned int bus_stat; /* 0x00000024 */
 437 +   /** I2C FIFO Configuration Register */
 438 +   unsigned int fifo_cfg; /* 0x00000028 */
 439 +   /** I2C Maximum Received Packet Size Register */
 440 +   unsigned int mrps_ctrl; /* 0x0000002C */
 441 +   /** I2C Received Packet Size Status Register */
 442 +   unsigned int rps_stat; /* 0x00000030 */
 443 +   /** I2C Transmit Packet Size Register */
 444 +   unsigned int tps_ctrl; /* 0x00000034 */
 445 +   /** I2C Filled FIFO Stages Status Register */
 446 +   unsigned int ffs_stat; /* 0x00000038 */
 447 +   /** Reserved */
 448 +   unsigned int res_2; /* 0x0000003C */
 449 +   /** I2C Timing Configuration Register */
 450 +   unsigned int tim_cfg; /* 0x00000040 */
 451 +   /** Reserved */
 452 +   unsigned int res_3[7]; /* 0x00000044 */
 453 +   /** I2C Error Interrupt Request Source Mask Register */
 454 +   unsigned int err_irqsm; /* 0x00000060 */
 455 +   /** I2C Error Interrupt Request Source Status Register */
 456 +   unsigned int err_irqss; /* 0x00000064 */
 457 +   /** I2C Error Interrupt Request Source Clear Register */
 458 +   unsigned int err_irqsc; /* 0x00000068 */
 459 +   /** Reserved */
 460 +   unsigned int res_4; /* 0x0000006C */
 461 +   /** I2C Protocol Interrupt Request Source Mask Register */
 462 +   unsigned int p_irqsm; /* 0x00000070 */
 463 +   /** I2C Protocol Interrupt Request Source Status Register */
 464 +   unsigned int p_irqss; /* 0x00000074 */
 465 +   /** I2C Protocol Interrupt Request Source Clear Register */
 466 +   unsigned int p_irqsc; /* 0x00000078 */
 467 +   /** Reserved */
 468 +   unsigned int res_5; /* 0x0000007C */
 469 +   /** I2C Raw Interrupt Status Register */
 470 +   unsigned int ris; /* 0x00000080 */
 471 +   /** I2C Interrupt Mask Control Register */
 472 +   unsigned int imsc; /* 0x00000084 */
 473 +   /** I2C Masked Interrupt Status Register */
 474 +   unsigned int mis; /* 0x00000088 */
 475 +   /** I2C Interrupt Clear Register */
 476 +   unsigned int icr; /* 0x0000008C */
 477 +   /** I2C Interrupt Set Register */
 478 +   unsigned int isr; /* 0x00000090 */
 479 +   /** I2C DMA Enable Register */
 480 +   unsigned int dmae; /* 0x00000094 */
 481 +   /** Reserved */
 482 +   unsigned int res_6[8154]; /* 0x00000098 */
 483 +   /** I2C Transmit Data Register */
 484 +   unsigned int txd; /* 0x00008000 */
 485 +   /** Reserved */
 486 +   unsigned int res_7[4095]; /* 0x00008004 */
 487 +   /** I2C Receive Data Register */
 488 +   unsigned int rxd; /* 0x0000C000 */
 489 +   /** Reserved */
 490 +   unsigned int res_8[4095]; /* 0x0000C004 */
 491 +};
 492 +
 493 +
 494 +/* Fields of "I2C Kernel Clock Control Register" */
 495 +/** Clock Divider for Optional Run Mode (AHB peripherals)
 496 +    Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */
 497 +#define I2C_CLC_ORMC_MASK 0x00FF0000
 498 +/** field offset */
 499 +#define I2C_CLC_ORMC_OFFSET 16
 500 +/** Clock Divider for Normal Run Mode
 501 +    Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */
 502 +#define I2C_CLC_RMC_MASK 0x0000FF00
 503 +/** field offset */
 504 +#define I2C_CLC_RMC_OFFSET 8
 505 +/** Fast Shut-Off Enable Bit */
 506 +#define I2C_CLC_FSOE 0x00000020
 507 +/* Disable
 508 +#define I2C_CLC_FSOE_DIS 0x00000000 */
 509 +/** Enable */
 510 +#define I2C_CLC_FSOE_EN 0x00000020
 511 +/** Suspend Bit Write Enable for OCDS */
 512 +#define I2C_CLC_SBWE 0x00000010
 513 +/* Disable
 514 +#define I2C_CLC_SBWE_DIS 0x00000000 */
 515 +/** Enable */
 516 +#define I2C_CLC_SBWE_EN 0x00000010
 517 +/** Disable External Request Disable */
 518 +#define I2C_CLC_EDIS 0x00000008
 519 +/* Enable
 520 +#define I2C_CLC_EDIS_EN 0x00000000 */
 521 +/** Disable */
 522 +#define I2C_CLC_EDIS_DIS 0x00000008
 523 +/** Suspend Enable Bit for OCDS */
 524 +#define I2C_CLC_SPEN 0x00000004
 525 +/* Disable
 526 +#define I2C_CLC_SPEN_DIS 0x00000000 */
 527 +/** Enable */
 528 +#define I2C_CLC_SPEN_EN 0x00000004
 529 +/** Disable Status Bit
 530 +    Bit DISS can be modified only by writing to bit DISR */
 531 +#define I2C_CLC_DISS 0x00000002
 532 +/* Enable
 533 +#define I2C_CLC_DISS_EN 0x00000000 */
 534 +/** Disable */
 535 +#define I2C_CLC_DISS_DIS 0x00000002
 536 +/** Disable Request Bit */
 537 +#define I2C_CLC_DISR 0x00000001
 538 +/* Module disable not requested
 539 +#define I2C_CLC_DISR_OFF 0x00000000 */
 540 +/** Module disable requested */
 541 +#define I2C_CLC_DISR_ON 0x00000001
 542 +
 543 +/* Fields of "I2C Identification Register" */
 544 +/** Module ID */
 545 +#define I2C_ID_ID_MASK 0x0000FF00
 546 +/** field offset */
 547 +#define I2C_ID_ID_OFFSET 8
 548 +/** Revision */
 549 +#define I2C_ID_REV_MASK 0x000000FF
 550 +/** field offset */
 551 +#define I2C_ID_REV_OFFSET 0
 552 +
 553 +/* Fields of "I2C RUN Control Register" */
 554 +/** Enabling I2C Interface
 555 +    Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */
 556 +#define I2C_RUN_CTRL_RUN 0x00000001
 557 +/* Disable
 558 +#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */
 559 +/** Enable */
 560 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
 561 +
 562 +/* Fields of "I2C End Data Control Register" */
 563 +/** Set End of Transmission
 564 +    Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */
 565 +#define I2C_ENDD_CTRL_SETEND 0x00000002
 566 +/* No-Operation
 567 +#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */
 568 +/** Master Receives Bytes */
 569 +#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002
 570 +/** Set Restart Condition */
 571 +#define I2C_ENDD_CTRL_SETRSC 0x00000001
 572 +/* No-Operation
 573 +#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */
 574 +/** Master Restart */
 575 +#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001
 576 +
 577 +/* Fields of "I2C Fractional Divider Configuration Register" */
 578 +/** Decrement Value of fractional divider */
 579 +#define I2C_FDIV_CFG_INC_MASK 0x00FF0000
 580 +/** field offset */
 581 +#define I2C_FDIV_CFG_INC_OFFSET 16
 582 +/** Increment Value of fractional divider */
 583 +#define I2C_FDIV_CFG_DEC_MASK 0x000007FF
 584 +/** field offset */
 585 +#define I2C_FDIV_CFG_DEC_OFFSET 0
 586 +
 587 +/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */
 588 +/** Decrement Value of fractional divider */
 589 +#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000
 590 +/** field offset */
 591 +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
 592 +/** Increment Value of fractional divider */
 593 +#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF
 594 +/** field offset */
 595 +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
 596 +
 597 +/* Fields of "I2C Address Configuration Register" */
 598 +/** Stop on Packet End
 599 +    If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */
 600 +#define I2C_ADDR_CFG_SOPE 0x00200000
 601 +/* Disable
 602 +#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */
 603 +/** Enable */
 604 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
 605 +/** Stop on Not Acknowledge
 606 +    After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */
 607 +#define I2C_ADDR_CFG_SONA 0x00100000
 608 +/* Disable
 609 +#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */
 610 +/** Enable */
 611 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
 612 +/** Master Enable */
 613 +#define I2C_ADDR_CFG_MnS 0x00080000
 614 +/* Disable
 615 +#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */
 616 +/** Enable */
 617 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
 618 +/** Master Code Enable */
 619 +#define I2C_ADDR_CFG_MCE 0x00040000
 620 +/* Disable
 621 +#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */
 622 +/** Enable */
 623 +#define I2C_ADDR_CFG_MCE_EN 0x00040000
 624 +/** General Call Enable */
 625 +#define I2C_ADDR_CFG_GCE 0x00020000
 626 +/* Disable
 627 +#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */
 628 +/** Enable */
 629 +#define I2C_ADDR_CFG_GCE_EN 0x00020000
 630 +/** Ten Bit Address Mode */
 631 +#define I2C_ADDR_CFG_TBAM 0x00010000
 632 +/* 7-bit address mode enabled.
 633 +#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */
 634 +/** 10-bit address mode enabled. */
 635 +#define I2C_ADDR_CFG_TBAM_10bit 0x00010000
 636 +/** I2C Bus device address
 637 +    This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */
 638 +#define I2C_ADDR_CFG_ADR_MASK 0x000003FF
 639 +/** field offset */
 640 +#define I2C_ADDR_CFG_ADR_OFFSET 0
 641 +
 642 +/* Fields of "I2C Bus Status Register" */
 643 +/** Read / not Write */
 644 +#define I2C_BUS_STAT_RNW 0x00000004
 645 +/* Write to I2C Bus.
 646 +#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */
 647 +/** Read from I2C Bus. */
 648 +#define I2C_BUS_STAT_RNW_READ 0x00000004
 649 +/** Bus Status */
 650 +#define I2C_BUS_STAT_BS_MASK 0x00000003
 651 +/** field offset */
 652 +#define I2C_BUS_STAT_BS_OFFSET 0
 653 +/** I2C Bus is free. */
 654 +#define I2C_BUS_STAT_BS_FREE 0x00000000
 655 +/** A start condition has been detected on the bus (bus busy). */
 656 +#define I2C_BUS_STAT_BS_SC 0x00000001
 657 +/** The device is working as master and has claimed the control on the I2C-bus (busy master). */
 658 +#define I2C_BUS_STAT_BS_BM 0x00000002
 659 +/** A remote master has accessed this device as slave. */
 660 +#define I2C_BUS_STAT_BS_RM 0x00000003
 661 +
 662 +/* Fields of "I2C FIFO Configuration Register" */
 663 +/** TX FIFO Flow Control */
 664 +#define I2C_FIFO_CFG_TXFC 0x00020000
 665 +/* TX FIFO not as Flow Controller
 666 +#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */
 667 +/** RX FIFO Flow Control */
 668 +#define I2C_FIFO_CFG_RXFC 0x00010000
 669 +/* RX FIFO not as Flow Controller
 670 +#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */
 671 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
 672 +#define I2C_FIFO_CFG_TXFA_MASK 0x00003000
 673 +/** field offset */
 674 +#define I2C_FIFO_CFG_TXFA_OFFSET 12
 675 +/** Byte aligned (character alignment) */
 676 +#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000
 677 +/** Half word aligned (character alignment of two characters) */
 678 +#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000
 679 +/** Word aligned (character alignment of four characters) */
 680 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
 681 +/** Double word aligned (character alignment of eight */
 682 +#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000
 683 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
 684 +#define I2C_FIFO_CFG_RXFA_MASK 0x00000300
 685 +/** field offset */
 686 +#define I2C_FIFO_CFG_RXFA_OFFSET 8
 687 +/** Byte aligned (character alignment) */
 688 +#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000
 689 +/** Half word aligned (character alignment of two characters) */
 690 +#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100
 691 +/** Word aligned (character alignment of four characters) */
 692 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
 693 +/** Double word aligned (character alignment of eight */
 694 +#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300
 695 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
 696 +#define I2C_FIFO_CFG_TXBS_MASK 0x00000030
 697 +/** field offset */
 698 +#define I2C_FIFO_CFG_TXBS_OFFSET 4
 699 +/** 1 word */
 700 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
 701 +/** 2 words */
 702 +#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010
 703 +/** 4 words */
 704 +#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020
 705 +/** 8 words */
 706 +#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030
 707 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
 708 +#define I2C_FIFO_CFG_RXBS_MASK 0x00000003
 709 +/** field offset */
 710 +#define I2C_FIFO_CFG_RXBS_OFFSET 0
 711 +/** 1 word */
 712 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
 713 +/** 2 words */
 714 +#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001
 715 +/** 4 words */
 716 +#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002
 717 +/** 8 words */
 718 +#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003
 719 +
 720 +/* Fields of "I2C Maximum Received Packet Size Register" */
 721 +/** MRPS */
 722 +#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF
 723 +/** field offset */
 724 +#define I2C_MRPS_CTRL_MRPS_OFFSET 0
 725 +
 726 +/* Fields of "I2C Received Packet Size Status Register" */
 727 +/** RPS */
 728 +#define I2C_RPS_STAT_RPS_MASK 0x00003FFF
 729 +/** field offset */
 730 +#define I2C_RPS_STAT_RPS_OFFSET 0
 731 +
 732 +/* Fields of "I2C Transmit Packet Size Register" */
 733 +/** TPS */
 734 +#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF
 735 +/** field offset */
 736 +#define I2C_TPS_CTRL_TPS_OFFSET 0
 737 +
 738 +/* Fields of "I2C Filled FIFO Stages Status Register" */
 739 +/** FFS */
 740 +#define I2C_FFS_STAT_FFS_MASK 0x0000000F
 741 +/** field offset */
 742 +#define I2C_FFS_STAT_FFS_OFFSET 0
 743 +
 744 +/* Fields of "I2C Timing Configuration Register" */
 745 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
 746 +    The actual delay is calculated as the value of this field + 3 */
 747 +#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000
 748 +/** field offset */
 749 +#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16
 750 +/** Enable Fast Mode SCL Low period timing */
 751 +#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000
 752 +/* Disable
 753 +#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */
 754 +/** Enable */
 755 +#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000
 756 +/** SCL Delay Stages for Hold Time Start (Restart) Bit.
 757 +    The actual delay is calculated as the value of this field + 2 */
 758 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00
 759 +/** field offset */
 760 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9
 761 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
 762 +    The actual delay is calculated as the value of this field + 3 */
 763 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0
 764 +/** field offset */
 765 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6
 766 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
 767 +    The actual delay is calculated as the value of this field + 3 */
 768 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F
 769 +/** field offset */
 770 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0
 771 +
 772 +/* Fields of "I2C Error Interrupt Request Source Mask Register" */
 773 +/** Enables the corresponding error interrupt. */
 774 +#define I2C_ERR_IRQSM_TXF_OFL 0x00000008
 775 +/* Disable
 776 +#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */
 777 +/** Enable */
 778 +#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008
 779 +/** Enables the corresponding error interrupt. */
 780 +#define I2C_ERR_IRQSM_TXF_UFL 0x00000004
 781 +/* Disable
 782 +#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */
 783 +/** Enable */
 784 +#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004
 785 +/** Enables the corresponding error interrupt. */
 786 +#define I2C_ERR_IRQSM_RXF_OFL 0x00000002
 787 +/* Disable
 788 +#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */
 789 +/** Enable */
 790 +#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002
 791 +/** Enables the corresponding error interrupt. */
 792 +#define I2C_ERR_IRQSM_RXF_UFL 0x00000001
 793 +/* Disable
 794 +#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */
 795 +/** Enable */
 796 +#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001
 797 +
 798 +/* Fields of "I2C Error Interrupt Request Source Status Register" */
 799 +/** TXF_OFL */
 800 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
 801 +/* Nothing
 802 +#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */
 803 +/** Read: Interrupt occurred. */
 804 +#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008
 805 +/** TXF_UFL */
 806 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
 807 +/* Nothing
 808 +#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */
 809 +/** Read: Interrupt occurred. */
 810 +#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004
 811 +/** RXF_OFL */
 812 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
 813 +/* Nothing
 814 +#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */
 815 +/** Read: Interrupt occurred. */
 816 +#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002
 817 +/** RXF_UFL */
 818 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
 819 +/* Nothing
 820 +#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */
 821 +/** Read: Interrupt occurred. */
 822 +#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001
 823 +
 824 +/* Fields of "I2C Error Interrupt Request Source Clear Register" */
 825 +/** TXF_OFL */
 826 +#define I2C_ERR_IRQSC_TXF_OFL 0x00000008
 827 +/* No-Operation
 828 +#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */
 829 +/** Clear */
 830 +#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008
 831 +/** TXF_UFL */
 832 +#define I2C_ERR_IRQSC_TXF_UFL 0x00000004
 833 +/* No-Operation
 834 +#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */
 835 +/** Clear */
 836 +#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004
 837 +/** RXF_OFL */
 838 +#define I2C_ERR_IRQSC_RXF_OFL 0x00000002
 839 +/* No-Operation
 840 +#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */
 841 +/** Clear */
 842 +#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002
 843 +/** RXF_UFL */
 844 +#define I2C_ERR_IRQSC_RXF_UFL 0x00000001
 845 +/* No-Operation
 846 +#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */
 847 +/** Clear */
 848 +#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001
 849 +
 850 +/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */
 851 +/** Enables the corresponding interrupt. */
 852 +#define I2C_P_IRQSM_RX 0x00000040
 853 +/* Disable
 854 +#define I2C_P_IRQSM_RX_DIS 0x00000000 */
 855 +/** Enable */
 856 +#define I2C_P_IRQSM_RX_EN 0x00000040
 857 +/** Enables the corresponding interrupt. */
 858 +#define I2C_P_IRQSM_TX_END 0x00000020
 859 +/* Disable
 860 +#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */
 861 +/** Enable */
 862 +#define I2C_P_IRQSM_TX_END_EN 0x00000020
 863 +/** Enables the corresponding interrupt. */
 864 +#define I2C_P_IRQSM_NACK 0x00000010
 865 +/* Disable
 866 +#define I2C_P_IRQSM_NACK_DIS 0x00000000 */
 867 +/** Enable */
 868 +#define I2C_P_IRQSM_NACK_EN 0x00000010
 869 +/** Enables the corresponding interrupt. */
 870 +#define I2C_P_IRQSM_AL 0x00000008
 871 +/* Disable
 872 +#define I2C_P_IRQSM_AL_DIS 0x00000000 */
 873 +/** Enable */
 874 +#define I2C_P_IRQSM_AL_EN 0x00000008
 875 +/** Enables the corresponding interrupt. */
 876 +#define I2C_P_IRQSM_MC 0x00000004
 877 +/* Disable
 878 +#define I2C_P_IRQSM_MC_DIS 0x00000000 */
 879 +/** Enable */
 880 +#define I2C_P_IRQSM_MC_EN 0x00000004
 881 +/** Enables the corresponding interrupt. */
 882 +#define I2C_P_IRQSM_GC 0x00000002
 883 +/* Disable
 884 +#define I2C_P_IRQSM_GC_DIS 0x00000000 */
 885 +/** Enable */
 886 +#define I2C_P_IRQSM_GC_EN 0x00000002
 887 +/** Enables the corresponding interrupt. */
 888 +#define I2C_P_IRQSM_AM 0x00000001
 889 +/* Disable
 890 +#define I2C_P_IRQSM_AM_DIS 0x00000000 */
 891 +/** Enable */
 892 +#define I2C_P_IRQSM_AM_EN 0x00000001
 893 +
 894 +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
 895 +/** RX */
 896 +#define I2C_P_IRQSS_RX 0x00000040
 897 +/* Nothing
 898 +#define I2C_P_IRQSS_RX_NULL 0x00000000 */
 899 +/** Read: Interrupt occurred. */
 900 +#define I2C_P_IRQSS_RX_INTOCC 0x00000040
 901 +/** TX_END */
 902 +#define I2C_P_IRQSS_TX_END 0x00000020
 903 +/* Nothing
 904 +#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */
 905 +/** Read: Interrupt occurred. */
 906 +#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020
 907 +/** NACK */
 908 +#define I2C_P_IRQSS_NACK 0x00000010
 909 +/* Nothing
 910 +#define I2C_P_IRQSS_NACK_NULL 0x00000000 */
 911 +/** Read: Interrupt occurred. */
 912 +#define I2C_P_IRQSS_NACK_INTOCC 0x00000010
 913 +/** AL */
 914 +#define I2C_P_IRQSS_AL 0x00000008
 915 +/* Nothing
 916 +#define I2C_P_IRQSS_AL_NULL 0x00000000 */
 917 +/** Read: Interrupt occurred. */
 918 +#define I2C_P_IRQSS_AL_INTOCC 0x00000008
 919 +/** MC */
 920 +#define I2C_P_IRQSS_MC 0x00000004
 921 +/* Nothing
 922 +#define I2C_P_IRQSS_MC_NULL 0x00000000 */
 923 +/** Read: Interrupt occurred. */
 924 +#define I2C_P_IRQSS_MC_INTOCC 0x00000004
 925 +/** GC */
 926 +#define I2C_P_IRQSS_GC 0x00000002
 927 +/* Nothing
 928 +#define I2C_P_IRQSS_GC_NULL 0x00000000 */
 929 +/** Read: Interrupt occurred. */
 930 +#define I2C_P_IRQSS_GC_INTOCC 0x00000002
 931 +/** AM */
 932 +#define I2C_P_IRQSS_AM 0x00000001
 933 +/* Nothing
 934 +#define I2C_P_IRQSS_AM_NULL 0x00000000 */
 935 +/** Read: Interrupt occurred. */
 936 +#define I2C_P_IRQSS_AM_INTOCC 0x00000001
 937 +
 938 +/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */
 939 +/** RX */
 940 +#define I2C_P_IRQSC_RX 0x00000040
 941 +/* No-Operation
 942 +#define I2C_P_IRQSC_RX_NOP 0x00000000 */
 943 +/** Clear */
 944 +#define I2C_P_IRQSC_RX_CLR 0x00000040
 945 +/** TX_END */
 946 +#define I2C_P_IRQSC_TX_END 0x00000020
 947 +/* No-Operation
 948 +#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */
 949 +/** Clear */
 950 +#define I2C_P_IRQSC_TX_END_CLR 0x00000020
 951 +/** NACK */
 952 +#define I2C_P_IRQSC_NACK 0x00000010
 953 +/* No-Operation
 954 +#define I2C_P_IRQSC_NACK_NOP 0x00000000 */
 955 +/** Clear */
 956 +#define I2C_P_IRQSC_NACK_CLR 0x00000010
 957 +/** AL */
 958 +#define I2C_P_IRQSC_AL 0x00000008
 959 +/* No-Operation
 960 +#define I2C_P_IRQSC_AL_NOP 0x00000000 */
 961 +/** Clear */
 962 +#define I2C_P_IRQSC_AL_CLR 0x00000008
 963 +/** MC */
 964 +#define I2C_P_IRQSC_MC 0x00000004
 965 +/* No-Operation
 966 +#define I2C_P_IRQSC_MC_NOP 0x00000000 */
 967 +/** Clear */
 968 +#define I2C_P_IRQSC_MC_CLR 0x00000004
 969 +/** GC */
 970 +#define I2C_P_IRQSC_GC 0x00000002
 971 +/* No-Operation
 972 +#define I2C_P_IRQSC_GC_NOP 0x00000000 */
 973 +/** Clear */
 974 +#define I2C_P_IRQSC_GC_CLR 0x00000002
 975 +/** AM */
 976 +#define I2C_P_IRQSC_AM 0x00000001
 977 +/* No-Operation
 978 +#define I2C_P_IRQSC_AM_NOP 0x00000000 */
 979 +/** Clear */
 980 +#define I2C_P_IRQSC_AM_CLR 0x00000001
 981 +
 982 +/* Fields of "I2C Raw Interrupt Status Register" */
 983 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
 984 +#define I2C_RIS_I2C_P_INT 0x00000020
 985 +/* Nothing
 986 +#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */
 987 +/** Read: Interrupt occurred. */
 988 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
 989 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
 990 +#define I2C_RIS_I2C_ERR_INT 0x00000010
 991 +/* Nothing
 992 +#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */
 993 +/** Read: Interrupt occurred. */
 994 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
 995 +/** BREQ_INT */
 996 +#define I2C_RIS_BREQ_INT 0x00000008
 997 +/* Nothing
 998 +#define I2C_RIS_BREQ_INT_NULL 0x00000000 */
 999 +/** Read: Interrupt occurred. */
1000 +#define I2C_RIS_BREQ_INT_INTOCC 0x00000008
1001 +/** LBREQ_INT */
1002 +#define I2C_RIS_LBREQ_INT 0x00000004
1003 +/* Nothing
1004 +#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */
1005 +/** Read: Interrupt occurred. */
1006 +#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004
1007 +/** SREQ_INT */
1008 +#define I2C_RIS_SREQ_INT 0x00000002
1009 +/* Nothing
1010 +#define I2C_RIS_SREQ_INT_NULL 0x00000000 */
1011 +/** Read: Interrupt occurred. */
1012 +#define I2C_RIS_SREQ_INT_INTOCC 0x00000002
1013 +/** LSREQ_INT */
1014 +#define I2C_RIS_LSREQ_INT 0x00000001
1015 +/* Nothing
1016 +#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */
1017 +/** Read: Interrupt occurred. */
1018 +#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001
1019 +
1020 +/* Fields of "I2C Interrupt Mask Control Register" */
1021 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1022 +#define I2C_IMSC_I2C_P_INT 0x00000020
1023 +/* Disable
1024 +#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */
1025 +/** Enable */
1026 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
1027 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1028 +#define I2C_IMSC_I2C_ERR_INT 0x00000010
1029 +/* Disable
1030 +#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */
1031 +/** Enable */
1032 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
1033 +/** BREQ_INT */
1034 +#define I2C_IMSC_BREQ_INT 0x00000008
1035 +/* Disable
1036 +#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */
1037 +/** Enable */
1038 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
1039 +/** LBREQ_INT */
1040 +#define I2C_IMSC_LBREQ_INT 0x00000004
1041 +/* Disable
1042 +#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */
1043 +/** Enable */
1044 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
1045 +/** SREQ_INT */
1046 +#define I2C_IMSC_SREQ_INT 0x00000002
1047 +/* Disable
1048 +#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */
1049 +/** Enable */
1050 +#define I2C_IMSC_SREQ_INT_EN 0x00000002
1051 +/** LSREQ_INT */
1052 +#define I2C_IMSC_LSREQ_INT 0x00000001
1053 +/* Disable
1054 +#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */
1055 +/** Enable */
1056 +#define I2C_IMSC_LSREQ_INT_EN 0x00000001
1057 +
1058 +/* Fields of "I2C Masked Interrupt Status Register" */
1059 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1060 +#define I2C_MIS_I2C_P_INT 0x00000020
1061 +/* Nothing
1062 +#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */
1063 +/** Read: Interrupt occurred. */
1064 +#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020
1065 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1066 +#define I2C_MIS_I2C_ERR_INT 0x00000010
1067 +/* Nothing
1068 +#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */
1069 +/** Read: Interrupt occurred. */
1070 +#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010
1071 +/** BREQ_INT */
1072 +#define I2C_MIS_BREQ_INT 0x00000008
1073 +/* Nothing
1074 +#define I2C_MIS_BREQ_INT_NULL 0x00000000 */
1075 +/** Read: Interrupt occurred. */
1076 +#define I2C_MIS_BREQ_INT_INTOCC 0x00000008
1077 +/** LBREQ_INT */
1078 +#define I2C_MIS_LBREQ_INT 0x00000004
1079 +/* Nothing
1080 +#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */
1081 +/** Read: Interrupt occurred. */
1082 +#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004
1083 +/** SREQ_INT */
1084 +#define I2C_MIS_SREQ_INT 0x00000002
1085 +/* Nothing
1086 +#define I2C_MIS_SREQ_INT_NULL 0x00000000 */
1087 +/** Read: Interrupt occurred. */
1088 +#define I2C_MIS_SREQ_INT_INTOCC 0x00000002
1089 +/** LSREQ_INT */
1090 +#define I2C_MIS_LSREQ_INT 0x00000001
1091 +/* Nothing
1092 +#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */
1093 +/** Read: Interrupt occurred. */
1094 +#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001
1095 +
1096 +/* Fields of "I2C Interrupt Clear Register" */
1097 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1098 +#define I2C_ICR_I2C_P_INT 0x00000020
1099 +/* No-Operation
1100 +#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */
1101 +/** Clear */
1102 +#define I2C_ICR_I2C_P_INT_CLR 0x00000020
1103 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1104 +#define I2C_ICR_I2C_ERR_INT 0x00000010
1105 +/* No-Operation
1106 +#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */
1107 +/** Clear */
1108 +#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010
1109 +/** BREQ_INT */
1110 +#define I2C_ICR_BREQ_INT 0x00000008
1111 +/* No-Operation
1112 +#define I2C_ICR_BREQ_INT_NOP 0x00000000 */
1113 +/** Clear */
1114 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
1115 +/** LBREQ_INT */
1116 +#define I2C_ICR_LBREQ_INT 0x00000004
1117 +/* No-Operation
1118 +#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */
1119 +/** Clear */
1120 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
1121 +/** SREQ_INT */
1122 +#define I2C_ICR_SREQ_INT 0x00000002
1123 +/* No-Operation
1124 +#define I2C_ICR_SREQ_INT_NOP 0x00000000 */
1125 +/** Clear */
1126 +#define I2C_ICR_SREQ_INT_CLR 0x00000002
1127 +/** LSREQ_INT */
1128 +#define I2C_ICR_LSREQ_INT 0x00000001
1129 +/* No-Operation
1130 +#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */
1131 +/** Clear */
1132 +#define I2C_ICR_LSREQ_INT_CLR 0x00000001
1133 +
1134 +/* Fields of "I2C Interrupt Set Register" */
1135 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1136 +#define I2C_ISR_I2C_P_INT 0x00000020
1137 +/* No-Operation
1138 +#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */
1139 +/** Set */
1140 +#define I2C_ISR_I2C_P_INT_SET 0x00000020
1141 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1142 +#define I2C_ISR_I2C_ERR_INT 0x00000010
1143 +/* No-Operation
1144 +#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */
1145 +/** Set */
1146 +#define I2C_ISR_I2C_ERR_INT_SET 0x00000010
1147 +/** BREQ_INT */
1148 +#define I2C_ISR_BREQ_INT 0x00000008
1149 +/* No-Operation
1150 +#define I2C_ISR_BREQ_INT_NOP 0x00000000 */
1151 +/** Set */
1152 +#define I2C_ISR_BREQ_INT_SET 0x00000008
1153 +/** LBREQ_INT */
1154 +#define I2C_ISR_LBREQ_INT 0x00000004
1155 +/* No-Operation
1156 +#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */
1157 +/** Set */
1158 +#define I2C_ISR_LBREQ_INT_SET 0x00000004
1159 +/** SREQ_INT */
1160 +#define I2C_ISR_SREQ_INT 0x00000002
1161 +/* No-Operation
1162 +#define I2C_ISR_SREQ_INT_NOP 0x00000000 */
1163 +/** Set */
1164 +#define I2C_ISR_SREQ_INT_SET 0x00000002
1165 +/** LSREQ_INT */
1166 +#define I2C_ISR_LSREQ_INT 0x00000001
1167 +/* No-Operation
1168 +#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */
1169 +/** Set */
1170 +#define I2C_ISR_LSREQ_INT_SET 0x00000001
1171 +
1172 +/* Fields of "I2C DMA Enable Register" */
1173 +/** BREQ_INT */
1174 +#define I2C_DMAE_BREQ_INT 0x00000008
1175 +/* Disable
1176 +#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */
1177 +/** Enable */
1178 +#define I2C_DMAE_BREQ_INT_EN 0x00000008
1179 +/** LBREQ_INT */
1180 +#define I2C_DMAE_LBREQ_INT 0x00000004
1181 +/* Disable
1182 +#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */
1183 +/** Enable */
1184 +#define I2C_DMAE_LBREQ_INT_EN 0x00000004
1185 +/** SREQ_INT */
1186 +#define I2C_DMAE_SREQ_INT 0x00000002
1187 +/* Disable
1188 +#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */
1189 +/** Enable */
1190 +#define I2C_DMAE_SREQ_INT_EN 0x00000002
1191 +/** LSREQ_INT */
1192 +#define I2C_DMAE_LSREQ_INT 0x00000001
1193 +/* Disable
1194 +#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */
1195 +/** Enable */
1196 +#define I2C_DMAE_LSREQ_INT_EN 0x00000001
1197 +
1198 +/* Fields of "I2C Transmit Data Register" */
1199 +/** Characters to be transmitted */
1200 +#define I2C_TXD_TXD_MASK 0xFFFFFFFF
1201 +/** field offset */
1202 +#define I2C_TXD_TXD_OFFSET 0
1203 +
1204 +/* Fields of "I2C Receive Data Register" */
1205 +/** Received characters */
1206 +#define I2C_RXD_RXD_MASK 0xFFFFFFFF
1207 +/** field offset */
1208 +#define I2C_RXD_RXD_OFFSET 0
1209 +
1210 +/*! @} */ /* I2C_REGISTER */
1211 +
1212 +#endif /* _i2c_reg_h */
1213 --- /dev/null
1214 +++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h
1215 @@ -0,0 +1,4324 @@
1216 +/******************************************************************************
1217 +
1218 +                               Copyright (c) 2010
1219 +                            Lantiq Deutschland GmbH
1220 +
1221 +  For licensing information, see the file 'LICENSE' in the root folder of
1222 +  this software module.
1223 +
1224 +******************************************************************************/
1225 +
1226 +#ifndef _icu0_reg_h
1227 +#define _icu0_reg_h
1228 +
1229 +/** \addtogroup ICU0_REGISTER
1230 +   @{
1231 +*/
1232 +/* access macros */
1233 +#define icu0_r32(reg) reg_r32(&icu0->reg)
1234 +#define icu0_w32(val, reg) reg_w32(val, &icu0->reg)
1235 +#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg)
1236 +#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx)
1237 +#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx)
1238 +#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx)
1239 +#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx)
1240 +
1241 +
1242 +/** ICU0 register structure */
1243 +struct gpon_reg_icu0
1244 +{
1245 +   /** IM0 Interrupt Status Register
1246 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1247 +   unsigned int im0_isr; /* 0x00000000 */
1248 +   /** Reserved */
1249 +   unsigned int res_0; /* 0x00000004 */
1250 +   /** IM0 Interrupt Enable Register
1251 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */
1252 +   unsigned int im0_ier; /* 0x00000008 */
1253 +   /** Reserved */
1254 +   unsigned int res_1; /* 0x0000000C */
1255 +   /** IM0 Interrupt Output Status Register
1256 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */
1257 +   unsigned int im0_iosr; /* 0x00000010 */
1258 +   /** Reserved */
1259 +   unsigned int res_2; /* 0x00000014 */
1260 +   /** IM0 Interrupt Request Set Register
1261 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1262 +   unsigned int im0_irsr; /* 0x00000018 */
1263 +   /** Reserved */
1264 +   unsigned int res_3; /* 0x0000001C */
1265 +   /** IM0 Interrupt Mode Register
1266 +       This register shows the type of interrupt for each bit. */
1267 +   unsigned int im0_imr; /* 0x00000020 */
1268 +   /** Reserved */
1269 +   unsigned int res_4; /* 0x00000024 */
1270 +   /** IM1 Interrupt Status Register
1271 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1272 +   unsigned int im1_isr; /* 0x00000028 */
1273 +   /** Reserved */
1274 +   unsigned int res_5; /* 0x0000002C */
1275 +   /** IM1 Interrupt Enable Register
1276 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */
1277 +   unsigned int im1_ier; /* 0x00000030 */
1278 +   /** Reserved */
1279 +   unsigned int res_6; /* 0x00000034 */
1280 +   /** IM1 Interrupt Output Status Register
1281 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */
1282 +   unsigned int im1_iosr; /* 0x00000038 */
1283 +   /** Reserved */
1284 +   unsigned int res_7; /* 0x0000003C */
1285 +   /** IM1 Interrupt Request Set Register
1286 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1287 +   unsigned int im1_irsr; /* 0x00000040 */
1288 +   /** Reserved */
1289 +   unsigned int res_8; /* 0x00000044 */
1290 +   /** IM1 Interrupt Mode Register
1291 +       This register shows the type of interrupt for each bit. */
1292 +   unsigned int im1_imr; /* 0x00000048 */
1293 +   /** Reserved */
1294 +   unsigned int res_9; /* 0x0000004C */
1295 +   /** IM2 Interrupt Status Register
1296 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1297 +   unsigned int im2_isr; /* 0x00000050 */
1298 +   /** Reserved */
1299 +   unsigned int res_10; /* 0x00000054 */
1300 +   /** IM2 Interrupt Enable Register
1301 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */
1302 +   unsigned int im2_ier; /* 0x00000058 */
1303 +   /** Reserved */
1304 +   unsigned int res_11; /* 0x0000005C */
1305 +   /** IM2 Interrupt Output Status Register
1306 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */
1307 +   unsigned int im2_iosr; /* 0x00000060 */
1308 +   /** Reserved */
1309 +   unsigned int res_12; /* 0x00000064 */
1310 +   /** IM2 Interrupt Request Set Register
1311 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1312 +   unsigned int im2_irsr; /* 0x00000068 */
1313 +   /** Reserved */
1314 +   unsigned int res_13; /* 0x0000006C */
1315 +   /** IM2 Interrupt Mode Register
1316 +       This register shows the type of interrupt for each bit. */
1317 +   unsigned int im2_imr; /* 0x00000070 */
1318 +   /** Reserved */
1319 +   unsigned int res_14; /* 0x00000074 */
1320 +   /** IM3 Interrupt Status Register
1321 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1322 +   unsigned int im3_isr; /* 0x00000078 */
1323 +   /** Reserved */
1324 +   unsigned int res_15; /* 0x0000007C */
1325 +   /** IM3 Interrupt Enable Register
1326 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */
1327 +   unsigned int im3_ier; /* 0x00000080 */
1328 +   /** Reserved */
1329 +   unsigned int res_16; /* 0x00000084 */
1330 +   /** IM3 Interrupt Output Status Register
1331 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */
1332 +   unsigned int im3_iosr; /* 0x00000088 */
1333 +   /** Reserved */
1334 +   unsigned int res_17; /* 0x0000008C */
1335 +   /** IM3 Interrupt Request Set Register
1336 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1337 +   unsigned int im3_irsr; /* 0x00000090 */
1338 +   /** Reserved */
1339 +   unsigned int res_18; /* 0x00000094 */
1340 +   /** IM3 Interrupt Mode Register
1341 +       This register shows the type of interrupt for each bit. */
1342 +   unsigned int im3_imr; /* 0x00000098 */
1343 +   /** Reserved */
1344 +   unsigned int res_19; /* 0x0000009C */
1345 +   /** IM4 Interrupt Status Register
1346 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1347 +   unsigned int im4_isr; /* 0x000000A0 */
1348 +   /** Reserved */
1349 +   unsigned int res_20; /* 0x000000A4 */
1350 +   /** IM4 Interrupt Enable Register
1351 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */
1352 +   unsigned int im4_ier; /* 0x000000A8 */
1353 +   /** Reserved */
1354 +   unsigned int res_21; /* 0x000000AC */
1355 +   /** IM4 Interrupt Output Status Register
1356 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */
1357 +   unsigned int im4_iosr; /* 0x000000B0 */
1358 +   /** Reserved */
1359 +   unsigned int res_22; /* 0x000000B4 */
1360 +   /** IM4 Interrupt Request Set Register
1361 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1362 +   unsigned int im4_irsr; /* 0x000000B8 */
1363 +   /** Reserved */
1364 +   unsigned int res_23; /* 0x000000BC */
1365 +   /** IM4 Interrupt Mode Register
1366 +       This register shows the type of interrupt for each bit. */
1367 +   unsigned int im4_imr; /* 0x000000C0 */
1368 +   /** Reserved */
1369 +   unsigned int res_24; /* 0x000000C4 */
1370 +   /** ICU Interrupt Vector Register (5 bit variant)
1371 +       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1372 +   unsigned int icu_ivec; /* 0x000000C8 */
1373 +   /** Reserved */
1374 +   unsigned int res_25; /* 0x000000CC */
1375 +   /** ICU Interrupt Vector Register (6 bit variant)
1376 +       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1377 +   unsigned int icu_ivec_6; /* 0x000000D0 */
1378 +   /** Reserved */
1379 +   unsigned int res_26[3]; /* 0x000000D4 */
1380 +};
1381 +
1382 +
1383 +/* Fields of "IM0 Interrupt Status Register" */
1384 +/** PCM Transmit Crash Interrupt
1385 +    This bit is an indirect interrupt. */
1386 +#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000
1387 +/* Nothing
1388 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */
1389 +/** Write: Acknowledge the interrupt. */
1390 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000
1391 +/** Read: Interrupt occurred. */
1392 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000
1393 +/** PCM Transmit Interrupt
1394 +    This bit is an indirect interrupt. */
1395 +#define ICU0_IM0_ISR_PCM_TX 0x40000000
1396 +/* Nothing
1397 +#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */
1398 +/** Write: Acknowledge the interrupt. */
1399 +#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000
1400 +/** Read: Interrupt occurred. */
1401 +#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000
1402 +/** PCM Receive Interrupt
1403 +    This bit is an indirect interrupt. */
1404 +#define ICU0_IM0_ISR_PCM_RX 0x20000000
1405 +/* Nothing
1406 +#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */
1407 +/** Write: Acknowledge the interrupt. */
1408 +#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000
1409 +/** Read: Interrupt occurred. */
1410 +#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000
1411 +/** Secure Hash Algorithm Interrupt
1412 +    This bit is a direct interrupt. */
1413 +#define ICU0_IM0_ISR_SHA1_HASH 0x10000000
1414 +/* Nothing
1415 +#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */
1416 +/** Write: Acknowledge the interrupt. */
1417 +#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000
1418 +/** Read: Interrupt occurred. */
1419 +#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000
1420 +/** Advanced Encryption Standard Interrupt
1421 +    This bit is a direct interrupt. */
1422 +#define ICU0_IM0_ISR_AES_AES 0x08000000
1423 +/* Nothing
1424 +#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */
1425 +/** Write: Acknowledge the interrupt. */
1426 +#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000
1427 +/** Read: Interrupt occurred. */
1428 +#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000
1429 +/** SSC Frame Interrupt
1430 +    This bit is a direct interrupt. */
1431 +#define ICU0_IM0_ISR_SSC0_F 0x00020000
1432 +/* Nothing
1433 +#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */
1434 +/** Write: Acknowledge the interrupt. */
1435 +#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000
1436 +/** Read: Interrupt occurred. */
1437 +#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000
1438 +/** SSC Error Interrupt
1439 +    This bit is a direct interrupt. */
1440 +#define ICU0_IM0_ISR_SSC0_E 0x00010000
1441 +/* Nothing
1442 +#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */
1443 +/** Write: Acknowledge the interrupt. */
1444 +#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000
1445 +/** Read: Interrupt occurred. */
1446 +#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000
1447 +/** SSC Receive Interrupt
1448 +    This bit is a direct interrupt. */
1449 +#define ICU0_IM0_ISR_SSC0_R 0x00008000
1450 +/* Nothing
1451 +#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */
1452 +/** Write: Acknowledge the interrupt. */
1453 +#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000
1454 +/** Read: Interrupt occurred. */
1455 +#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000
1456 +/** SSC Transmit Interrupt
1457 +    This bit is a direct interrupt. */
1458 +#define ICU0_IM0_ISR_SSC0_T 0x00004000
1459 +/* Nothing
1460 +#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */
1461 +/** Write: Acknowledge the interrupt. */
1462 +#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000
1463 +/** Read: Interrupt occurred. */
1464 +#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000
1465 +/** I2C Peripheral Interrupt
1466 +    This bit is an indirect interrupt. */
1467 +#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000
1468 +/* Nothing
1469 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */
1470 +/** Write: Acknowledge the interrupt. */
1471 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000
1472 +/** Read: Interrupt occurred. */
1473 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000
1474 +/** I2C Error Interrupt
1475 +    This bit is an indirect interrupt. */
1476 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000
1477 +/* Nothing
1478 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */
1479 +/** Write: Acknowledge the interrupt. */
1480 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000
1481 +/** Read: Interrupt occurred. */
1482 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000
1483 +/** I2C Burst Data Transfer Request
1484 +    This bit is an indirect interrupt. */
1485 +#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800
1486 +/* Nothing
1487 +#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */
1488 +/** Write: Acknowledge the interrupt. */
1489 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800
1490 +/** Read: Interrupt occurred. */
1491 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800
1492 +/** I2C Last Burst Data Transfer Request
1493 +    This bit is an indirect interrupt. */
1494 +#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400
1495 +/* Nothing
1496 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */
1497 +/** Write: Acknowledge the interrupt. */
1498 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400
1499 +/** Read: Interrupt occurred. */
1500 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400
1501 +/** I2C Single Data Transfer Request
1502 +    This bit is an indirect interrupt. */
1503 +#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200
1504 +/* Nothing
1505 +#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */
1506 +/** Write: Acknowledge the interrupt. */
1507 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200
1508 +/** Read: Interrupt occurred. */
1509 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200
1510 +/** I2C Last Single Data Transfer Request
1511 +    This bit is an indirect interrupt. */
1512 +#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100
1513 +/* Nothing
1514 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */
1515 +/** Write: Acknowledge the interrupt. */
1516 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100
1517 +/** Read: Interrupt occurred. */
1518 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100
1519 +/** HOST IF Mailbox1 Transmit Interrupt
1520 +    This bit is an indirect interrupt. */
1521 +#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010
1522 +/* Nothing
1523 +#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */
1524 +/** Write: Acknowledge the interrupt. */
1525 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010
1526 +/** Read: Interrupt occurred. */
1527 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010
1528 +/** HOST IF Mailbox1 Receive Interrupt
1529 +    This bit is an indirect interrupt. */
1530 +#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008
1531 +/* Nothing
1532 +#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */
1533 +/** Write: Acknowledge the interrupt. */
1534 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008
1535 +/** Read: Interrupt occurred. */
1536 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008
1537 +/** HOST IF Mailbox0 Transmit Interrupt
1538 +    This bit is an indirect interrupt. */
1539 +#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004
1540 +/* Nothing
1541 +#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */
1542 +/** Write: Acknowledge the interrupt. */
1543 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004
1544 +/** Read: Interrupt occurred. */
1545 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004
1546 +/** HOST IF Mailbox0 Receive Interrupt
1547 +    This bit is an indirect interrupt. */
1548 +#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002
1549 +/* Nothing
1550 +#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */
1551 +/** Write: Acknowledge the interrupt. */
1552 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002
1553 +/** Read: Interrupt occurred. */
1554 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002
1555 +/** HOST IF Event Interrupt
1556 +    This bit is an indirect interrupt. */
1557 +#define ICU0_IM0_ISR_HOST_EIR 0x00000001
1558 +/* Nothing
1559 +#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */
1560 +/** Write: Acknowledge the interrupt. */
1561 +#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001
1562 +/** Read: Interrupt occurred. */
1563 +#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001
1564 +
1565 +/* Fields of "IM0 Interrupt Enable Register" */
1566 +/** PCM Transmit Crash Interrupt
1567 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1568 +#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000
1569 +/* Disable
1570 +#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */
1571 +/** Enable */
1572 +#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000
1573 +/** PCM Transmit Interrupt
1574 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1575 +#define ICU0_IM0_IER_PCM_TX 0x40000000
1576 +/* Disable
1577 +#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */
1578 +/** Enable */
1579 +#define ICU0_IM0_IER_PCM_TX_EN 0x40000000
1580 +/** PCM Receive Interrupt
1581 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1582 +#define ICU0_IM0_IER_PCM_RX 0x20000000
1583 +/* Disable
1584 +#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */
1585 +/** Enable */
1586 +#define ICU0_IM0_IER_PCM_RX_EN 0x20000000
1587 +/** Secure Hash Algorithm Interrupt
1588 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1589 +#define ICU0_IM0_IER_SHA1_HASH 0x10000000
1590 +/* Disable
1591 +#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */
1592 +/** Enable */
1593 +#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000
1594 +/** Advanced Encryption Standard Interrupt
1595 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1596 +#define ICU0_IM0_IER_AES_AES 0x08000000
1597 +/* Disable
1598 +#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */
1599 +/** Enable */
1600 +#define ICU0_IM0_IER_AES_AES_EN 0x08000000
1601 +/** SSC Frame Interrupt
1602 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1603 +#define ICU0_IM0_IER_SSC0_F 0x00020000
1604 +/* Disable
1605 +#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */
1606 +/** Enable */
1607 +#define ICU0_IM0_IER_SSC0_F_EN 0x00020000
1608 +/** SSC Error Interrupt
1609 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1610 +#define ICU0_IM0_IER_SSC0_E 0x00010000
1611 +/* Disable
1612 +#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */
1613 +/** Enable */
1614 +#define ICU0_IM0_IER_SSC0_E_EN 0x00010000
1615 +/** SSC Receive Interrupt
1616 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1617 +#define ICU0_IM0_IER_SSC0_R 0x00008000
1618 +/* Disable
1619 +#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */
1620 +/** Enable */
1621 +#define ICU0_IM0_IER_SSC0_R_EN 0x00008000
1622 +/** SSC Transmit Interrupt
1623 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1624 +#define ICU0_IM0_IER_SSC0_T 0x00004000
1625 +/* Disable
1626 +#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */
1627 +/** Enable */
1628 +#define ICU0_IM0_IER_SSC0_T_EN 0x00004000
1629 +/** I2C Peripheral Interrupt
1630 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1631 +#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000
1632 +/* Disable
1633 +#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */
1634 +/** Enable */
1635 +#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000
1636 +/** I2C Error Interrupt
1637 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1638 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000
1639 +/* Disable
1640 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */
1641 +/** Enable */
1642 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000
1643 +/** I2C Burst Data Transfer Request
1644 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1645 +#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800
1646 +/* Disable
1647 +#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */
1648 +/** Enable */
1649 +#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800
1650 +/** I2C Last Burst Data Transfer Request
1651 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1652 +#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400
1653 +/* Disable
1654 +#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */
1655 +/** Enable */
1656 +#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400
1657 +/** I2C Single Data Transfer Request
1658 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1659 +#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200
1660 +/* Disable
1661 +#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */
1662 +/** Enable */
1663 +#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200
1664 +/** I2C Last Single Data Transfer Request
1665 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1666 +#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100
1667 +/* Disable
1668 +#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */
1669 +/** Enable */
1670 +#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100
1671 +/** HOST IF Mailbox1 Transmit Interrupt
1672 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1673 +#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010
1674 +/* Disable
1675 +#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */
1676 +/** Enable */
1677 +#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010
1678 +/** HOST IF Mailbox1 Receive Interrupt
1679 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1680 +#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008
1681 +/* Disable
1682 +#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */
1683 +/** Enable */
1684 +#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008
1685 +/** HOST IF Mailbox0 Transmit Interrupt
1686 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1687 +#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004
1688 +/* Disable
1689 +#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */
1690 +/** Enable */
1691 +#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004
1692 +/** HOST IF Mailbox0 Receive Interrupt
1693 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1694 +#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002
1695 +/* Disable
1696 +#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */
1697 +/** Enable */
1698 +#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002
1699 +/** HOST IF Event Interrupt
1700 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1701 +#define ICU0_IM0_IER_HOST_EIR 0x00000001
1702 +/* Disable
1703 +#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */
1704 +/** Enable */
1705 +#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001
1706 +
1707 +/* Fields of "IM0 Interrupt Output Status Register" */
1708 +/** PCM Transmit Crash Interrupt
1709 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1710 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000
1711 +/* Nothing
1712 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */
1713 +/** Read: Interrupt occurred. */
1714 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000
1715 +/** PCM Transmit Interrupt
1716 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1717 +#define ICU0_IM0_IOSR_PCM_TX 0x40000000
1718 +/* Nothing
1719 +#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */
1720 +/** Read: Interrupt occurred. */
1721 +#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000
1722 +/** PCM Receive Interrupt
1723 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1724 +#define ICU0_IM0_IOSR_PCM_RX 0x20000000
1725 +/* Nothing
1726 +#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */
1727 +/** Read: Interrupt occurred. */
1728 +#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000
1729 +/** Secure Hash Algorithm Interrupt
1730 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1731 +#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000
1732 +/* Nothing
1733 +#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */
1734 +/** Read: Interrupt occurred. */
1735 +#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000
1736 +/** Advanced Encryption Standard Interrupt
1737 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1738 +#define ICU0_IM0_IOSR_AES_AES 0x08000000
1739 +/* Nothing
1740 +#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */
1741 +/** Read: Interrupt occurred. */
1742 +#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000
1743 +/** SSC Frame Interrupt
1744 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1745 +#define ICU0_IM0_IOSR_SSC0_F 0x00020000
1746 +/* Nothing
1747 +#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */
1748 +/** Read: Interrupt occurred. */
1749 +#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000
1750 +/** SSC Error Interrupt
1751 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1752 +#define ICU0_IM0_IOSR_SSC0_E 0x00010000
1753 +/* Nothing
1754 +#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */
1755 +/** Read: Interrupt occurred. */
1756 +#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000
1757 +/** SSC Receive Interrupt
1758 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1759 +#define ICU0_IM0_IOSR_SSC0_R 0x00008000
1760 +/* Nothing
1761 +#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */
1762 +/** Read: Interrupt occurred. */
1763 +#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000
1764 +/** SSC Transmit Interrupt
1765 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1766 +#define ICU0_IM0_IOSR_SSC0_T 0x00004000
1767 +/* Nothing
1768 +#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */
1769 +/** Read: Interrupt occurred. */
1770 +#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000
1771 +/** I2C Peripheral Interrupt
1772 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1773 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000
1774 +/* Nothing
1775 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */
1776 +/** Read: Interrupt occurred. */
1777 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000
1778 +/** I2C Error Interrupt
1779 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1780 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000
1781 +/* Nothing
1782 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */
1783 +/** Read: Interrupt occurred. */
1784 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000
1785 +/** I2C Burst Data Transfer Request
1786 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1787 +#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800
1788 +/* Nothing
1789 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */
1790 +/** Read: Interrupt occurred. */
1791 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800
1792 +/** I2C Last Burst Data Transfer Request
1793 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1794 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400
1795 +/* Nothing
1796 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */
1797 +/** Read: Interrupt occurred. */
1798 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400
1799 +/** I2C Single Data Transfer Request
1800 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1801 +#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200
1802 +/* Nothing
1803 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */
1804 +/** Read: Interrupt occurred. */
1805 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200
1806 +/** I2C Last Single Data Transfer Request
1807 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1808 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100
1809 +/* Nothing
1810 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */
1811 +/** Read: Interrupt occurred. */
1812 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100
1813 +/** HOST IF Mailbox1 Transmit Interrupt
1814 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1815 +#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010
1816 +/* Nothing
1817 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */
1818 +/** Read: Interrupt occurred. */
1819 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010
1820 +/** HOST IF Mailbox1 Receive Interrupt
1821 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1822 +#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008
1823 +/* Nothing
1824 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */
1825 +/** Read: Interrupt occurred. */
1826 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008
1827 +/** HOST IF Mailbox0 Transmit Interrupt
1828 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1829 +#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004
1830 +/* Nothing
1831 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */
1832 +/** Read: Interrupt occurred. */
1833 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004
1834 +/** HOST IF Mailbox0 Receive Interrupt
1835 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1836 +#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002
1837 +/* Nothing
1838 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */
1839 +/** Read: Interrupt occurred. */
1840 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002
1841 +/** HOST IF Event Interrupt
1842 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1843 +#define ICU0_IM0_IOSR_HOST_EIR 0x00000001
1844 +/* Nothing
1845 +#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */
1846 +/** Read: Interrupt occurred. */
1847 +#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001
1848 +
1849 +/* Fields of "IM0 Interrupt Request Set Register" */
1850 +/** PCM Transmit Crash Interrupt
1851 +    Software control for the corresponding bit in the IM0_ISR register. */
1852 +#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000
1853 +/** PCM Transmit Interrupt
1854 +    Software control for the corresponding bit in the IM0_ISR register. */
1855 +#define ICU0_IM0_IRSR_PCM_TX 0x40000000
1856 +/** PCM Receive Interrupt
1857 +    Software control for the corresponding bit in the IM0_ISR register. */
1858 +#define ICU0_IM0_IRSR_PCM_RX 0x20000000
1859 +/** Secure Hash Algorithm Interrupt
1860 +    Software control for the corresponding bit in the IM0_ISR register. */
1861 +#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000
1862 +/** Advanced Encryption Standard Interrupt
1863 +    Software control for the corresponding bit in the IM0_ISR register. */
1864 +#define ICU0_IM0_IRSR_AES_AES 0x08000000
1865 +/** SSC Frame Interrupt
1866 +    Software control for the corresponding bit in the IM0_ISR register. */
1867 +#define ICU0_IM0_IRSR_SSC0_F 0x00020000
1868 +/** SSC Error Interrupt
1869 +    Software control for the corresponding bit in the IM0_ISR register. */
1870 +#define ICU0_IM0_IRSR_SSC0_E 0x00010000
1871 +/** SSC Receive Interrupt
1872 +    Software control for the corresponding bit in the IM0_ISR register. */
1873 +#define ICU0_IM0_IRSR_SSC0_R 0x00008000
1874 +/** SSC Transmit Interrupt
1875 +    Software control for the corresponding bit in the IM0_ISR register. */
1876 +#define ICU0_IM0_IRSR_SSC0_T 0x00004000
1877 +/** I2C Peripheral Interrupt
1878 +    Software control for the corresponding bit in the IM0_ISR register. */
1879 +#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000
1880 +/** I2C Error Interrupt
1881 +    Software control for the corresponding bit in the IM0_ISR register. */
1882 +#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000
1883 +/** I2C Burst Data Transfer Request
1884 +    Software control for the corresponding bit in the IM0_ISR register. */
1885 +#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800
1886 +/** I2C Last Burst Data Transfer Request
1887 +    Software control for the corresponding bit in the IM0_ISR register. */
1888 +#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400
1889 +/** I2C Single Data Transfer Request
1890 +    Software control for the corresponding bit in the IM0_ISR register. */
1891 +#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200
1892 +/** I2C Last Single Data Transfer Request
1893 +    Software control for the corresponding bit in the IM0_ISR register. */
1894 +#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100
1895 +/** HOST IF Mailbox1 Transmit Interrupt
1896 +    Software control for the corresponding bit in the IM0_ISR register. */
1897 +#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010
1898 +/** HOST IF Mailbox1 Receive Interrupt
1899 +    Software control for the corresponding bit in the IM0_ISR register. */
1900 +#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008
1901 +/** HOST IF Mailbox0 Transmit Interrupt
1902 +    Software control for the corresponding bit in the IM0_ISR register. */
1903 +#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004
1904 +/** HOST IF Mailbox0 Receive Interrupt
1905 +    Software control for the corresponding bit in the IM0_ISR register. */
1906 +#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002
1907 +/** HOST IF Event Interrupt
1908 +    Software control for the corresponding bit in the IM0_ISR register. */
1909 +#define ICU0_IM0_IRSR_HOST_EIR 0x00000001
1910 +
1911 +/* Fields of "IM0 Interrupt Mode Register" */
1912 +/** PCM Transmit Crash Interrupt
1913 +    Type of interrupt. */
1914 +#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000
1915 +/* Indirect Interrupt.
1916 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */
1917 +/** Direct Interrupt. */
1918 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000
1919 +/** PCM Transmit Interrupt
1920 +    Type of interrupt. */
1921 +#define ICU0_IM0_IMR_PCM_TX 0x40000000
1922 +/* Indirect Interrupt.
1923 +#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */
1924 +/** Direct Interrupt. */
1925 +#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000
1926 +/** PCM Receive Interrupt
1927 +    Type of interrupt. */
1928 +#define ICU0_IM0_IMR_PCM_RX 0x20000000
1929 +/* Indirect Interrupt.
1930 +#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */
1931 +/** Direct Interrupt. */
1932 +#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000
1933 +/** Secure Hash Algorithm Interrupt
1934 +    Type of interrupt. */
1935 +#define ICU0_IM0_IMR_SHA1_HASH 0x10000000
1936 +/* Indirect Interrupt.
1937 +#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */
1938 +/** Direct Interrupt. */
1939 +#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000
1940 +/** Advanced Encryption Standard Interrupt
1941 +    Type of interrupt. */
1942 +#define ICU0_IM0_IMR_AES_AES 0x08000000
1943 +/* Indirect Interrupt.
1944 +#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */
1945 +/** Direct Interrupt. */
1946 +#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000
1947 +/** SSC Frame Interrupt
1948 +    Type of interrupt. */
1949 +#define ICU0_IM0_IMR_SSC0_F 0x00020000
1950 +/* Indirect Interrupt.
1951 +#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */
1952 +/** Direct Interrupt. */
1953 +#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000
1954 +/** SSC Error Interrupt
1955 +    Type of interrupt. */
1956 +#define ICU0_IM0_IMR_SSC0_E 0x00010000
1957 +/* Indirect Interrupt.
1958 +#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */
1959 +/** Direct Interrupt. */
1960 +#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000
1961 +/** SSC Receive Interrupt
1962 +    Type of interrupt. */
1963 +#define ICU0_IM0_IMR_SSC0_R 0x00008000
1964 +/* Indirect Interrupt.
1965 +#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */
1966 +/** Direct Interrupt. */
1967 +#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000
1968 +/** SSC Transmit Interrupt
1969 +    Type of interrupt. */
1970 +#define ICU0_IM0_IMR_SSC0_T 0x00004000
1971 +/* Indirect Interrupt.
1972 +#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */
1973 +/** Direct Interrupt. */
1974 +#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000
1975 +/** I2C Peripheral Interrupt
1976 +    Type of interrupt. */
1977 +#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000
1978 +/* Indirect Interrupt.
1979 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */
1980 +/** Direct Interrupt. */
1981 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000
1982 +/** I2C Error Interrupt
1983 +    Type of interrupt. */
1984 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000
1985 +/* Indirect Interrupt.
1986 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */
1987 +/** Direct Interrupt. */
1988 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000
1989 +/** I2C Burst Data Transfer Request
1990 +    Type of interrupt. */
1991 +#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800
1992 +/* Indirect Interrupt.
1993 +#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */
1994 +/** Direct Interrupt. */
1995 +#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800
1996 +/** I2C Last Burst Data Transfer Request
1997 +    Type of interrupt. */
1998 +#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400
1999 +/* Indirect Interrupt.
2000 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */
2001 +/** Direct Interrupt. */
2002 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400
2003 +/** I2C Single Data Transfer Request
2004 +    Type of interrupt. */
2005 +#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200
2006 +/* Indirect Interrupt.
2007 +#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */
2008 +/** Direct Interrupt. */
2009 +#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200
2010 +/** I2C Last Single Data Transfer Request
2011 +    Type of interrupt. */
2012 +#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100
2013 +/* Indirect Interrupt.
2014 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */
2015 +/** Direct Interrupt. */
2016 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100
2017 +/** HOST IF Mailbox1 Transmit Interrupt
2018 +    Type of interrupt. */
2019 +#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010
2020 +/* Indirect Interrupt.
2021 +#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */
2022 +/** Direct Interrupt. */
2023 +#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010
2024 +/** HOST IF Mailbox1 Receive Interrupt
2025 +    Type of interrupt. */
2026 +#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008
2027 +/* Indirect Interrupt.
2028 +#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */
2029 +/** Direct Interrupt. */
2030 +#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008
2031 +/** HOST IF Mailbox0 Transmit Interrupt
2032 +    Type of interrupt. */
2033 +#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004
2034 +/* Indirect Interrupt.
2035 +#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */
2036 +/** Direct Interrupt. */
2037 +#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004
2038 +/** HOST IF Mailbox0 Receive Interrupt
2039 +    Type of interrupt. */
2040 +#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002
2041 +/* Indirect Interrupt.
2042 +#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */
2043 +/** Direct Interrupt. */
2044 +#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002
2045 +/** HOST IF Event Interrupt
2046 +    Type of interrupt. */
2047 +#define ICU0_IM0_IMR_HOST_EIR 0x00000001
2048 +/* Indirect Interrupt.
2049 +#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */
2050 +/** Direct Interrupt. */
2051 +#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001
2052 +
2053 +/* Fields of "IM1 Interrupt Status Register" */
2054 +/** Crossbar Error Interrupt
2055 +    This bit is an indirect interrupt. */
2056 +#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000
2057 +/* Nothing
2058 +#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */
2059 +/** Write: Acknowledge the interrupt. */
2060 +#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000
2061 +/** Read: Interrupt occurred. */
2062 +#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000
2063 +/** DDR Controller Interrupt
2064 +    This bit is an indirect interrupt. */
2065 +#define ICU0_IM1_ISR_DDR 0x40000000
2066 +/* Nothing
2067 +#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */
2068 +/** Write: Acknowledge the interrupt. */
2069 +#define ICU0_IM1_ISR_DDR_INTACK 0x40000000
2070 +/** Read: Interrupt occurred. */
2071 +#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000
2072 +/** FPI Bus Control Unit Interrupt
2073 +    This bit is a direct interrupt. */
2074 +#define ICU0_IM1_ISR_BCU0 0x20000000
2075 +/* Nothing
2076 +#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */
2077 +/** Write: Acknowledge the interrupt. */
2078 +#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000
2079 +/** Read: Interrupt occurred. */
2080 +#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000
2081 +/** SBIU interrupt
2082 +    This bit is an indirect interrupt. */
2083 +#define ICU0_IM1_ISR_SBIU0 0x08000000
2084 +/* Nothing
2085 +#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */
2086 +/** Write: Acknowledge the interrupt. */
2087 +#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000
2088 +/** Read: Interrupt occurred. */
2089 +#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000
2090 +/** Watchdog Prewarning Interrupt
2091 +    This bit is an indirect interrupt. */
2092 +#define ICU0_IM1_ISR_WDT_PIR 0x02000000
2093 +/* Nothing
2094 +#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */
2095 +/** Write: Acknowledge the interrupt. */
2096 +#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000
2097 +/** Read: Interrupt occurred. */
2098 +#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000
2099 +/** Watchdog Access Error Interrupt
2100 +    This bit is an indirect interrupt. */
2101 +#define ICU0_IM1_ISR_WDT_AEIR 0x01000000
2102 +/* Nothing
2103 +#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */
2104 +/** Write: Acknowledge the interrupt. */
2105 +#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000
2106 +/** Read: Interrupt occurred. */
2107 +#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000
2108 +/** SYS GPE Interrupt
2109 +    This bit is an indirect interrupt. */
2110 +#define ICU0_IM1_ISR_SYS_GPE 0x00200000
2111 +/* Nothing
2112 +#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */
2113 +/** Write: Acknowledge the interrupt. */
2114 +#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000
2115 +/** Read: Interrupt occurred. */
2116 +#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000
2117 +/** SYS1 Interrupt
2118 +    This bit is an indirect interrupt. */
2119 +#define ICU0_IM1_ISR_SYS1 0x00100000
2120 +/* Nothing
2121 +#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */
2122 +/** Write: Acknowledge the interrupt. */
2123 +#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000
2124 +/** Read: Interrupt occurred. */
2125 +#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000
2126 +/** PMA Interrupt from IntNode of the RX Clk Domain
2127 +    This bit is an indirect interrupt. */
2128 +#define ICU0_IM1_ISR_PMA_RX 0x00020000
2129 +/* Nothing
2130 +#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */
2131 +/** Write: Acknowledge the interrupt. */
2132 +#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000
2133 +/** Read: Interrupt occurred. */
2134 +#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000
2135 +/** PMA Interrupt from IntNode of the TX Clk Domain
2136 +    This bit is an indirect interrupt. */
2137 +#define ICU0_IM1_ISR_PMA_TX 0x00010000
2138 +/* Nothing
2139 +#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */
2140 +/** Write: Acknowledge the interrupt. */
2141 +#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000
2142 +/** Read: Interrupt occurred. */
2143 +#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000
2144 +/** PMA Interrupt from IntNode of the 200MHz Domain
2145 +    This bit is an indirect interrupt. */
2146 +#define ICU0_IM1_ISR_PMA_200M 0x00008000
2147 +/* Nothing
2148 +#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */
2149 +/** Write: Acknowledge the interrupt. */
2150 +#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000
2151 +/** Read: Interrupt occurred. */
2152 +#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000
2153 +/** Time of Day
2154 +    This bit is an indirect interrupt. */
2155 +#define ICU0_IM1_ISR_TOD 0x00004000
2156 +/* Nothing
2157 +#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */
2158 +/** Write: Acknowledge the interrupt. */
2159 +#define ICU0_IM1_ISR_TOD_INTACK 0x00004000
2160 +/** Read: Interrupt occurred. */
2161 +#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000
2162 +/** 8kHz root interrupt derived from GPON interface
2163 +    This bit is a direct interrupt. */
2164 +#define ICU0_IM1_ISR_FSC_ROOT 0x00002000
2165 +/* Nothing
2166 +#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */
2167 +/** Write: Acknowledge the interrupt. */
2168 +#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000
2169 +/** Read: Interrupt occurred. */
2170 +#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000
2171 +/** FSC Timer Interrupt 1
2172 +    Delayed version of FSCROOT. This bit is a direct interrupt. */
2173 +#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000
2174 +/* Nothing
2175 +#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */
2176 +/** Write: Acknowledge the interrupt. */
2177 +#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000
2178 +/** Read: Interrupt occurred. */
2179 +#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000
2180 +/** FSC Timer Interrupt 0
2181 +    Delayed version of FSCROOT. This bit is a direct interrupt. */
2182 +#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800
2183 +/* Nothing
2184 +#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */
2185 +/** Write: Acknowledge the interrupt. */
2186 +#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800
2187 +/** Read: Interrupt occurred. */
2188 +#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800
2189 +/** 8kHz backup interrupt derived from core-PLL
2190 +    This bit is an indirect interrupt. */
2191 +#define ICU0_IM1_ISR_FSC_BKP 0x00000400
2192 +/* Nothing
2193 +#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */
2194 +/** Write: Acknowledge the interrupt. */
2195 +#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400
2196 +/** Read: Interrupt occurred. */
2197 +#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400
2198 +/** External Interrupt from GPIO P4
2199 +    This bit is an indirect interrupt. */
2200 +#define ICU0_IM1_ISR_P4 0x00000100
2201 +/* Nothing
2202 +#define ICU0_IM1_ISR_P4_NULL 0x00000000 */
2203 +/** Write: Acknowledge the interrupt. */
2204 +#define ICU0_IM1_ISR_P4_INTACK 0x00000100
2205 +/** Read: Interrupt occurred. */
2206 +#define ICU0_IM1_ISR_P4_INTOCC 0x00000100
2207 +/** External Interrupt from GPIO P3
2208 +    This bit is an indirect interrupt. */
2209 +#define ICU0_IM1_ISR_P3 0x00000080
2210 +/* Nothing
2211 +#define ICU0_IM1_ISR_P3_NULL 0x00000000 */
2212 +/** Write: Acknowledge the interrupt. */
2213 +#define ICU0_IM1_ISR_P3_INTACK 0x00000080
2214 +/** Read: Interrupt occurred. */
2215 +#define ICU0_IM1_ISR_P3_INTOCC 0x00000080
2216 +/** External Interrupt from GPIO P2
2217 +    This bit is an indirect interrupt. */
2218 +#define ICU0_IM1_ISR_P2 0x00000040
2219 +/* Nothing
2220 +#define ICU0_IM1_ISR_P2_NULL 0x00000000 */
2221 +/** Write: Acknowledge the interrupt. */
2222 +#define ICU0_IM1_ISR_P2_INTACK 0x00000040
2223 +/** Read: Interrupt occurred. */
2224 +#define ICU0_IM1_ISR_P2_INTOCC 0x00000040
2225 +/** External Interrupt from GPIO P1
2226 +    This bit is an indirect interrupt. */
2227 +#define ICU0_IM1_ISR_P1 0x00000020
2228 +/* Nothing
2229 +#define ICU0_IM1_ISR_P1_NULL 0x00000000 */
2230 +/** Write: Acknowledge the interrupt. */
2231 +#define ICU0_IM1_ISR_P1_INTACK 0x00000020
2232 +/** Read: Interrupt occurred. */
2233 +#define ICU0_IM1_ISR_P1_INTOCC 0x00000020
2234 +/** External Interrupt from GPIO P0
2235 +    This bit is an indirect interrupt. */
2236 +#define ICU0_IM1_ISR_P0 0x00000010
2237 +/* Nothing
2238 +#define ICU0_IM1_ISR_P0_NULL 0x00000000 */
2239 +/** Write: Acknowledge the interrupt. */
2240 +#define ICU0_IM1_ISR_P0_INTACK 0x00000010
2241 +/** Read: Interrupt occurred. */
2242 +#define ICU0_IM1_ISR_P0_INTOCC 0x00000010
2243 +/** EBU Serial Flash Busy
2244 +    This bit is an indirect interrupt. */
2245 +#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004
2246 +/* Nothing
2247 +#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */
2248 +/** Write: Acknowledge the interrupt. */
2249 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004
2250 +/** Read: Interrupt occurred. */
2251 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004
2252 +/** EBU Serial Flash Command Overwrite Error
2253 +    This bit is an indirect interrupt. */
2254 +#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002
2255 +/* Nothing
2256 +#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */
2257 +/** Write: Acknowledge the interrupt. */
2258 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002
2259 +/** Read: Interrupt occurred. */
2260 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002
2261 +/** EBU Serial Flash Command Error
2262 +    This bit is an indirect interrupt. */
2263 +#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001
2264 +/* Nothing
2265 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */
2266 +/** Write: Acknowledge the interrupt. */
2267 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001
2268 +/** Read: Interrupt occurred. */
2269 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001
2270 +
2271 +/* Fields of "IM1 Interrupt Enable Register" */
2272 +/** Crossbar Error Interrupt
2273 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2274 +#define ICU0_IM1_IER_XBAR_ERROR 0x80000000
2275 +/* Disable
2276 +#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */
2277 +/** Enable */
2278 +#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000
2279 +/** DDR Controller Interrupt
2280 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2281 +#define ICU0_IM1_IER_DDR 0x40000000
2282 +/* Disable
2283 +#define ICU0_IM1_IER_DDR_DIS 0x00000000 */
2284 +/** Enable */
2285 +#define ICU0_IM1_IER_DDR_EN 0x40000000
2286 +/** FPI Bus Control Unit Interrupt
2287 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2288 +#define ICU0_IM1_IER_BCU0 0x20000000
2289 +/* Disable
2290 +#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */
2291 +/** Enable */
2292 +#define ICU0_IM1_IER_BCU0_EN 0x20000000
2293 +/** SBIU interrupt
2294 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2295 +#define ICU0_IM1_IER_SBIU0 0x08000000
2296 +/* Disable
2297 +#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */
2298 +/** Enable */
2299 +#define ICU0_IM1_IER_SBIU0_EN 0x08000000
2300 +/** Watchdog Prewarning Interrupt
2301 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2302 +#define ICU0_IM1_IER_WDT_PIR 0x02000000
2303 +/* Disable
2304 +#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */
2305 +/** Enable */
2306 +#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000
2307 +/** Watchdog Access Error Interrupt
2308 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2309 +#define ICU0_IM1_IER_WDT_AEIR 0x01000000
2310 +/* Disable
2311 +#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */
2312 +/** Enable */
2313 +#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000
2314 +/** SYS GPE Interrupt
2315 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2316 +#define ICU0_IM1_IER_SYS_GPE 0x00200000
2317 +/* Disable
2318 +#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */
2319 +/** Enable */
2320 +#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000
2321 +/** SYS1 Interrupt
2322 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2323 +#define ICU0_IM1_IER_SYS1 0x00100000
2324 +/* Disable
2325 +#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */
2326 +/** Enable */
2327 +#define ICU0_IM1_IER_SYS1_EN 0x00100000
2328 +/** PMA Interrupt from IntNode of the RX Clk Domain
2329 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2330 +#define ICU0_IM1_IER_PMA_RX 0x00020000
2331 +/* Disable
2332 +#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */
2333 +/** Enable */
2334 +#define ICU0_IM1_IER_PMA_RX_EN 0x00020000
2335 +/** PMA Interrupt from IntNode of the TX Clk Domain
2336 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2337 +#define ICU0_IM1_IER_PMA_TX 0x00010000
2338 +/* Disable
2339 +#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */
2340 +/** Enable */
2341 +#define ICU0_IM1_IER_PMA_TX_EN 0x00010000
2342 +/** PMA Interrupt from IntNode of the 200MHz Domain
2343 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2344 +#define ICU0_IM1_IER_PMA_200M 0x00008000
2345 +/* Disable
2346 +#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */
2347 +/** Enable */
2348 +#define ICU0_IM1_IER_PMA_200M_EN 0x00008000
2349 +/** Time of Day
2350 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2351 +#define ICU0_IM1_IER_TOD 0x00004000
2352 +/* Disable
2353 +#define ICU0_IM1_IER_TOD_DIS 0x00000000 */
2354 +/** Enable */
2355 +#define ICU0_IM1_IER_TOD_EN 0x00004000
2356 +/** 8kHz root interrupt derived from GPON interface
2357 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2358 +#define ICU0_IM1_IER_FSC_ROOT 0x00002000
2359 +/* Disable
2360 +#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */
2361 +/** Enable */
2362 +#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000
2363 +/** FSC Timer Interrupt 1
2364 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2365 +#define ICU0_IM1_IER_FSCT_CMP1 0x00001000
2366 +/* Disable
2367 +#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */
2368 +/** Enable */
2369 +#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000
2370 +/** FSC Timer Interrupt 0
2371 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2372 +#define ICU0_IM1_IER_FSCT_CMP0 0x00000800
2373 +/* Disable
2374 +#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */
2375 +/** Enable */
2376 +#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800
2377 +/** 8kHz backup interrupt derived from core-PLL
2378 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2379 +#define ICU0_IM1_IER_FSC_BKP 0x00000400
2380 +/* Disable
2381 +#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */
2382 +/** Enable */
2383 +#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400
2384 +/** External Interrupt from GPIO P4
2385 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2386 +#define ICU0_IM1_IER_P4 0x00000100
2387 +/* Disable
2388 +#define ICU0_IM1_IER_P4_DIS 0x00000000 */
2389 +/** Enable */
2390 +#define ICU0_IM1_IER_P4_EN 0x00000100
2391 +/** External Interrupt from GPIO P3
2392 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2393 +#define ICU0_IM1_IER_P3 0x00000080
2394 +/* Disable
2395 +#define ICU0_IM1_IER_P3_DIS 0x00000000 */
2396 +/** Enable */
2397 +#define ICU0_IM1_IER_P3_EN 0x00000080
2398 +/** External Interrupt from GPIO P2
2399 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2400 +#define ICU0_IM1_IER_P2 0x00000040
2401 +/* Disable
2402 +#define ICU0_IM1_IER_P2_DIS 0x00000000 */
2403 +/** Enable */
2404 +#define ICU0_IM1_IER_P2_EN 0x00000040
2405 +/** External Interrupt from GPIO P1
2406 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2407 +#define ICU0_IM1_IER_P1 0x00000020
2408 +/* Disable
2409 +#define ICU0_IM1_IER_P1_DIS 0x00000000 */
2410 +/** Enable */
2411 +#define ICU0_IM1_IER_P1_EN 0x00000020
2412 +/** External Interrupt from GPIO P0
2413 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2414 +#define ICU0_IM1_IER_P0 0x00000010
2415 +/* Disable
2416 +#define ICU0_IM1_IER_P0_DIS 0x00000000 */
2417 +/** Enable */
2418 +#define ICU0_IM1_IER_P0_EN 0x00000010
2419 +/** EBU Serial Flash Busy
2420 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2421 +#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004
2422 +/* Disable
2423 +#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */
2424 +/** Enable */
2425 +#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004
2426 +/** EBU Serial Flash Command Overwrite Error
2427 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2428 +#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002
2429 +/* Disable
2430 +#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */
2431 +/** Enable */
2432 +#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002
2433 +/** EBU Serial Flash Command Error
2434 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2435 +#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001
2436 +/* Disable
2437 +#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */
2438 +/** Enable */
2439 +#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001
2440 +
2441 +/* Fields of "IM1 Interrupt Output Status Register" */
2442 +/** Crossbar Error Interrupt
2443 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2444 +#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000
2445 +/* Nothing
2446 +#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */
2447 +/** Read: Interrupt occurred. */
2448 +#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000
2449 +/** DDR Controller Interrupt
2450 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2451 +#define ICU0_IM1_IOSR_DDR 0x40000000
2452 +/* Nothing
2453 +#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */
2454 +/** Read: Interrupt occurred. */
2455 +#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000
2456 +/** FPI Bus Control Unit Interrupt
2457 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2458 +#define ICU0_IM1_IOSR_BCU0 0x20000000
2459 +/* Nothing
2460 +#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */
2461 +/** Read: Interrupt occurred. */
2462 +#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000
2463 +/** SBIU interrupt
2464 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2465 +#define ICU0_IM1_IOSR_SBIU0 0x08000000
2466 +/* Nothing
2467 +#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */
2468 +/** Read: Interrupt occurred. */
2469 +#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000
2470 +/** Watchdog Prewarning Interrupt
2471 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2472 +#define ICU0_IM1_IOSR_WDT_PIR 0x02000000
2473 +/* Nothing
2474 +#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */
2475 +/** Read: Interrupt occurred. */
2476 +#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000
2477 +/** Watchdog Access Error Interrupt
2478 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2479 +#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000
2480 +/* Nothing
2481 +#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */
2482 +/** Read: Interrupt occurred. */
2483 +#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000
2484 +/** SYS GPE Interrupt
2485 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2486 +#define ICU0_IM1_IOSR_SYS_GPE 0x00200000
2487 +/* Nothing
2488 +#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */
2489 +/** Read: Interrupt occurred. */
2490 +#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000
2491 +/** SYS1 Interrupt
2492 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2493 +#define ICU0_IM1_IOSR_SYS1 0x00100000
2494 +/* Nothing
2495 +#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */
2496 +/** Read: Interrupt occurred. */
2497 +#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000
2498 +/** PMA Interrupt from IntNode of the RX Clk Domain
2499 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2500 +#define ICU0_IM1_IOSR_PMA_RX 0x00020000
2501 +/* Nothing
2502 +#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */
2503 +/** Read: Interrupt occurred. */
2504 +#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000
2505 +/** PMA Interrupt from IntNode of the TX Clk Domain
2506 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2507 +#define ICU0_IM1_IOSR_PMA_TX 0x00010000
2508 +/* Nothing
2509 +#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */
2510 +/** Read: Interrupt occurred. */
2511 +#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000
2512 +/** PMA Interrupt from IntNode of the 200MHz Domain
2513 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2514 +#define ICU0_IM1_IOSR_PMA_200M 0x00008000
2515 +/* Nothing
2516 +#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */
2517 +/** Read: Interrupt occurred. */
2518 +#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000
2519 +/** Time of Day
2520 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2521 +#define ICU0_IM1_IOSR_TOD 0x00004000
2522 +/* Nothing
2523 +#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */
2524 +/** Read: Interrupt occurred. */
2525 +#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000
2526 +/** 8kHz root interrupt derived from GPON interface
2527 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2528 +#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000
2529 +/* Nothing
2530 +#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */
2531 +/** Read: Interrupt occurred. */
2532 +#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000
2533 +/** FSC Timer Interrupt 1
2534 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2535 +#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000
2536 +/* Nothing
2537 +#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */
2538 +/** Read: Interrupt occurred. */
2539 +#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000
2540 +/** FSC Timer Interrupt 0
2541 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2542 +#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800
2543 +/* Nothing
2544 +#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */
2545 +/** Read: Interrupt occurred. */
2546 +#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800
2547 +/** 8kHz backup interrupt derived from core-PLL
2548 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2549 +#define ICU0_IM1_IOSR_FSC_BKP 0x00000400
2550 +/* Nothing
2551 +#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */
2552 +/** Read: Interrupt occurred. */
2553 +#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400
2554 +/** External Interrupt from GPIO P4
2555 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2556 +#define ICU0_IM1_IOSR_P4 0x00000100
2557 +/* Nothing
2558 +#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */
2559 +/** Read: Interrupt occurred. */
2560 +#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100
2561 +/** External Interrupt from GPIO P3
2562 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2563 +#define ICU0_IM1_IOSR_P3 0x00000080
2564 +/* Nothing
2565 +#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */
2566 +/** Read: Interrupt occurred. */
2567 +#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080
2568 +/** External Interrupt from GPIO P2
2569 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2570 +#define ICU0_IM1_IOSR_P2 0x00000040
2571 +/* Nothing
2572 +#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */
2573 +/** Read: Interrupt occurred. */
2574 +#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040
2575 +/** External Interrupt from GPIO P1
2576 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2577 +#define ICU0_IM1_IOSR_P1 0x00000020
2578 +/* Nothing
2579 +#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */
2580 +/** Read: Interrupt occurred. */
2581 +#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020
2582 +/** External Interrupt from GPIO P0
2583 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2584 +#define ICU0_IM1_IOSR_P0 0x00000010
2585 +/* Nothing
2586 +#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */
2587 +/** Read: Interrupt occurred. */
2588 +#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010
2589 +/** EBU Serial Flash Busy
2590 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2591 +#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004
2592 +/* Nothing
2593 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */
2594 +/** Read: Interrupt occurred. */
2595 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004
2596 +/** EBU Serial Flash Command Overwrite Error
2597 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2598 +#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002
2599 +/* Nothing
2600 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */
2601 +/** Read: Interrupt occurred. */
2602 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002
2603 +/** EBU Serial Flash Command Error
2604 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2605 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001
2606 +/* Nothing
2607 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */
2608 +/** Read: Interrupt occurred. */
2609 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001
2610 +
2611 +/* Fields of "IM1 Interrupt Request Set Register" */
2612 +/** Crossbar Error Interrupt
2613 +    Software control for the corresponding bit in the IM1_ISR register. */
2614 +#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000
2615 +/** DDR Controller Interrupt
2616 +    Software control for the corresponding bit in the IM1_ISR register. */
2617 +#define ICU0_IM1_IRSR_DDR 0x40000000
2618 +/** FPI Bus Control Unit Interrupt
2619 +    Software control for the corresponding bit in the IM1_ISR register. */
2620 +#define ICU0_IM1_IRSR_BCU0 0x20000000
2621 +/** SBIU interrupt
2622 +    Software control for the corresponding bit in the IM1_ISR register. */
2623 +#define ICU0_IM1_IRSR_SBIU0 0x08000000
2624 +/** Watchdog Prewarning Interrupt
2625 +    Software control for the corresponding bit in the IM1_ISR register. */
2626 +#define ICU0_IM1_IRSR_WDT_PIR 0x02000000
2627 +/** Watchdog Access Error Interrupt
2628 +    Software control for the corresponding bit in the IM1_ISR register. */
2629 +#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000
2630 +/** SYS GPE Interrupt
2631 +    Software control for the corresponding bit in the IM1_ISR register. */
2632 +#define ICU0_IM1_IRSR_SYS_GPE 0x00200000
2633 +/** SYS1 Interrupt
2634 +    Software control for the corresponding bit in the IM1_ISR register. */
2635 +#define ICU0_IM1_IRSR_SYS1 0x00100000
2636 +/** PMA Interrupt from IntNode of the RX Clk Domain
2637 +    Software control for the corresponding bit in the IM1_ISR register. */
2638 +#define ICU0_IM1_IRSR_PMA_RX 0x00020000
2639 +/** PMA Interrupt from IntNode of the TX Clk Domain
2640 +    Software control for the corresponding bit in the IM1_ISR register. */
2641 +#define ICU0_IM1_IRSR_PMA_TX 0x00010000
2642 +/** PMA Interrupt from IntNode of the 200MHz Domain
2643 +    Software control for the corresponding bit in the IM1_ISR register. */
2644 +#define ICU0_IM1_IRSR_PMA_200M 0x00008000
2645 +/** Time of Day
2646 +    Software control for the corresponding bit in the IM1_ISR register. */
2647 +#define ICU0_IM1_IRSR_TOD 0x00004000
2648 +/** 8kHz root interrupt derived from GPON interface
2649 +    Software control for the corresponding bit in the IM1_ISR register. */
2650 +#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000
2651 +/** FSC Timer Interrupt 1
2652 +    Software control for the corresponding bit in the IM1_ISR register. */
2653 +#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000
2654 +/** FSC Timer Interrupt 0
2655 +    Software control for the corresponding bit in the IM1_ISR register. */
2656 +#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800
2657 +/** 8kHz backup interrupt derived from core-PLL
2658 +    Software control for the corresponding bit in the IM1_ISR register. */
2659 +#define ICU0_IM1_IRSR_FSC_BKP 0x00000400
2660 +/** External Interrupt from GPIO P4
2661 +    Software control for the corresponding bit in the IM1_ISR register. */
2662 +#define ICU0_IM1_IRSR_P4 0x00000100
2663 +/** External Interrupt from GPIO P3
2664 +    Software control for the corresponding bit in the IM1_ISR register. */
2665 +#define ICU0_IM1_IRSR_P3 0x00000080
2666 +/** External Interrupt from GPIO P2
2667 +    Software control for the corresponding bit in the IM1_ISR register. */
2668 +#define ICU0_IM1_IRSR_P2 0x00000040
2669 +/** External Interrupt from GPIO P1
2670 +    Software control for the corresponding bit in the IM1_ISR register. */
2671 +#define ICU0_IM1_IRSR_P1 0x00000020
2672 +/** External Interrupt from GPIO P0
2673 +    Software control for the corresponding bit in the IM1_ISR register. */
2674 +#define ICU0_IM1_IRSR_P0 0x00000010
2675 +/** EBU Serial Flash Busy
2676 +    Software control for the corresponding bit in the IM1_ISR register. */
2677 +#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004
2678 +/** EBU Serial Flash Command Overwrite Error
2679 +    Software control for the corresponding bit in the IM1_ISR register. */
2680 +#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002
2681 +/** EBU Serial Flash Command Error
2682 +    Software control for the corresponding bit in the IM1_ISR register. */
2683 +#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001
2684 +
2685 +/* Fields of "IM1 Interrupt Mode Register" */
2686 +/** Crossbar Error Interrupt
2687 +    Type of interrupt. */
2688 +#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000
2689 +/* Indirect Interrupt.
2690 +#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */
2691 +/** Direct Interrupt. */
2692 +#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000
2693 +/** DDR Controller Interrupt
2694 +    Type of interrupt. */
2695 +#define ICU0_IM1_IMR_DDR 0x40000000
2696 +/* Indirect Interrupt.
2697 +#define ICU0_IM1_IMR_DDR_IND 0x00000000 */
2698 +/** Direct Interrupt. */
2699 +#define ICU0_IM1_IMR_DDR_DIR 0x40000000
2700 +/** FPI Bus Control Unit Interrupt
2701 +    Type of interrupt. */
2702 +#define ICU0_IM1_IMR_BCU0 0x20000000
2703 +/* Indirect Interrupt.
2704 +#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */
2705 +/** Direct Interrupt. */
2706 +#define ICU0_IM1_IMR_BCU0_DIR 0x20000000
2707 +/** SBIU interrupt
2708 +    Type of interrupt. */
2709 +#define ICU0_IM1_IMR_SBIU0 0x08000000
2710 +/* Indirect Interrupt.
2711 +#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */
2712 +/** Direct Interrupt. */
2713 +#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000
2714 +/** Watchdog Prewarning Interrupt
2715 +    Type of interrupt. */
2716 +#define ICU0_IM1_IMR_WDT_PIR 0x02000000
2717 +/* Indirect Interrupt.
2718 +#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */
2719 +/** Direct Interrupt. */
2720 +#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000
2721 +/** Watchdog Access Error Interrupt
2722 +    Type of interrupt. */
2723 +#define ICU0_IM1_IMR_WDT_AEIR 0x01000000
2724 +/* Indirect Interrupt.
2725 +#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */
2726 +/** Direct Interrupt. */
2727 +#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000
2728 +/** SYS GPE Interrupt
2729 +    Type of interrupt. */
2730 +#define ICU0_IM1_IMR_SYS_GPE 0x00200000
2731 +/* Indirect Interrupt.
2732 +#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */
2733 +/** Direct Interrupt. */
2734 +#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000
2735 +/** SYS1 Interrupt
2736 +    Type of interrupt. */
2737 +#define ICU0_IM1_IMR_SYS1 0x00100000
2738 +/* Indirect Interrupt.
2739 +#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */
2740 +/** Direct Interrupt. */
2741 +#define ICU0_IM1_IMR_SYS1_DIR 0x00100000
2742 +/** PMA Interrupt from IntNode of the RX Clk Domain
2743 +    Type of interrupt. */
2744 +#define ICU0_IM1_IMR_PMA_RX 0x00020000
2745 +/* Indirect Interrupt.
2746 +#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */
2747 +/** Direct Interrupt. */
2748 +#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000
2749 +/** PMA Interrupt from IntNode of the TX Clk Domain
2750 +    Type of interrupt. */
2751 +#define ICU0_IM1_IMR_PMA_TX 0x00010000
2752 +/* Indirect Interrupt.
2753 +#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */
2754 +/** Direct Interrupt. */
2755 +#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000
2756 +/** PMA Interrupt from IntNode of the 200MHz Domain
2757 +    Type of interrupt. */
2758 +#define ICU0_IM1_IMR_PMA_200M 0x00008000
2759 +/* Indirect Interrupt.
2760 +#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */
2761 +/** Direct Interrupt. */
2762 +#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000
2763 +/** Time of Day
2764 +    Type of interrupt. */
2765 +#define ICU0_IM1_IMR_TOD 0x00004000
2766 +/* Indirect Interrupt.
2767 +#define ICU0_IM1_IMR_TOD_IND 0x00000000 */
2768 +/** Direct Interrupt. */
2769 +#define ICU0_IM1_IMR_TOD_DIR 0x00004000
2770 +/** 8kHz root interrupt derived from GPON interface
2771 +    Type of interrupt. */
2772 +#define ICU0_IM1_IMR_FSC_ROOT 0x00002000
2773 +/* Indirect Interrupt.
2774 +#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */
2775 +/** Direct Interrupt. */
2776 +#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000
2777 +/** FSC Timer Interrupt 1
2778 +    Type of interrupt. */
2779 +#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000
2780 +/* Indirect Interrupt.
2781 +#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */
2782 +/** Direct Interrupt. */
2783 +#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000
2784 +/** FSC Timer Interrupt 0
2785 +    Type of interrupt. */
2786 +#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800
2787 +/* Indirect Interrupt.
2788 +#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */
2789 +/** Direct Interrupt. */
2790 +#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800
2791 +/** 8kHz backup interrupt derived from core-PLL
2792 +    Type of interrupt. */
2793 +#define ICU0_IM1_IMR_FSC_BKP 0x00000400
2794 +/* Indirect Interrupt.
2795 +#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */
2796 +/** Direct Interrupt. */
2797 +#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400
2798 +/** External Interrupt from GPIO P4
2799 +    Type of interrupt. */
2800 +#define ICU0_IM1_IMR_P4 0x00000100
2801 +/* Indirect Interrupt.
2802 +#define ICU0_IM1_IMR_P4_IND 0x00000000 */
2803 +/** Direct Interrupt. */
2804 +#define ICU0_IM1_IMR_P4_DIR 0x00000100
2805 +/** External Interrupt from GPIO P3
2806 +    Type of interrupt. */
2807 +#define ICU0_IM1_IMR_P3 0x00000080
2808 +/* Indirect Interrupt.
2809 +#define ICU0_IM1_IMR_P3_IND 0x00000000 */
2810 +/** Direct Interrupt. */
2811 +#define ICU0_IM1_IMR_P3_DIR 0x00000080
2812 +/** External Interrupt from GPIO P2
2813 +    Type of interrupt. */
2814 +#define ICU0_IM1_IMR_P2 0x00000040
2815 +/* Indirect Interrupt.
2816 +#define ICU0_IM1_IMR_P2_IND 0x00000000 */
2817 +/** Direct Interrupt. */
2818 +#define ICU0_IM1_IMR_P2_DIR 0x00000040
2819 +/** External Interrupt from GPIO P1
2820 +    Type of interrupt. */
2821 +#define ICU0_IM1_IMR_P1 0x00000020
2822 +/* Indirect Interrupt.
2823 +#define ICU0_IM1_IMR_P1_IND 0x00000000 */
2824 +/** Direct Interrupt. */
2825 +#define ICU0_IM1_IMR_P1_DIR 0x00000020
2826 +/** External Interrupt from GPIO P0
2827 +    Type of interrupt. */
2828 +#define ICU0_IM1_IMR_P0 0x00000010
2829 +/* Indirect Interrupt.
2830 +#define ICU0_IM1_IMR_P0_IND 0x00000000 */
2831 +/** Direct Interrupt. */
2832 +#define ICU0_IM1_IMR_P0_DIR 0x00000010
2833 +/** EBU Serial Flash Busy
2834 +    Type of interrupt. */
2835 +#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004
2836 +/* Indirect Interrupt.
2837 +#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */
2838 +/** Direct Interrupt. */
2839 +#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004
2840 +/** EBU Serial Flash Command Overwrite Error
2841 +    Type of interrupt. */
2842 +#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002
2843 +/* Indirect Interrupt.
2844 +#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */
2845 +/** Direct Interrupt. */
2846 +#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002
2847 +/** EBU Serial Flash Command Error
2848 +    Type of interrupt. */
2849 +#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001
2850 +/* Indirect Interrupt.
2851 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */
2852 +/** Direct Interrupt. */
2853 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001
2854 +
2855 +/* Fields of "IM2 Interrupt Status Register" */
2856 +/** EIM Interrupt
2857 +    This bit is an indirect interrupt. */
2858 +#define ICU0_IM2_ISR_EIM 0x80000000
2859 +/* Nothing
2860 +#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */
2861 +/** Write: Acknowledge the interrupt. */
2862 +#define ICU0_IM2_ISR_EIM_INTACK 0x80000000
2863 +/** Read: Interrupt occurred. */
2864 +#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000
2865 +/** GTC Upstream Interrupt
2866 +    This bit is an indirect interrupt. */
2867 +#define ICU0_IM2_ISR_GTC_US 0x40000000
2868 +/* Nothing
2869 +#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */
2870 +/** Write: Acknowledge the interrupt. */
2871 +#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000
2872 +/** Read: Interrupt occurred. */
2873 +#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000
2874 +/** GTC Downstream Interrupt
2875 +    This bit is an indirect interrupt. */
2876 +#define ICU0_IM2_ISR_GTC_DS 0x20000000
2877 +/* Nothing
2878 +#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */
2879 +/** Write: Acknowledge the interrupt. */
2880 +#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000
2881 +/** Read: Interrupt occurred. */
2882 +#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000
2883 +/** TBM Interrupt
2884 +    This bit is an indirect interrupt. */
2885 +#define ICU0_IM2_ISR_TBM 0x00400000
2886 +/* Nothing
2887 +#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */
2888 +/** Write: Acknowledge the interrupt. */
2889 +#define ICU0_IM2_ISR_TBM_INTACK 0x00400000
2890 +/** Read: Interrupt occurred. */
2891 +#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000
2892 +/** Dispatcher Interrupt
2893 +    This bit is an indirect interrupt. */
2894 +#define ICU0_IM2_ISR_DISP 0x00200000
2895 +/* Nothing
2896 +#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */
2897 +/** Write: Acknowledge the interrupt. */
2898 +#define ICU0_IM2_ISR_DISP_INTACK 0x00200000
2899 +/** Read: Interrupt occurred. */
2900 +#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000
2901 +/** CONFIG Interrupt
2902 +    This bit is an indirect interrupt. */
2903 +#define ICU0_IM2_ISR_CONFIG 0x00100000
2904 +/* Nothing
2905 +#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */
2906 +/** Write: Acknowledge the interrupt. */
2907 +#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000
2908 +/** Read: Interrupt occurred. */
2909 +#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000
2910 +/** CONFIG Break Interrupt
2911 +    This bit is an indirect interrupt. */
2912 +#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000
2913 +/* Nothing
2914 +#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */
2915 +/** Write: Acknowledge the interrupt. */
2916 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000
2917 +/** Read: Interrupt occurred. */
2918 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000
2919 +/** OCTRLC Interrupt
2920 +    This bit is an indirect interrupt. */
2921 +#define ICU0_IM2_ISR_OCTRLC 0x00040000
2922 +/* Nothing
2923 +#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */
2924 +/** Write: Acknowledge the interrupt. */
2925 +#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000
2926 +/** Read: Interrupt occurred. */
2927 +#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000
2928 +/** ICTRLC 1 Interrupt
2929 +    This bit is an indirect interrupt. */
2930 +#define ICU0_IM2_ISR_ICTRLC1 0x00020000
2931 +/* Nothing
2932 +#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */
2933 +/** Write: Acknowledge the interrupt. */
2934 +#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000
2935 +/** Read: Interrupt occurred. */
2936 +#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000
2937 +/** ICTRLC 0 Interrupt
2938 +    This bit is an indirect interrupt. */
2939 +#define ICU0_IM2_ISR_ICTRLC0 0x00010000
2940 +/* Nothing
2941 +#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */
2942 +/** Write: Acknowledge the interrupt. */
2943 +#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000
2944 +/** Read: Interrupt occurred. */
2945 +#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000
2946 +/** LINK 1 Interrupt
2947 +    This bit is an indirect interrupt. */
2948 +#define ICU0_IM2_ISR_LINK1 0x00004000
2949 +/* Nothing
2950 +#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */
2951 +/** Write: Acknowledge the interrupt. */
2952 +#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000
2953 +/** Read: Interrupt occurred. */
2954 +#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000
2955 +/** TMU Interrupt
2956 +    This bit is an indirect interrupt. */
2957 +#define ICU0_IM2_ISR_TMU 0x00001000
2958 +/* Nothing
2959 +#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */
2960 +/** Write: Acknowledge the interrupt. */
2961 +#define ICU0_IM2_ISR_TMU_INTACK 0x00001000
2962 +/** Read: Interrupt occurred. */
2963 +#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000
2964 +/** FSQM Interrupt
2965 +    This bit is an indirect interrupt. */
2966 +#define ICU0_IM2_ISR_FSQM 0x00000800
2967 +/* Nothing
2968 +#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */
2969 +/** Write: Acknowledge the interrupt. */
2970 +#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800
2971 +/** Read: Interrupt occurred. */
2972 +#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800
2973 +/** IQM Interrupt
2974 +    This bit is an indirect interrupt. */
2975 +#define ICU0_IM2_ISR_IQM 0x00000400
2976 +/* Nothing
2977 +#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */
2978 +/** Write: Acknowledge the interrupt. */
2979 +#define ICU0_IM2_ISR_IQM_INTACK 0x00000400
2980 +/** Read: Interrupt occurred. */
2981 +#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400
2982 +/** OCTRLG Interrupt
2983 +    This bit is an indirect interrupt. */
2984 +#define ICU0_IM2_ISR_OCTRLG 0x00000200
2985 +/* Nothing
2986 +#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */
2987 +/** Write: Acknowledge the interrupt. */
2988 +#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200
2989 +/** Read: Interrupt occurred. */
2990 +#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200
2991 +/** OCTRLL 3 Interrupt
2992 +    This bit is an indirect interrupt. */
2993 +#define ICU0_IM2_ISR_OCTRLL3 0x00000080
2994 +/* Nothing
2995 +#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */
2996 +/** Write: Acknowledge the interrupt. */
2997 +#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080
2998 +/** Read: Interrupt occurred. */
2999 +#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080
3000 +/** OCTRLL 2 Interrupt
3001 +    This bit is an indirect interrupt. */
3002 +#define ICU0_IM2_ISR_OCTRLL2 0x00000040
3003 +/* Nothing
3004 +#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */
3005 +/** Write: Acknowledge the interrupt. */
3006 +#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040
3007 +/** Read: Interrupt occurred. */
3008 +#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040
3009 +/** OCTRLL 1 Interrupt
3010 +    This bit is an indirect interrupt. */
3011 +#define ICU0_IM2_ISR_OCTRLL1 0x00000020
3012 +/* Nothing
3013 +#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */
3014 +/** Write: Acknowledge the interrupt. */
3015 +#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020
3016 +/** Read: Interrupt occurred. */
3017 +#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020
3018 +/** OCTRLL 0 Interrupt
3019 +    This bit is an indirect interrupt. */
3020 +#define ICU0_IM2_ISR_OCTRLL0 0x00000010
3021 +/* Nothing
3022 +#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */
3023 +/** Write: Acknowledge the interrupt. */
3024 +#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010
3025 +/** Read: Interrupt occurred. */
3026 +#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010
3027 +/** ICTRLL 3 Interrupt
3028 +    This bit is an indirect interrupt. */
3029 +#define ICU0_IM2_ISR_ICTRLL3 0x00000008
3030 +/* Nothing
3031 +#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */
3032 +/** Write: Acknowledge the interrupt. */
3033 +#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008
3034 +/** Read: Interrupt occurred. */
3035 +#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008
3036 +/** ICTRLL 2 Interrupt
3037 +    This bit is an indirect interrupt. */
3038 +#define ICU0_IM2_ISR_ICTRLL2 0x00000004
3039 +/* Nothing
3040 +#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */
3041 +/** Write: Acknowledge the interrupt. */
3042 +#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004
3043 +/** Read: Interrupt occurred. */
3044 +#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004
3045 +/** ICTRLL 1 Interrupt
3046 +    This bit is an indirect interrupt. */
3047 +#define ICU0_IM2_ISR_ICTRLL1 0x00000002
3048 +/* Nothing
3049 +#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */
3050 +/** Write: Acknowledge the interrupt. */
3051 +#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002
3052 +/** Read: Interrupt occurred. */
3053 +#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002
3054 +/** ICTRLL 0 Interrupt
3055 +    This bit is an indirect interrupt. */
3056 +#define ICU0_IM2_ISR_ICTRLL0 0x00000001
3057 +/* Nothing
3058 +#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */
3059 +/** Write: Acknowledge the interrupt. */
3060 +#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001
3061 +/** Read: Interrupt occurred. */
3062 +#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001
3063 +
3064 +/* Fields of "IM2 Interrupt Enable Register" */
3065 +/** EIM Interrupt
3066 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3067 +#define ICU0_IM2_IER_EIM 0x80000000
3068 +/* Disable
3069 +#define ICU0_IM2_IER_EIM_DIS 0x00000000 */
3070 +/** Enable */
3071 +#define ICU0_IM2_IER_EIM_EN 0x80000000
3072 +/** GTC Upstream Interrupt
3073 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3074 +#define ICU0_IM2_IER_GTC_US 0x40000000
3075 +/* Disable
3076 +#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */
3077 +/** Enable */
3078 +#define ICU0_IM2_IER_GTC_US_EN 0x40000000
3079 +/** GTC Downstream Interrupt
3080 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3081 +#define ICU0_IM2_IER_GTC_DS 0x20000000
3082 +/* Disable
3083 +#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */
3084 +/** Enable */
3085 +#define ICU0_IM2_IER_GTC_DS_EN 0x20000000
3086 +/** TBM Interrupt
3087 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3088 +#define ICU0_IM2_IER_TBM 0x00400000
3089 +/* Disable
3090 +#define ICU0_IM2_IER_TBM_DIS 0x00000000 */
3091 +/** Enable */
3092 +#define ICU0_IM2_IER_TBM_EN 0x00400000
3093 +/** Dispatcher Interrupt
3094 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3095 +#define ICU0_IM2_IER_DISP 0x00200000
3096 +/* Disable
3097 +#define ICU0_IM2_IER_DISP_DIS 0x00000000 */
3098 +/** Enable */
3099 +#define ICU0_IM2_IER_DISP_EN 0x00200000
3100 +/** CONFIG Interrupt
3101 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3102 +#define ICU0_IM2_IER_CONFIG 0x00100000
3103 +/* Disable
3104 +#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */
3105 +/** Enable */
3106 +#define ICU0_IM2_IER_CONFIG_EN 0x00100000
3107 +/** CONFIG Break Interrupt
3108 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3109 +#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000
3110 +/* Disable
3111 +#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */
3112 +/** Enable */
3113 +#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000
3114 +/** OCTRLC Interrupt
3115 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3116 +#define ICU0_IM2_IER_OCTRLC 0x00040000
3117 +/* Disable
3118 +#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */
3119 +/** Enable */
3120 +#define ICU0_IM2_IER_OCTRLC_EN 0x00040000
3121 +/** ICTRLC 1 Interrupt
3122 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3123 +#define ICU0_IM2_IER_ICTRLC1 0x00020000
3124 +/* Disable
3125 +#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */
3126 +/** Enable */
3127 +#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000
3128 +/** ICTRLC 0 Interrupt
3129 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3130 +#define ICU0_IM2_IER_ICTRLC0 0x00010000
3131 +/* Disable
3132 +#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */
3133 +/** Enable */
3134 +#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000
3135 +/** LINK 1 Interrupt
3136 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3137 +#define ICU0_IM2_IER_LINK1 0x00004000
3138 +/* Disable
3139 +#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */
3140 +/** Enable */
3141 +#define ICU0_IM2_IER_LINK1_EN 0x00004000
3142 +/** TMU Interrupt
3143 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3144 +#define ICU0_IM2_IER_TMU 0x00001000
3145 +/* Disable
3146 +#define ICU0_IM2_IER_TMU_DIS 0x00000000 */
3147 +/** Enable */
3148 +#define ICU0_IM2_IER_TMU_EN 0x00001000
3149 +/** FSQM Interrupt
3150 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3151 +#define ICU0_IM2_IER_FSQM 0x00000800
3152 +/* Disable
3153 +#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */
3154 +/** Enable */
3155 +#define ICU0_IM2_IER_FSQM_EN 0x00000800
3156 +/** IQM Interrupt
3157 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3158 +#define ICU0_IM2_IER_IQM 0x00000400
3159 +/* Disable
3160 +#define ICU0_IM2_IER_IQM_DIS 0x00000000 */
3161 +/** Enable */
3162 +#define ICU0_IM2_IER_IQM_EN 0x00000400
3163 +/** OCTRLG Interrupt
3164 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3165 +#define ICU0_IM2_IER_OCTRLG 0x00000200
3166 +/* Disable
3167 +#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */
3168 +/** Enable */
3169 +#define ICU0_IM2_IER_OCTRLG_EN 0x00000200
3170 +/** OCTRLL 3 Interrupt
3171 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3172 +#define ICU0_IM2_IER_OCTRLL3 0x00000080
3173 +/* Disable
3174 +#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */
3175 +/** Enable */
3176 +#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080
3177 +/** OCTRLL 2 Interrupt
3178 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3179 +#define ICU0_IM2_IER_OCTRLL2 0x00000040
3180 +/* Disable
3181 +#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */
3182 +/** Enable */
3183 +#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040
3184 +/** OCTRLL 1 Interrupt
3185 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3186 +#define ICU0_IM2_IER_OCTRLL1 0x00000020
3187 +/* Disable
3188 +#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */
3189 +/** Enable */
3190 +#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020
3191 +/** OCTRLL 0 Interrupt
3192 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3193 +#define ICU0_IM2_IER_OCTRLL0 0x00000010
3194 +/* Disable
3195 +#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */
3196 +/** Enable */
3197 +#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010
3198 +/** ICTRLL 3 Interrupt
3199 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3200 +#define ICU0_IM2_IER_ICTRLL3 0x00000008
3201 +/* Disable
3202 +#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */
3203 +/** Enable */
3204 +#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008
3205 +/** ICTRLL 2 Interrupt
3206 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3207 +#define ICU0_IM2_IER_ICTRLL2 0x00000004
3208 +/* Disable
3209 +#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */
3210 +/** Enable */
3211 +#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004
3212 +/** ICTRLL 1 Interrupt
3213 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3214 +#define ICU0_IM2_IER_ICTRLL1 0x00000002
3215 +/* Disable
3216 +#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */
3217 +/** Enable */
3218 +#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002
3219 +/** ICTRLL 0 Interrupt
3220 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3221 +#define ICU0_IM2_IER_ICTRLL0 0x00000001
3222 +/* Disable
3223 +#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */
3224 +/** Enable */
3225 +#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001
3226 +
3227 +/* Fields of "IM2 Interrupt Output Status Register" */
3228 +/** EIM Interrupt
3229 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3230 +#define ICU0_IM2_IOSR_EIM 0x80000000
3231 +/* Nothing
3232 +#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */
3233 +/** Read: Interrupt occurred. */
3234 +#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000
3235 +/** GTC Upstream Interrupt
3236 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3237 +#define ICU0_IM2_IOSR_GTC_US 0x40000000
3238 +/* Nothing
3239 +#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */
3240 +/** Read: Interrupt occurred. */
3241 +#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000
3242 +/** GTC Downstream Interrupt
3243 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3244 +#define ICU0_IM2_IOSR_GTC_DS 0x20000000
3245 +/* Nothing
3246 +#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */
3247 +/** Read: Interrupt occurred. */
3248 +#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000
3249 +/** TBM Interrupt
3250 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3251 +#define ICU0_IM2_IOSR_TBM 0x00400000
3252 +/* Nothing
3253 +#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */
3254 +/** Read: Interrupt occurred. */
3255 +#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000
3256 +/** Dispatcher Interrupt
3257 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3258 +#define ICU0_IM2_IOSR_DISP 0x00200000
3259 +/* Nothing
3260 +#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */
3261 +/** Read: Interrupt occurred. */
3262 +#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000
3263 +/** CONFIG Interrupt
3264 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3265 +#define ICU0_IM2_IOSR_CONFIG 0x00100000
3266 +/* Nothing
3267 +#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */
3268 +/** Read: Interrupt occurred. */
3269 +#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000
3270 +/** CONFIG Break Interrupt
3271 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3272 +#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000
3273 +/* Nothing
3274 +#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */
3275 +/** Read: Interrupt occurred. */
3276 +#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000
3277 +/** OCTRLC Interrupt
3278 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3279 +#define ICU0_IM2_IOSR_OCTRLC 0x00040000
3280 +/* Nothing
3281 +#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */
3282 +/** Read: Interrupt occurred. */
3283 +#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000
3284 +/** ICTRLC 1 Interrupt
3285 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3286 +#define ICU0_IM2_IOSR_ICTRLC1 0x00020000
3287 +/* Nothing
3288 +#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */
3289 +/** Read: Interrupt occurred. */
3290 +#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000
3291 +/** ICTRLC 0 Interrupt
3292 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3293 +#define ICU0_IM2_IOSR_ICTRLC0 0x00010000
3294 +/* Nothing
3295 +#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */
3296 +/** Read: Interrupt occurred. */
3297 +#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000
3298 +/** LINK 1 Interrupt
3299 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3300 +#define ICU0_IM2_IOSR_LINK1 0x00004000
3301 +/* Nothing
3302 +#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */
3303 +/** Read: Interrupt occurred. */
3304 +#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000
3305 +/** TMU Interrupt
3306 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3307 +#define ICU0_IM2_IOSR_TMU 0x00001000
3308 +/* Nothing
3309 +#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */
3310 +/** Read: Interrupt occurred. */
3311 +#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000
3312 +/** FSQM Interrupt
3313 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3314 +#define ICU0_IM2_IOSR_FSQM 0x00000800
3315 +/* Nothing
3316 +#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */
3317 +/** Read: Interrupt occurred. */
3318 +#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800
3319 +/** IQM Interrupt
3320 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3321 +#define ICU0_IM2_IOSR_IQM 0x00000400
3322 +/* Nothing
3323 +#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */
3324 +/** Read: Interrupt occurred. */
3325 +#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400
3326 +/** OCTRLG Interrupt
3327 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3328 +#define ICU0_IM2_IOSR_OCTRLG 0x00000200
3329 +/* Nothing
3330 +#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */
3331 +/** Read: Interrupt occurred. */
3332 +#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200
3333 +/** OCTRLL 3 Interrupt
3334 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3335 +#define ICU0_IM2_IOSR_OCTRLL3 0x00000080
3336 +/* Nothing
3337 +#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */
3338 +/** Read: Interrupt occurred. */
3339 +#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080
3340 +/** OCTRLL 2 Interrupt
3341 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3342 +#define ICU0_IM2_IOSR_OCTRLL2 0x00000040
3343 +/* Nothing
3344 +#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */
3345 +/** Read: Interrupt occurred. */
3346 +#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040
3347 +/** OCTRLL 1 Interrupt
3348 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3349 +#define ICU0_IM2_IOSR_OCTRLL1 0x00000020
3350 +/* Nothing
3351 +#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */
3352 +/** Read: Interrupt occurred. */
3353 +#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020
3354 +/** OCTRLL 0 Interrupt
3355 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3356 +#define ICU0_IM2_IOSR_OCTRLL0 0x00000010
3357 +/* Nothing
3358 +#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */
3359 +/** Read: Interrupt occurred. */
3360 +#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010
3361 +/** ICTRLL 3 Interrupt
3362 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3363 +#define ICU0_IM2_IOSR_ICTRLL3 0x00000008
3364 +/* Nothing
3365 +#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */
3366 +/** Read: Interrupt occurred. */
3367 +#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008
3368 +/** ICTRLL 2 Interrupt
3369 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3370 +#define ICU0_IM2_IOSR_ICTRLL2 0x00000004
3371 +/* Nothing
3372 +#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */
3373 +/** Read: Interrupt occurred. */
3374 +#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004
3375 +/** ICTRLL 1 Interrupt
3376 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3377 +#define ICU0_IM2_IOSR_ICTRLL1 0x00000002
3378 +/* Nothing
3379 +#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */
3380 +/** Read: Interrupt occurred. */
3381 +#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002
3382 +/** ICTRLL 0 Interrupt
3383 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3384 +#define ICU0_IM2_IOSR_ICTRLL0 0x00000001
3385 +/* Nothing
3386 +#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */
3387 +/** Read: Interrupt occurred. */
3388 +#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001
3389 +
3390 +/* Fields of "IM2 Interrupt Request Set Register" */
3391 +/** EIM Interrupt
3392 +    Software control for the corresponding bit in the IM2_ISR register. */
3393 +#define ICU0_IM2_IRSR_EIM 0x80000000
3394 +/** GTC Upstream Interrupt
3395 +    Software control for the corresponding bit in the IM2_ISR register. */
3396 +#define ICU0_IM2_IRSR_GTC_US 0x40000000
3397 +/** GTC Downstream Interrupt
3398 +    Software control for the corresponding bit in the IM2_ISR register. */
3399 +#define ICU0_IM2_IRSR_GTC_DS 0x20000000
3400 +/** TBM Interrupt
3401 +    Software control for the corresponding bit in the IM2_ISR register. */
3402 +#define ICU0_IM2_IRSR_TBM 0x00400000
3403 +/** Dispatcher Interrupt
3404 +    Software control for the corresponding bit in the IM2_ISR register. */
3405 +#define ICU0_IM2_IRSR_DISP 0x00200000
3406 +/** CONFIG Interrupt
3407 +    Software control for the corresponding bit in the IM2_ISR register. */
3408 +#define ICU0_IM2_IRSR_CONFIG 0x00100000
3409 +/** CONFIG Break Interrupt
3410 +    Software control for the corresponding bit in the IM2_ISR register. */
3411 +#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000
3412 +/** OCTRLC Interrupt
3413 +    Software control for the corresponding bit in the IM2_ISR register. */
3414 +#define ICU0_IM2_IRSR_OCTRLC 0x00040000
3415 +/** ICTRLC 1 Interrupt
3416 +    Software control for the corresponding bit in the IM2_ISR register. */
3417 +#define ICU0_IM2_IRSR_ICTRLC1 0x00020000
3418 +/** ICTRLC 0 Interrupt
3419 +    Software control for the corresponding bit in the IM2_ISR register. */
3420 +#define ICU0_IM2_IRSR_ICTRLC0 0x00010000
3421 +/** LINK 1 Interrupt
3422 +    Software control for the corresponding bit in the IM2_ISR register. */
3423 +#define ICU0_IM2_IRSR_LINK1 0x00004000
3424 +/** TMU Interrupt
3425 +    Software control for the corresponding bit in the IM2_ISR register. */
3426 +#define ICU0_IM2_IRSR_TMU 0x00001000
3427 +/** FSQM Interrupt
3428 +    Software control for the corresponding bit in the IM2_ISR register. */
3429 +#define ICU0_IM2_IRSR_FSQM 0x00000800
3430 +/** IQM Interrupt
3431 +    Software control for the corresponding bit in the IM2_ISR register. */
3432 +#define ICU0_IM2_IRSR_IQM 0x00000400
3433 +/** OCTRLG Interrupt
3434 +    Software control for the corresponding bit in the IM2_ISR register. */
3435 +#define ICU0_IM2_IRSR_OCTRLG 0x00000200
3436 +/** OCTRLL 3 Interrupt
3437 +    Software control for the corresponding bit in the IM2_ISR register. */
3438 +#define ICU0_IM2_IRSR_OCTRLL3 0x00000080
3439 +/** OCTRLL 2 Interrupt
3440 +    Software control for the corresponding bit in the IM2_ISR register. */
3441 +#define ICU0_IM2_IRSR_OCTRLL2 0x00000040
3442 +/** OCTRLL 1 Interrupt
3443 +    Software control for the corresponding bit in the IM2_ISR register. */
3444 +#define ICU0_IM2_IRSR_OCTRLL1 0x00000020
3445 +/** OCTRLL 0 Interrupt
3446 +    Software control for the corresponding bit in the IM2_ISR register. */
3447 +#define ICU0_IM2_IRSR_OCTRLL0 0x00000010
3448 +/** ICTRLL 3 Interrupt
3449 +    Software control for the corresponding bit in the IM2_ISR register. */
3450 +#define ICU0_IM2_IRSR_ICTRLL3 0x00000008
3451 +/** ICTRLL 2 Interrupt
3452 +    Software control for the corresponding bit in the IM2_ISR register. */
3453 +#define ICU0_IM2_IRSR_ICTRLL2 0x00000004
3454 +/** ICTRLL 1 Interrupt
3455 +    Software control for the corresponding bit in the IM2_ISR register. */
3456 +#define ICU0_IM2_IRSR_ICTRLL1 0x00000002
3457 +/** ICTRLL 0 Interrupt
3458 +    Software control for the corresponding bit in the IM2_ISR register. */
3459 +#define ICU0_IM2_IRSR_ICTRLL0 0x00000001
3460 +
3461 +/* Fields of "IM2 Interrupt Mode Register" */
3462 +/** EIM Interrupt
3463 +    Type of interrupt. */
3464 +#define ICU0_IM2_IMR_EIM 0x80000000
3465 +/* Indirect Interrupt.
3466 +#define ICU0_IM2_IMR_EIM_IND 0x00000000 */
3467 +/** Direct Interrupt. */
3468 +#define ICU0_IM2_IMR_EIM_DIR 0x80000000
3469 +/** GTC Upstream Interrupt
3470 +    Type of interrupt. */
3471 +#define ICU0_IM2_IMR_GTC_US 0x40000000
3472 +/* Indirect Interrupt.
3473 +#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */
3474 +/** Direct Interrupt. */
3475 +#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000
3476 +/** GTC Downstream Interrupt
3477 +    Type of interrupt. */
3478 +#define ICU0_IM2_IMR_GTC_DS 0x20000000
3479 +/* Indirect Interrupt.
3480 +#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */
3481 +/** Direct Interrupt. */
3482 +#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000
3483 +/** TBM Interrupt
3484 +    Type of interrupt. */
3485 +#define ICU0_IM2_IMR_TBM 0x00400000
3486 +/* Indirect Interrupt.
3487 +#define ICU0_IM2_IMR_TBM_IND 0x00000000 */
3488 +/** Direct Interrupt. */
3489 +#define ICU0_IM2_IMR_TBM_DIR 0x00400000
3490 +/** Dispatcher Interrupt
3491 +    Type of interrupt. */
3492 +#define ICU0_IM2_IMR_DISP 0x00200000
3493 +/* Indirect Interrupt.
3494 +#define ICU0_IM2_IMR_DISP_IND 0x00000000 */
3495 +/** Direct Interrupt. */
3496 +#define ICU0_IM2_IMR_DISP_DIR 0x00200000
3497 +/** CONFIG Interrupt
3498 +    Type of interrupt. */
3499 +#define ICU0_IM2_IMR_CONFIG 0x00100000
3500 +/* Indirect Interrupt.
3501 +#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */
3502 +/** Direct Interrupt. */
3503 +#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000
3504 +/** CONFIG Break Interrupt
3505 +    Type of interrupt. */
3506 +#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000
3507 +/* Indirect Interrupt.
3508 +#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */
3509 +/** Direct Interrupt. */
3510 +#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000
3511 +/** OCTRLC Interrupt
3512 +    Type of interrupt. */
3513 +#define ICU0_IM2_IMR_OCTRLC 0x00040000
3514 +/* Indirect Interrupt.
3515 +#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */
3516 +/** Direct Interrupt. */
3517 +#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000
3518 +/** ICTRLC 1 Interrupt
3519 +    Type of interrupt. */
3520 +#define ICU0_IM2_IMR_ICTRLC1 0x00020000
3521 +/* Indirect Interrupt.
3522 +#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */
3523 +/** Direct Interrupt. */
3524 +#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000
3525 +/** ICTRLC 0 Interrupt
3526 +    Type of interrupt. */
3527 +#define ICU0_IM2_IMR_ICTRLC0 0x00010000
3528 +/* Indirect Interrupt.
3529 +#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */
3530 +/** Direct Interrupt. */
3531 +#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000
3532 +/** LINK 1 Interrupt
3533 +    Type of interrupt. */
3534 +#define ICU0_IM2_IMR_LINK1 0x00004000
3535 +/* Indirect Interrupt.
3536 +#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */
3537 +/** Direct Interrupt. */
3538 +#define ICU0_IM2_IMR_LINK1_DIR 0x00004000
3539 +/** TMU Interrupt
3540 +    Type of interrupt. */
3541 +#define ICU0_IM2_IMR_TMU 0x00001000
3542 +/* Indirect Interrupt.
3543 +#define ICU0_IM2_IMR_TMU_IND 0x00000000 */
3544 +/** Direct Interrupt. */
3545 +#define ICU0_IM2_IMR_TMU_DIR 0x00001000
3546 +/** FSQM Interrupt
3547 +    Type of interrupt. */
3548 +#define ICU0_IM2_IMR_FSQM 0x00000800
3549 +/* Indirect Interrupt.
3550 +#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */
3551 +/** Direct Interrupt. */
3552 +#define ICU0_IM2_IMR_FSQM_DIR 0x00000800
3553 +/** IQM Interrupt
3554 +    Type of interrupt. */
3555 +#define ICU0_IM2_IMR_IQM 0x00000400
3556 +/* Indirect Interrupt.
3557 +#define ICU0_IM2_IMR_IQM_IND 0x00000000 */
3558 +/** Direct Interrupt. */
3559 +#define ICU0_IM2_IMR_IQM_DIR 0x00000400
3560 +/** OCTRLG Interrupt
3561 +    Type of interrupt. */
3562 +#define ICU0_IM2_IMR_OCTRLG 0x00000200
3563 +/* Indirect Interrupt.
3564 +#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */
3565 +/** Direct Interrupt. */
3566 +#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200
3567 +/** OCTRLL 3 Interrupt
3568 +    Type of interrupt. */
3569 +#define ICU0_IM2_IMR_OCTRLL3 0x00000080
3570 +/* Indirect Interrupt.
3571 +#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */
3572 +/** Direct Interrupt. */
3573 +#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080
3574 +/** OCTRLL 2 Interrupt
3575 +    Type of interrupt. */
3576 +#define ICU0_IM2_IMR_OCTRLL2 0x00000040
3577 +/* Indirect Interrupt.
3578 +#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */
3579 +/** Direct Interrupt. */
3580 +#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040
3581 +/** OCTRLL 1 Interrupt
3582 +    Type of interrupt. */
3583 +#define ICU0_IM2_IMR_OCTRLL1 0x00000020
3584 +/* Indirect Interrupt.
3585 +#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */
3586 +/** Direct Interrupt. */
3587 +#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020
3588 +/** OCTRLL 0 Interrupt
3589 +    Type of interrupt. */
3590 +#define ICU0_IM2_IMR_OCTRLL0 0x00000010
3591 +/* Indirect Interrupt.
3592 +#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */
3593 +/** Direct Interrupt. */
3594 +#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010
3595 +/** ICTRLL 3 Interrupt
3596 +    Type of interrupt. */
3597 +#define ICU0_IM2_IMR_ICTRLL3 0x00000008
3598 +/* Indirect Interrupt.
3599 +#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */
3600 +/** Direct Interrupt. */
3601 +#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008
3602 +/** ICTRLL 2 Interrupt
3603 +    Type of interrupt. */
3604 +#define ICU0_IM2_IMR_ICTRLL2 0x00000004
3605 +/* Indirect Interrupt.
3606 +#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */
3607 +/** Direct Interrupt. */
3608 +#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004
3609 +/** ICTRLL 1 Interrupt
3610 +    Type of interrupt. */
3611 +#define ICU0_IM2_IMR_ICTRLL1 0x00000002
3612 +/* Indirect Interrupt.
3613 +#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */
3614 +/** Direct Interrupt. */
3615 +#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002
3616 +/** ICTRLL 0 Interrupt
3617 +    Type of interrupt. */
3618 +#define ICU0_IM2_IMR_ICTRLL0 0x00000001
3619 +/* Indirect Interrupt.
3620 +#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */
3621 +/** Direct Interrupt. */
3622 +#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001
3623 +
3624 +/* Fields of "IM3 Interrupt Status Register" */
3625 +/** DFEV0, Channel 0 General Purpose Interrupt
3626 +    This bit is an indirect interrupt. */
3627 +#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000
3628 +/* Nothing
3629 +#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */
3630 +/** Write: Acknowledge the interrupt. */
3631 +#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000
3632 +/** Read: Interrupt occurred. */
3633 +#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000
3634 +/** DFEV0, Channel 0 Receive Interrupt
3635 +    This bit is an indirect interrupt. */
3636 +#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000
3637 +/* Nothing
3638 +#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */
3639 +/** Write: Acknowledge the interrupt. */
3640 +#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000
3641 +/** Read: Interrupt occurred. */
3642 +#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000
3643 +/** DFEV0, Channel 0 Transmit Interrupt
3644 +    This bit is an indirect interrupt. */
3645 +#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000
3646 +/* Nothing
3647 +#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */
3648 +/** Write: Acknowledge the interrupt. */
3649 +#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000
3650 +/** Read: Interrupt occurred. */
3651 +#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000
3652 +/** DFEV0, Channel 1 General Purpose Interrupt
3653 +    This bit is an indirect interrupt. */
3654 +#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000
3655 +/* Nothing
3656 +#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */
3657 +/** Write: Acknowledge the interrupt. */
3658 +#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000
3659 +/** Read: Interrupt occurred. */
3660 +#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000
3661 +/** DFEV0, Channel 1 Receive Interrupt
3662 +    This bit is an indirect interrupt. */
3663 +#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000
3664 +/* Nothing
3665 +#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */
3666 +/** Write: Acknowledge the interrupt. */
3667 +#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000
3668 +/** Read: Interrupt occurred. */
3669 +#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000
3670 +/** DFEV0, Channel 1 Transmit Interrupt
3671 +    This bit is an indirect interrupt. */
3672 +#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000
3673 +/* Nothing
3674 +#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */
3675 +/** Write: Acknowledge the interrupt. */
3676 +#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000
3677 +/** Read: Interrupt occurred. */
3678 +#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000
3679 +/** GPTC Timer/Counter 3B Interrupt
3680 +    This bit is a direct interrupt. */
3681 +#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000
3682 +/* Nothing
3683 +#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */
3684 +/** Write: Acknowledge the interrupt. */
3685 +#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000
3686 +/** Read: Interrupt occurred. */
3687 +#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000
3688 +/** GPTC Timer/Counter 3A Interrupt
3689 +    This bit is a direct interrupt. */
3690 +#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000
3691 +/* Nothing
3692 +#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */
3693 +/** Write: Acknowledge the interrupt. */
3694 +#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000
3695 +/** Read: Interrupt occurred. */
3696 +#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000
3697 +/** GPTC Timer/Counter 2B Interrupt
3698 +    This bit is a direct interrupt. */
3699 +#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000
3700 +/* Nothing
3701 +#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */
3702 +/** Write: Acknowledge the interrupt. */
3703 +#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000
3704 +/** Read: Interrupt occurred. */
3705 +#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000
3706 +/** GPTC Timer/Counter 2A Interrupt
3707 +    This bit is a direct interrupt. */
3708 +#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000
3709 +/* Nothing
3710 +#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */
3711 +/** Write: Acknowledge the interrupt. */
3712 +#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000
3713 +/** Read: Interrupt occurred. */
3714 +#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000
3715 +/** GPTC Timer/Counter 1B Interrupt
3716 +    This bit is a direct interrupt. */
3717 +#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000
3718 +/* Nothing
3719 +#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */
3720 +/** Write: Acknowledge the interrupt. */
3721 +#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000
3722 +/** Read: Interrupt occurred. */
3723 +#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000
3724 +/** GPTC Timer/Counter 1A Interrupt
3725 +    This bit is a direct interrupt. */
3726 +#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000
3727 +/* Nothing
3728 +#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */
3729 +/** Write: Acknowledge the interrupt. */
3730 +#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000
3731 +/** Read: Interrupt occurred. */
3732 +#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000
3733 +/** ASC1 Soft Flow Control Interrupt
3734 +    This bit is a direct interrupt. */
3735 +#define ICU0_IM3_ISR_ASC1_SFC 0x00008000
3736 +/* Nothing
3737 +#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */
3738 +/** Write: Acknowledge the interrupt. */
3739 +#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000
3740 +/** Read: Interrupt occurred. */
3741 +#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000
3742 +/** ASC1 Modem Status Interrupt
3743 +    This bit is a direct interrupt. */
3744 +#define ICU0_IM3_ISR_ASC1_MS 0x00004000
3745 +/* Nothing
3746 +#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */
3747 +/** Write: Acknowledge the interrupt. */
3748 +#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000
3749 +/** Read: Interrupt occurred. */
3750 +#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000
3751 +/** ASC1 Autobaud Detection Interrupt
3752 +    This bit is a direct interrupt. */
3753 +#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000
3754 +/* Nothing
3755 +#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */
3756 +/** Write: Acknowledge the interrupt. */
3757 +#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000
3758 +/** Read: Interrupt occurred. */
3759 +#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000
3760 +/** ASC1 Autobaud Start Interrupt
3761 +    This bit is a direct interrupt. */
3762 +#define ICU0_IM3_ISR_ASC1_ABST 0x00001000
3763 +/* Nothing
3764 +#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */
3765 +/** Write: Acknowledge the interrupt. */
3766 +#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000
3767 +/** Read: Interrupt occurred. */
3768 +#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000
3769 +/** ASC1 Transmit Buffer Interrupt
3770 +    This bit is a direct interrupt. */
3771 +#define ICU0_IM3_ISR_ASC1_TB 0x00000800
3772 +/* Nothing
3773 +#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */
3774 +/** Write: Acknowledge the interrupt. */
3775 +#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800
3776 +/** Read: Interrupt occurred. */
3777 +#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800
3778 +/** ASC1 Error Interrupt
3779 +    This bit is a direct interrupt. */
3780 +#define ICU0_IM3_ISR_ASC1_E 0x00000400
3781 +/* Nothing
3782 +#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */
3783 +/** Write: Acknowledge the interrupt. */
3784 +#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400
3785 +/** Read: Interrupt occurred. */
3786 +#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400
3787 +/** ASC1 Receive Interrupt
3788 +    This bit is a direct interrupt. */
3789 +#define ICU0_IM3_ISR_ASC1_R 0x00000200
3790 +/* Nothing
3791 +#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */
3792 +/** Write: Acknowledge the interrupt. */
3793 +#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200
3794 +/** Read: Interrupt occurred. */
3795 +#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200
3796 +/** ASC1 Transmit Interrupt
3797 +    This bit is a direct interrupt. */
3798 +#define ICU0_IM3_ISR_ASC1_T 0x00000100
3799 +/* Nothing
3800 +#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */
3801 +/** Write: Acknowledge the interrupt. */
3802 +#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100
3803 +/** Read: Interrupt occurred. */
3804 +#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100
3805 +/** ASC0 Soft Flow Control Interrupt
3806 +    This bit is a direct interrupt. */
3807 +#define ICU0_IM3_ISR_ASC0_SFC 0x00000080
3808 +/* Nothing
3809 +#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */
3810 +/** Write: Acknowledge the interrupt. */
3811 +#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080
3812 +/** Read: Interrupt occurred. */
3813 +#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080
3814 +/** ASC1 Modem Status Interrupt
3815 +    This bit is a direct interrupt. */
3816 +#define ICU0_IM3_ISR_ASC0_MS 0x00000040
3817 +/* Nothing
3818 +#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */
3819 +/** Write: Acknowledge the interrupt. */
3820 +#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040
3821 +/** Read: Interrupt occurred. */
3822 +#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040
3823 +/** ASC0 Autobaud Detection Interrupt
3824 +    This bit is a direct interrupt. */
3825 +#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020
3826 +/* Nothing
3827 +#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */
3828 +/** Write: Acknowledge the interrupt. */
3829 +#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020
3830 +/** Read: Interrupt occurred. */
3831 +#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020
3832 +/** ASC0 Autobaud Start Interrupt
3833 +    This bit is a direct interrupt. */
3834 +#define ICU0_IM3_ISR_ASC0_ABST 0x00000010
3835 +/* Nothing
3836 +#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */
3837 +/** Write: Acknowledge the interrupt. */
3838 +#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010
3839 +/** Read: Interrupt occurred. */
3840 +#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010
3841 +/** ASC0 Transmit Buffer Interrupt
3842 +    This bit is a direct interrupt. */
3843 +#define ICU0_IM3_ISR_ASC0_TB 0x00000008
3844 +/* Nothing
3845 +#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */
3846 +/** Write: Acknowledge the interrupt. */
3847 +#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008
3848 +/** Read: Interrupt occurred. */
3849 +#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008
3850 +/** ASC0 Error Interrupt
3851 +    This bit is a direct interrupt. */
3852 +#define ICU0_IM3_ISR_ASC0_E 0x00000004
3853 +/* Nothing
3854 +#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */
3855 +/** Write: Acknowledge the interrupt. */
3856 +#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004
3857 +/** Read: Interrupt occurred. */
3858 +#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004
3859 +/** ASC0 Receive Interrupt
3860 +    This bit is a direct interrupt. */
3861 +#define ICU0_IM3_ISR_ASC0_R 0x00000002
3862 +/* Nothing
3863 +#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */
3864 +/** Write: Acknowledge the interrupt. */
3865 +#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002
3866 +/** Read: Interrupt occurred. */
3867 +#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002
3868 +/** ASC0 Transmit Interrupt
3869 +    This bit is a direct interrupt. */
3870 +#define ICU0_IM3_ISR_ASC0_T 0x00000001
3871 +/* Nothing
3872 +#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */
3873 +/** Write: Acknowledge the interrupt. */
3874 +#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001
3875 +/** Read: Interrupt occurred. */
3876 +#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001
3877 +
3878 +/* Fields of "IM3 Interrupt Enable Register" */
3879 +/** DFEV0, Channel 0 General Purpose Interrupt
3880 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3881 +#define ICU0_IM3_IER_DFEV0_1GP 0x80000000
3882 +/* Disable
3883 +#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */
3884 +/** Enable */
3885 +#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000
3886 +/** DFEV0, Channel 0 Receive Interrupt
3887 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3888 +#define ICU0_IM3_IER_DFEV0_1RX 0x40000000
3889 +/* Disable
3890 +#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */
3891 +/** Enable */
3892 +#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000
3893 +/** DFEV0, Channel 0 Transmit Interrupt
3894 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3895 +#define ICU0_IM3_IER_DFEV0_1TX 0x20000000
3896 +/* Disable
3897 +#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */
3898 +/** Enable */
3899 +#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000
3900 +/** DFEV0, Channel 1 General Purpose Interrupt
3901 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3902 +#define ICU0_IM3_IER_DFEV0_2GP 0x10000000
3903 +/* Disable
3904 +#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */
3905 +/** Enable */
3906 +#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000
3907 +/** DFEV0, Channel 1 Receive Interrupt
3908 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3909 +#define ICU0_IM3_IER_DFEV0_2RX 0x08000000
3910 +/* Disable
3911 +#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */
3912 +/** Enable */
3913 +#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000
3914 +/** DFEV0, Channel 1 Transmit Interrupt
3915 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3916 +#define ICU0_IM3_IER_DFEV0_2TX 0x04000000
3917 +/* Disable
3918 +#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */
3919 +/** Enable */
3920 +#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000
3921 +/** GPTC Timer/Counter 3B Interrupt
3922 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3923 +#define ICU0_IM3_IER_GPTC_TC3B 0x00200000
3924 +/* Disable
3925 +#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */
3926 +/** Enable */
3927 +#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000
3928 +/** GPTC Timer/Counter 3A Interrupt
3929 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3930 +#define ICU0_IM3_IER_GPTC_TC3A 0x00100000
3931 +/* Disable
3932 +#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */
3933 +/** Enable */
3934 +#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000
3935 +/** GPTC Timer/Counter 2B Interrupt
3936 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3937 +#define ICU0_IM3_IER_GPTC_TC2B 0x00080000
3938 +/* Disable
3939 +#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */
3940 +/** Enable */
3941 +#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000
3942 +/** GPTC Timer/Counter 2A Interrupt
3943 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3944 +#define ICU0_IM3_IER_GPTC_TC2A 0x00040000
3945 +/* Disable
3946 +#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */
3947 +/** Enable */
3948 +#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000
3949 +/** GPTC Timer/Counter 1B Interrupt
3950 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3951 +#define ICU0_IM3_IER_GPTC_TC1B 0x00020000
3952 +/* Disable
3953 +#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */
3954 +/** Enable */
3955 +#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000
3956 +/** GPTC Timer/Counter 1A Interrupt
3957 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3958 +#define ICU0_IM3_IER_GPTC_TC1A 0x00010000
3959 +/* Disable
3960 +#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */
3961 +/** Enable */
3962 +#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000
3963 +/** ASC1 Soft Flow Control Interrupt
3964 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3965 +#define ICU0_IM3_IER_ASC1_SFC 0x00008000
3966 +/* Disable
3967 +#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */
3968 +/** Enable */
3969 +#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000
3970 +/** ASC1 Modem Status Interrupt
3971 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3972 +#define ICU0_IM3_IER_ASC1_MS 0x00004000
3973 +/* Disable
3974 +#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */
3975 +/** Enable */
3976 +#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000
3977 +/** ASC1 Autobaud Detection Interrupt
3978 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3979 +#define ICU0_IM3_IER_ASC1_ABDET 0x00002000
3980 +/* Disable
3981 +#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */
3982 +/** Enable */
3983 +#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000
3984 +/** ASC1 Autobaud Start Interrupt
3985 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3986 +#define ICU0_IM3_IER_ASC1_ABST 0x00001000
3987 +/* Disable
3988 +#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */
3989 +/** Enable */
3990 +#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000
3991 +/** ASC1 Transmit Buffer Interrupt
3992 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
3993 +#define ICU0_IM3_IER_ASC1_TB 0x00000800
3994 +/* Disable
3995 +#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */
3996 +/** Enable */
3997 +#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800
3998 +/** ASC1 Error Interrupt
3999 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4000 +#define ICU0_IM3_IER_ASC1_E 0x00000400
4001 +/* Disable
4002 +#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */
4003 +/** Enable */
4004 +#define ICU0_IM3_IER_ASC1_E_EN 0x00000400
4005 +/** ASC1 Receive Interrupt
4006 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4007 +#define ICU0_IM3_IER_ASC1_R 0x00000200
4008 +/* Disable
4009 +#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */
4010 +/** Enable */
4011 +#define ICU0_IM3_IER_ASC1_R_EN 0x00000200
4012 +/** ASC1 Transmit Interrupt
4013 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4014 +#define ICU0_IM3_IER_ASC1_T 0x00000100
4015 +/* Disable
4016 +#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */
4017 +/** Enable */
4018 +#define ICU0_IM3_IER_ASC1_T_EN 0x00000100
4019 +/** ASC0 Soft Flow Control Interrupt
4020 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4021 +#define ICU0_IM3_IER_ASC0_SFC 0x00000080
4022 +/* Disable
4023 +#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */
4024 +/** Enable */
4025 +#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080
4026 +/** ASC1 Modem Status Interrupt
4027 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4028 +#define ICU0_IM3_IER_ASC0_MS 0x00000040
4029 +/* Disable
4030 +#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */
4031 +/** Enable */
4032 +#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040
4033 +/** ASC0 Autobaud Detection Interrupt
4034 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4035 +#define ICU0_IM3_IER_ASC0_ABDET 0x00000020
4036 +/* Disable
4037 +#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */
4038 +/** Enable */
4039 +#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020
4040 +/** ASC0 Autobaud Start Interrupt
4041 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4042 +#define ICU0_IM3_IER_ASC0_ABST 0x00000010
4043 +/* Disable
4044 +#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */
4045 +/** Enable */
4046 +#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010
4047 +/** ASC0 Transmit Buffer Interrupt
4048 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4049 +#define ICU0_IM3_IER_ASC0_TB 0x00000008
4050 +/* Disable
4051 +#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */
4052 +/** Enable */
4053 +#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008
4054 +/** ASC0 Error Interrupt
4055 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4056 +#define ICU0_IM3_IER_ASC0_E 0x00000004
4057 +/* Disable
4058 +#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */
4059 +/** Enable */
4060 +#define ICU0_IM3_IER_ASC0_E_EN 0x00000004
4061 +/** ASC0 Receive Interrupt
4062 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4063 +#define ICU0_IM3_IER_ASC0_R 0x00000002
4064 +/* Disable
4065 +#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */
4066 +/** Enable */
4067 +#define ICU0_IM3_IER_ASC0_R_EN 0x00000002
4068 +/** ASC0 Transmit Interrupt
4069 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4070 +#define ICU0_IM3_IER_ASC0_T 0x00000001
4071 +/* Disable
4072 +#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */
4073 +/** Enable */
4074 +#define ICU0_IM3_IER_ASC0_T_EN 0x00000001
4075 +
4076 +/* Fields of "IM3 Interrupt Output Status Register" */
4077 +/** DFEV0, Channel 0 General Purpose Interrupt
4078 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4079 +#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000
4080 +/* Nothing
4081 +#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */
4082 +/** Read: Interrupt occurred. */
4083 +#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000
4084 +/** DFEV0, Channel 0 Receive Interrupt
4085 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4086 +#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000
4087 +/* Nothing
4088 +#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */
4089 +/** Read: Interrupt occurred. */
4090 +#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000
4091 +/** DFEV0, Channel 0 Transmit Interrupt
4092 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4093 +#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000
4094 +/* Nothing
4095 +#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */
4096 +/** Read: Interrupt occurred. */
4097 +#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000
4098 +/** DFEV0, Channel 1 General Purpose Interrupt
4099 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4100 +#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000
4101 +/* Nothing
4102 +#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */
4103 +/** Read: Interrupt occurred. */
4104 +#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000
4105 +/** DFEV0, Channel 1 Receive Interrupt
4106 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4107 +#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000
4108 +/* Nothing
4109 +#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */
4110 +/** Read: Interrupt occurred. */
4111 +#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000
4112 +/** DFEV0, Channel 1 Transmit Interrupt
4113 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4114 +#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000
4115 +/* Nothing
4116 +#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */
4117 +/** Read: Interrupt occurred. */
4118 +#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000
4119 +/** GPTC Timer/Counter 3B Interrupt
4120 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4121 +#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000
4122 +/* Nothing
4123 +#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */
4124 +/** Read: Interrupt occurred. */
4125 +#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000
4126 +/** GPTC Timer/Counter 3A Interrupt
4127 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4128 +#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000
4129 +/* Nothing
4130 +#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */
4131 +/** Read: Interrupt occurred. */
4132 +#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000
4133 +/** GPTC Timer/Counter 2B Interrupt
4134 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4135 +#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000
4136 +/* Nothing
4137 +#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */
4138 +/** Read: Interrupt occurred. */
4139 +#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000
4140 +/** GPTC Timer/Counter 2A Interrupt
4141 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4142 +#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000
4143 +/* Nothing
4144 +#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */
4145 +/** Read: Interrupt occurred. */
4146 +#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000
4147 +/** GPTC Timer/Counter 1B Interrupt
4148 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4149 +#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000
4150 +/* Nothing
4151 +#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */
4152 +/** Read: Interrupt occurred. */
4153 +#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000
4154 +/** GPTC Timer/Counter 1A Interrupt
4155 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4156 +#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000
4157 +/* Nothing
4158 +#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */
4159 +/** Read: Interrupt occurred. */
4160 +#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000
4161 +/** ASC1 Soft Flow Control Interrupt
4162 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4163 +#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000
4164 +/* Nothing
4165 +#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */
4166 +/** Read: Interrupt occurred. */
4167 +#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000
4168 +/** ASC1 Modem Status Interrupt
4169 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4170 +#define ICU0_IM3_IOSR_ASC1_MS 0x00004000
4171 +/* Nothing
4172 +#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */
4173 +/** Read: Interrupt occurred. */
4174 +#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000
4175 +/** ASC1 Autobaud Detection Interrupt
4176 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4177 +#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000
4178 +/* Nothing
4179 +#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */
4180 +/** Read: Interrupt occurred. */
4181 +#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000
4182 +/** ASC1 Autobaud Start Interrupt
4183 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4184 +#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000
4185 +/* Nothing
4186 +#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */
4187 +/** Read: Interrupt occurred. */
4188 +#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000
4189 +/** ASC1 Transmit Buffer Interrupt
4190 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4191 +#define ICU0_IM3_IOSR_ASC1_TB 0x00000800
4192 +/* Nothing
4193 +#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */
4194 +/** Read: Interrupt occurred. */
4195 +#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800
4196 +/** ASC1 Error Interrupt
4197 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4198 +#define ICU0_IM3_IOSR_ASC1_E 0x00000400
4199 +/* Nothing
4200 +#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */
4201 +/** Read: Interrupt occurred. */
4202 +#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400
4203 +/** ASC1 Receive Interrupt
4204 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4205 +#define ICU0_IM3_IOSR_ASC1_R 0x00000200
4206 +/* Nothing
4207 +#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */
4208 +/** Read: Interrupt occurred. */
4209 +#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200
4210 +/** ASC1 Transmit Interrupt
4211 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4212 +#define ICU0_IM3_IOSR_ASC1_T 0x00000100
4213 +/* Nothing
4214 +#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */
4215 +/** Read: Interrupt occurred. */
4216 +#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100
4217 +/** ASC0 Soft Flow Control Interrupt
4218 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4219 +#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080
4220 +/* Nothing
4221 +#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */
4222 +/** Read: Interrupt occurred. */
4223 +#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080
4224 +/** ASC1 Modem Status Interrupt
4225 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4226 +#define ICU0_IM3_IOSR_ASC0_MS 0x00000040
4227 +/* Nothing
4228 +#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */
4229 +/** Read: Interrupt occurred. */
4230 +#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040
4231 +/** ASC0 Autobaud Detection Interrupt
4232 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4233 +#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020
4234 +/* Nothing
4235 +#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */
4236 +/** Read: Interrupt occurred. */
4237 +#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020
4238 +/** ASC0 Autobaud Start Interrupt
4239 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4240 +#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010
4241 +/* Nothing
4242 +#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */
4243 +/** Read: Interrupt occurred. */
4244 +#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010
4245 +/** ASC0 Transmit Buffer Interrupt
4246 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4247 +#define ICU0_IM3_IOSR_ASC0_TB 0x00000008
4248 +/* Nothing
4249 +#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */
4250 +/** Read: Interrupt occurred. */
4251 +#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008
4252 +/** ASC0 Error Interrupt
4253 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4254 +#define ICU0_IM3_IOSR_ASC0_E 0x00000004
4255 +/* Nothing
4256 +#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */
4257 +/** Read: Interrupt occurred. */
4258 +#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004
4259 +/** ASC0 Receive Interrupt
4260 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4261 +#define ICU0_IM3_IOSR_ASC0_R 0x00000002
4262 +/* Nothing
4263 +#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */
4264 +/** Read: Interrupt occurred. */
4265 +#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002
4266 +/** ASC0 Transmit Interrupt
4267 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4268 +#define ICU0_IM3_IOSR_ASC0_T 0x00000001
4269 +/* Nothing
4270 +#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */
4271 +/** Read: Interrupt occurred. */
4272 +#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001
4273 +
4274 +/* Fields of "IM3 Interrupt Request Set Register" */
4275 +/** DFEV0, Channel 0 General Purpose Interrupt
4276 +    Software control for the corresponding bit in the IM3_ISR register. */
4277 +#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000
4278 +/** DFEV0, Channel 0 Receive Interrupt
4279 +    Software control for the corresponding bit in the IM3_ISR register. */
4280 +#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000
4281 +/** DFEV0, Channel 0 Transmit Interrupt
4282 +    Software control for the corresponding bit in the IM3_ISR register. */
4283 +#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000
4284 +/** DFEV0, Channel 1 General Purpose Interrupt
4285 +    Software control for the corresponding bit in the IM3_ISR register. */
4286 +#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000
4287 +/** DFEV0, Channel 1 Receive Interrupt
4288 +    Software control for the corresponding bit in the IM3_ISR register. */
4289 +#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000
4290 +/** DFEV0, Channel 1 Transmit Interrupt
4291 +    Software control for the corresponding bit in the IM3_ISR register. */
4292 +#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000
4293 +/** GPTC Timer/Counter 3B Interrupt
4294 +    Software control for the corresponding bit in the IM3_ISR register. */
4295 +#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000
4296 +/** GPTC Timer/Counter 3A Interrupt
4297 +    Software control for the corresponding bit in the IM3_ISR register. */
4298 +#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000
4299 +/** GPTC Timer/Counter 2B Interrupt
4300 +    Software control for the corresponding bit in the IM3_ISR register. */
4301 +#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000
4302 +/** GPTC Timer/Counter 2A Interrupt
4303 +    Software control for the corresponding bit in the IM3_ISR register. */
4304 +#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000
4305 +/** GPTC Timer/Counter 1B Interrupt
4306 +    Software control for the corresponding bit in the IM3_ISR register. */
4307 +#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000
4308 +/** GPTC Timer/Counter 1A Interrupt
4309 +    Software control for the corresponding bit in the IM3_ISR register. */
4310 +#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000
4311 +/** ASC1 Soft Flow Control Interrupt
4312 +    Software control for the corresponding bit in the IM3_ISR register. */
4313 +#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000
4314 +/** ASC1 Modem Status Interrupt
4315 +    Software control for the corresponding bit in the IM3_ISR register. */
4316 +#define ICU0_IM3_IRSR_ASC1_MS 0x00004000
4317 +/** ASC1 Autobaud Detection Interrupt
4318 +    Software control for the corresponding bit in the IM3_ISR register. */
4319 +#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000
4320 +/** ASC1 Autobaud Start Interrupt
4321 +    Software control for the corresponding bit in the IM3_ISR register. */
4322 +#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000
4323 +/** ASC1 Transmit Buffer Interrupt
4324 +    Software control for the corresponding bit in the IM3_ISR register. */
4325 +#define ICU0_IM3_IRSR_ASC1_TB 0x00000800
4326 +/** ASC1 Error Interrupt
4327 +    Software control for the corresponding bit in the IM3_ISR register. */
4328 +#define ICU0_IM3_IRSR_ASC1_E 0x00000400
4329 +/** ASC1 Receive Interrupt
4330 +    Software control for the corresponding bit in the IM3_ISR register. */
4331 +#define ICU0_IM3_IRSR_ASC1_R 0x00000200
4332 +/** ASC1 Transmit Interrupt
4333 +    Software control for the corresponding bit in the IM3_ISR register. */
4334 +#define ICU0_IM3_IRSR_ASC1_T 0x00000100
4335 +/** ASC0 Soft Flow Control Interrupt
4336 +    Software control for the corresponding bit in the IM3_ISR register. */
4337 +#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080
4338 +/** ASC1 Modem Status Interrupt
4339 +    Software control for the corresponding bit in the IM3_ISR register. */
4340 +#define ICU0_IM3_IRSR_ASC0_MS 0x00000040
4341 +/** ASC0 Autobaud Detection Interrupt
4342 +    Software control for the corresponding bit in the IM3_ISR register. */
4343 +#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020
4344 +/** ASC0 Autobaud Start Interrupt
4345 +    Software control for the corresponding bit in the IM3_ISR register. */
4346 +#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010
4347 +/** ASC0 Transmit Buffer Interrupt
4348 +    Software control for the corresponding bit in the IM3_ISR register. */
4349 +#define ICU0_IM3_IRSR_ASC0_TB 0x00000008
4350 +/** ASC0 Error Interrupt
4351 +    Software control for the corresponding bit in the IM3_ISR register. */
4352 +#define ICU0_IM3_IRSR_ASC0_E 0x00000004
4353 +/** ASC0 Receive Interrupt
4354 +    Software control for the corresponding bit in the IM3_ISR register. */
4355 +#define ICU0_IM3_IRSR_ASC0_R 0x00000002
4356 +/** ASC0 Transmit Interrupt
4357 +    Software control for the corresponding bit in the IM3_ISR register. */
4358 +#define ICU0_IM3_IRSR_ASC0_T 0x00000001
4359 +
4360 +/* Fields of "IM3 Interrupt Mode Register" */
4361 +/** DFEV0, Channel 0 General Purpose Interrupt
4362 +    Type of interrupt. */
4363 +#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000
4364 +/* Indirect Interrupt.
4365 +#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */
4366 +/** Direct Interrupt. */
4367 +#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000
4368 +/** DFEV0, Channel 0 Receive Interrupt
4369 +    Type of interrupt. */
4370 +#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000
4371 +/* Indirect Interrupt.
4372 +#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */
4373 +/** Direct Interrupt. */
4374 +#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000
4375 +/** DFEV0, Channel 0 Transmit Interrupt
4376 +    Type of interrupt. */
4377 +#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000
4378 +/* Indirect Interrupt.
4379 +#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */
4380 +/** Direct Interrupt. */
4381 +#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000
4382 +/** DFEV0, Channel 1 General Purpose Interrupt
4383 +    Type of interrupt. */
4384 +#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000
4385 +/* Indirect Interrupt.
4386 +#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */
4387 +/** Direct Interrupt. */
4388 +#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000
4389 +/** DFEV0, Channel 1 Receive Interrupt
4390 +    Type of interrupt. */
4391 +#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000
4392 +/* Indirect Interrupt.
4393 +#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */
4394 +/** Direct Interrupt. */
4395 +#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000
4396 +/** DFEV0, Channel 1 Transmit Interrupt
4397 +    Type of interrupt. */
4398 +#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000
4399 +/* Indirect Interrupt.
4400 +#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */
4401 +/** Direct Interrupt. */
4402 +#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000
4403 +/** GPTC Timer/Counter 3B Interrupt
4404 +    Type of interrupt. */
4405 +#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000
4406 +/* Indirect Interrupt.
4407 +#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */
4408 +/** Direct Interrupt. */
4409 +#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000
4410 +/** GPTC Timer/Counter 3A Interrupt
4411 +    Type of interrupt. */
4412 +#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000
4413 +/* Indirect Interrupt.
4414 +#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */
4415 +/** Direct Interrupt. */
4416 +#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000
4417 +/** GPTC Timer/Counter 2B Interrupt
4418 +    Type of interrupt. */
4419 +#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000
4420 +/* Indirect Interrupt.
4421 +#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */
4422 +/** Direct Interrupt. */
4423 +#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000
4424 +/** GPTC Timer/Counter 2A Interrupt
4425 +    Type of interrupt. */
4426 +#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000
4427 +/* Indirect Interrupt.
4428 +#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */
4429 +/** Direct Interrupt. */
4430 +#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000
4431 +/** GPTC Timer/Counter 1B Interrupt
4432 +    Type of interrupt. */
4433 +#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000
4434 +/* Indirect Interrupt.
4435 +#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */
4436 +/** Direct Interrupt. */
4437 +#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000
4438 +/** GPTC Timer/Counter 1A Interrupt
4439 +    Type of interrupt. */
4440 +#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000
4441 +/* Indirect Interrupt.
4442 +#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */
4443 +/** Direct Interrupt. */
4444 +#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000
4445 +/** ASC1 Soft Flow Control Interrupt
4446 +    Type of interrupt. */
4447 +#define ICU0_IM3_IMR_ASC1_SFC 0x00008000
4448 +/* Indirect Interrupt.
4449 +#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */
4450 +/** Direct Interrupt. */
4451 +#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000
4452 +/** ASC1 Modem Status Interrupt
4453 +    Type of interrupt. */
4454 +#define ICU0_IM3_IMR_ASC1_MS 0x00004000
4455 +/* Indirect Interrupt.
4456 +#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */
4457 +/** Direct Interrupt. */
4458 +#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000
4459 +/** ASC1 Autobaud Detection Interrupt
4460 +    Type of interrupt. */
4461 +#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000
4462 +/* Indirect Interrupt.
4463 +#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */
4464 +/** Direct Interrupt. */
4465 +#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000
4466 +/** ASC1 Autobaud Start Interrupt
4467 +    Type of interrupt. */
4468 +#define ICU0_IM3_IMR_ASC1_ABST 0x00001000
4469 +/* Indirect Interrupt.
4470 +#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */
4471 +/** Direct Interrupt. */
4472 +#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000
4473 +/** ASC1 Transmit Buffer Interrupt
4474 +    Type of interrupt. */
4475 +#define ICU0_IM3_IMR_ASC1_TB 0x00000800
4476 +/* Indirect Interrupt.
4477 +#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */
4478 +/** Direct Interrupt. */
4479 +#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800
4480 +/** ASC1 Error Interrupt
4481 +    Type of interrupt. */
4482 +#define ICU0_IM3_IMR_ASC1_E 0x00000400
4483 +/* Indirect Interrupt.
4484 +#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */
4485 +/** Direct Interrupt. */
4486 +#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400
4487 +/** ASC1 Receive Interrupt
4488 +    Type of interrupt. */
4489 +#define ICU0_IM3_IMR_ASC1_R 0x00000200
4490 +/* Indirect Interrupt.
4491 +#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */
4492 +/** Direct Interrupt. */
4493 +#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200
4494 +/** ASC1 Transmit Interrupt
4495 +    Type of interrupt. */
4496 +#define ICU0_IM3_IMR_ASC1_T 0x00000100
4497 +/* Indirect Interrupt.
4498 +#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */
4499 +/** Direct Interrupt. */
4500 +#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100
4501 +/** ASC0 Soft Flow Control Interrupt
4502 +    Type of interrupt. */
4503 +#define ICU0_IM3_IMR_ASC0_SFC 0x00000080
4504 +/* Indirect Interrupt.
4505 +#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */
4506 +/** Direct Interrupt. */
4507 +#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080
4508 +/** ASC1 Modem Status Interrupt
4509 +    Type of interrupt. */
4510 +#define ICU0_IM3_IMR_ASC0_MS 0x00000040
4511 +/* Indirect Interrupt.
4512 +#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */
4513 +/** Direct Interrupt. */
4514 +#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040
4515 +/** ASC0 Autobaud Detection Interrupt
4516 +    Type of interrupt. */
4517 +#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020
4518 +/* Indirect Interrupt.
4519 +#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */
4520 +/** Direct Interrupt. */
4521 +#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020
4522 +/** ASC0 Autobaud Start Interrupt
4523 +    Type of interrupt. */
4524 +#define ICU0_IM3_IMR_ASC0_ABST 0x00000010
4525 +/* Indirect Interrupt.
4526 +#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */
4527 +/** Direct Interrupt. */
4528 +#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010
4529 +/** ASC0 Transmit Buffer Interrupt
4530 +    Type of interrupt. */
4531 +#define ICU0_IM3_IMR_ASC0_TB 0x00000008
4532 +/* Indirect Interrupt.
4533 +#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */
4534 +/** Direct Interrupt. */
4535 +#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008
4536 +/** ASC0 Error Interrupt
4537 +    Type of interrupt. */
4538 +#define ICU0_IM3_IMR_ASC0_E 0x00000004
4539 +/* Indirect Interrupt.
4540 +#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */
4541 +/** Direct Interrupt. */
4542 +#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004
4543 +/** ASC0 Receive Interrupt
4544 +    Type of interrupt. */
4545 +#define ICU0_IM3_IMR_ASC0_R 0x00000002
4546 +/* Indirect Interrupt.
4547 +#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */
4548 +/** Direct Interrupt. */
4549 +#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002
4550 +/** ASC0 Transmit Interrupt
4551 +    Type of interrupt. */
4552 +#define ICU0_IM3_IMR_ASC0_T 0x00000001
4553 +/* Indirect Interrupt.
4554 +#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */
4555 +/** Direct Interrupt. */
4556 +#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001
4557 +
4558 +/* Fields of "IM4 Interrupt Status Register" */
4559 +/** VPE0 Performance Monitoring Counter Interrupt
4560 +    This bit is an indirect interrupt. */
4561 +#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000
4562 +/* Nothing
4563 +#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */
4564 +/** Write: Acknowledge the interrupt. */
4565 +#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000
4566 +/** Read: Interrupt occurred. */
4567 +#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000
4568 +/** VPE0 Error Level Flag Interrupt
4569 +    This bit is an indirect interrupt. */
4570 +#define ICU0_IM4_ISR_VPE0_ERL 0x40000000
4571 +/* Nothing
4572 +#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */
4573 +/** Write: Acknowledge the interrupt. */
4574 +#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000
4575 +/** Read: Interrupt occurred. */
4576 +#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000
4577 +/** VPE0 Exception Level Flag Interrupt
4578 +    This bit is an indirect interrupt. */
4579 +#define ICU0_IM4_ISR_VPE0_EXL 0x20000000
4580 +/* Nothing
4581 +#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */
4582 +/** Write: Acknowledge the interrupt. */
4583 +#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000
4584 +/** Read: Interrupt occurred. */
4585 +#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000
4586 +/** MPS Bin. Sem Interrupt to VPE0
4587 +    This bit is an indirect interrupt. */
4588 +#define ICU0_IM4_ISR_MPS_IR8 0x00400000
4589 +/* Nothing
4590 +#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */
4591 +/** Write: Acknowledge the interrupt. */
4592 +#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000
4593 +/** Read: Interrupt occurred. */
4594 +#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000
4595 +/** MPS Global Interrupt to VPE0
4596 +    This bit is an indirect interrupt. */
4597 +#define ICU0_IM4_ISR_MPS_IR7 0x00200000
4598 +/* Nothing
4599 +#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */
4600 +/** Write: Acknowledge the interrupt. */
4601 +#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000
4602 +/** Read: Interrupt occurred. */
4603 +#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000
4604 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
4605 +    This bit is an indirect interrupt. */
4606 +#define ICU0_IM4_ISR_MPS_IR6 0x00100000
4607 +/* Nothing
4608 +#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */
4609 +/** Write: Acknowledge the interrupt. */
4610 +#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000
4611 +/** Read: Interrupt occurred. */
4612 +#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000
4613 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
4614 +    This bit is an indirect interrupt. */
4615 +#define ICU0_IM4_ISR_MPS_IR5 0x00080000
4616 +/* Nothing
4617 +#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */
4618 +/** Write: Acknowledge the interrupt. */
4619 +#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000
4620 +/** Read: Interrupt occurred. */
4621 +#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000
4622 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
4623 +    This bit is an indirect interrupt. */
4624 +#define ICU0_IM4_ISR_MPS_IR4 0x00040000
4625 +/* Nothing
4626 +#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */
4627 +/** Write: Acknowledge the interrupt. */
4628 +#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000
4629 +/** Read: Interrupt occurred. */
4630 +#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000
4631 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
4632 +    This bit is an indirect interrupt. */
4633 +#define ICU0_IM4_ISR_MPS_IR3 0x00020000
4634 +/* Nothing
4635 +#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */
4636 +/** Write: Acknowledge the interrupt. */
4637 +#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000
4638 +/** Read: Interrupt occurred. */
4639 +#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000
4640 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
4641 +    This bit is an indirect interrupt. */
4642 +#define ICU0_IM4_ISR_MPS_IR2 0x00010000
4643 +/* Nothing
4644 +#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */
4645 +/** Write: Acknowledge the interrupt. */
4646 +#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000
4647 +/** Read: Interrupt occurred. */
4648 +#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000
4649 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
4650 +    This bit is an indirect interrupt. */
4651 +#define ICU0_IM4_ISR_MPS_IR1 0x00008000
4652 +/* Nothing
4653 +#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */
4654 +/** Write: Acknowledge the interrupt. */
4655 +#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000
4656 +/** Read: Interrupt occurred. */
4657 +#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000
4658 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
4659 +    This bit is an indirect interrupt. */
4660 +#define ICU0_IM4_ISR_MPS_IR0 0x00004000
4661 +/* Nothing
4662 +#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */
4663 +/** Write: Acknowledge the interrupt. */
4664 +#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000
4665 +/** Read: Interrupt occurred. */
4666 +#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000
4667 +/** TMU Error
4668 +    This bit is an indirect interrupt. */
4669 +#define ICU0_IM4_ISR_TMU_ERR 0x00001000
4670 +/* Nothing
4671 +#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */
4672 +/** Write: Acknowledge the interrupt. */
4673 +#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000
4674 +/** Read: Interrupt occurred. */
4675 +#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000
4676 +/** FSQM Error
4677 +    This bit is an indirect interrupt. */
4678 +#define ICU0_IM4_ISR_FSQM_ERR 0x00000800
4679 +/* Nothing
4680 +#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */
4681 +/** Write: Acknowledge the interrupt. */
4682 +#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800
4683 +/** Read: Interrupt occurred. */
4684 +#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800
4685 +/** IQM Error
4686 +    This bit is an indirect interrupt. */
4687 +#define ICU0_IM4_ISR_IQM_ERR 0x00000400
4688 +/* Nothing
4689 +#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */
4690 +/** Write: Acknowledge the interrupt. */
4691 +#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400
4692 +/** Read: Interrupt occurred. */
4693 +#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400
4694 +/** OCTRLG Error
4695 +    This bit is an indirect interrupt. */
4696 +#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200
4697 +/* Nothing
4698 +#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */
4699 +/** Write: Acknowledge the interrupt. */
4700 +#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200
4701 +/** Read: Interrupt occurred. */
4702 +#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200
4703 +/** ICTRLG Error
4704 +    This bit is an indirect interrupt. */
4705 +#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100
4706 +/* Nothing
4707 +#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */
4708 +/** Write: Acknowledge the interrupt. */
4709 +#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100
4710 +/** Read: Interrupt occurred. */
4711 +#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100
4712 +/** OCTRLL 3 Error
4713 +    This bit is an indirect interrupt. */
4714 +#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080
4715 +/* Nothing
4716 +#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */
4717 +/** Write: Acknowledge the interrupt. */
4718 +#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080
4719 +/** Read: Interrupt occurred. */
4720 +#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080
4721 +/** OCTRLL 2 Error
4722 +    This bit is an indirect interrupt. */
4723 +#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040
4724 +/* Nothing
4725 +#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */
4726 +/** Write: Acknowledge the interrupt. */
4727 +#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040
4728 +/** Read: Interrupt occurred. */
4729 +#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040
4730 +/** OCTRLL 1 Error
4731 +    This bit is an indirect interrupt. */
4732 +#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020
4733 +/* Nothing
4734 +#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */
4735 +/** Write: Acknowledge the interrupt. */
4736 +#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020
4737 +/** Read: Interrupt occurred. */
4738 +#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020
4739 +/** OCTRLL 0 Error
4740 +    This bit is an indirect interrupt. */
4741 +#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010
4742 +/* Nothing
4743 +#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */
4744 +/** Write: Acknowledge the interrupt. */
4745 +#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010
4746 +/** Read: Interrupt occurred. */
4747 +#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010
4748 +/** ICTRLL 3 Error
4749 +    This bit is an indirect interrupt. */
4750 +#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008
4751 +/* Nothing
4752 +#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */
4753 +/** Write: Acknowledge the interrupt. */
4754 +#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008
4755 +/** Read: Interrupt occurred. */
4756 +#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008
4757 +/** ICTRLL 2 Error
4758 +    This bit is an indirect interrupt. */
4759 +#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004
4760 +/* Nothing
4761 +#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */
4762 +/** Write: Acknowledge the interrupt. */
4763 +#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004
4764 +/** Read: Interrupt occurred. */
4765 +#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004
4766 +/** ICTRLL 1 Error
4767 +    This bit is an indirect interrupt. */
4768 +#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002
4769 +/* Nothing
4770 +#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */
4771 +/** Write: Acknowledge the interrupt. */
4772 +#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002
4773 +/** Read: Interrupt occurred. */
4774 +#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002
4775 +/** ICTRLL 0 Error
4776 +    This bit is an indirect interrupt. */
4777 +#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001
4778 +/* Nothing
4779 +#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */
4780 +/** Write: Acknowledge the interrupt. */
4781 +#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001
4782 +/** Read: Interrupt occurred. */
4783 +#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001
4784 +
4785 +/* Fields of "IM4 Interrupt Enable Register" */
4786 +/** VPE0 Performance Monitoring Counter Interrupt
4787 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4788 +#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000
4789 +/* Disable
4790 +#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */
4791 +/** Enable */
4792 +#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000
4793 +/** VPE0 Error Level Flag Interrupt
4794 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4795 +#define ICU0_IM4_IER_VPE0_ERL 0x40000000
4796 +/* Disable
4797 +#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */
4798 +/** Enable */
4799 +#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000
4800 +/** VPE0 Exception Level Flag Interrupt
4801 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4802 +#define ICU0_IM4_IER_VPE0_EXL 0x20000000
4803 +/* Disable
4804 +#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */
4805 +/** Enable */
4806 +#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000
4807 +/** MPS Bin. Sem Interrupt to VPE0
4808 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4809 +#define ICU0_IM4_IER_MPS_IR8 0x00400000
4810 +/* Disable
4811 +#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */
4812 +/** Enable */
4813 +#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000
4814 +/** MPS Global Interrupt to VPE0
4815 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4816 +#define ICU0_IM4_IER_MPS_IR7 0x00200000
4817 +/* Disable
4818 +#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */
4819 +/** Enable */
4820 +#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000
4821 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
4822 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4823 +#define ICU0_IM4_IER_MPS_IR6 0x00100000
4824 +/* Disable
4825 +#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */
4826 +/** Enable */
4827 +#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000
4828 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
4829 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4830 +#define ICU0_IM4_IER_MPS_IR5 0x00080000
4831 +/* Disable
4832 +#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */
4833 +/** Enable */
4834 +#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000
4835 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
4836 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4837 +#define ICU0_IM4_IER_MPS_IR4 0x00040000
4838 +/* Disable
4839 +#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */
4840 +/** Enable */
4841 +#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000
4842 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
4843 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4844 +#define ICU0_IM4_IER_MPS_IR3 0x00020000
4845 +/* Disable
4846 +#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */
4847 +/** Enable */
4848 +#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000
4849 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
4850 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4851 +#define ICU0_IM4_IER_MPS_IR2 0x00010000
4852 +/* Disable
4853 +#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */
4854 +/** Enable */
4855 +#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000
4856 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
4857 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4858 +#define ICU0_IM4_IER_MPS_IR1 0x00008000
4859 +/* Disable
4860 +#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */
4861 +/** Enable */
4862 +#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000
4863 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
4864 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4865 +#define ICU0_IM4_IER_MPS_IR0 0x00004000
4866 +/* Disable
4867 +#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */
4868 +/** Enable */
4869 +#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000
4870 +/** TMU Error
4871 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4872 +#define ICU0_IM4_IER_TMU_ERR 0x00001000
4873 +/* Disable
4874 +#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */
4875 +/** Enable */
4876 +#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000
4877 +/** FSQM Error
4878 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4879 +#define ICU0_IM4_IER_FSQM_ERR 0x00000800
4880 +/* Disable
4881 +#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */
4882 +/** Enable */
4883 +#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800
4884 +/** IQM Error
4885 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4886 +#define ICU0_IM4_IER_IQM_ERR 0x00000400
4887 +/* Disable
4888 +#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */
4889 +/** Enable */
4890 +#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400
4891 +/** OCTRLG Error
4892 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4893 +#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200
4894 +/* Disable
4895 +#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */
4896 +/** Enable */
4897 +#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200
4898 +/** ICTRLG Error
4899 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4900 +#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100
4901 +/* Disable
4902 +#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */
4903 +/** Enable */
4904 +#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100
4905 +/** OCTRLL 3 Error
4906 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4907 +#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080
4908 +/* Disable
4909 +#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */
4910 +/** Enable */
4911 +#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080
4912 +/** OCTRLL 2 Error
4913 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4914 +#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040
4915 +/* Disable
4916 +#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */
4917 +/** Enable */
4918 +#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040
4919 +/** OCTRLL 1 Error
4920 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4921 +#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020
4922 +/* Disable
4923 +#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */
4924 +/** Enable */
4925 +#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020
4926 +/** OCTRLL 0 Error
4927 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4928 +#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010
4929 +/* Disable
4930 +#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */
4931 +/** Enable */
4932 +#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010
4933 +/** ICTRLL 3 Error
4934 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4935 +#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008
4936 +/* Disable
4937 +#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */
4938 +/** Enable */
4939 +#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008
4940 +/** ICTRLL 2 Error
4941 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4942 +#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004
4943 +/* Disable
4944 +#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */
4945 +/** Enable */
4946 +#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004
4947 +/** ICTRLL 1 Error
4948 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4949 +#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002
4950 +/* Disable
4951 +#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */
4952 +/** Enable */
4953 +#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002
4954 +/** ICTRLL 0 Error
4955 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
4956 +#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001
4957 +/* Disable
4958 +#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */
4959 +/** Enable */
4960 +#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001
4961 +
4962 +/* Fields of "IM4 Interrupt Output Status Register" */
4963 +/** VPE0 Performance Monitoring Counter Interrupt
4964 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
4965 +#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000
4966 +/* Nothing
4967 +#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */
4968 +/** Read: Interrupt occurred. */
4969 +#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000
4970 +/** VPE0 Error Level Flag Interrupt
4971 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
4972 +#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000
4973 +/* Nothing
4974 +#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */
4975 +/** Read: Interrupt occurred. */
4976 +#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000
4977 +/** VPE0 Exception Level Flag Interrupt
4978 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
4979 +#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000
4980 +/* Nothing
4981 +#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */
4982 +/** Read: Interrupt occurred. */
4983 +#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000
4984 +/** MPS Bin. Sem Interrupt to VPE0
4985 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
4986 +#define ICU0_IM4_IOSR_MPS_IR8 0x00400000
4987 +/* Nothing
4988 +#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */
4989 +/** Read: Interrupt occurred. */
4990 +#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000
4991 +/** MPS Global Interrupt to VPE0
4992 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
4993 +#define ICU0_IM4_IOSR_MPS_IR7 0x00200000
4994 +/* Nothing
4995 +#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */
4996 +/** Read: Interrupt occurred. */
4997 +#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000
4998 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
4999 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5000 +#define ICU0_IM4_IOSR_MPS_IR6 0x00100000
5001 +/* Nothing
5002 +#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */
5003 +/** Read: Interrupt occurred. */
5004 +#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000
5005 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5006 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5007 +#define ICU0_IM4_IOSR_MPS_IR5 0x00080000
5008 +/* Nothing
5009 +#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */
5010 +/** Read: Interrupt occurred. */
5011 +#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000
5012 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5013 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5014 +#define ICU0_IM4_IOSR_MPS_IR4 0x00040000
5015 +/* Nothing
5016 +#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */
5017 +/** Read: Interrupt occurred. */
5018 +#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000
5019 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5020 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5021 +#define ICU0_IM4_IOSR_MPS_IR3 0x00020000
5022 +/* Nothing
5023 +#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */
5024 +/** Read: Interrupt occurred. */
5025 +#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000
5026 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5027 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5028 +#define ICU0_IM4_IOSR_MPS_IR2 0x00010000
5029 +/* Nothing
5030 +#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */
5031 +/** Read: Interrupt occurred. */
5032 +#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000
5033 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5034 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5035 +#define ICU0_IM4_IOSR_MPS_IR1 0x00008000
5036 +/* Nothing
5037 +#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */
5038 +/** Read: Interrupt occurred. */
5039 +#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000
5040 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5041 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5042 +#define ICU0_IM4_IOSR_MPS_IR0 0x00004000
5043 +/* Nothing
5044 +#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */
5045 +/** Read: Interrupt occurred. */
5046 +#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000
5047 +/** TMU Error
5048 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5049 +#define ICU0_IM4_IOSR_TMU_ERR 0x00001000
5050 +/* Nothing
5051 +#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */
5052 +/** Read: Interrupt occurred. */
5053 +#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000
5054 +/** FSQM Error
5055 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5056 +#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800
5057 +/* Nothing
5058 +#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */
5059 +/** Read: Interrupt occurred. */
5060 +#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800
5061 +/** IQM Error
5062 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5063 +#define ICU0_IM4_IOSR_IQM_ERR 0x00000400
5064 +/* Nothing
5065 +#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */
5066 +/** Read: Interrupt occurred. */
5067 +#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400
5068 +/** OCTRLG Error
5069 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5070 +#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200
5071 +/* Nothing
5072 +#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */
5073 +/** Read: Interrupt occurred. */
5074 +#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200
5075 +/** ICTRLG Error
5076 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5077 +#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100
5078 +/* Nothing
5079 +#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */
5080 +/** Read: Interrupt occurred. */
5081 +#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100
5082 +/** OCTRLL 3 Error
5083 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5084 +#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080
5085 +/* Nothing
5086 +#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */
5087 +/** Read: Interrupt occurred. */
5088 +#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080
5089 +/** OCTRLL 2 Error
5090 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5091 +#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040
5092 +/* Nothing
5093 +#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */
5094 +/** Read: Interrupt occurred. */
5095 +#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040
5096 +/** OCTRLL 1 Error
5097 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5098 +#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020
5099 +/* Nothing
5100 +#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */
5101 +/** Read: Interrupt occurred. */
5102 +#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020
5103 +/** OCTRLL 0 Error
5104 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5105 +#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010
5106 +/* Nothing
5107 +#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */
5108 +/** Read: Interrupt occurred. */
5109 +#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010
5110 +/** ICTRLL 3 Error
5111 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5112 +#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008
5113 +/* Nothing
5114 +#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */
5115 +/** Read: Interrupt occurred. */
5116 +#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008
5117 +/** ICTRLL 2 Error
5118 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5119 +#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004
5120 +/* Nothing
5121 +#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */
5122 +/** Read: Interrupt occurred. */
5123 +#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004
5124 +/** ICTRLL 1 Error
5125 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5126 +#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002
5127 +/* Nothing
5128 +#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */
5129 +/** Read: Interrupt occurred. */
5130 +#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002
5131 +/** ICTRLL 0 Error
5132 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5133 +#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001
5134 +/* Nothing
5135 +#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */
5136 +/** Read: Interrupt occurred. */
5137 +#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001
5138 +
5139 +/* Fields of "IM4 Interrupt Request Set Register" */
5140 +/** VPE0 Performance Monitoring Counter Interrupt
5141 +    Software control for the corresponding bit in the IM4_ISR register. */
5142 +#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000
5143 +/** VPE0 Error Level Flag Interrupt
5144 +    Software control for the corresponding bit in the IM4_ISR register. */
5145 +#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000
5146 +/** VPE0 Exception Level Flag Interrupt
5147 +    Software control for the corresponding bit in the IM4_ISR register. */
5148 +#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000
5149 +/** MPS Bin. Sem Interrupt to VPE0
5150 +    Software control for the corresponding bit in the IM4_ISR register. */
5151 +#define ICU0_IM4_IRSR_MPS_IR8 0x00400000
5152 +/** MPS Global Interrupt to VPE0
5153 +    Software control for the corresponding bit in the IM4_ISR register. */
5154 +#define ICU0_IM4_IRSR_MPS_IR7 0x00200000
5155 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5156 +    Software control for the corresponding bit in the IM4_ISR register. */
5157 +#define ICU0_IM4_IRSR_MPS_IR6 0x00100000
5158 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5159 +    Software control for the corresponding bit in the IM4_ISR register. */
5160 +#define ICU0_IM4_IRSR_MPS_IR5 0x00080000
5161 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5162 +    Software control for the corresponding bit in the IM4_ISR register. */
5163 +#define ICU0_IM4_IRSR_MPS_IR4 0x00040000
5164 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5165 +    Software control for the corresponding bit in the IM4_ISR register. */
5166 +#define ICU0_IM4_IRSR_MPS_IR3 0x00020000
5167 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5168 +    Software control for the corresponding bit in the IM4_ISR register. */
5169 +#define ICU0_IM4_IRSR_MPS_IR2 0x00010000
5170 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5171 +    Software control for the corresponding bit in the IM4_ISR register. */
5172 +#define ICU0_IM4_IRSR_MPS_IR1 0x00008000
5173 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5174 +    Software control for the corresponding bit in the IM4_ISR register. */
5175 +#define ICU0_IM4_IRSR_MPS_IR0 0x00004000
5176 +/** TMU Error
5177 +    Software control for the corresponding bit in the IM4_ISR register. */
5178 +#define ICU0_IM4_IRSR_TMU_ERR 0x00001000
5179 +/** FSQM Error
5180 +    Software control for the corresponding bit in the IM4_ISR register. */
5181 +#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800
5182 +/** IQM Error
5183 +    Software control for the corresponding bit in the IM4_ISR register. */
5184 +#define ICU0_IM4_IRSR_IQM_ERR 0x00000400
5185 +/** OCTRLG Error
5186 +    Software control for the corresponding bit in the IM4_ISR register. */
5187 +#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200
5188 +/** ICTRLG Error
5189 +    Software control for the corresponding bit in the IM4_ISR register. */
5190 +#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100
5191 +/** OCTRLL 3 Error
5192 +    Software control for the corresponding bit in the IM4_ISR register. */
5193 +#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080
5194 +/** OCTRLL 2 Error
5195 +    Software control for the corresponding bit in the IM4_ISR register. */
5196 +#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040
5197 +/** OCTRLL 1 Error
5198 +    Software control for the corresponding bit in the IM4_ISR register. */
5199 +#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020
5200 +/** OCTRLL 0 Error
5201 +    Software control for the corresponding bit in the IM4_ISR register. */
5202 +#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010
5203 +/** ICTRLL 3 Error
5204 +    Software control for the corresponding bit in the IM4_ISR register. */
5205 +#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008
5206 +/** ICTRLL 2 Error
5207 +    Software control for the corresponding bit in the IM4_ISR register. */
5208 +#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004
5209 +/** ICTRLL 1 Error
5210 +    Software control for the corresponding bit in the IM4_ISR register. */
5211 +#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002
5212 +/** ICTRLL 0 Error
5213 +    Software control for the corresponding bit in the IM4_ISR register. */
5214 +#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001
5215 +
5216 +/* Fields of "IM4 Interrupt Mode Register" */
5217 +/** VPE0 Performance Monitoring Counter Interrupt
5218 +    Type of interrupt. */
5219 +#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000
5220 +/* Indirect Interrupt.
5221 +#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */
5222 +/** Direct Interrupt. */
5223 +#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000
5224 +/** VPE0 Error Level Flag Interrupt
5225 +    Type of interrupt. */
5226 +#define ICU0_IM4_IMR_VPE0_ERL 0x40000000
5227 +/* Indirect Interrupt.
5228 +#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */
5229 +/** Direct Interrupt. */
5230 +#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000
5231 +/** VPE0 Exception Level Flag Interrupt
5232 +    Type of interrupt. */
5233 +#define ICU0_IM4_IMR_VPE0_EXL 0x20000000
5234 +/* Indirect Interrupt.
5235 +#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */
5236 +/** Direct Interrupt. */
5237 +#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000
5238 +/** MPS Bin. Sem Interrupt to VPE0
5239 +    Type of interrupt. */
5240 +#define ICU0_IM4_IMR_MPS_IR8 0x00400000
5241 +/* Indirect Interrupt.
5242 +#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */
5243 +/** Direct Interrupt. */
5244 +#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000
5245 +/** MPS Global Interrupt to VPE0
5246 +    Type of interrupt. */
5247 +#define ICU0_IM4_IMR_MPS_IR7 0x00200000
5248 +/* Indirect Interrupt.
5249 +#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */
5250 +/** Direct Interrupt. */
5251 +#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000
5252 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5253 +    Type of interrupt. */
5254 +#define ICU0_IM4_IMR_MPS_IR6 0x00100000
5255 +/* Indirect Interrupt.
5256 +#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */
5257 +/** Direct Interrupt. */
5258 +#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000
5259 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5260 +    Type of interrupt. */
5261 +#define ICU0_IM4_IMR_MPS_IR5 0x00080000
5262 +/* Indirect Interrupt.
5263 +#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */
5264 +/** Direct Interrupt. */
5265 +#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000
5266 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5267 +    Type of interrupt. */
5268 +#define ICU0_IM4_IMR_MPS_IR4 0x00040000
5269 +/* Indirect Interrupt.
5270 +#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */
5271 +/** Direct Interrupt. */
5272 +#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000
5273 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5274 +    Type of interrupt. */
5275 +#define ICU0_IM4_IMR_MPS_IR3 0x00020000
5276 +/* Indirect Interrupt.
5277 +#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */
5278 +/** Direct Interrupt. */
5279 +#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000
5280 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5281 +    Type of interrupt. */
5282 +#define ICU0_IM4_IMR_MPS_IR2 0x00010000
5283 +/* Indirect Interrupt.
5284 +#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */
5285 +/** Direct Interrupt. */
5286 +#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000
5287 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5288 +    Type of interrupt. */
5289 +#define ICU0_IM4_IMR_MPS_IR1 0x00008000
5290 +/* Indirect Interrupt.
5291 +#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */
5292 +/** Direct Interrupt. */
5293 +#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000
5294 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5295 +    Type of interrupt. */
5296 +#define ICU0_IM4_IMR_MPS_IR0 0x00004000
5297 +/* Indirect Interrupt.
5298 +#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */
5299 +/** Direct Interrupt. */
5300 +#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000
5301 +/** TMU Error
5302 +    Type of interrupt. */
5303 +#define ICU0_IM4_IMR_TMU_ERR 0x00001000
5304 +/* Indirect Interrupt.
5305 +#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */
5306 +/** Direct Interrupt. */
5307 +#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000
5308 +/** FSQM Error
5309 +    Type of interrupt. */
5310 +#define ICU0_IM4_IMR_FSQM_ERR 0x00000800
5311 +/* Indirect Interrupt.
5312 +#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */
5313 +/** Direct Interrupt. */
5314 +#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800
5315 +/** IQM Error
5316 +    Type of interrupt. */
5317 +#define ICU0_IM4_IMR_IQM_ERR 0x00000400
5318 +/* Indirect Interrupt.
5319 +#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */
5320 +/** Direct Interrupt. */
5321 +#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400
5322 +/** OCTRLG Error
5323 +    Type of interrupt. */
5324 +#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200
5325 +/* Indirect Interrupt.
5326 +#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */
5327 +/** Direct Interrupt. */
5328 +#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200
5329 +/** ICTRLG Error
5330 +    Type of interrupt. */
5331 +#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100
5332 +/* Indirect Interrupt.
5333 +#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */
5334 +/** Direct Interrupt. */
5335 +#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100
5336 +/** OCTRLL 3 Error
5337 +    Type of interrupt. */
5338 +#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080
5339 +/* Indirect Interrupt.
5340 +#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */
5341 +/** Direct Interrupt. */
5342 +#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080
5343 +/** OCTRLL 2 Error
5344 +    Type of interrupt. */
5345 +#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040
5346 +/* Indirect Interrupt.
5347 +#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */
5348 +/** Direct Interrupt. */
5349 +#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040
5350 +/** OCTRLL 1 Error
5351 +    Type of interrupt. */
5352 +#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020
5353 +/* Indirect Interrupt.
5354 +#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */
5355 +/** Direct Interrupt. */
5356 +#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020
5357 +/** OCTRLL 0 Error
5358 +    Type of interrupt. */
5359 +#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010
5360 +/* Indirect Interrupt.
5361 +#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */
5362 +/** Direct Interrupt. */
5363 +#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010
5364 +/** ICTRLL 3 Error
5365 +    Type of interrupt. */
5366 +#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008
5367 +/* Indirect Interrupt.
5368 +#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */
5369 +/** Direct Interrupt. */
5370 +#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008
5371 +/** ICTRLL 2 Error
5372 +    Type of interrupt. */
5373 +#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004
5374 +/* Indirect Interrupt.
5375 +#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */
5376 +/** Direct Interrupt. */
5377 +#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004
5378 +/** ICTRLL 1 Error
5379 +    Type of interrupt. */
5380 +#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002
5381 +/* Indirect Interrupt.
5382 +#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */
5383 +/** Direct Interrupt. */
5384 +#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002
5385 +/** ICTRLL 0 Error
5386 +    Type of interrupt. */
5387 +#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001
5388 +/* Indirect Interrupt.
5389 +#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */
5390 +/** Direct Interrupt. */
5391 +#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001
5392 +
5393 +/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */
5394 +/** IM4 Interrupt Vector Value
5395 +    Returns the highest priority pending interrupt vector. */
5396 +#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000
5397 +/** field offset */
5398 +#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20
5399 +/** Interrupt pending at bit 31 or no pending interrupt */
5400 +#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000
5401 +/** Interrupt pending at bit 0. */
5402 +#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000
5403 +/** Interrupt pending at bit 1. */
5404 +#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000
5405 +/** Interrupt pending at bit 30. */
5406 +#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000
5407 +/** IM3 Interrupt Vector Value
5408 +    Returns the highest priority pending interrupt vector. */
5409 +#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000
5410 +/** field offset */
5411 +#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15
5412 +/** Interrupt pending at bit 31 or no pending interrupt */
5413 +#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000
5414 +/** Interrupt pending at bit 0. */
5415 +#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000
5416 +/** Interrupt pending at bit 1. */
5417 +#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000
5418 +/** Interrupt pending at bit 30. */
5419 +#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000
5420 +/** IM2 Interrupt Vector Value
5421 +    Returns the highest priority pending interrupt vector. */
5422 +#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00
5423 +/** field offset */
5424 +#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10
5425 +/** Interrupt pending at bit 31 or no pending interrupt */
5426 +#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000
5427 +/** Interrupt pending at bit 0. */
5428 +#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400
5429 +/** Interrupt pending at bit 1. */
5430 +#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800
5431 +/** Interrupt pending at bit 30. */
5432 +#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00
5433 +/** IM1 Interrupt Vector Value
5434 +    Returns the highest priority pending interrupt vector. */
5435 +#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0
5436 +/** field offset */
5437 +#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5
5438 +/** Interrupt pending at bit 31 or no pending interrupt */
5439 +#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000
5440 +/** Interrupt pending at bit 0. */
5441 +#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020
5442 +/** Interrupt pending at bit 1. */
5443 +#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040
5444 +/** Interrupt pending at bit 30. */
5445 +#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0
5446 +/** IM0 Interrupt Vector Value
5447 +    Returns the highest priority pending interrupt vector. */
5448 +#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F
5449 +/** field offset */
5450 +#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0
5451 +/** Interrupt pending at bit 31 or no pending interrupt */
5452 +#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000
5453 +/** Interrupt pending at bit 0. */
5454 +#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001
5455 +/** Interrupt pending at bit 1. */
5456 +#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002
5457 +/** Interrupt pending at bit 30. */
5458 +#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F
5459 +
5460 +/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */
5461 +/** IM4 Interrupt Vector Value
5462 +    Returns the highest priority pending interrupt vector. */
5463 +#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000
5464 +/** field offset */
5465 +#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24
5466 +/** No pending interrupt */
5467 +#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000
5468 +/** Interrupt pending at bit 0. */
5469 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000
5470 +/** Interrupt pending at bit 1. */
5471 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000
5472 +/** Interrupt pending at bit 30. */
5473 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000
5474 +/** Interrupt pending at bit 31. */
5475 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000
5476 +/** IM3 Interrupt Vector Value
5477 +    Returns the highest priority pending interrupt vector. */
5478 +#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000
5479 +/** field offset */
5480 +#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18
5481 +/** No pending interrupt */
5482 +#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000
5483 +/** Interrupt pending at bit 0. */
5484 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000
5485 +/** Interrupt pending at bit 1. */
5486 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000
5487 +/** Interrupt pending at bit 30. */
5488 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000
5489 +/** Interrupt pending at bit 31. */
5490 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000
5491 +/** IM2 Interrupt Vector Value
5492 +    Returns the highest priority pending interrupt vector. */
5493 +#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000
5494 +/** field offset */
5495 +#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12
5496 +/** No pending interrupt */
5497 +#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000
5498 +/** Interrupt pending at bit 0. */
5499 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000
5500 +/** Interrupt pending at bit 1. */
5501 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000
5502 +/** Interrupt pending at bit 30. */
5503 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000
5504 +/** Interrupt pending at bit 31. */
5505 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000
5506 +/** IM1 Interrupt Vector Value
5507 +    Returns the highest priority pending interrupt vector. */
5508 +#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0
5509 +/** field offset */
5510 +#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6
5511 +/** No pending interrupt */
5512 +#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000
5513 +/** Interrupt pending at bit 0. */
5514 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040
5515 +/** Interrupt pending at bit 1. */
5516 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080
5517 +/** Interrupt pending at bit 30. */
5518 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0
5519 +/** Interrupt pending at bit 31. */
5520 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800
5521 +/** IM0 Interrupt Vector Value
5522 +    Returns the highest priority pending interrupt vector. */
5523 +#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F
5524 +/** field offset */
5525 +#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0
5526 +/** No pending interrupt */
5527 +#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000
5528 +/** Interrupt pending at bit 0. */
5529 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001
5530 +/** Interrupt pending at bit 1. */
5531 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002
5532 +/** Interrupt pending at bit 30. */
5533 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F
5534 +/** Interrupt pending at bit 31. */
5535 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020
5536 +
5537 +/*! @} */ /* ICU0_REGISTER */
5538 +
5539 +#endif /* _icu0_reg_h */
5540 --- /dev/null
5541 +++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h
5542 @@ -0,0 +1,529 @@
5543 +/******************************************************************************
5544 +
5545 +                               Copyright (c) 2010
5546 +                            Lantiq Deutschland GmbH
5547 +
5548 +  For licensing information, see the file 'LICENSE' in the root folder of
5549 +  this software module.
5550 +
5551 +******************************************************************************/
5552 +
5553 +#ifndef _status_reg_h
5554 +#define _status_reg_h
5555 +
5556 +/** \addtogroup STATUS_REGISTER
5557 +   @{
5558 +*/
5559 +/* access macros */
5560 +#define status_r32(reg) reg_r32(&status->reg)
5561 +#define status_w32(val, reg) reg_w32(val, &status->reg)
5562 +#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg)
5563 +#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx)
5564 +#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx)
5565 +#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx)
5566 +#define status_adr_table(reg, idx) adr_table(status->reg, idx)
5567 +
5568 +
5569 +/** STATUS register structure */
5570 +struct gpon_reg_status
5571 +{
5572 +   /** Reserved */
5573 +   unsigned int res_0[3]; /* 0x00000000 */
5574 +   /** Chip Identification Register */
5575 +   unsigned int chipid; /* 0x0000000C */
5576 +   /** Chip Location Register
5577 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5578 +   unsigned int chiploc; /* 0x00000010 */
5579 +   /** Redundancy register
5580 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5581 +   unsigned int red0; /* 0x00000014 */
5582 +   /** Redundancy register
5583 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5584 +   unsigned int red1; /* 0x00000018 */
5585 +   /** Redundancy register
5586 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5587 +   unsigned int red2; /* 0x0000001C */
5588 +   /** Redundancy register
5589 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5590 +   unsigned int red3; /* 0x00000020 */
5591 +   /** Redundancy register
5592 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5593 +   unsigned int red4; /* 0x00000024 */
5594 +   /** Redundancy register
5595 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5596 +   unsigned int red5; /* 0x00000028 */
5597 +   /** Redundancy register
5598 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5599 +   unsigned int red6; /* 0x0000002C */
5600 +   /** Redundancy register
5601 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5602 +   unsigned int red7; /* 0x00000030 */
5603 +   /** Redundancy register
5604 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5605 +   unsigned int red8; /* 0x00000034 */
5606 +   /** SPARE fuse register 0
5607 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5608 +   unsigned int fuse0; /* 0x00000038 */
5609 +   /** Fuses for Analog modules
5610 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5611 +   unsigned int analog; /* 0x0000003C */
5612 +   /** Configuration fuses for drivers and pll
5613 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5614 +   unsigned int config; /* 0x00000040 */
5615 +   /** SPARE fuse register 1
5616 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5617 +   unsigned int fuse1; /* 0x00000044 */
5618 +   /** Configuration for sbs0 rambist */
5619 +   unsigned int mbcfg; /* 0x00000048 */
5620 +   /** sbs0 bist result and debug data */
5621 +   unsigned int mbdata; /* 0x0000004C */
5622 +   /** Reserved */
5623 +   unsigned int res_1[12]; /* 0x00000050 */
5624 +};
5625 +
5626 +
5627 +/* Fields of "Chip Identification Register" */
5628 +/** Chip Version Number
5629 +    Version number */
5630 +#define STATUS_CHIPID_VERSION_MASK 0xF0000000
5631 +/** field offset */
5632 +#define STATUS_CHIPID_VERSION_OFFSET 28
5633 +/** Part Number, Constant Part
5634 +    The Part Number is fixed to 016Bhex. */
5635 +#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000
5636 +/** field offset */
5637 +#define STATUS_CHIPID_PARTNR_OFFSET 12
5638 +/** Manufacturer ID
5639 +    The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */
5640 +#define STATUS_CHIPID_MANID_MASK 0x00000FFE
5641 +/** field offset */
5642 +#define STATUS_CHIPID_MANID_OFFSET 1
5643 +/** Constant bit
5644 +    The value of bit field CONST1 is fixed to 1hex */
5645 +#define STATUS_CHIPID_CONST1 0x00000001
5646 +
5647 +/* Fields of "Chip Location Register" */
5648 +/** Chip Lot ID */
5649 +#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000
5650 +/** field offset */
5651 +#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16
5652 +/** Chip X Coordinate */
5653 +#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00
5654 +/** field offset */
5655 +#define STATUS_CHIPLOC_CHIPX_OFFSET 8
5656 +/** Chip Y Coordinate */
5657 +#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF
5658 +/** field offset */
5659 +#define STATUS_CHIPLOC_CHIPY_OFFSET 0
5660 +
5661 +/* Fields of "Redundancy register" */
5662 +/** Redundancy
5663 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5664 +#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF
5665 +/** field offset */
5666 +#define STATUS_RED0_REDUNDANCY_OFFSET 0
5667 +
5668 +/* Fields of "Redundancy register" */
5669 +/** Redundancy
5670 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5671 +#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF
5672 +/** field offset */
5673 +#define STATUS_RED1_REDUNDANCY_OFFSET 0
5674 +
5675 +/* Fields of "Redundancy register" */
5676 +/** Redundancy
5677 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5678 +#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF
5679 +/** field offset */
5680 +#define STATUS_RED2_REDUNDANCY_OFFSET 0
5681 +
5682 +/* Fields of "Redundancy register" */
5683 +/** Redundancy
5684 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5685 +#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF
5686 +/** field offset */
5687 +#define STATUS_RED3_REDUNDANCY_OFFSET 0
5688 +
5689 +/* Fields of "Redundancy register" */
5690 +/** Redundancy
5691 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5692 +#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF
5693 +/** field offset */
5694 +#define STATUS_RED4_REDUNDANCY_OFFSET 0
5695 +
5696 +/* Fields of "Redundancy register" */
5697 +/** Redundancy
5698 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5699 +#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF
5700 +/** field offset */
5701 +#define STATUS_RED5_REDUNDANCY_OFFSET 0
5702 +
5703 +/* Fields of "Redundancy register" */
5704 +/** Redundancy
5705 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5706 +#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF
5707 +/** field offset */
5708 +#define STATUS_RED6_REDUNDANCY_OFFSET 0
5709 +
5710 +/* Fields of "Redundancy register" */
5711 +/** Redundancy
5712 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5713 +#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF
5714 +/** field offset */
5715 +#define STATUS_RED7_REDUNDANCY_OFFSET 0
5716 +
5717 +/* Fields of "Redundancy register" */
5718 +/** Redundancy
5719 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5720 +#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF
5721 +/** field offset */
5722 +#define STATUS_RED8_REDUNDANCY_OFFSET 0
5723 +
5724 +/* Fields of "SPARE fuse register 0" */
5725 +/** Soft fuse control
5726 +    Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */
5727 +#define STATUS_FUSE0_SFC 0x80000000
5728 +/* Not selected
5729 +#define STATUS_FUSE0_SFC_NSEL 0x00000000 */
5730 +/** Selected */
5731 +#define STATUS_FUSE0_SFC_SEL 0x80000000
5732 +/** Soft control MBCFG
5733 +    Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */
5734 +#define STATUS_FUSE0_SC_MBCFG 0x40000000
5735 +/* Not selected
5736 +#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */
5737 +/** Selected */
5738 +#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000
5739 +/** spare fuse0
5740 +    eFuses not assigned to hw/sw, can be used for future applications */
5741 +#define STATUS_FUSE0_F0_MASK 0x3C000000
5742 +/** field offset */
5743 +#define STATUS_FUSE0_F0_OFFSET 26
5744 +/** VCALMM20 Voltage Reference
5745 +    Voltage Reference for calibration via R and constant current (20 uA) */
5746 +#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000
5747 +/** field offset */
5748 +#define STATUS_FUSE0_VCALMM20_OFFSET 20
5749 +/** VCALMM100 Voltage Reference
5750 +    Voltage Reference for calibration via R and constant current (100 uA) */
5751 +#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000
5752 +/** field offset */
5753 +#define STATUS_FUSE0_VCALMM100_OFFSET 14
5754 +/** VCALMM400 Voltage Reference
5755 +    Voltage Reference for calibration via R and constant current (400 uA) */
5756 +#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00
5757 +/** field offset */
5758 +#define STATUS_FUSE0_VCALMM400_OFFSET 8
5759 +/** RCALMM R error correction
5760 +    The resistance deviation from ideal R (1000 Ohm) */
5761 +#define STATUS_FUSE0_RCALMM_MASK 0x000000FF
5762 +/** field offset */
5763 +#define STATUS_FUSE0_RCALMM_OFFSET 0
5764 +
5765 +/* Fields of "Fuses for Analog modules" */
5766 +/** reserved Analog eFuses
5767 +    Reserved Register contains information stored in eFuses needed for the analog modules */
5768 +#define STATUS_ANALOG_A0_MASK 0xFF000000
5769 +/** field offset */
5770 +#define STATUS_ANALOG_A0_OFFSET 24
5771 +/** Absolut Temperature
5772 +    Temperature ERROR */
5773 +#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000
5774 +/** field offset */
5775 +#define STATUS_ANALOG_TEMPMM_OFFSET 18
5776 +/** Bias Voltage Generation
5777 +    temperature dependency */
5778 +#define STATUS_ANALOG_TBGP_MASK 0x00038000
5779 +/** field offset */
5780 +#define STATUS_ANALOG_TBGP_OFFSET 15
5781 +/** Bias Voltage Generation
5782 +    voltage dependency */
5783 +#define STATUS_ANALOG_VBGP_MASK 0x00007000
5784 +/** field offset */
5785 +#define STATUS_ANALOG_VBGP_OFFSET 12
5786 +/** Bias Current Generation */
5787 +#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00
5788 +/** field offset */
5789 +#define STATUS_ANALOG_IREFBGP_OFFSET 8
5790 +/** Drive DAC Gain */
5791 +#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0
5792 +/** field offset */
5793 +#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4
5794 +/** BIAS DAC Gain */
5795 +#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F
5796 +/** field offset */
5797 +#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0
5798 +
5799 +/* Fields of "Configuration fuses for drivers and pll" */
5800 +/** ddr PU driver
5801 +    ddr pullup driver strength adjustment */
5802 +#define STATUS_CONFIG_DDRPU_MASK 0xC0000000
5803 +/** field offset */
5804 +#define STATUS_CONFIG_DDRPU_OFFSET 30
5805 +/** ddr PD driver
5806 +    ddr pulldown driver strength adjustment */
5807 +#define STATUS_CONFIG_DDRPD_MASK 0x30000000
5808 +/** field offset */
5809 +#define STATUS_CONFIG_DDRPD_OFFSET 28
5810 +/** Authentification Unit enable
5811 +    This bit can only be set via eFuse and enables the authentification unit. */
5812 +#define STATUS_CONFIG_SHA1EN 0x08000000
5813 +/* Not selected
5814 +#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */
5815 +/** Selected */
5816 +#define STATUS_CONFIG_SHA1EN_SEL 0x08000000
5817 +/** Encryption Unit enable
5818 +    This bit can only be set via eFuse and enables the encryption unit. */
5819 +#define STATUS_CONFIG_AESEN 0x04000000
5820 +/* Not selected
5821 +#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */
5822 +/** Selected */
5823 +#define STATUS_CONFIG_AESEN_SEL 0x04000000
5824 +/** Subversion Number
5825 +    The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */
5826 +#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000
5827 +/** field offset */
5828 +#define STATUS_CONFIG_SUBVERS_OFFSET 22
5829 +/** PLL settings
5830 +    PLL settings for infrastructure block */
5831 +#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000
5832 +/** field offset */
5833 +#define STATUS_CONFIG_PLLINFRA_OFFSET 12
5834 +/** GPE frequency selection
5835 +    Scaling down the GPE frequency for debugging purpose */
5836 +#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00
5837 +/** field offset */
5838 +#define STATUS_CONFIG_GPEFREQ_OFFSET 10
5839 +/** RM enable
5840 +    Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */
5841 +#define STATUS_CONFIG_RME 0x00000200
5842 +/* Not selected
5843 +#define STATUS_CONFIG_RME_NSEL 0x00000000 */
5844 +/** Selected */
5845 +#define STATUS_CONFIG_RME_SEL 0x00000200
5846 +/** RM settings
5847 +    Read Marging Settings for all VIRAGE Memories except GPE */
5848 +#define STATUS_CONFIG_RM_MASK 0x000001E0
5849 +/** field offset */
5850 +#define STATUS_CONFIG_RM_OFFSET 5
5851 +/** RM enable for GPE Memories
5852 +    Activates the Read Margin Settings defined in the RM Field */
5853 +#define STATUS_CONFIG_RMEGPE 0x00000010
5854 +/* Not selected
5855 +#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */
5856 +/** Selected */
5857 +#define STATUS_CONFIG_RMEGPE_SEL 0x00000010
5858 +/** RM settings for GPE Memories
5859 +    Read Marging Settings for VIRAGE Memories in GPE module */
5860 +#define STATUS_CONFIG_RMGPE_MASK 0x0000000F
5861 +/** field offset */
5862 +#define STATUS_CONFIG_RMGPE_OFFSET 0
5863 +
5864 +/* Fields of "SPARE fuse register 1" */
5865 +/** spare fuse1
5866 +    eFuses not assigned to hw/sw, can be used for future applications */
5867 +#define STATUS_FUSE1_F1_MASK 0xFFF00000
5868 +/** field offset */
5869 +#define STATUS_FUSE1_F1_OFFSET 20
5870 +/** DCDC DDR OFFSET
5871 +    offset error sense path */
5872 +#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000
5873 +/** field offset */
5874 +#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16
5875 +/** DCDC DDR GAIN
5876 +    gain error sense path */
5877 +#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00
5878 +/** field offset */
5879 +#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10
5880 +/** DCDC APD OFFSET
5881 +    offset error sense path */
5882 +#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0
5883 +/** field offset */
5884 +#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6
5885 +/** DCDC APD GAIN
5886 +    gain error sense path */
5887 +#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F
5888 +/** field offset */
5889 +#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0
5890 +
5891 +/* Fields of "Configuration for sbs0 rambist" */
5892 +/** Disable asc monitoring during boot-up
5893 +    Bit is used to avoid asc output for reducing pattern count on testsystem */
5894 +#define STATUS_MBCFG_ASC_DBGDIS 0x01000000
5895 +/* Disable
5896 +#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */
5897 +/** Enable */
5898 +#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000
5899 +/** Descrambling Enable/Disable
5900 +    Enables Address and Data Descrambling for internal Memory Test */
5901 +#define STATUS_MBCFG_DSC 0x00800000
5902 +/* Disable
5903 +#define STATUS_MBCFG_DSC_DIS 0x00000000 */
5904 +/** Enable */
5905 +#define STATUS_MBCFG_DSC_EN 0x00800000
5906 +/** Enable repair mode
5907 +    When bit is set redundancy repair mode is activated */
5908 +#define STATUS_MBCFG_REPAIR 0x00400000
5909 +/* Disable
5910 +#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */
5911 +/** Enable */
5912 +#define STATUS_MBCFG_REPAIR_EN 0x00400000
5913 +/** DEBUG Mode */
5914 +#define STATUS_MBCFG_DBG 0x00200000
5915 +/* Disable
5916 +#define STATUS_MBCFG_DBG_DIS 0x00000000 */
5917 +/** Enable */
5918 +#define STATUS_MBCFG_DBG_EN 0x00200000
5919 +/** Retention Time
5920 +    Length oft the Retention Time */
5921 +#define STATUS_MBCFG_RTIME_MASK 0x001C0000
5922 +/** field offset */
5923 +#define STATUS_MBCFG_RTIME_OFFSET 18
5924 +/** retention mode is switched off */
5925 +#define STATUS_MBCFG_RTIME_RET0 0x00000000
5926 +/** Retention time 50 ms */
5927 +#define STATUS_MBCFG_RTIME_RET50 0x00040000
5928 +/** Retention time 60 ms */
5929 +#define STATUS_MBCFG_RTIME_RET60 0x00080000
5930 +/** Retention time 70 ms */
5931 +#define STATUS_MBCFG_RTIME_RET70 0x000C0000
5932 +/** Retention time 80 ms */
5933 +#define STATUS_MBCFG_RTIME_RET80 0x00100000
5934 +/** Retention time 90 ms */
5935 +#define STATUS_MBCFG_RTIME_RET90 0x00140000
5936 +/** Retention time 1000 ms */
5937 +#define STATUS_MBCFG_RTIME_RET1000 0x00180000
5938 +/** Test ID
5939 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
5940 +#define STATUS_MBCFG_TID_5_MASK 0x00038000
5941 +/** field offset */
5942 +#define STATUS_MBCFG_TID_5_OFFSET 15
5943 +/** No test is performed */
5944 +#define STATUS_MBCFG_TID_5_NONE 0x00000000
5945 +/** March test */
5946 +#define STATUS_MBCFG_TID_5_MARCH 0x00008000
5947 +/** Checkerboard test */
5948 +#define STATUS_MBCFG_TID_5_CHCK 0x00010000
5949 +/** Hammer test */
5950 +#define STATUS_MBCFG_TID_5_HAM 0x00018000
5951 +/** Address decoder test */
5952 +#define STATUS_MBCFG_TID_5_ADEC 0x00020000
5953 +/** Write mask byte test */
5954 +#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000
5955 +/** Reserved */
5956 +#define STATUS_MBCFG_TID_5_RES 0x00030000
5957 +/** Test ID
5958 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
5959 +#define STATUS_MBCFG_TID_4_MASK 0x00007000
5960 +/** field offset */
5961 +#define STATUS_MBCFG_TID_4_OFFSET 12
5962 +/** No test is performed */
5963 +#define STATUS_MBCFG_TID_4_NONE 0x00000000
5964 +/** March test */
5965 +#define STATUS_MBCFG_TID_4_MARCH 0x00001000
5966 +/** Checkerboard test */
5967 +#define STATUS_MBCFG_TID_4_CHCK 0x00002000
5968 +/** Hammer test */
5969 +#define STATUS_MBCFG_TID_4_HAM 0x00003000
5970 +/** Address decoder test */
5971 +#define STATUS_MBCFG_TID_4_ADEC 0x00004000
5972 +/** Write mask byte test */
5973 +#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000
5974 +/** Reserved */
5975 +#define STATUS_MBCFG_TID_4_RES 0x00006000
5976 +/** Test ID
5977 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
5978 +#define STATUS_MBCFG_TID_3_MASK 0x00000E00
5979 +/** field offset */
5980 +#define STATUS_MBCFG_TID_3_OFFSET 9
5981 +/** No test is performed */
5982 +#define STATUS_MBCFG_TID_3_NONE 0x00000000
5983 +/** March test */
5984 +#define STATUS_MBCFG_TID_3_MARCH 0x00000200
5985 +/** Checkerboard test */
5986 +#define STATUS_MBCFG_TID_3_CHCK 0x00000400
5987 +/** Hammer test */
5988 +#define STATUS_MBCFG_TID_3_HAM 0x00000600
5989 +/** Address decoder test */
5990 +#define STATUS_MBCFG_TID_3_ADEC 0x00000800
5991 +/** Write mask byte test */
5992 +#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00
5993 +/** Reserved */
5994 +#define STATUS_MBCFG_TID_3_RES 0x00000C00
5995 +/** Test ID
5996 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
5997 +#define STATUS_MBCFG_TID_2_MASK 0x000001C0
5998 +/** field offset */
5999 +#define STATUS_MBCFG_TID_2_OFFSET 6
6000 +/** No test is performed */
6001 +#define STATUS_MBCFG_TID_2_NONE 0x00000000
6002 +/** March test */
6003 +#define STATUS_MBCFG_TID_2_MARCH 0x00000040
6004 +/** Checkerboard test */
6005 +#define STATUS_MBCFG_TID_2_CHCK 0x00000080
6006 +/** Hammer test */
6007 +#define STATUS_MBCFG_TID_2_HAM 0x000000C0
6008 +/** Address decoder test */
6009 +#define STATUS_MBCFG_TID_2_ADEC 0x00000100
6010 +/** Write mask byte test */
6011 +#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140
6012 +/** Reserved */
6013 +#define STATUS_MBCFG_TID_2_RES 0x00000180
6014 +/** Test ID
6015 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6016 +#define STATUS_MBCFG_TID_1_MASK 0x00000038
6017 +/** field offset */
6018 +#define STATUS_MBCFG_TID_1_OFFSET 3
6019 +/** No test is performed */
6020 +#define STATUS_MBCFG_TID_1_NONE 0x00000000
6021 +/** March test */
6022 +#define STATUS_MBCFG_TID_1_MARCH 0x00000008
6023 +/** Checkerboard test */
6024 +#define STATUS_MBCFG_TID_1_CHCK 0x00000010
6025 +/** Hammer test */
6026 +#define STATUS_MBCFG_TID_1_HAM 0x00000018
6027 +/** Address decoder test */
6028 +#define STATUS_MBCFG_TID_1_ADEC 0x00000020
6029 +/** Write mask byte test */
6030 +#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028
6031 +/** Reserved */
6032 +#define STATUS_MBCFG_TID_1_RES 0x00000030
6033 +/** Test ID
6034 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6035 +#define STATUS_MBCFG_TID_0_MASK 0x00000007
6036 +/** field offset */
6037 +#define STATUS_MBCFG_TID_0_OFFSET 0
6038 +/** No test is performed */
6039 +#define STATUS_MBCFG_TID_0_NONE 0x00000000
6040 +/** March test */
6041 +#define STATUS_MBCFG_TID_0_MARCH 0x00000001
6042 +/** Checkerboard test */
6043 +#define STATUS_MBCFG_TID_0_CHCK 0x00000002
6044 +/** Hammer test */
6045 +#define STATUS_MBCFG_TID_0_HAM 0x00000003
6046 +/** Address decoder test */
6047 +#define STATUS_MBCFG_TID_0_ADEC 0x00000004
6048 +/** Write mask byte test */
6049 +#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005
6050 +/** Reserved */
6051 +#define STATUS_MBCFG_TID_0_RES 0x00000006
6052 +
6053 +/* Fields of "sbs0 bist result and debug data" */
6054 +/** BIST result and debug data
6055 +    Stores additional debug information */
6056 +#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8
6057 +/** field offset */
6058 +#define STATUS_MBDATA_DATA_OFFSET 3
6059 +/** MBIST NOGO
6060 +    The BIST failed and cannot be repaired due to many failure locations */
6061 +#define STATUS_MBDATA_MBNOGO 0x00000004
6062 +/** MBIST FAILED
6063 +    The BIST failed but can be repaired */
6064 +#define STATUS_MBDATA_MBFAIL 0x00000002
6065 +/** MBIST PASSED
6066 +    The BIST passed without any Failures */
6067 +#define STATUS_MBDATA_MBPASS 0x00000001
6068 +
6069 +/*! @} */ /* STATUS_REGISTER */
6070 +
6071 +#endif /* _status_reg_h */
6072 --- /dev/null
6073 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h
6074 @@ -0,0 +1,2008 @@
6075 +/******************************************************************************
6076 +
6077 +                               Copyright (c) 2010
6078 +                            Lantiq Deutschland GmbH
6079 +
6080 +  For licensing information, see the file 'LICENSE' in the root folder of
6081 +  this software module.
6082 +
6083 +******************************************************************************/
6084 +
6085 +#ifndef _sys1_reg_h
6086 +#define _sys1_reg_h
6087 +
6088 +/** \addtogroup SYS1_REGISTER
6089 +   @{
6090 +*/
6091 +/* access macros */
6092 +#define sys1_r32(reg) reg_r32(&sys1->reg)
6093 +#define sys1_w32(val, reg) reg_w32(val, &sys1->reg)
6094 +#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg)
6095 +#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx)
6096 +#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx)
6097 +#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx)
6098 +#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx)
6099 +
6100 +
6101 +/** SYS1 register structure */
6102 +struct gpon_reg_sys1
6103 +{
6104 +   /** Clock Status Register */
6105 +   unsigned int clks; /* 0x00000000 */
6106 +   /** Clock Enable Register
6107 +       Via this register the clocks for the domains can be enabled. */
6108 +   unsigned int clken; /* 0x00000004 */
6109 +   /** Clock Clear Register
6110 +       Via this register the clocks for the domains can be disabled. */
6111 +   unsigned int clkclr; /* 0x00000008 */
6112 +   /** Reserved */
6113 +   unsigned int res_0[5]; /* 0x0000000C */
6114 +   /** Activation Status Register */
6115 +   unsigned int acts; /* 0x00000020 */
6116 +   /** Activation Register
6117 +       Via this register the domains can be activated. */
6118 +   unsigned int act; /* 0x00000024 */
6119 +   /** Deactivation Register
6120 +       Via this register the domains can be deactivated. */
6121 +   unsigned int deact; /* 0x00000028 */
6122 +   /** Reboot Trigger Register
6123 +       Via this register the domains can be rebooted (sent through reset). */
6124 +   unsigned int rbt; /* 0x0000002C */
6125 +   /** Reserved */
6126 +   unsigned int res_1[4]; /* 0x00000030 */
6127 +   /** CPU0 Clock Control Register
6128 +       Clock control register for CPU0 */
6129 +   unsigned int cpu0cc; /* 0x00000040 */
6130 +   /** Reserved */
6131 +   unsigned int res_2[7]; /* 0x00000044 */
6132 +   /** CPU0 Reset Source Register
6133 +       Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */
6134 +   unsigned int cpu0rs; /* 0x00000060 */
6135 +   /** Reserved */
6136 +   unsigned int res_3[7]; /* 0x00000064 */
6137 +   /** CPU0 Wakeup Configuration Register
6138 +       Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */
6139 +   unsigned int cpu0wcfg; /* 0x00000080 */
6140 +   /** Reserved */
6141 +   unsigned int res_4[7]; /* 0x00000084 */
6142 +   /** Bootmode Control Register
6143 +       Reflects the bootmode for the CPU and provides means to manipulate it. */
6144 +   unsigned int bmc; /* 0x000000A0 */
6145 +   /** Reserved */
6146 +   unsigned int res_5[3]; /* 0x000000A4 */
6147 +   /** Sleep Configuration Register */
6148 +   unsigned int scfg; /* 0x000000B0 */
6149 +   /** Power Down Configuration Register
6150 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */
6151 +   unsigned int pdcfg; /* 0x000000B4 */
6152 +   /** CLKO Pad Control Register
6153 +       Controls the behaviour of the CLKO pad/ball. */
6154 +   unsigned int clkoc; /* 0x000000B8 */
6155 +   /** Infrastructure Control Register
6156 +       Controls the behaviour of the components of the infrastructure block. */
6157 +   unsigned int infrac; /* 0x000000BC */
6158 +   /** HRST_OUT_N Control Register
6159 +       Controls the behaviour of the HRST_OUT_N pin. */
6160 +   unsigned int hrstoutc; /* 0x000000C0 */
6161 +   /** EBU Clock Control Register
6162 +       Clock control register for the EBU. */
6163 +   unsigned int ebucc; /* 0x000000C4 */
6164 +   /** Reserved */
6165 +   unsigned int res_6[2]; /* 0x000000C8 */
6166 +   /** NMI Status Register
6167 +       The Test NMI source is the GPTC counter 1A overflow bit. */
6168 +   unsigned int nmis; /* 0x000000D0 */
6169 +   /** NMI Set Register */
6170 +   unsigned int nmiset; /* 0x000000D4 */
6171 +   /** NMI Clear Register */
6172 +   unsigned int nmiclr; /* 0x000000D8 */
6173 +   /** NMI Test Configuration Register */
6174 +   unsigned int nmitcfg; /* 0x000000DC */
6175 +   /** NMI VPE1 Control Register */
6176 +   unsigned int nmivpe1c; /* 0x000000E0 */
6177 +   /** Reserved */
6178 +   unsigned int res_7[3]; /* 0x000000E4 */
6179 +   /** IRN Capture Register
6180 +       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
6181 +   unsigned int irncr; /* 0x000000F0 */
6182 +   /** IRN Interrupt Control Register
6183 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
6184 +   unsigned int irnicr; /* 0x000000F4 */
6185 +   /** IRN Interrupt Enable Register
6186 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
6187 +   unsigned int irnen; /* 0x000000F8 */
6188 +   /** Reserved */
6189 +   unsigned int res_8; /* 0x000000FC */
6190 +};
6191 +
6192 +
6193 +/* Fields of "Clock Status Register" */
6194 +/** STATUS Clock Enable
6195 +    Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */
6196 +#define CLKS_STATUS 0x80000000
6197 +/* Disable
6198 +#define CLKS_STATUS_DIS 0x00000000 */
6199 +/** Enable */
6200 +#define CLKS_STATUS_EN 0x80000000
6201 +/** SHA1 Clock Enable
6202 +    Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */
6203 +#define CLKS_SHA1 0x40000000
6204 +/* Disable
6205 +#define CLKS_SHA1_DIS 0x00000000 */
6206 +/** Enable */
6207 +#define CLKS_SHA1_EN 0x40000000
6208 +/** AES Clock Enable
6209 +    Shows the clock enable bit for the AES domain. This domain contains the AES block. */
6210 +#define CLKS_AES 0x20000000
6211 +/* Disable
6212 +#define CLKS_AES_DIS 0x00000000 */
6213 +/** Enable */
6214 +#define CLKS_AES_EN 0x20000000
6215 +/** PCM Clock Enable
6216 +    Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */
6217 +#define CLKS_PCM 0x10000000
6218 +/* Disable
6219 +#define CLKS_PCM_DIS 0x00000000 */
6220 +/** Enable */
6221 +#define CLKS_PCM_EN 0x10000000
6222 +/** FSCT Clock Enable
6223 +    Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */
6224 +#define CLKS_FSCT 0x08000000
6225 +/* Disable
6226 +#define CLKS_FSCT_DIS 0x00000000 */
6227 +/** Enable */
6228 +#define CLKS_FSCT_EN 0x08000000
6229 +/** GPTC Clock Enable
6230 +    Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */
6231 +#define CLKS_GPTC 0x04000000
6232 +/* Disable
6233 +#define CLKS_GPTC_DIS 0x00000000 */
6234 +/** Enable */
6235 +#define CLKS_GPTC_EN 0x04000000
6236 +/** MPS Clock Enable
6237 +    Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */
6238 +#define CLKS_MPS 0x02000000
6239 +/* Disable
6240 +#define CLKS_MPS_DIS 0x00000000 */
6241 +/** Enable */
6242 +#define CLKS_MPS_EN 0x02000000
6243 +/** DFEV0 Clock Enable
6244 +    Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */
6245 +#define CLKS_DFEV0 0x01000000
6246 +/* Disable
6247 +#define CLKS_DFEV0_DIS 0x00000000 */
6248 +/** Enable */
6249 +#define CLKS_DFEV0_EN 0x01000000
6250 +/** PADCTRL4 Clock Enable
6251 +    Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6252 +#define CLKS_PADCTRL4 0x00400000
6253 +/* Disable
6254 +#define CLKS_PADCTRL4_DIS 0x00000000 */
6255 +/** Enable */
6256 +#define CLKS_PADCTRL4_EN 0x00400000
6257 +/** PADCTRL3 Clock Enable
6258 +    Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6259 +#define CLKS_PADCTRL3 0x00200000
6260 +/* Disable
6261 +#define CLKS_PADCTRL3_DIS 0x00000000 */
6262 +/** Enable */
6263 +#define CLKS_PADCTRL3_EN 0x00200000
6264 +/** PADCTRL1 Clock Enable
6265 +    Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6266 +#define CLKS_PADCTRL1 0x00100000
6267 +/* Disable
6268 +#define CLKS_PADCTRL1_DIS 0x00000000 */
6269 +/** Enable */
6270 +#define CLKS_PADCTRL1_EN 0x00100000
6271 +/** P4 Clock Enable
6272 +    Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */
6273 +#define CLKS_P4 0x00040000
6274 +/* Disable
6275 +#define CLKS_P4_DIS 0x00000000 */
6276 +/** Enable */
6277 +#define CLKS_P4_EN 0x00040000
6278 +/** P3 Clock Enable
6279 +    Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */
6280 +#define CLKS_P3 0x00020000
6281 +/* Disable
6282 +#define CLKS_P3_DIS 0x00000000 */
6283 +/** Enable */
6284 +#define CLKS_P3_EN 0x00020000
6285 +/** P1 Clock Enable
6286 +    Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */
6287 +#define CLKS_P1 0x00010000
6288 +/* Disable
6289 +#define CLKS_P1_DIS 0x00000000 */
6290 +/** Enable */
6291 +#define CLKS_P1_EN 0x00010000
6292 +/** HOST Clock Enable
6293 +    Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */
6294 +#define CLKS_HOST 0x00008000
6295 +/* Disable
6296 +#define CLKS_HOST_DIS 0x00000000 */
6297 +/** Enable */
6298 +#define CLKS_HOST_EN 0x00008000
6299 +/** I2C Clock Enable
6300 +    Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */
6301 +#define CLKS_I2C 0x00004000
6302 +/* Disable
6303 +#define CLKS_I2C_DIS 0x00000000 */
6304 +/** Enable */
6305 +#define CLKS_I2C_EN 0x00004000
6306 +/** SSC0 Clock Enable
6307 +    Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */
6308 +#define CLKS_SSC0 0x00002000
6309 +/* Disable
6310 +#define CLKS_SSC0_DIS 0x00000000 */
6311 +/** Enable */
6312 +#define CLKS_SSC0_EN 0x00002000
6313 +/** ASC0 Clock Enable
6314 +    Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */
6315 +#define CLKS_ASC0 0x00001000
6316 +/* Disable
6317 +#define CLKS_ASC0_DIS 0x00000000 */
6318 +/** Enable */
6319 +#define CLKS_ASC0_EN 0x00001000
6320 +/** ASC1 Clock Enable
6321 +    Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */
6322 +#define CLKS_ASC1 0x00000800
6323 +/* Disable
6324 +#define CLKS_ASC1_DIS 0x00000000 */
6325 +/** Enable */
6326 +#define CLKS_ASC1_EN 0x00000800
6327 +/** DCDCAPD Clock Enable
6328 +    Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6329 +#define CLKS_DCDCAPD 0x00000400
6330 +/* Disable
6331 +#define CLKS_DCDCAPD_DIS 0x00000000 */
6332 +/** Enable */
6333 +#define CLKS_DCDCAPD_EN 0x00000400
6334 +/** DCDCDDR Clock Enable
6335 +    Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6336 +#define CLKS_DCDCDDR 0x00000200
6337 +/* Disable
6338 +#define CLKS_DCDCDDR_DIS 0x00000000 */
6339 +/** Enable */
6340 +#define CLKS_DCDCDDR_EN 0x00000200
6341 +/** DCDC1V0 Clock Enable
6342 +    Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6343 +#define CLKS_DCDC1V0 0x00000100
6344 +/* Disable
6345 +#define CLKS_DCDC1V0_DIS 0x00000000 */
6346 +/** Enable */
6347 +#define CLKS_DCDC1V0_EN 0x00000100
6348 +/** TRC2MEM Clock Enable
6349 +    Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */
6350 +#define CLKS_TRC2MEM 0x00000040
6351 +/* Disable
6352 +#define CLKS_TRC2MEM_DIS 0x00000000 */
6353 +/** Enable */
6354 +#define CLKS_TRC2MEM_EN 0x00000040
6355 +/** DDR Clock Enable
6356 +    Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */
6357 +#define CLKS_DDR 0x00000020
6358 +/* Disable
6359 +#define CLKS_DDR_DIS 0x00000000 */
6360 +/** Enable */
6361 +#define CLKS_DDR_EN 0x00000020
6362 +/** EBU Clock Enable
6363 +    Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */
6364 +#define CLKS_EBU 0x00000010
6365 +/* Disable
6366 +#define CLKS_EBU_DIS 0x00000000 */
6367 +/** Enable */
6368 +#define CLKS_EBU_EN 0x00000010
6369 +
6370 +/* Fields of "Clock Enable Register" */
6371 +/** Set Clock Enable STATUS
6372 +    Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
6373 +#define CLKEN_STATUS 0x80000000
6374 +/* No-Operation
6375 +#define CLKEN_STATUS_NOP 0x00000000 */
6376 +/** Set */
6377 +#define CLKEN_STATUS_SET 0x80000000
6378 +/** Set Clock Enable SHA1
6379 +    Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
6380 +#define CLKEN_SHA1 0x40000000
6381 +/* No-Operation
6382 +#define CLKEN_SHA1_NOP 0x00000000 */
6383 +/** Set */
6384 +#define CLKEN_SHA1_SET 0x40000000
6385 +/** Set Clock Enable AES
6386 +    Sets the clock enable bit of the AES domain. This domain contains the AES block. */
6387 +#define CLKEN_AES 0x20000000
6388 +/* No-Operation
6389 +#define CLKEN_AES_NOP 0x00000000 */
6390 +/** Set */
6391 +#define CLKEN_AES_SET 0x20000000
6392 +/** Set Clock Enable PCM
6393 +    Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
6394 +#define CLKEN_PCM 0x10000000
6395 +/* No-Operation
6396 +#define CLKEN_PCM_NOP 0x00000000 */
6397 +/** Set */
6398 +#define CLKEN_PCM_SET 0x10000000
6399 +/** Set Clock Enable FSCT
6400 +    Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
6401 +#define CLKEN_FSCT 0x08000000
6402 +/* No-Operation
6403 +#define CLKEN_FSCT_NOP 0x00000000 */
6404 +/** Set */
6405 +#define CLKEN_FSCT_SET 0x08000000
6406 +/** Set Clock Enable GPTC
6407 +    Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
6408 +#define CLKEN_GPTC 0x04000000
6409 +/* No-Operation
6410 +#define CLKEN_GPTC_NOP 0x00000000 */
6411 +/** Set */
6412 +#define CLKEN_GPTC_SET 0x04000000
6413 +/** Set Clock Enable MPS
6414 +    Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */
6415 +#define CLKEN_MPS 0x02000000
6416 +/* No-Operation
6417 +#define CLKEN_MPS_NOP 0x00000000 */
6418 +/** Set */
6419 +#define CLKEN_MPS_SET 0x02000000
6420 +/** Set Clock Enable DFEV0
6421 +    Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
6422 +#define CLKEN_DFEV0 0x01000000
6423 +/* No-Operation
6424 +#define CLKEN_DFEV0_NOP 0x00000000 */
6425 +/** Set */
6426 +#define CLKEN_DFEV0_SET 0x01000000
6427 +/** Set Clock Enable PADCTRL4
6428 +    Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6429 +#define CLKEN_PADCTRL4 0x00400000
6430 +/* No-Operation
6431 +#define CLKEN_PADCTRL4_NOP 0x00000000 */
6432 +/** Set */
6433 +#define CLKEN_PADCTRL4_SET 0x00400000
6434 +/** Set Clock Enable PADCTRL3
6435 +    Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6436 +#define CLKEN_PADCTRL3 0x00200000
6437 +/* No-Operation
6438 +#define CLKEN_PADCTRL3_NOP 0x00000000 */
6439 +/** Set */
6440 +#define CLKEN_PADCTRL3_SET 0x00200000
6441 +/** Set Clock Enable PADCTRL1
6442 +    Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6443 +#define CLKEN_PADCTRL1 0x00100000
6444 +/* No-Operation
6445 +#define CLKEN_PADCTRL1_NOP 0x00000000 */
6446 +/** Set */
6447 +#define CLKEN_PADCTRL1_SET 0x00100000
6448 +/** Set Clock Enable P4
6449 +    Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6450 +#define CLKEN_P4 0x00040000
6451 +/* No-Operation
6452 +#define CLKEN_P4_NOP 0x00000000 */
6453 +/** Set */
6454 +#define CLKEN_P4_SET 0x00040000
6455 +/** Set Clock Enable P3
6456 +    Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6457 +#define CLKEN_P3 0x00020000
6458 +/* No-Operation
6459 +#define CLKEN_P3_NOP 0x00000000 */
6460 +/** Set */
6461 +#define CLKEN_P3_SET 0x00020000
6462 +/** Set Clock Enable P1
6463 +    Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6464 +#define CLKEN_P1 0x00010000
6465 +/* No-Operation
6466 +#define CLKEN_P1_NOP 0x00000000 */
6467 +/** Set */
6468 +#define CLKEN_P1_SET 0x00010000
6469 +/** Set Clock Enable HOST
6470 +    Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
6471 +#define CLKEN_HOST 0x00008000
6472 +/* No-Operation
6473 +#define CLKEN_HOST_NOP 0x00000000 */
6474 +/** Set */
6475 +#define CLKEN_HOST_SET 0x00008000
6476 +/** Set Clock Enable I2C
6477 +    Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
6478 +#define CLKEN_I2C 0x00004000
6479 +/* No-Operation
6480 +#define CLKEN_I2C_NOP 0x00000000 */
6481 +/** Set */
6482 +#define CLKEN_I2C_SET 0x00004000
6483 +/** Set Clock Enable SSC0
6484 +    Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
6485 +#define CLKEN_SSC0 0x00002000
6486 +/* No-Operation
6487 +#define CLKEN_SSC0_NOP 0x00000000 */
6488 +/** Set */
6489 +#define CLKEN_SSC0_SET 0x00002000
6490 +/** Set Clock Enable ASC0
6491 +    Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
6492 +#define CLKEN_ASC0 0x00001000
6493 +/* No-Operation
6494 +#define CLKEN_ASC0_NOP 0x00000000 */
6495 +/** Set */
6496 +#define CLKEN_ASC0_SET 0x00001000
6497 +/** Set Clock Enable ASC1
6498 +    Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
6499 +#define CLKEN_ASC1 0x00000800
6500 +/* No-Operation
6501 +#define CLKEN_ASC1_NOP 0x00000000 */
6502 +/** Set */
6503 +#define CLKEN_ASC1_SET 0x00000800
6504 +/** Set Clock Enable DCDCAPD
6505 +    Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6506 +#define CLKEN_DCDCAPD 0x00000400
6507 +/* No-Operation
6508 +#define CLKEN_DCDCAPD_NOP 0x00000000 */
6509 +/** Set */
6510 +#define CLKEN_DCDCAPD_SET 0x00000400
6511 +/** Set Clock Enable DCDCDDR
6512 +    Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6513 +#define CLKEN_DCDCDDR 0x00000200
6514 +/* No-Operation
6515 +#define CLKEN_DCDCDDR_NOP 0x00000000 */
6516 +/** Set */
6517 +#define CLKEN_DCDCDDR_SET 0x00000200
6518 +/** Set Clock Enable DCDC1V0
6519 +    Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6520 +#define CLKEN_DCDC1V0 0x00000100
6521 +/* No-Operation
6522 +#define CLKEN_DCDC1V0_NOP 0x00000000 */
6523 +/** Set */
6524 +#define CLKEN_DCDC1V0_SET 0x00000100
6525 +/** Set Clock Enable TRC2MEM
6526 +    Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
6527 +#define CLKEN_TRC2MEM 0x00000040
6528 +/* No-Operation
6529 +#define CLKEN_TRC2MEM_NOP 0x00000000 */
6530 +/** Set */
6531 +#define CLKEN_TRC2MEM_SET 0x00000040
6532 +/** Set Clock Enable DDR
6533 +    Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
6534 +#define CLKEN_DDR 0x00000020
6535 +/* No-Operation
6536 +#define CLKEN_DDR_NOP 0x00000000 */
6537 +/** Set */
6538 +#define CLKEN_DDR_SET 0x00000020
6539 +/** Set Clock Enable EBU
6540 +    Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
6541 +#define CLKEN_EBU 0x00000010
6542 +/* No-Operation
6543 +#define CLKEN_EBU_NOP 0x00000000 */
6544 +/** Set */
6545 +#define CLKEN_EBU_SET 0x00000010
6546 +
6547 +/* Fields of "Clock Clear Register" */
6548 +/** Clear Clock Enable STATUS
6549 +    Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
6550 +#define CLKCLR_STATUS 0x80000000
6551 +/* No-Operation
6552 +#define CLKCLR_STATUS_NOP 0x00000000 */
6553 +/** Clear */
6554 +#define CLKCLR_STATUS_CLR 0x80000000
6555 +/** Clear Clock Enable SHA1
6556 +    Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
6557 +#define CLKCLR_SHA1 0x40000000
6558 +/* No-Operation
6559 +#define CLKCLR_SHA1_NOP 0x00000000 */
6560 +/** Clear */
6561 +#define CLKCLR_SHA1_CLR 0x40000000
6562 +/** Clear Clock Enable AES
6563 +    Clears the clock enable bit of the AES domain. This domain contains the AES block. */
6564 +#define CLKCLR_AES 0x20000000
6565 +/* No-Operation
6566 +#define CLKCLR_AES_NOP 0x00000000 */
6567 +/** Clear */
6568 +#define CLKCLR_AES_CLR 0x20000000
6569 +/** Clear Clock Enable PCM
6570 +    Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
6571 +#define CLKCLR_PCM 0x10000000
6572 +/* No-Operation
6573 +#define CLKCLR_PCM_NOP 0x00000000 */
6574 +/** Clear */
6575 +#define CLKCLR_PCM_CLR 0x10000000
6576 +/** Clear Clock Enable FSCT
6577 +    Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
6578 +#define CLKCLR_FSCT 0x08000000
6579 +/* No-Operation
6580 +#define CLKCLR_FSCT_NOP 0x00000000 */
6581 +/** Clear */
6582 +#define CLKCLR_FSCT_CLR 0x08000000
6583 +/** Clear Clock Enable GPTC
6584 +    Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
6585 +#define CLKCLR_GPTC 0x04000000
6586 +/* No-Operation
6587 +#define CLKCLR_GPTC_NOP 0x00000000 */
6588 +/** Clear */
6589 +#define CLKCLR_GPTC_CLR 0x04000000
6590 +/** Clear Clock Enable MPS
6591 +    Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */
6592 +#define CLKCLR_MPS 0x02000000
6593 +/* No-Operation
6594 +#define CLKCLR_MPS_NOP 0x00000000 */
6595 +/** Clear */
6596 +#define CLKCLR_MPS_CLR 0x02000000
6597 +/** Clear Clock Enable DFEV0
6598 +    Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
6599 +#define CLKCLR_DFEV0 0x01000000
6600 +/* No-Operation
6601 +#define CLKCLR_DFEV0_NOP 0x00000000 */
6602 +/** Clear */
6603 +#define CLKCLR_DFEV0_CLR 0x01000000
6604 +/** Clear Clock Enable PADCTRL4
6605 +    Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6606 +#define CLKCLR_PADCTRL4 0x00400000
6607 +/* No-Operation
6608 +#define CLKCLR_PADCTRL4_NOP 0x00000000 */
6609 +/** Clear */
6610 +#define CLKCLR_PADCTRL4_CLR 0x00400000
6611 +/** Clear Clock Enable PADCTRL3
6612 +    Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6613 +#define CLKCLR_PADCTRL3 0x00200000
6614 +/* No-Operation
6615 +#define CLKCLR_PADCTRL3_NOP 0x00000000 */
6616 +/** Clear */
6617 +#define CLKCLR_PADCTRL3_CLR 0x00200000
6618 +/** Clear Clock Enable PADCTRL1
6619 +    Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6620 +#define CLKCLR_PADCTRL1 0x00100000
6621 +/* No-Operation
6622 +#define CLKCLR_PADCTRL1_NOP 0x00000000 */
6623 +/** Clear */
6624 +#define CLKCLR_PADCTRL1_CLR 0x00100000
6625 +/** Clear Clock Enable P4
6626 +    Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6627 +#define CLKCLR_P4 0x00040000
6628 +/* No-Operation
6629 +#define CLKCLR_P4_NOP 0x00000000 */
6630 +/** Clear */
6631 +#define CLKCLR_P4_CLR 0x00040000
6632 +/** Clear Clock Enable P3
6633 +    Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6634 +#define CLKCLR_P3 0x00020000
6635 +/* No-Operation
6636 +#define CLKCLR_P3_NOP 0x00000000 */
6637 +/** Clear */
6638 +#define CLKCLR_P3_CLR 0x00020000
6639 +/** Clear Clock Enable P1
6640 +    Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6641 +#define CLKCLR_P1 0x00010000
6642 +/* No-Operation
6643 +#define CLKCLR_P1_NOP 0x00000000 */
6644 +/** Clear */
6645 +#define CLKCLR_P1_CLR 0x00010000
6646 +/** Clear Clock Enable HOST
6647 +    Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
6648 +#define CLKCLR_HOST 0x00008000
6649 +/* No-Operation
6650 +#define CLKCLR_HOST_NOP 0x00000000 */
6651 +/** Clear */
6652 +#define CLKCLR_HOST_CLR 0x00008000
6653 +/** Clear Clock Enable I2C
6654 +    Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
6655 +#define CLKCLR_I2C 0x00004000
6656 +/* No-Operation
6657 +#define CLKCLR_I2C_NOP 0x00000000 */
6658 +/** Clear */
6659 +#define CLKCLR_I2C_CLR 0x00004000
6660 +/** Clear Clock Enable SSC0
6661 +    Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
6662 +#define CLKCLR_SSC0 0x00002000
6663 +/* No-Operation
6664 +#define CLKCLR_SSC0_NOP 0x00000000 */
6665 +/** Clear */
6666 +#define CLKCLR_SSC0_CLR 0x00002000
6667 +/** Clear Clock Enable ASC0
6668 +    Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
6669 +#define CLKCLR_ASC0 0x00001000
6670 +/* No-Operation
6671 +#define CLKCLR_ASC0_NOP 0x00000000 */
6672 +/** Clear */
6673 +#define CLKCLR_ASC0_CLR 0x00001000
6674 +/** Clear Clock Enable ASC1
6675 +    Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
6676 +#define CLKCLR_ASC1 0x00000800
6677 +/* No-Operation
6678 +#define CLKCLR_ASC1_NOP 0x00000000 */
6679 +/** Clear */
6680 +#define CLKCLR_ASC1_CLR 0x00000800
6681 +/** Clear Clock Enable DCDCAPD
6682 +    Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6683 +#define CLKCLR_DCDCAPD 0x00000400
6684 +/* No-Operation
6685 +#define CLKCLR_DCDCAPD_NOP 0x00000000 */
6686 +/** Clear */
6687 +#define CLKCLR_DCDCAPD_CLR 0x00000400
6688 +/** Clear Clock Enable DCDCDDR
6689 +    Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6690 +#define CLKCLR_DCDCDDR 0x00000200
6691 +/* No-Operation
6692 +#define CLKCLR_DCDCDDR_NOP 0x00000000 */
6693 +/** Clear */
6694 +#define CLKCLR_DCDCDDR_CLR 0x00000200
6695 +/** Clear Clock Enable DCDC1V0
6696 +    Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6697 +#define CLKCLR_DCDC1V0 0x00000100
6698 +/* No-Operation
6699 +#define CLKCLR_DCDC1V0_NOP 0x00000000 */
6700 +/** Clear */
6701 +#define CLKCLR_DCDC1V0_CLR 0x00000100
6702 +/** Clear Clock Enable TRC2MEM
6703 +    Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
6704 +#define CLKCLR_TRC2MEM 0x00000040
6705 +/* No-Operation
6706 +#define CLKCLR_TRC2MEM_NOP 0x00000000 */
6707 +/** Clear */
6708 +#define CLKCLR_TRC2MEM_CLR 0x00000040
6709 +/** Clear Clock Enable DDR
6710 +    Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
6711 +#define CLKCLR_DDR 0x00000020
6712 +/* No-Operation
6713 +#define CLKCLR_DDR_NOP 0x00000000 */
6714 +/** Clear */
6715 +#define CLKCLR_DDR_CLR 0x00000020
6716 +/** Clear Clock Enable EBU
6717 +    Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
6718 +#define CLKCLR_EBU 0x00000010
6719 +/* No-Operation
6720 +#define CLKCLR_EBU_NOP 0x00000000 */
6721 +/** Clear */
6722 +#define CLKCLR_EBU_CLR 0x00000010
6723 +
6724 +/* Fields of "Activation Status Register" */
6725 +/** STATUS Status
6726 +    Shows the activation status of the STATUS domain. This domain contains the STATUS block. */
6727 +#define ACTS_STATUS 0x80000000
6728 +/* The block is inactive.
6729 +#define ACTS_STATUS_INACT 0x00000000 */
6730 +/** The block is active. */
6731 +#define ACTS_STATUS_ACT 0x80000000
6732 +/** SHA1 Status
6733 +    Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */
6734 +#define ACTS_SHA1 0x40000000
6735 +/* The block is inactive.
6736 +#define ACTS_SHA1_INACT 0x00000000 */
6737 +/** The block is active. */
6738 +#define ACTS_SHA1_ACT 0x40000000
6739 +/** AES Status
6740 +    Shows the activation status of the AES domain. This domain contains the AES block. */
6741 +#define ACTS_AES 0x20000000
6742 +/* The block is inactive.
6743 +#define ACTS_AES_INACT 0x00000000 */
6744 +/** The block is active. */
6745 +#define ACTS_AES_ACT 0x20000000
6746 +/** PCM Status
6747 +    Shows the activation status of the PCM domain. This domain contains the PCM interface block. */
6748 +#define ACTS_PCM 0x10000000
6749 +/* The block is inactive.
6750 +#define ACTS_PCM_INACT 0x00000000 */
6751 +/** The block is active. */
6752 +#define ACTS_PCM_ACT 0x10000000
6753 +/** FSCT Status
6754 +    Shows the activation status of the FSCT domain. This domain contains the FSCT block. */
6755 +#define ACTS_FSCT 0x08000000
6756 +/* The block is inactive.
6757 +#define ACTS_FSCT_INACT 0x00000000 */
6758 +/** The block is active. */
6759 +#define ACTS_FSCT_ACT 0x08000000
6760 +/** GPTC Status
6761 +    Shows the activation status of the GPTC domain. This domain contains the GPTC block. */
6762 +#define ACTS_GPTC 0x04000000
6763 +/* The block is inactive.
6764 +#define ACTS_GPTC_INACT 0x00000000 */
6765 +/** The block is active. */
6766 +#define ACTS_GPTC_ACT 0x04000000
6767 +/** MPS Status
6768 +    Shows the activation status of the MPS domain. This domain contains the MPS block. */
6769 +#define ACTS_MPS 0x02000000
6770 +/* The block is inactive.
6771 +#define ACTS_MPS_INACT 0x00000000 */
6772 +/** The block is active. */
6773 +#define ACTS_MPS_ACT 0x02000000
6774 +/** DFEV0 Status
6775 +    Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */
6776 +#define ACTS_DFEV0 0x01000000
6777 +/* The block is inactive.
6778 +#define ACTS_DFEV0_INACT 0x00000000 */
6779 +/** The block is active. */
6780 +#define ACTS_DFEV0_ACT 0x01000000
6781 +/** PADCTRL4 Status
6782 +    Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6783 +#define ACTS_PADCTRL4 0x00400000
6784 +/* The block is inactive.
6785 +#define ACTS_PADCTRL4_INACT 0x00000000 */
6786 +/** The block is active. */
6787 +#define ACTS_PADCTRL4_ACT 0x00400000
6788 +/** PADCTRL3 Status
6789 +    Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6790 +#define ACTS_PADCTRL3 0x00200000
6791 +/* The block is inactive.
6792 +#define ACTS_PADCTRL3_INACT 0x00000000 */
6793 +/** The block is active. */
6794 +#define ACTS_PADCTRL3_ACT 0x00200000
6795 +/** PADCTRL1 Status
6796 +    Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6797 +#define ACTS_PADCTRL1 0x00100000
6798 +/* The block is inactive.
6799 +#define ACTS_PADCTRL1_INACT 0x00000000 */
6800 +/** The block is active. */
6801 +#define ACTS_PADCTRL1_ACT 0x00100000
6802 +/** P4 Status
6803 +    Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6804 +#define ACTS_P4 0x00040000
6805 +/* The block is inactive.
6806 +#define ACTS_P4_INACT 0x00000000 */
6807 +/** The block is active. */
6808 +#define ACTS_P4_ACT 0x00040000
6809 +/** P3 Status
6810 +    Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6811 +#define ACTS_P3 0x00020000
6812 +/* The block is inactive.
6813 +#define ACTS_P3_INACT 0x00000000 */
6814 +/** The block is active. */
6815 +#define ACTS_P3_ACT 0x00020000
6816 +/** P1 Status
6817 +    Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6818 +#define ACTS_P1 0x00010000
6819 +/* The block is inactive.
6820 +#define ACTS_P1_INACT 0x00000000 */
6821 +/** The block is active. */
6822 +#define ACTS_P1_ACT 0x00010000
6823 +/** HOST Status
6824 +    Shows the activation status of the HOST domain. This domain contains the HOST interface block. */
6825 +#define ACTS_HOST 0x00008000
6826 +/* The block is inactive.
6827 +#define ACTS_HOST_INACT 0x00000000 */
6828 +/** The block is active. */
6829 +#define ACTS_HOST_ACT 0x00008000
6830 +/** I2C Status
6831 +    Shows the activation status of the I2C domain. This domain contains the I2C interface block. */
6832 +#define ACTS_I2C 0x00004000
6833 +/* The block is inactive.
6834 +#define ACTS_I2C_INACT 0x00000000 */
6835 +/** The block is active. */
6836 +#define ACTS_I2C_ACT 0x00004000
6837 +/** SSC0 Status
6838 +    Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */
6839 +#define ACTS_SSC0 0x00002000
6840 +/* The block is inactive.
6841 +#define ACTS_SSC0_INACT 0x00000000 */
6842 +/** The block is active. */
6843 +#define ACTS_SSC0_ACT 0x00002000
6844 +/** ASC0 Status
6845 +    Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */
6846 +#define ACTS_ASC0 0x00001000
6847 +/* The block is inactive.
6848 +#define ACTS_ASC0_INACT 0x00000000 */
6849 +/** The block is active. */
6850 +#define ACTS_ASC0_ACT 0x00001000
6851 +/** ASC1 Status
6852 +    Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */
6853 +#define ACTS_ASC1 0x00000800
6854 +/* The block is inactive.
6855 +#define ACTS_ASC1_INACT 0x00000000 */
6856 +/** The block is active. */
6857 +#define ACTS_ASC1_ACT 0x00000800
6858 +/** DCDCAPD Status
6859 +    Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6860 +#define ACTS_DCDCAPD 0x00000400
6861 +/* The block is inactive.
6862 +#define ACTS_DCDCAPD_INACT 0x00000000 */
6863 +/** The block is active. */
6864 +#define ACTS_DCDCAPD_ACT 0x00000400
6865 +/** DCDCDDR Status
6866 +    Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6867 +#define ACTS_DCDCDDR 0x00000200
6868 +/* The block is inactive.
6869 +#define ACTS_DCDCDDR_INACT 0x00000000 */
6870 +/** The block is active. */
6871 +#define ACTS_DCDCDDR_ACT 0x00000200
6872 +/** DCDC1V0 Status
6873 +    Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6874 +#define ACTS_DCDC1V0 0x00000100
6875 +/* The block is inactive.
6876 +#define ACTS_DCDC1V0_INACT 0x00000000 */
6877 +/** The block is active. */
6878 +#define ACTS_DCDC1V0_ACT 0x00000100
6879 +/** TRC2MEM Status
6880 +    Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */
6881 +#define ACTS_TRC2MEM 0x00000040
6882 +/* The block is inactive.
6883 +#define ACTS_TRC2MEM_INACT 0x00000000 */
6884 +/** The block is active. */
6885 +#define ACTS_TRC2MEM_ACT 0x00000040
6886 +/** DDR Status
6887 +    Shows the activation status of the DDR domain. This domain contains the DDR interface block. */
6888 +#define ACTS_DDR 0x00000020
6889 +/* The block is inactive.
6890 +#define ACTS_DDR_INACT 0x00000000 */
6891 +/** The block is active. */
6892 +#define ACTS_DDR_ACT 0x00000020
6893 +/** EBU Status
6894 +    Shows the activation status of the EBU domain. This domain contains the EBU interface block. */
6895 +#define ACTS_EBU 0x00000010
6896 +/* The block is inactive.
6897 +#define ACTS_EBU_INACT 0x00000000 */
6898 +/** The block is active. */
6899 +#define ACTS_EBU_ACT 0x00000010
6900 +
6901 +/* Fields of "Activation Register" */
6902 +/** Activate STATUS
6903 +    Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */
6904 +#define ACT_STATUS 0x80000000
6905 +/* No-Operation
6906 +#define ACT_STATUS_NOP 0x00000000 */
6907 +/** Set */
6908 +#define ACT_STATUS_SET 0x80000000
6909 +/** Activate SHA1
6910 +    Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
6911 +#define ACT_SHA1 0x40000000
6912 +/* No-Operation
6913 +#define ACT_SHA1_NOP 0x00000000 */
6914 +/** Set */
6915 +#define ACT_SHA1_SET 0x40000000
6916 +/** Activate AES
6917 +    Sets the activation flag of the AES domain. This domain contains the AES block. */
6918 +#define ACT_AES 0x20000000
6919 +/* No-Operation
6920 +#define ACT_AES_NOP 0x00000000 */
6921 +/** Set */
6922 +#define ACT_AES_SET 0x20000000
6923 +/** Activate PCM
6924 +    Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */
6925 +#define ACT_PCM 0x10000000
6926 +/* No-Operation
6927 +#define ACT_PCM_NOP 0x00000000 */
6928 +/** Set */
6929 +#define ACT_PCM_SET 0x10000000
6930 +/** Activate FSCT
6931 +    Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */
6932 +#define ACT_FSCT 0x08000000
6933 +/* No-Operation
6934 +#define ACT_FSCT_NOP 0x00000000 */
6935 +/** Set */
6936 +#define ACT_FSCT_SET 0x08000000
6937 +/** Activate GPTC
6938 +    Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */
6939 +#define ACT_GPTC 0x04000000
6940 +/* No-Operation
6941 +#define ACT_GPTC_NOP 0x00000000 */
6942 +/** Set */
6943 +#define ACT_GPTC_SET 0x04000000
6944 +/** Activate MPS
6945 +    Sets the activation flag of the MPS domain. This domain contains the MPS block. */
6946 +#define ACT_MPS 0x02000000
6947 +/* No-Operation
6948 +#define ACT_MPS_NOP 0x00000000 */
6949 +/** Set */
6950 +#define ACT_MPS_SET 0x02000000
6951 +/** Activate DFEV0
6952 +    Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
6953 +#define ACT_DFEV0 0x01000000
6954 +/* No-Operation
6955 +#define ACT_DFEV0_NOP 0x00000000 */
6956 +/** Set */
6957 +#define ACT_DFEV0_SET 0x01000000
6958 +/** Activate PADCTRL4
6959 +    Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6960 +#define ACT_PADCTRL4 0x00400000
6961 +/* No-Operation
6962 +#define ACT_PADCTRL4_NOP 0x00000000 */
6963 +/** Set */
6964 +#define ACT_PADCTRL4_SET 0x00400000
6965 +/** Activate PADCTRL3
6966 +    Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6967 +#define ACT_PADCTRL3 0x00200000
6968 +/* No-Operation
6969 +#define ACT_PADCTRL3_NOP 0x00000000 */
6970 +/** Set */
6971 +#define ACT_PADCTRL3_SET 0x00200000
6972 +/** Activate PADCTRL1
6973 +    Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6974 +#define ACT_PADCTRL1 0x00100000
6975 +/* No-Operation
6976 +#define ACT_PADCTRL1_NOP 0x00000000 */
6977 +/** Set */
6978 +#define ACT_PADCTRL1_SET 0x00100000
6979 +/** Activate P4
6980 +    Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6981 +#define ACT_P4 0x00040000
6982 +/* No-Operation
6983 +#define ACT_P4_NOP 0x00000000 */
6984 +/** Set */
6985 +#define ACT_P4_SET 0x00040000
6986 +/** Activate P3
6987 +    Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6988 +#define ACT_P3 0x00020000
6989 +/* No-Operation
6990 +#define ACT_P3_NOP 0x00000000 */
6991 +/** Set */
6992 +#define ACT_P3_SET 0x00020000
6993 +/** Activate P1
6994 +    Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6995 +#define ACT_P1 0x00010000
6996 +/* No-Operation
6997 +#define ACT_P1_NOP 0x00000000 */
6998 +/** Set */
6999 +#define ACT_P1_SET 0x00010000
7000 +/** Activate HOST
7001 +    Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */
7002 +#define ACT_HOST 0x00008000
7003 +/* No-Operation
7004 +#define ACT_HOST_NOP 0x00000000 */
7005 +/** Set */
7006 +#define ACT_HOST_SET 0x00008000
7007 +/** Activate I2C
7008 +    Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */
7009 +#define ACT_I2C 0x00004000
7010 +/* No-Operation
7011 +#define ACT_I2C_NOP 0x00000000 */
7012 +/** Set */
7013 +#define ACT_I2C_SET 0x00004000
7014 +/** Activate SSC0
7015 +    Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
7016 +#define ACT_SSC0 0x00002000
7017 +/* No-Operation
7018 +#define ACT_SSC0_NOP 0x00000000 */
7019 +/** Set */
7020 +#define ACT_SSC0_SET 0x00002000
7021 +/** Activate ASC0
7022 +    Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
7023 +#define ACT_ASC0 0x00001000
7024 +/* No-Operation
7025 +#define ACT_ASC0_NOP 0x00000000 */
7026 +/** Set */
7027 +#define ACT_ASC0_SET 0x00001000
7028 +/** Activate ASC1
7029 +    Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
7030 +#define ACT_ASC1 0x00000800
7031 +/* No-Operation
7032 +#define ACT_ASC1_NOP 0x00000000 */
7033 +/** Set */
7034 +#define ACT_ASC1_SET 0x00000800
7035 +/** Activate DCDCAPD
7036 +    Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7037 +#define ACT_DCDCAPD 0x00000400
7038 +/* No-Operation
7039 +#define ACT_DCDCAPD_NOP 0x00000000 */
7040 +/** Set */
7041 +#define ACT_DCDCAPD_SET 0x00000400
7042 +/** Activate DCDCDDR
7043 +    Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7044 +#define ACT_DCDCDDR 0x00000200
7045 +/* No-Operation
7046 +#define ACT_DCDCDDR_NOP 0x00000000 */
7047 +/** Set */
7048 +#define ACT_DCDCDDR_SET 0x00000200
7049 +/** Activate DCDC1V0
7050 +    Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7051 +#define ACT_DCDC1V0 0x00000100
7052 +/* No-Operation
7053 +#define ACT_DCDC1V0_NOP 0x00000000 */
7054 +/** Set */
7055 +#define ACT_DCDC1V0_SET 0x00000100
7056 +/** Activate TRC2MEM
7057 +    Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7058 +#define ACT_TRC2MEM 0x00000040
7059 +/* No-Operation
7060 +#define ACT_TRC2MEM_NOP 0x00000000 */
7061 +/** Set */
7062 +#define ACT_TRC2MEM_SET 0x00000040
7063 +/** Activate DDR
7064 +    Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */
7065 +#define ACT_DDR 0x00000020
7066 +/* No-Operation
7067 +#define ACT_DDR_NOP 0x00000000 */
7068 +/** Set */
7069 +#define ACT_DDR_SET 0x00000020
7070 +/** Activate EBU
7071 +    Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */
7072 +#define ACT_EBU 0x00000010
7073 +/* No-Operation
7074 +#define ACT_EBU_NOP 0x00000000 */
7075 +/** Set */
7076 +#define ACT_EBU_SET 0x00000010
7077 +
7078 +/* Fields of "Deactivation Register" */
7079 +/** Deactivate STATUS
7080 +    Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */
7081 +#define DEACT_STATUS 0x80000000
7082 +/* No-Operation
7083 +#define DEACT_STATUS_NOP 0x00000000 */
7084 +/** Clear */
7085 +#define DEACT_STATUS_CLR 0x80000000
7086 +/** Deactivate SHA1
7087 +    Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
7088 +#define DEACT_SHA1 0x40000000
7089 +/* No-Operation
7090 +#define DEACT_SHA1_NOP 0x00000000 */
7091 +/** Clear */
7092 +#define DEACT_SHA1_CLR 0x40000000
7093 +/** Deactivate AES
7094 +    Clears the activation flag of the AES domain. This domain contains the AES block. */
7095 +#define DEACT_AES 0x20000000
7096 +/* No-Operation
7097 +#define DEACT_AES_NOP 0x00000000 */
7098 +/** Clear */
7099 +#define DEACT_AES_CLR 0x20000000
7100 +/** Deactivate PCM
7101 +    Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */
7102 +#define DEACT_PCM 0x10000000
7103 +/* No-Operation
7104 +#define DEACT_PCM_NOP 0x00000000 */
7105 +/** Clear */
7106 +#define DEACT_PCM_CLR 0x10000000
7107 +/** Deactivate FSCT
7108 +    Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */
7109 +#define DEACT_FSCT 0x08000000
7110 +/* No-Operation
7111 +#define DEACT_FSCT_NOP 0x00000000 */
7112 +/** Clear */
7113 +#define DEACT_FSCT_CLR 0x08000000
7114 +/** Deactivate GPTC
7115 +    Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */
7116 +#define DEACT_GPTC 0x04000000
7117 +/* No-Operation
7118 +#define DEACT_GPTC_NOP 0x00000000 */
7119 +/** Clear */
7120 +#define DEACT_GPTC_CLR 0x04000000
7121 +/** Deactivate MPS
7122 +    Clears the activation flag of the MPS domain. This domain contains the MPS block. */
7123 +#define DEACT_MPS 0x02000000
7124 +/* No-Operation
7125 +#define DEACT_MPS_NOP 0x00000000 */
7126 +/** Clear */
7127 +#define DEACT_MPS_CLR 0x02000000
7128 +/** Deactivate DFEV0
7129 +    Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
7130 +#define DEACT_DFEV0 0x01000000
7131 +/* No-Operation
7132 +#define DEACT_DFEV0_NOP 0x00000000 */
7133 +/** Clear */
7134 +#define DEACT_DFEV0_CLR 0x01000000
7135 +/** Deactivate PADCTRL4
7136 +    Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7137 +#define DEACT_PADCTRL4 0x00400000
7138 +/* No-Operation
7139 +#define DEACT_PADCTRL4_NOP 0x00000000 */
7140 +/** Clear */
7141 +#define DEACT_PADCTRL4_CLR 0x00400000
7142 +/** Deactivate PADCTRL3
7143 +    Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7144 +#define DEACT_PADCTRL3 0x00200000
7145 +/* No-Operation
7146 +#define DEACT_PADCTRL3_NOP 0x00000000 */
7147 +/** Clear */
7148 +#define DEACT_PADCTRL3_CLR 0x00200000
7149 +/** Deactivate PADCTRL1
7150 +    Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7151 +#define DEACT_PADCTRL1 0x00100000
7152 +/* No-Operation
7153 +#define DEACT_PADCTRL1_NOP 0x00000000 */
7154 +/** Clear */
7155 +#define DEACT_PADCTRL1_CLR 0x00100000
7156 +/** Deactivate P4
7157 +    Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7158 +#define DEACT_P4 0x00040000
7159 +/* No-Operation
7160 +#define DEACT_P4_NOP 0x00000000 */
7161 +/** Clear */
7162 +#define DEACT_P4_CLR 0x00040000
7163 +/** Deactivate P3
7164 +    Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7165 +#define DEACT_P3 0x00020000
7166 +/* No-Operation
7167 +#define DEACT_P3_NOP 0x00000000 */
7168 +/** Clear */
7169 +#define DEACT_P3_CLR 0x00020000
7170 +/** Deactivate P1
7171 +    Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7172 +#define DEACT_P1 0x00010000
7173 +/* No-Operation
7174 +#define DEACT_P1_NOP 0x00000000 */
7175 +/** Clear */
7176 +#define DEACT_P1_CLR 0x00010000
7177 +/** Deactivate HOST
7178 +    Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */
7179 +#define DEACT_HOST 0x00008000
7180 +/* No-Operation
7181 +#define DEACT_HOST_NOP 0x00000000 */
7182 +/** Clear */
7183 +#define DEACT_HOST_CLR 0x00008000
7184 +/** Deactivate I2C
7185 +    Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */
7186 +#define DEACT_I2C 0x00004000
7187 +/* No-Operation
7188 +#define DEACT_I2C_NOP 0x00000000 */
7189 +/** Clear */
7190 +#define DEACT_I2C_CLR 0x00004000
7191 +/** Deactivate SSC0
7192 +    Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
7193 +#define DEACT_SSC0 0x00002000
7194 +/* No-Operation
7195 +#define DEACT_SSC0_NOP 0x00000000 */
7196 +/** Clear */
7197 +#define DEACT_SSC0_CLR 0x00002000
7198 +/** Deactivate ASC0
7199 +    Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
7200 +#define DEACT_ASC0 0x00001000
7201 +/* No-Operation
7202 +#define DEACT_ASC0_NOP 0x00000000 */
7203 +/** Clear */
7204 +#define DEACT_ASC0_CLR 0x00001000
7205 +/** Deactivate ASC1
7206 +    Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
7207 +#define DEACT_ASC1 0x00000800
7208 +/* No-Operation
7209 +#define DEACT_ASC1_NOP 0x00000000 */
7210 +/** Clear */
7211 +#define DEACT_ASC1_CLR 0x00000800
7212 +/** Deactivate DCDCAPD
7213 +    Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7214 +#define DEACT_DCDCAPD 0x00000400
7215 +/* No-Operation
7216 +#define DEACT_DCDCAPD_NOP 0x00000000 */
7217 +/** Clear */
7218 +#define DEACT_DCDCAPD_CLR 0x00000400
7219 +/** Deactivate DCDCDDR
7220 +    Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7221 +#define DEACT_DCDCDDR 0x00000200
7222 +/* No-Operation
7223 +#define DEACT_DCDCDDR_NOP 0x00000000 */
7224 +/** Clear */
7225 +#define DEACT_DCDCDDR_CLR 0x00000200
7226 +/** Deactivate DCDC1V0
7227 +    Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7228 +#define DEACT_DCDC1V0 0x00000100
7229 +/* No-Operation
7230 +#define DEACT_DCDC1V0_NOP 0x00000000 */
7231 +/** Clear */
7232 +#define DEACT_DCDC1V0_CLR 0x00000100
7233 +/** Deactivate TRC2MEM
7234 +    Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7235 +#define DEACT_TRC2MEM 0x00000040
7236 +/* No-Operation
7237 +#define DEACT_TRC2MEM_NOP 0x00000000 */
7238 +/** Clear */
7239 +#define DEACT_TRC2MEM_CLR 0x00000040
7240 +/** Deactivate DDR
7241 +    Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */
7242 +#define DEACT_DDR 0x00000020
7243 +/* No-Operation
7244 +#define DEACT_DDR_NOP 0x00000000 */
7245 +/** Clear */
7246 +#define DEACT_DDR_CLR 0x00000020
7247 +/** Deactivate EBU
7248 +    Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */
7249 +#define DEACT_EBU 0x00000010
7250 +/* No-Operation
7251 +#define DEACT_EBU_NOP 0x00000000 */
7252 +/** Clear */
7253 +#define DEACT_EBU_CLR 0x00000010
7254 +
7255 +/* Fields of "Reboot Trigger Register" */
7256 +/** Reboot STATUS
7257 +    Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */
7258 +#define RBT_STATUS 0x80000000
7259 +/* No-Operation
7260 +#define RBT_STATUS_NOP 0x00000000 */
7261 +/** Trigger */
7262 +#define RBT_STATUS_TRIG 0x80000000
7263 +/** Reboot SHA1
7264 +    Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */
7265 +#define RBT_SHA1 0x40000000
7266 +/* No-Operation
7267 +#define RBT_SHA1_NOP 0x00000000 */
7268 +/** Trigger */
7269 +#define RBT_SHA1_TRIG 0x40000000
7270 +/** Reboot AES
7271 +    Triggers a reboot of the AES domain. This domain contains the AES block. */
7272 +#define RBT_AES 0x20000000
7273 +/* No-Operation
7274 +#define RBT_AES_NOP 0x00000000 */
7275 +/** Trigger */
7276 +#define RBT_AES_TRIG 0x20000000
7277 +/** Reboot PCM
7278 +    Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */
7279 +#define RBT_PCM 0x10000000
7280 +/* No-Operation
7281 +#define RBT_PCM_NOP 0x00000000 */
7282 +/** Trigger */
7283 +#define RBT_PCM_TRIG 0x10000000
7284 +/** Reboot FSCT
7285 +    Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */
7286 +#define RBT_FSCT 0x08000000
7287 +/* No-Operation
7288 +#define RBT_FSCT_NOP 0x00000000 */
7289 +/** Trigger */
7290 +#define RBT_FSCT_TRIG 0x08000000
7291 +/** Reboot GPTC
7292 +    Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */
7293 +#define RBT_GPTC 0x04000000
7294 +/* No-Operation
7295 +#define RBT_GPTC_NOP 0x00000000 */
7296 +/** Trigger */
7297 +#define RBT_GPTC_TRIG 0x04000000
7298 +/** Reboot MPS
7299 +    Triggers a reboot of the MPS domain. This domain contains the MPS block. */
7300 +#define RBT_MPS 0x02000000
7301 +/* No-Operation
7302 +#define RBT_MPS_NOP 0x00000000 */
7303 +/** Trigger */
7304 +#define RBT_MPS_TRIG 0x02000000
7305 +/** Reboot DFEV0
7306 +    Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */
7307 +#define RBT_DFEV0 0x01000000
7308 +/* No-Operation
7309 +#define RBT_DFEV0_NOP 0x00000000 */
7310 +/** Trigger */
7311 +#define RBT_DFEV0_TRIG 0x01000000
7312 +/** Reboot PADCTRL4
7313 +    Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7314 +#define RBT_PADCTRL4 0x00400000
7315 +/* No-Operation
7316 +#define RBT_PADCTRL4_NOP 0x00000000 */
7317 +/** Trigger */
7318 +#define RBT_PADCTRL4_TRIG 0x00400000
7319 +/** Reboot PADCTRL3
7320 +    Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7321 +#define RBT_PADCTRL3 0x00200000
7322 +/* No-Operation
7323 +#define RBT_PADCTRL3_NOP 0x00000000 */
7324 +/** Trigger */
7325 +#define RBT_PADCTRL3_TRIG 0x00200000
7326 +/** Reboot PADCTRL1
7327 +    Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7328 +#define RBT_PADCTRL1 0x00100000
7329 +/* No-Operation
7330 +#define RBT_PADCTRL1_NOP 0x00000000 */
7331 +/** Trigger */
7332 +#define RBT_PADCTRL1_TRIG 0x00100000
7333 +/** Reboot P4
7334 +    Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7335 +#define RBT_P4 0x00040000
7336 +/* No-Operation
7337 +#define RBT_P4_NOP 0x00000000 */
7338 +/** Trigger */
7339 +#define RBT_P4_TRIG 0x00040000
7340 +/** Reboot P3
7341 +    Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7342 +#define RBT_P3 0x00020000
7343 +/* No-Operation
7344 +#define RBT_P3_NOP 0x00000000 */
7345 +/** Trigger */
7346 +#define RBT_P3_TRIG 0x00020000
7347 +/** Reboot P1
7348 +    Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7349 +#define RBT_P1 0x00010000
7350 +/* No-Operation
7351 +#define RBT_P1_NOP 0x00000000 */
7352 +/** Trigger */
7353 +#define RBT_P1_TRIG 0x00010000
7354 +/** Reboot HOST
7355 +    Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */
7356 +#define RBT_HOST 0x00008000
7357 +/* No-Operation
7358 +#define RBT_HOST_NOP 0x00000000 */
7359 +/** Trigger */
7360 +#define RBT_HOST_TRIG 0x00008000
7361 +/** Reboot I2C
7362 +    Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */
7363 +#define RBT_I2C 0x00004000
7364 +/* No-Operation
7365 +#define RBT_I2C_NOP 0x00000000 */
7366 +/** Trigger */
7367 +#define RBT_I2C_TRIG 0x00004000
7368 +/** Reboot SSC0
7369 +    Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */
7370 +#define RBT_SSC0 0x00002000
7371 +/* No-Operation
7372 +#define RBT_SSC0_NOP 0x00000000 */
7373 +/** Trigger */
7374 +#define RBT_SSC0_TRIG 0x00002000
7375 +/** Reboot ASC0
7376 +    Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */
7377 +#define RBT_ASC0 0x00001000
7378 +/* No-Operation
7379 +#define RBT_ASC0_NOP 0x00000000 */
7380 +/** Trigger */
7381 +#define RBT_ASC0_TRIG 0x00001000
7382 +/** Reboot ASC1
7383 +    Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */
7384 +#define RBT_ASC1 0x00000800
7385 +/* No-Operation
7386 +#define RBT_ASC1_NOP 0x00000000 */
7387 +/** Trigger */
7388 +#define RBT_ASC1_TRIG 0x00000800
7389 +/** Reboot DCDCAPD
7390 +    Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7391 +#define RBT_DCDCAPD 0x00000400
7392 +/* No-Operation
7393 +#define RBT_DCDCAPD_NOP 0x00000000 */
7394 +/** Trigger */
7395 +#define RBT_DCDCAPD_TRIG 0x00000400
7396 +/** Reboot DCDCDDR
7397 +    Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7398 +#define RBT_DCDCDDR 0x00000200
7399 +/* No-Operation
7400 +#define RBT_DCDCDDR_NOP 0x00000000 */
7401 +/** Trigger */
7402 +#define RBT_DCDCDDR_TRIG 0x00000200
7403 +/** Reboot DCDC1V0
7404 +    Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7405 +#define RBT_DCDC1V0 0x00000100
7406 +/* No-Operation
7407 +#define RBT_DCDC1V0_NOP 0x00000000 */
7408 +/** Trigger */
7409 +#define RBT_DCDC1V0_TRIG 0x00000100
7410 +/** Reboot TRC2MEM
7411 +    Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7412 +#define RBT_TRC2MEM 0x00000040
7413 +/* No-Operation
7414 +#define RBT_TRC2MEM_NOP 0x00000000 */
7415 +/** Trigger */
7416 +#define RBT_TRC2MEM_TRIG 0x00000040
7417 +/** Reboot DDR
7418 +    Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */
7419 +#define RBT_DDR 0x00000020
7420 +/* No-Operation
7421 +#define RBT_DDR_NOP 0x00000000 */
7422 +/** Trigger */
7423 +#define RBT_DDR_TRIG 0x00000020
7424 +/** Reboot EBU
7425 +    Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */
7426 +#define RBT_EBU 0x00000010
7427 +/* No-Operation
7428 +#define RBT_EBU_NOP 0x00000000 */
7429 +/** Trigger */
7430 +#define RBT_EBU_TRIG 0x00000010
7431 +/** Reboot XBAR
7432 +    Triggers a reboot of the XBAR. */
7433 +#define RBT_XBAR 0x00000002
7434 +/* No-Operation
7435 +#define RBT_XBAR_NOP 0x00000000 */
7436 +/** Trigger */
7437 +#define RBT_XBAR_TRIG 0x00000002
7438 +/** Reboot CPU
7439 +    Triggers a reboot of the CPU. */
7440 +#define RBT_CPU 0x00000001
7441 +/* No-Operation
7442 +#define RBT_CPU_NOP 0x00000000 */
7443 +/** Trigger */
7444 +#define RBT_CPU_TRIG 0x00000001
7445 +
7446 +/* Fields of "CPU0 Clock Control Register" */
7447 +/** CPU Clock Divider
7448 +    Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */
7449 +#define CPU0CC_CPUDIV 0x00000001
7450 +/* Frequency set to the nominal value.
7451 +#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */
7452 +/** Frequency set to half of its nominal value. */
7453 +#define CPU0CC_CPUDIV_SELFHALF 0x00000001
7454 +
7455 +/* Fields of "CPU0 Reset Source Register" */
7456 +/** Software Reboot Request Occurred
7457 +    This bit can be acknowledged by a write operation. */
7458 +#define CPU0RS_SWRRO 0x00000004
7459 +/* Nothing
7460 +#define CPU0RS_SWRRO_NULL 0x00000000 */
7461 +/** Write: Acknowledge the event. */
7462 +#define CPU0RS_SWRRO_EVACK 0x00000004
7463 +/** Read: Event occurred. */
7464 +#define CPU0RS_SWRRO_EVOCC 0x00000004
7465 +/** Hardware Reset Source
7466 +    Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */
7467 +#define CPU0RS_HWRS_MASK 0x00000003
7468 +/** field offset */
7469 +#define CPU0RS_HWRS_OFFSET 0
7470 +/** Power-on reset. */
7471 +#define CPU0RS_HWRS_POR 0x00000000
7472 +/** RST pin. */
7473 +#define CPU0RS_HWRS_RST 0x00000001
7474 +/** Watchdog reset request. */
7475 +#define CPU0RS_HWRS_WDT 0x00000002
7476 +
7477 +/* Fields of "CPU0 Wakeup Configuration Register" */
7478 +/** Wakeup Request Source Yield Resume 15
7479 +    Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */
7480 +#define CPU0WCFG_WRSYR15 0x80000000
7481 +/* Not selected
7482 +#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */
7483 +/** Selected */
7484 +#define CPU0WCFG_WRSYR15_SEL 0x80000000
7485 +/** Wakeup Request Source Yield Resume 14
7486 +    Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */
7487 +#define CPU0WCFG_WRSYR14 0x40000000
7488 +/* Not selected
7489 +#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */
7490 +/** Selected */
7491 +#define CPU0WCFG_WRSYR14_SEL 0x40000000
7492 +/** Wakeup Request Source Yield Resume 13
7493 +    Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */
7494 +#define CPU0WCFG_WRSYR13 0x20000000
7495 +/* Not selected
7496 +#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */
7497 +/** Selected */
7498 +#define CPU0WCFG_WRSYR13_SEL 0x20000000
7499 +/** Wakeup Request Source Yield Resume 12
7500 +    Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */
7501 +#define CPU0WCFG_WRSYR12 0x10000000
7502 +/* Not selected
7503 +#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */
7504 +/** Selected */
7505 +#define CPU0WCFG_WRSYR12_SEL 0x10000000
7506 +/** Wakeup Request Source Yield Resume 11
7507 +    Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */
7508 +#define CPU0WCFG_WRSYR11 0x08000000
7509 +/* Not selected
7510 +#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */
7511 +/** Selected */
7512 +#define CPU0WCFG_WRSYR11_SEL 0x08000000
7513 +/** Wakeup Request Source Yield Resume 10
7514 +    Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */
7515 +#define CPU0WCFG_WRSYR10 0x04000000
7516 +/* Not selected
7517 +#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */
7518 +/** Selected */
7519 +#define CPU0WCFG_WRSYR10_SEL 0x04000000
7520 +/** Wakeup Request Source Yield Resume 9
7521 +    Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */
7522 +#define CPU0WCFG_WRSYR9 0x02000000
7523 +/* Not selected
7524 +#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */
7525 +/** Selected */
7526 +#define CPU0WCFG_WRSYR9_SEL 0x02000000
7527 +/** Wakeup Request Source Yield Resume 8
7528 +    Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */
7529 +#define CPU0WCFG_WRSYR8 0x01000000
7530 +/* Not selected
7531 +#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */
7532 +/** Selected */
7533 +#define CPU0WCFG_WRSYR8_SEL 0x01000000
7534 +/** Wakeup Request Source Yield Resume 7
7535 +    Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */
7536 +#define CPU0WCFG_WRSYR7 0x00800000
7537 +/* Not selected
7538 +#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */
7539 +/** Selected */
7540 +#define CPU0WCFG_WRSYR7_SEL 0x00800000
7541 +/** Wakeup Request Source Yield Resume 6
7542 +    Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */
7543 +#define CPU0WCFG_WRSYR6 0x00400000
7544 +/* Not selected
7545 +#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */
7546 +/** Selected */
7547 +#define CPU0WCFG_WRSYR6_SEL 0x00400000
7548 +/** Wakeup Request Source Yield Resume 5
7549 +    Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */
7550 +#define CPU0WCFG_WRSYR5 0x00200000
7551 +/* Not selected
7552 +#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */
7553 +/** Selected */
7554 +#define CPU0WCFG_WRSYR5_SEL 0x00200000
7555 +/** Wakeup Request Source Yield Resume 4
7556 +    Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */
7557 +#define CPU0WCFG_WRSYR4 0x00100000
7558 +/* Not selected
7559 +#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */
7560 +/** Selected */
7561 +#define CPU0WCFG_WRSYR4_SEL 0x00100000
7562 +/** Wakeup Request Source Yield Resume 3
7563 +    Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */
7564 +#define CPU0WCFG_WRSYR3 0x00080000
7565 +/* Not selected
7566 +#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */
7567 +/** Selected */
7568 +#define CPU0WCFG_WRSYR3_SEL 0x00080000
7569 +/** Wakeup Request Source Yield Resume 2
7570 +    Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */
7571 +#define CPU0WCFG_WRSYR2 0x00040000
7572 +/* Not selected
7573 +#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */
7574 +/** Selected */
7575 +#define CPU0WCFG_WRSYR2_SEL 0x00040000
7576 +/** Wakeup Request Source Yield Resume 1
7577 +    Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */
7578 +#define CPU0WCFG_WRSYR1 0x00020000
7579 +/* Not selected
7580 +#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */
7581 +/** Selected */
7582 +#define CPU0WCFG_WRSYR1_SEL 0x00020000
7583 +/** Wakeup Request Source Yield Resume 0
7584 +    Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */
7585 +#define CPU0WCFG_WRSYR0 0x00010000
7586 +/* Not selected
7587 +#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */
7588 +/** Selected */
7589 +#define CPU0WCFG_WRSYR0_SEL 0x00010000
7590 +/** Wakeup Request Source Debug
7591 +    Select signal EJ_DINT as source for wakeup from sleep state. */
7592 +#define CPU0WCFG_WRSDBG 0x00000100
7593 +/* Not selected
7594 +#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */
7595 +/** Selected */
7596 +#define CPU0WCFG_WRSDBG_SEL 0x00000100
7597 +/** Wakeup Request Source ICU of VPE1
7598 +    Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */
7599 +#define CPU0WCFG_WRSICUVPE1 0x00000002
7600 +/* Not selected
7601 +#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */
7602 +/** Selected */
7603 +#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002
7604 +/** Wakeup Request Source ICU of VPE0
7605 +    Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */
7606 +#define CPU0WCFG_WRSICUVPE0 0x00000001
7607 +/* Not selected
7608 +#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */
7609 +/** Selected */
7610 +#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001
7611 +
7612 +/* Fields of "Bootmode Control Register" */
7613 +/** Software Bootmode Select
7614 +    Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */
7615 +#define BMC_BMSW 0x80000000
7616 +/* Disable
7617 +#define BMC_BMSW_DIS 0x00000000 */
7618 +/** Enable */
7619 +#define BMC_BMSW_EN 0x80000000
7620 +/** Bootmode
7621 +    Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */
7622 +#define BMC_BM_MASK 0x0000007F
7623 +/** field offset */
7624 +#define BMC_BM_OFFSET 0
7625 +
7626 +/* Fields of "Sleep Configuration Register" */
7627 +/** Enable XBAR Clockoff When All XBAR masters Clockoff
7628 +    Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */
7629 +#define SCFG_XBAR 0x00010000
7630 +/* Disable
7631 +#define SCFG_XBAR_DIS 0x00000000 */
7632 +/** Enable */
7633 +#define SCFG_XBAR_EN 0x00010000
7634 +/** CPU0 Clockoff On Sleep
7635 +    Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */
7636 +#define SCFG_CPU0 0x00000001
7637 +/* Disable
7638 +#define SCFG_CPU0_DIS 0x00000000 */
7639 +/** Enable */
7640 +#define SCFG_CPU0_EN 0x00000001
7641 +
7642 +/* Fields of "Power Down Configuration Register" */
7643 +/** Enable Power Down STATUS
7644 +    Ignore this bit as power-gating is not supported for this chip. */
7645 +#define PDCFG_STATUS 0x80000000
7646 +/* Disable
7647 +#define PDCFG_STATUS_DIS 0x00000000 */
7648 +/** Enable */
7649 +#define PDCFG_STATUS_EN 0x80000000
7650 +/** Enable Power Down SHA1
7651 +    Ignore this bit as power-gating is not supported for this chip. */
7652 +#define PDCFG_SHA1 0x40000000
7653 +/* Disable
7654 +#define PDCFG_SHA1_DIS 0x00000000 */
7655 +/** Enable */
7656 +#define PDCFG_SHA1_EN 0x40000000
7657 +/** Enable Power Down AES
7658 +    Ignore this bit as power-gating is not supported for this chip. */
7659 +#define PDCFG_AES 0x20000000
7660 +/* Disable
7661 +#define PDCFG_AES_DIS 0x00000000 */
7662 +/** Enable */
7663 +#define PDCFG_AES_EN 0x20000000
7664 +/** Enable Power Down PCM
7665 +    Ignore this bit as power-gating is not supported for this chip. */
7666 +#define PDCFG_PCM 0x10000000
7667 +/* Disable
7668 +#define PDCFG_PCM_DIS 0x00000000 */
7669 +/** Enable */
7670 +#define PDCFG_PCM_EN 0x10000000
7671 +/** Enable Power Down FSCT
7672 +    Ignore this bit as power-gating is not supported for this chip. */
7673 +#define PDCFG_FSCT 0x08000000
7674 +/* Disable
7675 +#define PDCFG_FSCT_DIS 0x00000000 */
7676 +/** Enable */
7677 +#define PDCFG_FSCT_EN 0x08000000
7678 +/** Enable Power Down GPTC
7679 +    Ignore this bit as power-gating is not supported for this chip. */
7680 +#define PDCFG_GPTC 0x04000000
7681 +/* Disable
7682 +#define PDCFG_GPTC_DIS 0x00000000 */
7683 +/** Enable */
7684 +#define PDCFG_GPTC_EN 0x04000000
7685 +/** Enable Power Down MPS
7686 +    Ignore this bit as power-gating is not supported for this chip. */
7687 +#define PDCFG_MPS 0x02000000
7688 +/* Disable
7689 +#define PDCFG_MPS_DIS 0x00000000 */
7690 +/** Enable */
7691 +#define PDCFG_MPS_EN 0x02000000
7692 +/** Enable Power Down DFEV0
7693 +    Ignore this bit as power-gating is not supported for this chip. */
7694 +#define PDCFG_DFEV0 0x01000000
7695 +/* Disable
7696 +#define PDCFG_DFEV0_DIS 0x00000000 */
7697 +/** Enable */
7698 +#define PDCFG_DFEV0_EN 0x01000000
7699 +/** Enable Power Down PADCTRL4
7700 +    Ignore this bit as power-gating is not supported for this chip. */
7701 +#define PDCFG_PADCTRL4 0x00400000
7702 +/* Disable
7703 +#define PDCFG_PADCTRL4_DIS 0x00000000 */
7704 +/** Enable */
7705 +#define PDCFG_PADCTRL4_EN 0x00400000
7706 +/** Enable Power Down PADCTRL3
7707 +    Ignore this bit as power-gating is not supported for this chip. */
7708 +#define PDCFG_PADCTRL3 0x00200000
7709 +/* Disable
7710 +#define PDCFG_PADCTRL3_DIS 0x00000000 */
7711 +/** Enable */
7712 +#define PDCFG_PADCTRL3_EN 0x00200000
7713 +/** Enable Power Down PADCTRL1
7714 +    Ignore this bit as power-gating is not supported for this chip. */
7715 +#define PDCFG_PADCTRL1 0x00100000
7716 +/* Disable
7717 +#define PDCFG_PADCTRL1_DIS 0x00000000 */
7718 +/** Enable */
7719 +#define PDCFG_PADCTRL1_EN 0x00100000
7720 +/** Enable Power Down P4
7721 +    Ignore this bit as power-gating is not supported for this chip. */
7722 +#define PDCFG_P4 0x00040000
7723 +/* Disable
7724 +#define PDCFG_P4_DIS 0x00000000 */
7725 +/** Enable */
7726 +#define PDCFG_P4_EN 0x00040000
7727 +/** Enable Power Down P3
7728 +    Ignore this bit as power-gating is not supported for this chip. */
7729 +#define PDCFG_P3 0x00020000
7730 +/* Disable
7731 +#define PDCFG_P3_DIS 0x00000000 */
7732 +/** Enable */
7733 +#define PDCFG_P3_EN 0x00020000
7734 +/** Enable Power Down P1
7735 +    Ignore this bit as power-gating is not supported for this chip. */
7736 +#define PDCFG_P1 0x00010000
7737 +/* Disable
7738 +#define PDCFG_P1_DIS 0x00000000 */
7739 +/** Enable */
7740 +#define PDCFG_P1_EN 0x00010000
7741 +/** Enable Power Down HOST
7742 +    Ignore this bit as power-gating is not supported for this chip. */
7743 +#define PDCFG_HOST 0x00008000
7744 +/* Disable
7745 +#define PDCFG_HOST_DIS 0x00000000 */
7746 +/** Enable */
7747 +#define PDCFG_HOST_EN 0x00008000
7748 +/** Enable Power Down I2C
7749 +    Ignore this bit as power-gating is not supported for this chip. */
7750 +#define PDCFG_I2C 0x00004000
7751 +/* Disable
7752 +#define PDCFG_I2C_DIS 0x00000000 */
7753 +/** Enable */
7754 +#define PDCFG_I2C_EN 0x00004000
7755 +/** Enable Power Down SSC0
7756 +    Ignore this bit as power-gating is not supported for this chip. */
7757 +#define PDCFG_SSC0 0x00002000
7758 +/* Disable
7759 +#define PDCFG_SSC0_DIS 0x00000000 */
7760 +/** Enable */
7761 +#define PDCFG_SSC0_EN 0x00002000
7762 +/** Enable Power Down ASC0
7763 +    Ignore this bit as power-gating is not supported for this chip. */
7764 +#define PDCFG_ASC0 0x00001000
7765 +/* Disable
7766 +#define PDCFG_ASC0_DIS 0x00000000 */
7767 +/** Enable */
7768 +#define PDCFG_ASC0_EN 0x00001000
7769 +/** Enable Power Down ASC1
7770 +    Ignore this bit as power-gating is not supported for this chip. */
7771 +#define PDCFG_ASC1 0x00000800
7772 +/* Disable
7773 +#define PDCFG_ASC1_DIS 0x00000000 */
7774 +/** Enable */
7775 +#define PDCFG_ASC1_EN 0x00000800
7776 +/** Enable Power Down DCDCAPD
7777 +    Ignore this bit as power-gating is not supported for this chip. */
7778 +#define PDCFG_DCDCAPD 0x00000400
7779 +/* Disable
7780 +#define PDCFG_DCDCAPD_DIS 0x00000000 */
7781 +/** Enable */
7782 +#define PDCFG_DCDCAPD_EN 0x00000400
7783 +/** Enable Power Down DCDCDDR
7784 +    Ignore this bit as power-gating is not supported for this chip. */
7785 +#define PDCFG_DCDCDDR 0x00000200
7786 +/* Disable
7787 +#define PDCFG_DCDCDDR_DIS 0x00000000 */
7788 +/** Enable */
7789 +#define PDCFG_DCDCDDR_EN 0x00000200
7790 +/** Enable Power Down DCDC1V0
7791 +    Ignore this bit as power-gating is not supported for this chip. */
7792 +#define PDCFG_DCDC1V0 0x00000100
7793 +/* Disable
7794 +#define PDCFG_DCDC1V0_DIS 0x00000000 */
7795 +/** Enable */
7796 +#define PDCFG_DCDC1V0_EN 0x00000100
7797 +/** Enable Power Down TRC2MEM
7798 +    Ignore this bit as power-gating is not supported for this chip. */
7799 +#define PDCFG_TRC2MEM 0x00000040
7800 +/* Disable
7801 +#define PDCFG_TRC2MEM_DIS 0x00000000 */
7802 +/** Enable */
7803 +#define PDCFG_TRC2MEM_EN 0x00000040
7804 +/** Enable Power Down DDR
7805 +    Ignore this bit as power-gating is not supported for this chip. */
7806 +#define PDCFG_DDR 0x00000020
7807 +/* Disable
7808 +#define PDCFG_DDR_DIS 0x00000000 */
7809 +/** Enable */
7810 +#define PDCFG_DDR_EN 0x00000020
7811 +/** Enable Power Down EBU
7812 +    Ignore this bit as power-gating is not supported for this chip. */
7813 +#define PDCFG_EBU 0x00000010
7814 +/* Disable
7815 +#define PDCFG_EBU_DIS 0x00000000 */
7816 +/** Enable */
7817 +#define PDCFG_EBU_EN 0x00000010
7818 +
7819 +/* Fields of "CLKO Pad Control Register" */
7820 +/** Ethernet Reference Clock CLKO Select
7821 +    Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */
7822 +#define CLKOC_ETHREF 0x00000002
7823 +/* Not selected
7824 +#define CLKOC_ETHREF_NSEL 0x00000000 */
7825 +/** Selected */
7826 +#define CLKOC_ETHREF_SEL 0x00000002
7827 +/** Output Enable
7828 +    Enables the output driver of the CLKO pad. */
7829 +#define CLKOC_OEN 0x00000001
7830 +/* Disable
7831 +#define CLKOC_OEN_DIS 0x00000000 */
7832 +/** Enable */
7833 +#define CLKOC_OEN_EN 0x00000001
7834 +
7835 +/* Fields of "Infrastructure Control Register" */
7836 +/** General Purpose Control
7837 +    Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */
7838 +#define INFRAC_GP_MASK 0x1F000000
7839 +/** field offset */
7840 +#define INFRAC_GP_OFFSET 24
7841 +/** CMOS2CML Ethernet Control
7842 +    CMOS2CML Ethernet Control. */
7843 +#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000
7844 +/** field offset */
7845 +#define INFRAC_CMOS2CML_GPON_OFFSET 12
7846 +/** CMOS2CML Ethernet Control
7847 +    CMOS2CML Ethernet Control. */
7848 +#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00
7849 +/** field offset */
7850 +#define INFRAC_CMOS2CML_ETH_OFFSET 8
7851 +/** Dying Gasp Enable
7852 +    Enables the dying gasp detector. */
7853 +#define INFRAC_DGASPEN 0x00000040
7854 +/* Disable
7855 +#define INFRAC_DGASPEN_DIS 0x00000000 */
7856 +/** Enable */
7857 +#define INFRAC_DGASPEN_EN 0x00000040
7858 +/** Dying Gasp Hysteresis Control
7859 +    Dying Gasp Hysteresis Control. */
7860 +#define INFRAC_DGASPHYS_MASK 0x00000030
7861 +/** field offset */
7862 +#define INFRAC_DGASPHYS_OFFSET 4
7863 +/** Linear Regulator 1.5V Enable
7864 +    Enables 1.5V linear regulator. */
7865 +#define INFRAC_LIN1V5EN 0x00000008
7866 +/* Disable
7867 +#define INFRAC_LIN1V5EN_DIS 0x00000000 */
7868 +/** Enable */
7869 +#define INFRAC_LIN1V5EN_EN 0x00000008
7870 +/** Linear Regulator 1.5V Control
7871 +    Linear regulator 1.5V control. */
7872 +#define INFRAC_LIN1V5C_MASK 0x00000007
7873 +/** field offset */
7874 +#define INFRAC_LIN1V5C_OFFSET 0
7875 +
7876 +/* Fields of "HRST_OUT_N Control Register" */
7877 +/** HRST_OUT_N Pin Value
7878 +    Controls the value of the HRST_OUT_N pin. */
7879 +#define HRSTOUTC_VALUE 0x00000001
7880 +
7881 +/* Fields of "EBU Clock Control Register" */
7882 +/** EBU Clock Divider
7883 +    Via this bit the frequency of the clock of the EBU can be selected. */
7884 +#define EBUCC_EBUDIV 0x00000001
7885 +/* Frequency set to 50MHz.
7886 +#define EBUCC_EBUDIV_SELF50 0x00000000 */
7887 +/** Frequency set to 100MHz. */
7888 +#define EBUCC_EBUDIV_SELF100 0x00000001
7889 +
7890 +/* Fields of "NMI Status Register" */
7891 +/** NMI Status Flag TEST
7892 +    Shows whether the event NMI TEST occurred. */
7893 +#define NMIS_TEST 0x00000100
7894 +/* Nothing
7895 +#define NMIS_TEST_NULL 0x00000000 */
7896 +/** Read: Event occurred. */
7897 +#define NMIS_TEST_EVOCC 0x00000100
7898 +/** NMI Status Flag DGASP
7899 +    Shows whether the event NMI DGASP occurred. */
7900 +#define NMIS_DGASP 0x00000004
7901 +/* Nothing
7902 +#define NMIS_DGASP_NULL 0x00000000 */
7903 +/** Read: Event occurred. */
7904 +#define NMIS_DGASP_EVOCC 0x00000004
7905 +/** NMI Status Flag HOST
7906 +    Shows whether the event NMI HOST occurred. */
7907 +#define NMIS_HOST 0x00000002
7908 +/* Nothing
7909 +#define NMIS_HOST_NULL 0x00000000 */
7910 +/** Read: Event occurred. */
7911 +#define NMIS_HOST_EVOCC 0x00000002
7912 +/** NMI Status Flag PIN
7913 +    Shows whether the event NMI PIN occurred. */
7914 +#define NMIS_PIN 0x00000001
7915 +/* Nothing
7916 +#define NMIS_PIN_NULL 0x00000000 */
7917 +/** Read: Event occurred. */
7918 +#define NMIS_PIN_EVOCC 0x00000001
7919 +
7920 +/* Fields of "NMI Set Register" */
7921 +/** Set NMI Status Flag TEST
7922 +    Sets the corresponding NMI status flag. */
7923 +#define NMISET_TEST 0x00000100
7924 +/* Nothing
7925 +#define NMISET_TEST_NULL 0x00000000 */
7926 +/** Set */
7927 +#define NMISET_TEST_SET 0x00000100
7928 +/** Set NMI Status Flag DGASP
7929 +    Sets the corresponding NMI status flag. */
7930 +#define NMISET_DGASP 0x00000004
7931 +/* Nothing
7932 +#define NMISET_DGASP_NULL 0x00000000 */
7933 +/** Set */
7934 +#define NMISET_DGASP_SET 0x00000004
7935 +/** Set NMI Status Flag HOST
7936 +    Sets the corresponding NMI status flag. */
7937 +#define NMISET_HOST 0x00000002
7938 +/* Nothing
7939 +#define NMISET_HOST_NULL 0x00000000 */
7940 +/** Set */
7941 +#define NMISET_HOST_SET 0x00000002
7942 +/** Set NMI Status Flag PIN
7943 +    Sets the corresponding NMI status flag. */
7944 +#define NMISET_PIN 0x00000001
7945 +/* Nothing
7946 +#define NMISET_PIN_NULL 0x00000000 */
7947 +/** Set */
7948 +#define NMISET_PIN_SET 0x00000001
7949 +
7950 +/* Fields of "NMI Clear Register" */
7951 +/** Clear NMI Status Flag TEST
7952 +    Clears the corresponding NMI status flag. */
7953 +#define NMICLR_TEST 0x00000100
7954 +/* Nothing
7955 +#define NMICLR_TEST_NULL 0x00000000 */
7956 +/** Clear */
7957 +#define NMICLR_TEST_CLR 0x00000100
7958 +/** Clear NMI Status Flag DGASP
7959 +    Clears the corresponding NMI status flag. */
7960 +#define NMICLR_DGASP 0x00000004
7961 +/* Nothing
7962 +#define NMICLR_DGASP_NULL 0x00000000 */
7963 +/** Clear */
7964 +#define NMICLR_DGASP_CLR 0x00000004
7965 +/** Clear NMI Status Flag HOST
7966 +    Clears the corresponding NMI status flag. */
7967 +#define NMICLR_HOST 0x00000002
7968 +/* Nothing
7969 +#define NMICLR_HOST_NULL 0x00000000 */
7970 +/** Clear */
7971 +#define NMICLR_HOST_CLR 0x00000002
7972 +/** Clear NMI Status Flag PIN
7973 +    Clears the corresponding NMI status flag. */
7974 +#define NMICLR_PIN 0x00000001
7975 +/* Nothing
7976 +#define NMICLR_PIN_NULL 0x00000000 */
7977 +/** Clear */
7978 +#define NMICLR_PIN_CLR 0x00000001
7979 +
7980 +/* Fields of "NMI Test Configuration Register" */
7981 +/** Enable NMI Test Feature
7982 +    Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */
7983 +#define NMITCFG_TEN 0x00000100
7984 +/* Disable
7985 +#define NMITCFG_TEN_DIS 0x00000000 */
7986 +/** Enable */
7987 +#define NMITCFG_TEN_EN 0x00000100
7988 +
7989 +/* Fields of "NMI VPE1 Control Register" */
7990 +/** NMI VPE1 State
7991 +    Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */
7992 +#define NMIVPE1C_NMI 0x00000001
7993 +/* False
7994 +#define NMIVPE1C_NMI_FALSE 0x00000000 */
7995 +/** True */
7996 +#define NMIVPE1C_NMI_TRUE 0x00000001
7997 +
7998 +/* Fields of "IRN Capture Register" */
7999 +/** DCDCAPD Alarm
8000 +    The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8001 +#define IRNCR_DCDCAPD 0x00400000
8002 +/* Nothing
8003 +#define IRNCR_DCDCAPD_NULL 0x00000000 */
8004 +/** Write: Acknowledge the interrupt. */
8005 +#define IRNCR_DCDCAPD_INTACK 0x00400000
8006 +/** Read: Interrupt occurred. */
8007 +#define IRNCR_DCDCAPD_INTOCC 0x00400000
8008 +/** DCDCDDR Alarm
8009 +    The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8010 +#define IRNCR_DCDCDDR 0x00200000
8011 +/* Nothing
8012 +#define IRNCR_DCDCDDR_NULL 0x00000000 */
8013 +/** Write: Acknowledge the interrupt. */
8014 +#define IRNCR_DCDCDDR_INTACK 0x00200000
8015 +/** Read: Interrupt occurred. */
8016 +#define IRNCR_DCDCDDR_INTOCC 0x00200000
8017 +/** DCDC1V0 Alarm
8018 +    The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8019 +#define IRNCR_DCDC1V0 0x00100000
8020 +/* Nothing
8021 +#define IRNCR_DCDC1V0_NULL 0x00000000 */
8022 +/** Write: Acknowledge the interrupt. */
8023 +#define IRNCR_DCDC1V0_INTACK 0x00100000
8024 +/** Read: Interrupt occurred. */
8025 +#define IRNCR_DCDC1V0_INTOCC 0x00100000
8026 +/** SIF0 wakeup request
8027 +    SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8028 +#define IRNCR_SIF0 0x00010000
8029 +/* Nothing
8030 +#define IRNCR_SIF0_NULL 0x00000000 */
8031 +/** Write: Acknowledge the interrupt. */
8032 +#define IRNCR_SIF0_INTACK 0x00010000
8033 +/** Read: Interrupt occurred. */
8034 +#define IRNCR_SIF0_INTOCC 0x00010000
8035 +
8036 +/* Fields of "IRN Interrupt Control Register" */
8037 +/** DCDCAPD Alarm
8038 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8039 +#define IRNICR_DCDCAPD 0x00400000
8040 +/** DCDCDDR Alarm
8041 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8042 +#define IRNICR_DCDCDDR 0x00200000
8043 +/** DCDC1V0 Alarm
8044 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8045 +#define IRNICR_DCDC1V0 0x00100000
8046 +/** SIF0 wakeup request
8047 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8048 +#define IRNICR_SIF0 0x00010000
8049 +
8050 +/* Fields of "IRN Interrupt Enable Register" */
8051 +/** DCDCAPD Alarm
8052 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8053 +#define IRNEN_DCDCAPD 0x00400000
8054 +/* Disable
8055 +#define IRNEN_DCDCAPD_DIS 0x00000000 */
8056 +/** Enable */
8057 +#define IRNEN_DCDCAPD_EN 0x00400000
8058 +/** DCDCDDR Alarm
8059 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8060 +#define IRNEN_DCDCDDR 0x00200000
8061 +/* Disable
8062 +#define IRNEN_DCDCDDR_DIS 0x00000000 */
8063 +/** Enable */
8064 +#define IRNEN_DCDCDDR_EN 0x00200000
8065 +/** DCDC1V0 Alarm
8066 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8067 +#define IRNEN_DCDC1V0 0x00100000
8068 +/* Disable
8069 +#define IRNEN_DCDC1V0_DIS 0x00000000 */
8070 +/** Enable */
8071 +#define IRNEN_DCDC1V0_EN 0x00100000
8072 +/** SIF0 wakeup request
8073 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8074 +#define IRNEN_SIF0 0x00010000
8075 +/* Disable
8076 +#define IRNEN_SIF0_DIS 0x00000000 */
8077 +/** Enable */
8078 +#define IRNEN_SIF0_EN 0x00010000
8079 +
8080 +/*! @} */ /* SYS1_REGISTER */
8081 +
8082 +#endif /* _sys1_reg_h */
8083 --- /dev/null
8084 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h
8085 @@ -0,0 +1,1132 @@
8086 +/******************************************************************************
8087 +
8088 +                               Copyright (c) 2010
8089 +                            Lantiq Deutschland GmbH
8090 +
8091 +  For licensing information, see the file 'LICENSE' in the root folder of
8092 +  this software module.
8093 +
8094 +******************************************************************************/
8095 +
8096 +#ifndef _sys_eth_reg_h
8097 +#define _sys_eth_reg_h
8098 +
8099 +/** \addtogroup SYS_ETH_REGISTER
8100 +   @{
8101 +*/
8102 +/* access macros */
8103 +#define sys_eth_r32(reg) reg_r32(&sys_eth->reg)
8104 +#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg)
8105 +#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg)
8106 +#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx)
8107 +#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx)
8108 +#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx)
8109 +#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx)
8110 +
8111 +
8112 +/** SYS_ETH register structure */
8113 +struct gpon_reg_sys_eth
8114 +{
8115 +   /** Clock Status Register */
8116 +   unsigned int clks; /* 0x00000000 */
8117 +   /** Clock Enable Register
8118 +       Via this register the clocks for the domains can be enabled. */
8119 +   unsigned int clken; /* 0x00000004 */
8120 +   /** Clock Clear Register
8121 +       Via this register the clocks for the domains can be disabled. */
8122 +   unsigned int clkclr; /* 0x00000008 */
8123 +   /** Reserved */
8124 +   unsigned int res_0[5]; /* 0x0000000C */
8125 +   /** Activation Status Register */
8126 +   unsigned int acts; /* 0x00000020 */
8127 +   /** Activation Register
8128 +       Via this register the domains can be activated. */
8129 +   unsigned int act; /* 0x00000024 */
8130 +   /** Deactivation Register
8131 +       Via this register the domains can be deactivated. */
8132 +   unsigned int deact; /* 0x00000028 */
8133 +   /** Reboot Trigger Register
8134 +       Via this register the domains can be rebooted (sent through reset). */
8135 +   unsigned int rbt; /* 0x0000002C */
8136 +   /** Reserved */
8137 +   unsigned int res_1[32]; /* 0x00000030 */
8138 +   /** External PHY Control Register */
8139 +   unsigned int extphyc; /* 0x000000B0 */
8140 +   /** Power Down Configuration Register
8141 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
8142 +   unsigned int pdcfg; /* 0x000000B4 */
8143 +   /** Datarate Control Register
8144 +       Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */
8145 +   unsigned int drc; /* 0x000000B8 */
8146 +   /** GMAC Multiplexer Control Register
8147 +       Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */
8148 +   unsigned int gmuxc; /* 0x000000BC */
8149 +   /** Datarate Status Register
8150 +       Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */
8151 +   unsigned int drs; /* 0x000000C0 */
8152 +   /** SGMII Control Register */
8153 +   unsigned int sgmiic; /* 0x000000C4 */
8154 +   /** Reserved */
8155 +   unsigned int res_2[14]; /* 0x000000C8 */
8156 +};
8157 +
8158 +
8159 +/* Fields of "Clock Status Register" */
8160 +/** GPHY1MII2 Clock Enable
8161 +    Shows the clock enable bit for GPHY1MII2. */
8162 +#define SYS_ETH_CLKS_GPHY1MII2 0x02000000
8163 +/* Disable
8164 +#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */
8165 +/** Enable */
8166 +#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000
8167 +/** GPHY0MII2 Clock Enable
8168 +    Shows the clock enable bit for GPHY0MII2. */
8169 +#define SYS_ETH_CLKS_GPHY0MII2 0x01000000
8170 +/* Disable
8171 +#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */
8172 +/** Enable */
8173 +#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000
8174 +/** PADCTRL2 Clock Enable
8175 +    Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8176 +#define SYS_ETH_CLKS_PADCTRL2 0x00200000
8177 +/* Disable
8178 +#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */
8179 +/** Enable */
8180 +#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000
8181 +/** PADCTRL0 Clock Enable
8182 +    Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8183 +#define SYS_ETH_CLKS_PADCTRL0 0x00100000
8184 +/* Disable
8185 +#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */
8186 +/** Enable */
8187 +#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000
8188 +/** P2 Clock Enable
8189 +    Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */
8190 +#define SYS_ETH_CLKS_P2 0x00020000
8191 +/* Disable
8192 +#define SYS_ETH_CLKS_P2_DIS 0x00000000 */
8193 +/** Enable */
8194 +#define SYS_ETH_CLKS_P2_EN 0x00020000
8195 +/** P0 Clock Enable
8196 +    Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */
8197 +#define SYS_ETH_CLKS_P0 0x00010000
8198 +/* Disable
8199 +#define SYS_ETH_CLKS_P0_DIS 0x00000000 */
8200 +/** Enable */
8201 +#define SYS_ETH_CLKS_P0_EN 0x00010000
8202 +/** xMII Clock Enable
8203 +    Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8204 +#define SYS_ETH_CLKS_xMII 0x00000800
8205 +/* Disable
8206 +#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */
8207 +/** Enable */
8208 +#define SYS_ETH_CLKS_xMII_EN 0x00000800
8209 +/** SGMII Clock Enable
8210 +    Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8211 +#define SYS_ETH_CLKS_SGMII 0x00000400
8212 +/* Disable
8213 +#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */
8214 +/** Enable */
8215 +#define SYS_ETH_CLKS_SGMII_EN 0x00000400
8216 +/** GPHY1 Clock Enable
8217 +    Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8218 +#define SYS_ETH_CLKS_GPHY1 0x00000200
8219 +/* Disable
8220 +#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */
8221 +/** Enable */
8222 +#define SYS_ETH_CLKS_GPHY1_EN 0x00000200
8223 +/** GPHY0 Clock Enable
8224 +    Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8225 +#define SYS_ETH_CLKS_GPHY0 0x00000100
8226 +/* Disable
8227 +#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */
8228 +/** Enable */
8229 +#define SYS_ETH_CLKS_GPHY0_EN 0x00000100
8230 +/** MDIO Clock Enable
8231 +    Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */
8232 +#define SYS_ETH_CLKS_MDIO 0x00000080
8233 +/* Disable
8234 +#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */
8235 +/** Enable */
8236 +#define SYS_ETH_CLKS_MDIO_EN 0x00000080
8237 +/** GMAC3 Clock Enable
8238 +    Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */
8239 +#define SYS_ETH_CLKS_GMAC3 0x00000008
8240 +/* Disable
8241 +#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */
8242 +/** Enable */
8243 +#define SYS_ETH_CLKS_GMAC3_EN 0x00000008
8244 +/** GMAC2 Clock Enable
8245 +    Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */
8246 +#define SYS_ETH_CLKS_GMAC2 0x00000004
8247 +/* Disable
8248 +#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */
8249 +/** Enable */
8250 +#define SYS_ETH_CLKS_GMAC2_EN 0x00000004
8251 +/** GMAC1 Clock Enable
8252 +    Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */
8253 +#define SYS_ETH_CLKS_GMAC1 0x00000002
8254 +/* Disable
8255 +#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */
8256 +/** Enable */
8257 +#define SYS_ETH_CLKS_GMAC1_EN 0x00000002
8258 +/** GMAC0 Clock Enable
8259 +    Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */
8260 +#define SYS_ETH_CLKS_GMAC0 0x00000001
8261 +/* Disable
8262 +#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */
8263 +/** Enable */
8264 +#define SYS_ETH_CLKS_GMAC0_EN 0x00000001
8265 +
8266 +/* Fields of "Clock Enable Register" */
8267 +/** Set Clock Enable GPHY1MII2
8268 +    Sets the clock enable bit of the GPHY1MII2. */
8269 +#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000
8270 +/* No-Operation
8271 +#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */
8272 +/** Set */
8273 +#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000
8274 +/** Set Clock Enable GPHY0MII2
8275 +    Sets the clock enable bit of the GPHY0MII2. */
8276 +#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000
8277 +/* No-Operation
8278 +#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */
8279 +/** Set */
8280 +#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000
8281 +/** Set Clock Enable PADCTRL2
8282 +    Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8283 +#define SYS_ETH_CLKEN_PADCTRL2 0x00200000
8284 +/* No-Operation
8285 +#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */
8286 +/** Set */
8287 +#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000
8288 +/** Set Clock Enable PADCTRL0
8289 +    Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8290 +#define SYS_ETH_CLKEN_PADCTRL0 0x00100000
8291 +/* No-Operation
8292 +#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */
8293 +/** Set */
8294 +#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000
8295 +/** Set Clock Enable P2
8296 +    Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8297 +#define SYS_ETH_CLKEN_P2 0x00020000
8298 +/* No-Operation
8299 +#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */
8300 +/** Set */
8301 +#define SYS_ETH_CLKEN_P2_SET 0x00020000
8302 +/** Set Clock Enable P0
8303 +    Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8304 +#define SYS_ETH_CLKEN_P0 0x00010000
8305 +/* No-Operation
8306 +#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */
8307 +/** Set */
8308 +#define SYS_ETH_CLKEN_P0_SET 0x00010000
8309 +/** Set Clock Enable xMII
8310 +    Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8311 +#define SYS_ETH_CLKEN_xMII 0x00000800
8312 +/* No-Operation
8313 +#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */
8314 +/** Set */
8315 +#define SYS_ETH_CLKEN_xMII_SET 0x00000800
8316 +/** Set Clock Enable SGMII
8317 +    Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8318 +#define SYS_ETH_CLKEN_SGMII 0x00000400
8319 +/* No-Operation
8320 +#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */
8321 +/** Set */
8322 +#define SYS_ETH_CLKEN_SGMII_SET 0x00000400
8323 +/** Set Clock Enable GPHY1
8324 +    Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8325 +#define SYS_ETH_CLKEN_GPHY1 0x00000200
8326 +/* No-Operation
8327 +#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */
8328 +/** Set */
8329 +#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200
8330 +/** Set Clock Enable GPHY0
8331 +    Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8332 +#define SYS_ETH_CLKEN_GPHY0 0x00000100
8333 +/* No-Operation
8334 +#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */
8335 +/** Set */
8336 +#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100
8337 +/** Set Clock Enable MDIO
8338 +    Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
8339 +#define SYS_ETH_CLKEN_MDIO 0x00000080
8340 +/* No-Operation
8341 +#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */
8342 +/** Set */
8343 +#define SYS_ETH_CLKEN_MDIO_SET 0x00000080
8344 +/** Set Clock Enable GMAC3
8345 +    Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
8346 +#define SYS_ETH_CLKEN_GMAC3 0x00000008
8347 +/* No-Operation
8348 +#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */
8349 +/** Set */
8350 +#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008
8351 +/** Set Clock Enable GMAC2
8352 +    Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
8353 +#define SYS_ETH_CLKEN_GMAC2 0x00000004
8354 +/* No-Operation
8355 +#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */
8356 +/** Set */
8357 +#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004
8358 +/** Set Clock Enable GMAC1
8359 +    Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
8360 +#define SYS_ETH_CLKEN_GMAC1 0x00000002
8361 +/* No-Operation
8362 +#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */
8363 +/** Set */
8364 +#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002
8365 +/** Set Clock Enable GMAC0
8366 +    Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
8367 +#define SYS_ETH_CLKEN_GMAC0 0x00000001
8368 +/* No-Operation
8369 +#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */
8370 +/** Set */
8371 +#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001
8372 +
8373 +/* Fields of "Clock Clear Register" */
8374 +/** Clear Clock Enable GPHY1MII2
8375 +    Clears the clock enable bit of the GPHY1MII2. */
8376 +#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000
8377 +/* No-Operation
8378 +#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */
8379 +/** Clear */
8380 +#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000
8381 +/** Clear Clock Enable GPHY0MII2
8382 +    Clears the clock enable bit of the GPHY0MII2. */
8383 +#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000
8384 +/* No-Operation
8385 +#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */
8386 +/** Clear */
8387 +#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000
8388 +/** Clear Clock Enable PADCTRL2
8389 +    Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8390 +#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000
8391 +/* No-Operation
8392 +#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */
8393 +/** Clear */
8394 +#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000
8395 +/** Clear Clock Enable PADCTRL0
8396 +    Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8397 +#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000
8398 +/* No-Operation
8399 +#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */
8400 +/** Clear */
8401 +#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000
8402 +/** Clear Clock Enable P2
8403 +    Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8404 +#define SYS_ETH_CLKCLR_P2 0x00020000
8405 +/* No-Operation
8406 +#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */
8407 +/** Clear */
8408 +#define SYS_ETH_CLKCLR_P2_CLR 0x00020000
8409 +/** Clear Clock Enable P0
8410 +    Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8411 +#define SYS_ETH_CLKCLR_P0 0x00010000
8412 +/* No-Operation
8413 +#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */
8414 +/** Clear */
8415 +#define SYS_ETH_CLKCLR_P0_CLR 0x00010000
8416 +/** Clear Clock Enable xMII
8417 +    Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8418 +#define SYS_ETH_CLKCLR_xMII 0x00000800
8419 +/* No-Operation
8420 +#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */
8421 +/** Clear */
8422 +#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800
8423 +/** Clear Clock Enable SGMII
8424 +    Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8425 +#define SYS_ETH_CLKCLR_SGMII 0x00000400
8426 +/* No-Operation
8427 +#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */
8428 +/** Clear */
8429 +#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400
8430 +/** Clear Clock Enable GPHY1
8431 +    Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8432 +#define SYS_ETH_CLKCLR_GPHY1 0x00000200
8433 +/* No-Operation
8434 +#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */
8435 +/** Clear */
8436 +#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200
8437 +/** Clear Clock Enable GPHY0
8438 +    Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8439 +#define SYS_ETH_CLKCLR_GPHY0 0x00000100
8440 +/* No-Operation
8441 +#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */
8442 +/** Clear */
8443 +#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100
8444 +/** Clear Clock Enable MDIO
8445 +    Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
8446 +#define SYS_ETH_CLKCLR_MDIO 0x00000080
8447 +/* No-Operation
8448 +#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */
8449 +/** Clear */
8450 +#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080
8451 +/** Clear Clock Enable GMAC3
8452 +    Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
8453 +#define SYS_ETH_CLKCLR_GMAC3 0x00000008
8454 +/* No-Operation
8455 +#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */
8456 +/** Clear */
8457 +#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008
8458 +/** Clear Clock Enable GMAC2
8459 +    Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
8460 +#define SYS_ETH_CLKCLR_GMAC2 0x00000004
8461 +/* No-Operation
8462 +#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */
8463 +/** Clear */
8464 +#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004
8465 +/** Clear Clock Enable GMAC1
8466 +    Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
8467 +#define SYS_ETH_CLKCLR_GMAC1 0x00000002
8468 +/* No-Operation
8469 +#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */
8470 +/** Clear */
8471 +#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002
8472 +/** Clear Clock Enable GMAC0
8473 +    Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
8474 +#define SYS_ETH_CLKCLR_GMAC0 0x00000001
8475 +/* No-Operation
8476 +#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */
8477 +/** Clear */
8478 +#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001
8479 +
8480 +/* Fields of "Activation Status Register" */
8481 +/** PADCTRL2 Status
8482 +    Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8483 +#define SYS_ETH_ACTS_PADCTRL2 0x00200000
8484 +/* The block is inactive.
8485 +#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */
8486 +/** The block is active. */
8487 +#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000
8488 +/** PADCTRL0 Status
8489 +    Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8490 +#define SYS_ETH_ACTS_PADCTRL0 0x00100000
8491 +/* The block is inactive.
8492 +#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */
8493 +/** The block is active. */
8494 +#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000
8495 +/** P2 Status
8496 +    Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8497 +#define SYS_ETH_ACTS_P2 0x00020000
8498 +/* The block is inactive.
8499 +#define SYS_ETH_ACTS_P2_INACT 0x00000000 */
8500 +/** The block is active. */
8501 +#define SYS_ETH_ACTS_P2_ACT 0x00020000
8502 +/** P0 Status
8503 +    Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8504 +#define SYS_ETH_ACTS_P0 0x00010000
8505 +/* The block is inactive.
8506 +#define SYS_ETH_ACTS_P0_INACT 0x00000000 */
8507 +/** The block is active. */
8508 +#define SYS_ETH_ACTS_P0_ACT 0x00010000
8509 +/** xMII Status
8510 +    Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8511 +#define SYS_ETH_ACTS_xMII 0x00000800
8512 +/* The block is inactive.
8513 +#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */
8514 +/** The block is active. */
8515 +#define SYS_ETH_ACTS_xMII_ACT 0x00000800
8516 +/** SGMII Status
8517 +    Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8518 +#define SYS_ETH_ACTS_SGMII 0x00000400
8519 +/* The block is inactive.
8520 +#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */
8521 +/** The block is active. */
8522 +#define SYS_ETH_ACTS_SGMII_ACT 0x00000400
8523 +/** GPHY1 Status
8524 +    Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8525 +#define SYS_ETH_ACTS_GPHY1 0x00000200
8526 +/* The block is inactive.
8527 +#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */
8528 +/** The block is active. */
8529 +#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200
8530 +/** GPHY0 Status
8531 +    Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8532 +#define SYS_ETH_ACTS_GPHY0 0x00000100
8533 +/* The block is inactive.
8534 +#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */
8535 +/** The block is active. */
8536 +#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100
8537 +/** MDIO Status
8538 +    Shows the activation status of the MDIO domain. This domain contains the MDIO block. */
8539 +#define SYS_ETH_ACTS_MDIO 0x00000080
8540 +/* The block is inactive.
8541 +#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */
8542 +/** The block is active. */
8543 +#define SYS_ETH_ACTS_MDIO_ACT 0x00000080
8544 +/** GMAC3 Status
8545 +    Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */
8546 +#define SYS_ETH_ACTS_GMAC3 0x00000008
8547 +/* The block is inactive.
8548 +#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */
8549 +/** The block is active. */
8550 +#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008
8551 +/** GMAC2 Status
8552 +    Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */
8553 +#define SYS_ETH_ACTS_GMAC2 0x00000004
8554 +/* The block is inactive.
8555 +#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */
8556 +/** The block is active. */
8557 +#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004
8558 +/** GMAC1 Status
8559 +    Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */
8560 +#define SYS_ETH_ACTS_GMAC1 0x00000002
8561 +/* The block is inactive.
8562 +#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */
8563 +/** The block is active. */
8564 +#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002
8565 +/** GMAC0 Status
8566 +    Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */
8567 +#define SYS_ETH_ACTS_GMAC0 0x00000001
8568 +/* The block is inactive.
8569 +#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */
8570 +/** The block is active. */
8571 +#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001
8572 +
8573 +/* Fields of "Activation Register" */
8574 +/** Activate PADCTRL2
8575 +    Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8576 +#define SYS_ETH_ACT_PADCTRL2 0x00200000
8577 +/* No-Operation
8578 +#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */
8579 +/** Set */
8580 +#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000
8581 +/** Activate PADCTRL0
8582 +    Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8583 +#define SYS_ETH_ACT_PADCTRL0 0x00100000
8584 +/* No-Operation
8585 +#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */
8586 +/** Set */
8587 +#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000
8588 +/** Activate P2
8589 +    Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8590 +#define SYS_ETH_ACT_P2 0x00020000
8591 +/* No-Operation
8592 +#define SYS_ETH_ACT_P2_NOP 0x00000000 */
8593 +/** Set */
8594 +#define SYS_ETH_ACT_P2_SET 0x00020000
8595 +/** Activate P0
8596 +    Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8597 +#define SYS_ETH_ACT_P0 0x00010000
8598 +/* No-Operation
8599 +#define SYS_ETH_ACT_P0_NOP 0x00000000 */
8600 +/** Set */
8601 +#define SYS_ETH_ACT_P0_SET 0x00010000
8602 +/** Activate xMII
8603 +    Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8604 +#define SYS_ETH_ACT_xMII 0x00000800
8605 +/* No-Operation
8606 +#define SYS_ETH_ACT_xMII_NOP 0x00000000 */
8607 +/** Set */
8608 +#define SYS_ETH_ACT_xMII_SET 0x00000800
8609 +/** Activate SGMII
8610 +    Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8611 +#define SYS_ETH_ACT_SGMII 0x00000400
8612 +/* No-Operation
8613 +#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */
8614 +/** Set */
8615 +#define SYS_ETH_ACT_SGMII_SET 0x00000400
8616 +/** Activate GPHY1
8617 +    Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8618 +#define SYS_ETH_ACT_GPHY1 0x00000200
8619 +/* No-Operation
8620 +#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */
8621 +/** Set */
8622 +#define SYS_ETH_ACT_GPHY1_SET 0x00000200
8623 +/** Activate GPHY0
8624 +    Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8625 +#define SYS_ETH_ACT_GPHY0 0x00000100
8626 +/* No-Operation
8627 +#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */
8628 +/** Set */
8629 +#define SYS_ETH_ACT_GPHY0_SET 0x00000100
8630 +/** Activate MDIO
8631 +    Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */
8632 +#define SYS_ETH_ACT_MDIO 0x00000080
8633 +/* No-Operation
8634 +#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */
8635 +/** Set */
8636 +#define SYS_ETH_ACT_MDIO_SET 0x00000080
8637 +/** Activate GMAC3
8638 +    Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
8639 +#define SYS_ETH_ACT_GMAC3 0x00000008
8640 +/* No-Operation
8641 +#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */
8642 +/** Set */
8643 +#define SYS_ETH_ACT_GMAC3_SET 0x00000008
8644 +/** Activate GMAC2
8645 +    Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
8646 +#define SYS_ETH_ACT_GMAC2 0x00000004
8647 +/* No-Operation
8648 +#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */
8649 +/** Set */
8650 +#define SYS_ETH_ACT_GMAC2_SET 0x00000004
8651 +/** Activate GMAC1
8652 +    Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
8653 +#define SYS_ETH_ACT_GMAC1 0x00000002
8654 +/* No-Operation
8655 +#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */
8656 +/** Set */
8657 +#define SYS_ETH_ACT_GMAC1_SET 0x00000002
8658 +/** Activate GMAC0
8659 +    Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
8660 +#define SYS_ETH_ACT_GMAC0 0x00000001
8661 +/* No-Operation
8662 +#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */
8663 +/** Set */
8664 +#define SYS_ETH_ACT_GMAC0_SET 0x00000001
8665 +
8666 +/* Fields of "Deactivation Register" */
8667 +/** Deactivate PADCTRL2
8668 +    Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8669 +#define SYS_ETH_DEACT_PADCTRL2 0x00200000
8670 +/* No-Operation
8671 +#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */
8672 +/** Clear */
8673 +#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000
8674 +/** Deactivate PADCTRL0
8675 +    Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8676 +#define SYS_ETH_DEACT_PADCTRL0 0x00100000
8677 +/* No-Operation
8678 +#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */
8679 +/** Clear */
8680 +#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000
8681 +/** Deactivate P2
8682 +    Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8683 +#define SYS_ETH_DEACT_P2 0x00020000
8684 +/* No-Operation
8685 +#define SYS_ETH_DEACT_P2_NOP 0x00000000 */
8686 +/** Clear */
8687 +#define SYS_ETH_DEACT_P2_CLR 0x00020000
8688 +/** Deactivate P0
8689 +    Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8690 +#define SYS_ETH_DEACT_P0 0x00010000
8691 +/* No-Operation
8692 +#define SYS_ETH_DEACT_P0_NOP 0x00000000 */
8693 +/** Clear */
8694 +#define SYS_ETH_DEACT_P0_CLR 0x00010000
8695 +/** Deactivate xMII
8696 +    Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8697 +#define SYS_ETH_DEACT_xMII 0x00000800
8698 +/* No-Operation
8699 +#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */
8700 +/** Clear */
8701 +#define SYS_ETH_DEACT_xMII_CLR 0x00000800
8702 +/** Deactivate SGMII
8703 +    Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8704 +#define SYS_ETH_DEACT_SGMII 0x00000400
8705 +/* No-Operation
8706 +#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */
8707 +/** Clear */
8708 +#define SYS_ETH_DEACT_SGMII_CLR 0x00000400
8709 +/** Deactivate GPHY1
8710 +    Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8711 +#define SYS_ETH_DEACT_GPHY1 0x00000200
8712 +/* No-Operation
8713 +#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */
8714 +/** Clear */
8715 +#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200
8716 +/** Deactivate GPHY0
8717 +    Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8718 +#define SYS_ETH_DEACT_GPHY0 0x00000100
8719 +/* No-Operation
8720 +#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */
8721 +/** Clear */
8722 +#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100
8723 +/** Deactivate MDIO
8724 +    Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */
8725 +#define SYS_ETH_DEACT_MDIO 0x00000080
8726 +/* No-Operation
8727 +#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */
8728 +/** Clear */
8729 +#define SYS_ETH_DEACT_MDIO_CLR 0x00000080
8730 +/** Deactivate GMAC3
8731 +    Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
8732 +#define SYS_ETH_DEACT_GMAC3 0x00000008
8733 +/* No-Operation
8734 +#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */
8735 +/** Clear */
8736 +#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008
8737 +/** Deactivate GMAC2
8738 +    Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
8739 +#define SYS_ETH_DEACT_GMAC2 0x00000004
8740 +/* No-Operation
8741 +#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */
8742 +/** Clear */
8743 +#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004
8744 +/** Deactivate GMAC1
8745 +    Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
8746 +#define SYS_ETH_DEACT_GMAC1 0x00000002
8747 +/* No-Operation
8748 +#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */
8749 +/** Clear */
8750 +#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002
8751 +/** Deactivate GMAC0
8752 +    Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
8753 +#define SYS_ETH_DEACT_GMAC0 0x00000001
8754 +/* No-Operation
8755 +#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */
8756 +/** Clear */
8757 +#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001
8758 +
8759 +/* Fields of "Reboot Trigger Register" */
8760 +/** Reboot PADCTRL2
8761 +    Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8762 +#define SYS_ETH_RBT_PADCTRL2 0x00200000
8763 +/* No-Operation
8764 +#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */
8765 +/** Trigger */
8766 +#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000
8767 +/** Reboot PADCTRL0
8768 +    Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8769 +#define SYS_ETH_RBT_PADCTRL0 0x00100000
8770 +/* No-Operation
8771 +#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */
8772 +/** Trigger */
8773 +#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000
8774 +/** Reboot P2
8775 +    Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8776 +#define SYS_ETH_RBT_P2 0x00020000
8777 +/* No-Operation
8778 +#define SYS_ETH_RBT_P2_NOP 0x00000000 */
8779 +/** Trigger */
8780 +#define SYS_ETH_RBT_P2_TRIG 0x00020000
8781 +/** Reboot P0
8782 +    Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8783 +#define SYS_ETH_RBT_P0 0x00010000
8784 +/* No-Operation
8785 +#define SYS_ETH_RBT_P0_NOP 0x00000000 */
8786 +/** Trigger */
8787 +#define SYS_ETH_RBT_P0_TRIG 0x00010000
8788 +/** Reboot xMII
8789 +    Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8790 +#define SYS_ETH_RBT_xMII 0x00000800
8791 +/* No-Operation
8792 +#define SYS_ETH_RBT_xMII_NOP 0x00000000 */
8793 +/** Trigger */
8794 +#define SYS_ETH_RBT_xMII_TRIG 0x00000800
8795 +/** Reboot SGMII
8796 +    Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8797 +#define SYS_ETH_RBT_SGMII 0x00000400
8798 +/* No-Operation
8799 +#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */
8800 +/** Trigger */
8801 +#define SYS_ETH_RBT_SGMII_TRIG 0x00000400
8802 +/** Reboot GPHY1
8803 +    Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8804 +#define SYS_ETH_RBT_GPHY1 0x00000200
8805 +/* No-Operation
8806 +#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */
8807 +/** Trigger */
8808 +#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200
8809 +/** Reboot GPHY0
8810 +    Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8811 +#define SYS_ETH_RBT_GPHY0 0x00000100
8812 +/* No-Operation
8813 +#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */
8814 +/** Trigger */
8815 +#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100
8816 +/** Reboot MDIO
8817 +    Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */
8818 +#define SYS_ETH_RBT_MDIO 0x00000080
8819 +/* No-Operation
8820 +#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */
8821 +/** Trigger */
8822 +#define SYS_ETH_RBT_MDIO_TRIG 0x00000080
8823 +/** Reboot GMAC3
8824 +    Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */
8825 +#define SYS_ETH_RBT_GMAC3 0x00000008
8826 +/* No-Operation
8827 +#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */
8828 +/** Trigger */
8829 +#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008
8830 +/** Reboot GMAC2
8831 +    Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */
8832 +#define SYS_ETH_RBT_GMAC2 0x00000004
8833 +/* No-Operation
8834 +#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */
8835 +/** Trigger */
8836 +#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004
8837 +/** Reboot GMAC1
8838 +    Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */
8839 +#define SYS_ETH_RBT_GMAC1 0x00000002
8840 +/* No-Operation
8841 +#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */
8842 +/** Trigger */
8843 +#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002
8844 +/** Reboot GMAC0
8845 +    Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */
8846 +#define SYS_ETH_RBT_GMAC0 0x00000001
8847 +/* No-Operation
8848 +#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */
8849 +/** Trigger */
8850 +#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001
8851 +
8852 +/* Fields of "External PHY Control Register" */
8853 +/** PHY_CLKO Output Enable
8854 +    Enables the output driver of the PHY_CLKO pin. */
8855 +#define SYS_ETH_EXTPHYC_CLKEN 0x80000000
8856 +/* Disable
8857 +#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */
8858 +/** Enable */
8859 +#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000
8860 +/** PHY_CLKO Frequency Select
8861 +    Selects the frequency of the PHY_CLKO pin. */
8862 +#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007
8863 +/** field offset */
8864 +#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0
8865 +/** 25 MHz. */
8866 +#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001
8867 +/** 125 MHz. */
8868 +#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002
8869 +/** 50 MHz. */
8870 +#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005
8871 +
8872 +/* Fields of "Power Down Configuration Register" */
8873 +/** Enable Power Down PADCTRL2
8874 +    Ignore this bit as power-gating is not supported for this chip. */
8875 +#define SYS_ETH_PDCFG_PADCTRL2 0x00200000
8876 +/* Disable
8877 +#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */
8878 +/** Enable */
8879 +#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000
8880 +/** Enable Power Down PADCTRL0
8881 +    Ignore this bit as power-gating is not supported for this chip. */
8882 +#define SYS_ETH_PDCFG_PADCTRL0 0x00100000
8883 +/* Disable
8884 +#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */
8885 +/** Enable */
8886 +#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000
8887 +/** Enable Power Down P2
8888 +    Ignore this bit as power-gating is not supported for this chip. */
8889 +#define SYS_ETH_PDCFG_P2 0x00020000
8890 +/* Disable
8891 +#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */
8892 +/** Enable */
8893 +#define SYS_ETH_PDCFG_P2_EN 0x00020000
8894 +/** Enable Power Down P0
8895 +    Ignore this bit as power-gating is not supported for this chip. */
8896 +#define SYS_ETH_PDCFG_P0 0x00010000
8897 +/* Disable
8898 +#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */
8899 +/** Enable */
8900 +#define SYS_ETH_PDCFG_P0_EN 0x00010000
8901 +/** Enable Power Down xMII
8902 +    Ignore this bit as power-gating is not supported for this chip. */
8903 +#define SYS_ETH_PDCFG_xMII 0x00000800
8904 +/* Disable
8905 +#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */
8906 +/** Enable */
8907 +#define SYS_ETH_PDCFG_xMII_EN 0x00000800
8908 +/** Enable Power Down SGMII
8909 +    Ignore this bit as power-gating is not supported for this chip. */
8910 +#define SYS_ETH_PDCFG_SGMII 0x00000400
8911 +/* Disable
8912 +#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */
8913 +/** Enable */
8914 +#define SYS_ETH_PDCFG_SGMII_EN 0x00000400
8915 +/** Enable Power Down GPHY1
8916 +    Ignore this bit as power-gating is not supported for this chip. */
8917 +#define SYS_ETH_PDCFG_GPHY1 0x00000200
8918 +/* Disable
8919 +#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */
8920 +/** Enable */
8921 +#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200
8922 +/** Enable Power Down GPHY0
8923 +    Ignore this bit as power-gating is not supported for this chip. */
8924 +#define SYS_ETH_PDCFG_GPHY0 0x00000100
8925 +/* Disable
8926 +#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */
8927 +/** Enable */
8928 +#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100
8929 +/** Enable Power Down MDIO
8930 +    Ignore this bit as power-gating is not supported for this chip. */
8931 +#define SYS_ETH_PDCFG_MDIO 0x00000080
8932 +/* Disable
8933 +#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */
8934 +/** Enable */
8935 +#define SYS_ETH_PDCFG_MDIO_EN 0x00000080
8936 +/** Enable Power Down GMAC3
8937 +    Ignore this bit as power-gating is not supported for this chip. */
8938 +#define SYS_ETH_PDCFG_GMAC3 0x00000008
8939 +/* Disable
8940 +#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */
8941 +/** Enable */
8942 +#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008
8943 +/** Enable Power Down GMAC2
8944 +    Ignore this bit as power-gating is not supported for this chip. */
8945 +#define SYS_ETH_PDCFG_GMAC2 0x00000004
8946 +/* Disable
8947 +#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */
8948 +/** Enable */
8949 +#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004
8950 +/** Enable Power Down GMAC1
8951 +    Ignore this bit as power-gating is not supported for this chip. */
8952 +#define SYS_ETH_PDCFG_GMAC1 0x00000002
8953 +/* Disable
8954 +#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */
8955 +/** Enable */
8956 +#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002
8957 +/** Enable Power Down GMAC0
8958 +    Ignore this bit as power-gating is not supported for this chip. */
8959 +#define SYS_ETH_PDCFG_GMAC0 0x00000001
8960 +/* Disable
8961 +#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */
8962 +/** Enable */
8963 +#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001
8964 +
8965 +/* Fields of "Datarate Control Register" */
8966 +/** MDC Clockrate
8967 +    Selects the clockrate of the MDIO interface. */
8968 +#define SYS_ETH_DRC_MDC_MASK 0x30000000
8969 +/** field offset */
8970 +#define SYS_ETH_DRC_MDC_OFFSET 28
8971 +/** 312.5/128 = appr. 2.44 MHz. */
8972 +#define SYS_ETH_DRC_MDC_F2M44 0x00000000
8973 +/** 312.5/64 = appr. 4.88 MHz. */
8974 +#define SYS_ETH_DRC_MDC_F4M88 0x10000000
8975 +/** 312.5/32 = appr. 9.77 MHz. */
8976 +#define SYS_ETH_DRC_MDC_F9M77 0x20000000
8977 +/** 312.5/16 = appr. 19.5 MHz. */
8978 +#define SYS_ETH_DRC_MDC_F19M5 0x30000000
8979 +/** xMII1 Datarate
8980 +    Selects the datarate of the xMII1 interface. */
8981 +#define SYS_ETH_DRC_xMII1_MASK 0x07000000
8982 +/** field offset */
8983 +#define SYS_ETH_DRC_xMII1_OFFSET 24
8984 +/** 10 MBit/s. */
8985 +#define SYS_ETH_DRC_xMII1_DR10 0x00000000
8986 +/** 100 MBit/s. */
8987 +#define SYS_ETH_DRC_xMII1_DR100 0x01000000
8988 +/** 1000 MBit/s. */
8989 +#define SYS_ETH_DRC_xMII1_DR1000 0x02000000
8990 +/** 200 MBit/s. */
8991 +#define SYS_ETH_DRC_xMII1_DR200 0x05000000
8992 +/** xMII0 Datarate
8993 +    Selects the datarate of the xMII0 interface. */
8994 +#define SYS_ETH_DRC_xMII0_MASK 0x00700000
8995 +/** field offset */
8996 +#define SYS_ETH_DRC_xMII0_OFFSET 20
8997 +/** 10 MBit/s. */
8998 +#define SYS_ETH_DRC_xMII0_DR10 0x00000000
8999 +/** 100 MBit/s. */
9000 +#define SYS_ETH_DRC_xMII0_DR100 0x00100000
9001 +/** 1000 MBit/s. */
9002 +#define SYS_ETH_DRC_xMII0_DR1000 0x00200000
9003 +/** 200 MBit/s. */
9004 +#define SYS_ETH_DRC_xMII0_DR200 0x00500000
9005 +/** SGMII Datarate
9006 +    Selects the datarate of the SGMII interface. */
9007 +#define SYS_ETH_DRC_SGMII_MASK 0x00070000
9008 +/** field offset */
9009 +#define SYS_ETH_DRC_SGMII_OFFSET 16
9010 +/** 10 MBit/s. */
9011 +#define SYS_ETH_DRC_SGMII_DR10 0x00000000
9012 +/** 100 MBit/s. */
9013 +#define SYS_ETH_DRC_SGMII_DR100 0x00010000
9014 +/** 1000 MBit/s. */
9015 +#define SYS_ETH_DRC_SGMII_DR1000 0x00020000
9016 +/** 2500 MBit/s. */
9017 +#define SYS_ETH_DRC_SGMII_DR2500 0x00040000
9018 +/** GPHY1_MII2 Datarate
9019 +    Shows the datarate of the GPHY1_MII2 interface. */
9020 +#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000
9021 +/** field offset */
9022 +#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12
9023 +/** 10 MBit/s. */
9024 +#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000
9025 +/** 100 MBit/s. */
9026 +#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000
9027 +/** GPHY1_GMII Datarate
9028 +    Shows the datarate of the GPHY1_GMII interface. */
9029 +#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700
9030 +/** field offset */
9031 +#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8
9032 +/** 10 MBit/s. */
9033 +#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000
9034 +/** 100 MBit/s. */
9035 +#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100
9036 +/** 1000 MBit/s. */
9037 +#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200
9038 +/** GPHY0_MII2 Datarate
9039 +    Shows the datarate of the GPHY0_MII2 interface. */
9040 +#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070
9041 +/** field offset */
9042 +#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4
9043 +/** 10 MBit/s. */
9044 +#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000
9045 +/** 100 MBit/s. */
9046 +#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010
9047 +/** GPHY0_GMII Datarate
9048 +    Shows the datarate of the GPHY0_GMII interface. */
9049 +#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007
9050 +/** field offset */
9051 +#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0
9052 +/** 10 MBit/s. */
9053 +#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000
9054 +/** 100 MBit/s. */
9055 +#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001
9056 +/** 1000 MBit/s. */
9057 +#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002
9058 +
9059 +/* Fields of "GMAC Multiplexer Control Register" */
9060 +/** GMAC 3 MUX setting
9061 +    Selects the physical layer to be connected to GMAC3 */
9062 +#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000
9063 +/** field offset */
9064 +#define SYS_ETH_GMUXC_GMAC3_OFFSET 12
9065 +/** GMAC connects to GPHY0_GMII interface */
9066 +#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000
9067 +/** GMAC connects to GPHY0_MII2 interface */
9068 +#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000
9069 +/** GMAC connects to GPHY1_GMII interface */
9070 +#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000
9071 +/** GMAC connects to GPHY1_MII2 interface */
9072 +#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000
9073 +/** GMAC connects to SGMII interface */
9074 +#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000
9075 +/** GMAC connects to xMII0 interface */
9076 +#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000
9077 +/** GMAC connects to xMII1 interface */
9078 +#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000
9079 +/** GMAC 2 MUX setting
9080 +    Selects the physical layer to be connected to GMAC2 */
9081 +#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700
9082 +/** field offset */
9083 +#define SYS_ETH_GMUXC_GMAC2_OFFSET 8
9084 +/** GMAC connects to GPHY0_GMII interface */
9085 +#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000
9086 +/** GMAC connects to GPHY0_MII2 interface */
9087 +#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100
9088 +/** GMAC connects to GPHY1_GMII interface */
9089 +#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200
9090 +/** GMAC connects to GPHY1_MII2 interface */
9091 +#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300
9092 +/** GMAC connects to SGMII interface */
9093 +#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400
9094 +/** GMAC connects to xMII0 interface */
9095 +#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500
9096 +/** GMAC connects to xMII1 interface */
9097 +#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600
9098 +/** GMAC 1 MUX setting
9099 +    Selects the physical layer to be connected to GMAC1 */
9100 +#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070
9101 +/** field offset */
9102 +#define SYS_ETH_GMUXC_GMAC1_OFFSET 4
9103 +/** GMAC connects to GPHY0_GMII interface */
9104 +#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000
9105 +/** GMAC connects to GPHY0_MII2 interface */
9106 +#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010
9107 +/** GMAC connects to GPHY1_GMII interface */
9108 +#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020
9109 +/** GMAC connects to GPHY1_MII2 interface */
9110 +#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030
9111 +/** GMAC connects to SGMII interface */
9112 +#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040
9113 +/** GMAC connects to xMII0 interface */
9114 +#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050
9115 +/** GMAC connects to xMII1 interface */
9116 +#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060
9117 +/** GMAC 0 MUX setting
9118 +    Selects the physical layer to be connected to GMAC0 */
9119 +#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007
9120 +/** field offset */
9121 +#define SYS_ETH_GMUXC_GMAC0_OFFSET 0
9122 +/** GMAC connects to GPHY0_GMII interface */
9123 +#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000
9124 +/** GMAC connects to GPHY0_MII2 interface */
9125 +#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001
9126 +/** GMAC connects to GPHY1_GMII interface */
9127 +#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002
9128 +/** GMAC connects to GPHY1_MII2 interface */
9129 +#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003
9130 +/** GMAC connects to SGMII interface */
9131 +#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004
9132 +/** GMAC connects to xMII0 interface */
9133 +#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005
9134 +/** GMAC connects to xMII1 interface */
9135 +#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006
9136 +
9137 +/* Fields of "Datarate Status Register" */
9138 +/** GMAC 3 datarate
9139 +    Shows the datarate of GMAC3 */
9140 +#define SYS_ETH_DRS_GMAC3_MASK 0x00007000
9141 +/** field offset */
9142 +#define SYS_ETH_DRS_GMAC3_OFFSET 12
9143 +/** 10 MBit/s. */
9144 +#define SYS_ETH_DRS_GMAC3_DR10 0x00000000
9145 +/** 100 MBit/s. */
9146 +#define SYS_ETH_DRS_GMAC3_DR100 0x00001000
9147 +/** 1000 MBit/s. */
9148 +#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000
9149 +/** 2500 MBit/s. */
9150 +#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000
9151 +/** 200 MBit/s. */
9152 +#define SYS_ETH_DRS_GMAC3_DR200 0x00005000
9153 +/** GMAC 2 datarate
9154 +    Shows the datarate of GMAC2 */
9155 +#define SYS_ETH_DRS_GMAC2_MASK 0x00000700
9156 +/** field offset */
9157 +#define SYS_ETH_DRS_GMAC2_OFFSET 8
9158 +/** 10 MBit/s. */
9159 +#define SYS_ETH_DRS_GMAC2_DR10 0x00000000
9160 +/** 100 MBit/s. */
9161 +#define SYS_ETH_DRS_GMAC2_DR100 0x00000100
9162 +/** 1000 MBit/s. */
9163 +#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200
9164 +/** 2500 MBit/s. */
9165 +#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400
9166 +/** 200 MBit/s. */
9167 +#define SYS_ETH_DRS_GMAC2_DR200 0x00000500
9168 +/** GMAC 1 datarate
9169 +    Shows the datarate of GMAC1 */
9170 +#define SYS_ETH_DRS_GMAC1_MASK 0x00000070
9171 +/** field offset */
9172 +#define SYS_ETH_DRS_GMAC1_OFFSET 4
9173 +/** 10 MBit/s. */
9174 +#define SYS_ETH_DRS_GMAC1_DR10 0x00000000
9175 +/** 100 MBit/s. */
9176 +#define SYS_ETH_DRS_GMAC1_DR100 0x00000010
9177 +/** 1000 MBit/s. */
9178 +#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020
9179 +/** 2500 MBit/s. */
9180 +#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040
9181 +/** 200 MBit/s. */
9182 +#define SYS_ETH_DRS_GMAC1_DR200 0x00000050
9183 +/** GMAC 0 datarate
9184 +    Shows the datarate of GMAC0 */
9185 +#define SYS_ETH_DRS_GMAC0_MASK 0x00000007
9186 +/** field offset */
9187 +#define SYS_ETH_DRS_GMAC0_OFFSET 0
9188 +/** 10 MBit/s. */
9189 +#define SYS_ETH_DRS_GMAC0_DR10 0x00000000
9190 +/** 100 MBit/s. */
9191 +#define SYS_ETH_DRS_GMAC0_DR100 0x00000001
9192 +/** 1000 MBit/s. */
9193 +#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002
9194 +/** 2500 MBit/s. */
9195 +#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004
9196 +/** 200 MBit/s. */
9197 +#define SYS_ETH_DRS_GMAC0_DR200 0x00000005
9198 +
9199 +/* Fields of "SGMII Control Register" */
9200 +/** Auto Negotiation Protocol
9201 +    Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */
9202 +#define SYS_ETH_SGMIIC_ANP 0x00000002
9203 +/* TBX Mode (IEEE 802.3 Clause 37 ANEG)
9204 +#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */
9205 +/** SGMII Mode (Cisco Aneg) */
9206 +#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002
9207 +/** Auto Negotiation MAC/PHY
9208 +    Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */
9209 +#define SYS_ETH_SGMIIC_ANMP 0x00000001
9210 +/* MAC Mode
9211 +#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */
9212 +/** PHY Mode */
9213 +#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001
9214 +
9215 +/*! @} */ /* SYS_ETH_REGISTER */
9216 +
9217 +#endif /* _sys_eth_reg_h */
9218 --- /dev/null
9219 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h
9220 @@ -0,0 +1,2829 @@
9221 +/******************************************************************************
9222 +
9223 +                               Copyright (c) 2010
9224 +                            Lantiq Deutschland GmbH
9225 +
9226 +  For licensing information, see the file 'LICENSE' in the root folder of
9227 +  this software module.
9228 +
9229 +******************************************************************************/
9230 +
9231 +#ifndef _sys_gpe_reg_h
9232 +#define _sys_gpe_reg_h
9233 +
9234 +/** \addtogroup SYS_GPE_REGISTER
9235 +   @{
9236 +*/
9237 +/* access macros */
9238 +#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg)
9239 +#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg)
9240 +#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg)
9241 +#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx)
9242 +#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx)
9243 +#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx)
9244 +#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx)
9245 +
9246 +
9247 +/** SYS_GPE register structure */
9248 +struct gpon_reg_sys_gpe
9249 +{
9250 +   /** Clock Status Register
9251 +       The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */
9252 +   unsigned int clks; /* 0x00000000 */
9253 +   /** Clock Enable Register
9254 +       Via this register the clocks for the domains can be enabled. */
9255 +   unsigned int clken; /* 0x00000004 */
9256 +   /** Clock Clear Register
9257 +       Via this register the clocks for the domains can be disabled. */
9258 +   unsigned int clkclr; /* 0x00000008 */
9259 +   /** Reserved */
9260 +   unsigned int res_0[5]; /* 0x0000000C */
9261 +   /** Activation Status Register */
9262 +   unsigned int acts; /* 0x00000020 */
9263 +   /** Activation Register
9264 +       Via this register the domains can be activated. */
9265 +   unsigned int act; /* 0x00000024 */
9266 +   /** Deactivation Register
9267 +       Via this register the domains can be deactivated. */
9268 +   unsigned int deact; /* 0x00000028 */
9269 +   /** Reboot Trigger Register
9270 +       Via this register the domains can be rebooted (sent through reset). */
9271 +   unsigned int rbt; /* 0x0000002C */
9272 +   /** Reserved */
9273 +   unsigned int res_1[33]; /* 0x00000030 */
9274 +   /** Power Down Configuration Register
9275 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
9276 +   unsigned int pdcfg; /* 0x000000B4 */
9277 +   /** Sleep Source Configuration Register
9278 +       All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */
9279 +   unsigned int sscfg; /* 0x000000B8 */
9280 +   /** Sleep Source Timer Register */
9281 +   unsigned int sst; /* 0x000000BC */
9282 +   /** Sleep Destination Status Register
9283 +       Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */
9284 +   unsigned int sds; /* 0x000000C0 */
9285 +   /** Sleep Destination Set Register
9286 +       Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */
9287 +   unsigned int sdset; /* 0x000000C4 */
9288 +   /** Sleep Destination Clear Register
9289 +       Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */
9290 +   unsigned int sdclr; /* 0x000000C8 */
9291 +   /** Reserved */
9292 +   unsigned int res_2[9]; /* 0x000000CC */
9293 +   /** IRNCS Capture Register
9294 +       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */
9295 +   unsigned int irncscr; /* 0x000000F0 */
9296 +   /** IRNCS Interrupt Control Register
9297 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
9298 +   unsigned int irncsicr; /* 0x000000F4 */
9299 +   /** IRNCS Interrupt Enable Register
9300 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */
9301 +   unsigned int irncsen; /* 0x000000F8 */
9302 +   /** Reserved */
9303 +   unsigned int res_3; /* 0x000000FC */
9304 +};
9305 +
9306 +
9307 +/* Fields of "Clock Status Register" */
9308 +/** COP7 Clock Enable
9309 +    Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9310 +#define SYS_GPE_CLKS_COP7 0x80000000
9311 +/* Disable
9312 +#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */
9313 +/** Enable */
9314 +#define SYS_GPE_CLKS_COP7_EN 0x80000000
9315 +/** COP6 Clock Enable
9316 +    Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9317 +#define SYS_GPE_CLKS_COP6 0x40000000
9318 +/* Disable
9319 +#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */
9320 +/** Enable */
9321 +#define SYS_GPE_CLKS_COP6_EN 0x40000000
9322 +/** COP5 Clock Enable
9323 +    Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9324 +#define SYS_GPE_CLKS_COP5 0x20000000
9325 +/* Disable
9326 +#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */
9327 +/** Enable */
9328 +#define SYS_GPE_CLKS_COP5_EN 0x20000000
9329 +/** COP4 Clock Enable
9330 +    Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9331 +#define SYS_GPE_CLKS_COP4 0x10000000
9332 +/* Disable
9333 +#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */
9334 +/** Enable */
9335 +#define SYS_GPE_CLKS_COP4_EN 0x10000000
9336 +/** COP3 Clock Enable
9337 +    Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9338 +#define SYS_GPE_CLKS_COP3 0x08000000
9339 +/* Disable
9340 +#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */
9341 +/** Enable */
9342 +#define SYS_GPE_CLKS_COP3_EN 0x08000000
9343 +/** COP2 Clock Enable
9344 +    Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9345 +#define SYS_GPE_CLKS_COP2 0x04000000
9346 +/* Disable
9347 +#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */
9348 +/** Enable */
9349 +#define SYS_GPE_CLKS_COP2_EN 0x04000000
9350 +/** COP1 Clock Enable
9351 +    Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9352 +#define SYS_GPE_CLKS_COP1 0x02000000
9353 +/* Disable
9354 +#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */
9355 +/** Enable */
9356 +#define SYS_GPE_CLKS_COP1_EN 0x02000000
9357 +/** COP0 Clock Enable
9358 +    Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9359 +#define SYS_GPE_CLKS_COP0 0x01000000
9360 +/* Disable
9361 +#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */
9362 +/** Enable */
9363 +#define SYS_GPE_CLKS_COP0_EN 0x01000000
9364 +/** PE5 Clock Enable
9365 +    Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9366 +#define SYS_GPE_CLKS_PE5 0x00200000
9367 +/* Disable
9368 +#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */
9369 +/** Enable */
9370 +#define SYS_GPE_CLKS_PE5_EN 0x00200000
9371 +/** PE4 Clock Enable
9372 +    Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9373 +#define SYS_GPE_CLKS_PE4 0x00100000
9374 +/* Disable
9375 +#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */
9376 +/** Enable */
9377 +#define SYS_GPE_CLKS_PE4_EN 0x00100000
9378 +/** PE3 Clock Enable
9379 +    Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9380 +#define SYS_GPE_CLKS_PE3 0x00080000
9381 +/* Disable
9382 +#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */
9383 +/** Enable */
9384 +#define SYS_GPE_CLKS_PE3_EN 0x00080000
9385 +/** PE2 Clock Enable
9386 +    Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9387 +#define SYS_GPE_CLKS_PE2 0x00040000
9388 +/* Disable
9389 +#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */
9390 +/** Enable */
9391 +#define SYS_GPE_CLKS_PE2_EN 0x00040000
9392 +/** PE1 Clock Enable
9393 +    Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9394 +#define SYS_GPE_CLKS_PE1 0x00020000
9395 +/* Disable
9396 +#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */
9397 +/** Enable */
9398 +#define SYS_GPE_CLKS_PE1_EN 0x00020000
9399 +/** PE0 Clock Enable
9400 +    Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9401 +#define SYS_GPE_CLKS_PE0 0x00010000
9402 +/* Disable
9403 +#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */
9404 +/** Enable */
9405 +#define SYS_GPE_CLKS_PE0_EN 0x00010000
9406 +/** ARB Clock Enable
9407 +    Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */
9408 +#define SYS_GPE_CLKS_ARB 0x00002000
9409 +/* Disable
9410 +#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */
9411 +/** Enable */
9412 +#define SYS_GPE_CLKS_ARB_EN 0x00002000
9413 +/** FSQM Clock Enable
9414 +    Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */
9415 +#define SYS_GPE_CLKS_FSQM 0x00001000
9416 +/* Disable
9417 +#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */
9418 +/** Enable */
9419 +#define SYS_GPE_CLKS_FSQM_EN 0x00001000
9420 +/** TMU Clock Enable
9421 +    Shows the clock enable bit for the TMU domain. This domain contains the TMU. */
9422 +#define SYS_GPE_CLKS_TMU 0x00000800
9423 +/* Disable
9424 +#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */
9425 +/** Enable */
9426 +#define SYS_GPE_CLKS_TMU_EN 0x00000800
9427 +/** MRG Clock Enable
9428 +    Shows the clock enable bit for the MRG domain. This domain contains the Merger. */
9429 +#define SYS_GPE_CLKS_MRG 0x00000400
9430 +/* Disable
9431 +#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */
9432 +/** Enable */
9433 +#define SYS_GPE_CLKS_MRG_EN 0x00000400
9434 +/** DISP Clock Enable
9435 +    Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */
9436 +#define SYS_GPE_CLKS_DISP 0x00000200
9437 +/* Disable
9438 +#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */
9439 +/** Enable */
9440 +#define SYS_GPE_CLKS_DISP_EN 0x00000200
9441 +/** IQM Clock Enable
9442 +    Shows the clock enable bit for the IQM domain. This domain contains the IQM. */
9443 +#define SYS_GPE_CLKS_IQM 0x00000100
9444 +/* Disable
9445 +#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */
9446 +/** Enable */
9447 +#define SYS_GPE_CLKS_IQM_EN 0x00000100
9448 +/** CPUE Clock Enable
9449 +    Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
9450 +#define SYS_GPE_CLKS_CPUE 0x00000080
9451 +/* Disable
9452 +#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */
9453 +/** Enable */
9454 +#define SYS_GPE_CLKS_CPUE_EN 0x00000080
9455 +/** CPUI Clock Enable
9456 +    Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
9457 +#define SYS_GPE_CLKS_CPUI 0x00000040
9458 +/* Disable
9459 +#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */
9460 +/** Enable */
9461 +#define SYS_GPE_CLKS_CPUI_EN 0x00000040
9462 +/** GPONE Clock Enable
9463 +    Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
9464 +#define SYS_GPE_CLKS_GPONE 0x00000020
9465 +/* Disable
9466 +#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */
9467 +/** Enable */
9468 +#define SYS_GPE_CLKS_GPONE_EN 0x00000020
9469 +/** GPONI Clock Enable
9470 +    Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
9471 +#define SYS_GPE_CLKS_GPONI 0x00000010
9472 +/* Disable
9473 +#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */
9474 +/** Enable */
9475 +#define SYS_GPE_CLKS_GPONI_EN 0x00000010
9476 +/** LAN3 Clock Enable
9477 +    Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
9478 +#define SYS_GPE_CLKS_LAN3 0x00000008
9479 +/* Disable
9480 +#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */
9481 +/** Enable */
9482 +#define SYS_GPE_CLKS_LAN3_EN 0x00000008
9483 +/** LAN2 Clock Enable
9484 +    Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
9485 +#define SYS_GPE_CLKS_LAN2 0x00000004
9486 +/* Disable
9487 +#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */
9488 +/** Enable */
9489 +#define SYS_GPE_CLKS_LAN2_EN 0x00000004
9490 +/** LAN1 Clock Enable
9491 +    Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
9492 +#define SYS_GPE_CLKS_LAN1 0x00000002
9493 +/* Disable
9494 +#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */
9495 +/** Enable */
9496 +#define SYS_GPE_CLKS_LAN1_EN 0x00000002
9497 +/** LAN0 Clock Enable
9498 +    Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
9499 +#define SYS_GPE_CLKS_LAN0 0x00000001
9500 +/* Disable
9501 +#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */
9502 +/** Enable */
9503 +#define SYS_GPE_CLKS_LAN0_EN 0x00000001
9504 +
9505 +/* Fields of "Clock Enable Register" */
9506 +/** Set Clock Enable COP7
9507 +    Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9508 +#define SYS_GPE_CLKEN_COP7 0x80000000
9509 +/* No-Operation
9510 +#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */
9511 +/** Set */
9512 +#define SYS_GPE_CLKEN_COP7_SET 0x80000000
9513 +/** Set Clock Enable COP6
9514 +    Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9515 +#define SYS_GPE_CLKEN_COP6 0x40000000
9516 +/* No-Operation
9517 +#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */
9518 +/** Set */
9519 +#define SYS_GPE_CLKEN_COP6_SET 0x40000000
9520 +/** Set Clock Enable COP5
9521 +    Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9522 +#define SYS_GPE_CLKEN_COP5 0x20000000
9523 +/* No-Operation
9524 +#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */
9525 +/** Set */
9526 +#define SYS_GPE_CLKEN_COP5_SET 0x20000000
9527 +/** Set Clock Enable COP4
9528 +    Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9529 +#define SYS_GPE_CLKEN_COP4 0x10000000
9530 +/* No-Operation
9531 +#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */
9532 +/** Set */
9533 +#define SYS_GPE_CLKEN_COP4_SET 0x10000000
9534 +/** Set Clock Enable COP3
9535 +    Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9536 +#define SYS_GPE_CLKEN_COP3 0x08000000
9537 +/* No-Operation
9538 +#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */
9539 +/** Set */
9540 +#define SYS_GPE_CLKEN_COP3_SET 0x08000000
9541 +/** Set Clock Enable COP2
9542 +    Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9543 +#define SYS_GPE_CLKEN_COP2 0x04000000
9544 +/* No-Operation
9545 +#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */
9546 +/** Set */
9547 +#define SYS_GPE_CLKEN_COP2_SET 0x04000000
9548 +/** Set Clock Enable COP1
9549 +    Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9550 +#define SYS_GPE_CLKEN_COP1 0x02000000
9551 +/* No-Operation
9552 +#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */
9553 +/** Set */
9554 +#define SYS_GPE_CLKEN_COP1_SET 0x02000000
9555 +/** Set Clock Enable COP0
9556 +    Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9557 +#define SYS_GPE_CLKEN_COP0 0x01000000
9558 +/* No-Operation
9559 +#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */
9560 +/** Set */
9561 +#define SYS_GPE_CLKEN_COP0_SET 0x01000000
9562 +/** Set Clock Enable PE5
9563 +    Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9564 +#define SYS_GPE_CLKEN_PE5 0x00200000
9565 +/* No-Operation
9566 +#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */
9567 +/** Set */
9568 +#define SYS_GPE_CLKEN_PE5_SET 0x00200000
9569 +/** Set Clock Enable PE4
9570 +    Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9571 +#define SYS_GPE_CLKEN_PE4 0x00100000
9572 +/* No-Operation
9573 +#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */
9574 +/** Set */
9575 +#define SYS_GPE_CLKEN_PE4_SET 0x00100000
9576 +/** Set Clock Enable PE3
9577 +    Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9578 +#define SYS_GPE_CLKEN_PE3 0x00080000
9579 +/* No-Operation
9580 +#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */
9581 +/** Set */
9582 +#define SYS_GPE_CLKEN_PE3_SET 0x00080000
9583 +/** Set Clock Enable PE2
9584 +    Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9585 +#define SYS_GPE_CLKEN_PE2 0x00040000
9586 +/* No-Operation
9587 +#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */
9588 +/** Set */
9589 +#define SYS_GPE_CLKEN_PE2_SET 0x00040000
9590 +/** Set Clock Enable PE1
9591 +    Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9592 +#define SYS_GPE_CLKEN_PE1 0x00020000
9593 +/* No-Operation
9594 +#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */
9595 +/** Set */
9596 +#define SYS_GPE_CLKEN_PE1_SET 0x00020000
9597 +/** Set Clock Enable PE0
9598 +    Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9599 +#define SYS_GPE_CLKEN_PE0 0x00010000
9600 +/* No-Operation
9601 +#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */
9602 +/** Set */
9603 +#define SYS_GPE_CLKEN_PE0_SET 0x00010000
9604 +/** Set Clock Enable ARB
9605 +    Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */
9606 +#define SYS_GPE_CLKEN_ARB 0x00002000
9607 +/* No-Operation
9608 +#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */
9609 +/** Set */
9610 +#define SYS_GPE_CLKEN_ARB_SET 0x00002000
9611 +/** Set Clock Enable FSQM
9612 +    Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */
9613 +#define SYS_GPE_CLKEN_FSQM 0x00001000
9614 +/* No-Operation
9615 +#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */
9616 +/** Set */
9617 +#define SYS_GPE_CLKEN_FSQM_SET 0x00001000
9618 +/** Set Clock Enable TMU
9619 +    Sets the clock enable bit of the TMU domain. This domain contains the TMU. */
9620 +#define SYS_GPE_CLKEN_TMU 0x00000800
9621 +/* No-Operation
9622 +#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */
9623 +/** Set */
9624 +#define SYS_GPE_CLKEN_TMU_SET 0x00000800
9625 +/** Set Clock Enable MRG
9626 +    Sets the clock enable bit of the MRG domain. This domain contains the Merger. */
9627 +#define SYS_GPE_CLKEN_MRG 0x00000400
9628 +/* No-Operation
9629 +#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */
9630 +/** Set */
9631 +#define SYS_GPE_CLKEN_MRG_SET 0x00000400
9632 +/** Set Clock Enable DISP
9633 +    Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
9634 +#define SYS_GPE_CLKEN_DISP 0x00000200
9635 +/* No-Operation
9636 +#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */
9637 +/** Set */
9638 +#define SYS_GPE_CLKEN_DISP_SET 0x00000200
9639 +/** Set Clock Enable IQM
9640 +    Sets the clock enable bit of the IQM domain. This domain contains the IQM. */
9641 +#define SYS_GPE_CLKEN_IQM 0x00000100
9642 +/* No-Operation
9643 +#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */
9644 +/** Set */
9645 +#define SYS_GPE_CLKEN_IQM_SET 0x00000100
9646 +/** Set Clock Enable CPUE
9647 +    Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
9648 +#define SYS_GPE_CLKEN_CPUE 0x00000080
9649 +/* No-Operation
9650 +#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */
9651 +/** Set */
9652 +#define SYS_GPE_CLKEN_CPUE_SET 0x00000080
9653 +/** Set Clock Enable CPUI
9654 +    Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
9655 +#define SYS_GPE_CLKEN_CPUI 0x00000040
9656 +/* No-Operation
9657 +#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */
9658 +/** Set */
9659 +#define SYS_GPE_CLKEN_CPUI_SET 0x00000040
9660 +/** Set Clock Enable GPONE
9661 +    Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
9662 +#define SYS_GPE_CLKEN_GPONE 0x00000020
9663 +/* No-Operation
9664 +#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */
9665 +/** Set */
9666 +#define SYS_GPE_CLKEN_GPONE_SET 0x00000020
9667 +/** Set Clock Enable GPONI
9668 +    Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
9669 +#define SYS_GPE_CLKEN_GPONI 0x00000010
9670 +/* No-Operation
9671 +#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */
9672 +/** Set */
9673 +#define SYS_GPE_CLKEN_GPONI_SET 0x00000010
9674 +/** Set Clock Enable LAN3
9675 +    Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
9676 +#define SYS_GPE_CLKEN_LAN3 0x00000008
9677 +/* No-Operation
9678 +#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */
9679 +/** Set */
9680 +#define SYS_GPE_CLKEN_LAN3_SET 0x00000008
9681 +/** Set Clock Enable LAN2
9682 +    Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
9683 +#define SYS_GPE_CLKEN_LAN2 0x00000004
9684 +/* No-Operation
9685 +#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */
9686 +/** Set */
9687 +#define SYS_GPE_CLKEN_LAN2_SET 0x00000004
9688 +/** Set Clock Enable LAN1
9689 +    Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
9690 +#define SYS_GPE_CLKEN_LAN1 0x00000002
9691 +/* No-Operation
9692 +#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */
9693 +/** Set */
9694 +#define SYS_GPE_CLKEN_LAN1_SET 0x00000002
9695 +/** Set Clock Enable LAN0
9696 +    Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
9697 +#define SYS_GPE_CLKEN_LAN0 0x00000001
9698 +/* No-Operation
9699 +#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */
9700 +/** Set */
9701 +#define SYS_GPE_CLKEN_LAN0_SET 0x00000001
9702 +
9703 +/* Fields of "Clock Clear Register" */
9704 +/** Clear Clock Enable COP7
9705 +    Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9706 +#define SYS_GPE_CLKCLR_COP7 0x80000000
9707 +/* No-Operation
9708 +#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */
9709 +/** Clear */
9710 +#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000
9711 +/** Clear Clock Enable COP6
9712 +    Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9713 +#define SYS_GPE_CLKCLR_COP6 0x40000000
9714 +/* No-Operation
9715 +#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */
9716 +/** Clear */
9717 +#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000
9718 +/** Clear Clock Enable COP5
9719 +    Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9720 +#define SYS_GPE_CLKCLR_COP5 0x20000000
9721 +/* No-Operation
9722 +#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */
9723 +/** Clear */
9724 +#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000
9725 +/** Clear Clock Enable COP4
9726 +    Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9727 +#define SYS_GPE_CLKCLR_COP4 0x10000000
9728 +/* No-Operation
9729 +#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */
9730 +/** Clear */
9731 +#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000
9732 +/** Clear Clock Enable COP3
9733 +    Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9734 +#define SYS_GPE_CLKCLR_COP3 0x08000000
9735 +/* No-Operation
9736 +#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */
9737 +/** Clear */
9738 +#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000
9739 +/** Clear Clock Enable COP2
9740 +    Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9741 +#define SYS_GPE_CLKCLR_COP2 0x04000000
9742 +/* No-Operation
9743 +#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */
9744 +/** Clear */
9745 +#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000
9746 +/** Clear Clock Enable COP1
9747 +    Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9748 +#define SYS_GPE_CLKCLR_COP1 0x02000000
9749 +/* No-Operation
9750 +#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */
9751 +/** Clear */
9752 +#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000
9753 +/** Clear Clock Enable COP0
9754 +    Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9755 +#define SYS_GPE_CLKCLR_COP0 0x01000000
9756 +/* No-Operation
9757 +#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */
9758 +/** Clear */
9759 +#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000
9760 +/** Clear Clock Enable PE5
9761 +    Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9762 +#define SYS_GPE_CLKCLR_PE5 0x00200000
9763 +/* No-Operation
9764 +#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */
9765 +/** Clear */
9766 +#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000
9767 +/** Clear Clock Enable PE4
9768 +    Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9769 +#define SYS_GPE_CLKCLR_PE4 0x00100000
9770 +/* No-Operation
9771 +#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */
9772 +/** Clear */
9773 +#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000
9774 +/** Clear Clock Enable PE3
9775 +    Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9776 +#define SYS_GPE_CLKCLR_PE3 0x00080000
9777 +/* No-Operation
9778 +#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */
9779 +/** Clear */
9780 +#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000
9781 +/** Clear Clock Enable PE2
9782 +    Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9783 +#define SYS_GPE_CLKCLR_PE2 0x00040000
9784 +/* No-Operation
9785 +#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */
9786 +/** Clear */
9787 +#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000
9788 +/** Clear Clock Enable PE1
9789 +    Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9790 +#define SYS_GPE_CLKCLR_PE1 0x00020000
9791 +/* No-Operation
9792 +#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */
9793 +/** Clear */
9794 +#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000
9795 +/** Clear Clock Enable PE0
9796 +    Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9797 +#define SYS_GPE_CLKCLR_PE0 0x00010000
9798 +/* No-Operation
9799 +#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */
9800 +/** Clear */
9801 +#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000
9802 +/** Clear Clock Enable ARB
9803 +    Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */
9804 +#define SYS_GPE_CLKCLR_ARB 0x00002000
9805 +/* No-Operation
9806 +#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */
9807 +/** Clear */
9808 +#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000
9809 +/** Clear Clock Enable FSQM
9810 +    Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */
9811 +#define SYS_GPE_CLKCLR_FSQM 0x00001000
9812 +/* No-Operation
9813 +#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */
9814 +/** Clear */
9815 +#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000
9816 +/** Clear Clock Enable TMU
9817 +    Clears the clock enable bit of the TMU domain. This domain contains the TMU. */
9818 +#define SYS_GPE_CLKCLR_TMU 0x00000800
9819 +/* No-Operation
9820 +#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */
9821 +/** Clear */
9822 +#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800
9823 +/** Clear Clock Enable MRG
9824 +    Clears the clock enable bit of the MRG domain. This domain contains the Merger. */
9825 +#define SYS_GPE_CLKCLR_MRG 0x00000400
9826 +/* No-Operation
9827 +#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */
9828 +/** Clear */
9829 +#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400
9830 +/** Clear Clock Enable DISP
9831 +    Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
9832 +#define SYS_GPE_CLKCLR_DISP 0x00000200
9833 +/* No-Operation
9834 +#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */
9835 +/** Clear */
9836 +#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200
9837 +/** Clear Clock Enable IQM
9838 +    Clears the clock enable bit of the IQM domain. This domain contains the IQM. */
9839 +#define SYS_GPE_CLKCLR_IQM 0x00000100
9840 +/* No-Operation
9841 +#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */
9842 +/** Clear */
9843 +#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100
9844 +/** Clear Clock Enable CPUE
9845 +    Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
9846 +#define SYS_GPE_CLKCLR_CPUE 0x00000080
9847 +/* No-Operation
9848 +#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */
9849 +/** Clear */
9850 +#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080
9851 +/** Clear Clock Enable CPUI
9852 +    Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
9853 +#define SYS_GPE_CLKCLR_CPUI 0x00000040
9854 +/* No-Operation
9855 +#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */
9856 +/** Clear */
9857 +#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040
9858 +/** Clear Clock Enable GPONE
9859 +    Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
9860 +#define SYS_GPE_CLKCLR_GPONE 0x00000020
9861 +/* No-Operation
9862 +#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */
9863 +/** Clear */
9864 +#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020
9865 +/** Clear Clock Enable GPONI
9866 +    Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
9867 +#define SYS_GPE_CLKCLR_GPONI 0x00000010
9868 +/* No-Operation
9869 +#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */
9870 +/** Clear */
9871 +#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010
9872 +/** Clear Clock Enable LAN3
9873 +    Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
9874 +#define SYS_GPE_CLKCLR_LAN3 0x00000008
9875 +/* No-Operation
9876 +#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */
9877 +/** Clear */
9878 +#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008
9879 +/** Clear Clock Enable LAN2
9880 +    Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
9881 +#define SYS_GPE_CLKCLR_LAN2 0x00000004
9882 +/* No-Operation
9883 +#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */
9884 +/** Clear */
9885 +#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004
9886 +/** Clear Clock Enable LAN1
9887 +    Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
9888 +#define SYS_GPE_CLKCLR_LAN1 0x00000002
9889 +/* No-Operation
9890 +#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */
9891 +/** Clear */
9892 +#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002
9893 +/** Clear Clock Enable LAN0
9894 +    Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
9895 +#define SYS_GPE_CLKCLR_LAN0 0x00000001
9896 +/* No-Operation
9897 +#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */
9898 +/** Clear */
9899 +#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001
9900 +
9901 +/* Fields of "Activation Status Register" */
9902 +/** COP7 Status
9903 +    Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9904 +#define SYS_GPE_ACTS_COP7 0x80000000
9905 +/* The block is inactive.
9906 +#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */
9907 +/** The block is active. */
9908 +#define SYS_GPE_ACTS_COP7_ACT 0x80000000
9909 +/** COP6 Status
9910 +    Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9911 +#define SYS_GPE_ACTS_COP6 0x40000000
9912 +/* The block is inactive.
9913 +#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */
9914 +/** The block is active. */
9915 +#define SYS_GPE_ACTS_COP6_ACT 0x40000000
9916 +/** COP5 Status
9917 +    Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9918 +#define SYS_GPE_ACTS_COP5 0x20000000
9919 +/* The block is inactive.
9920 +#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */
9921 +/** The block is active. */
9922 +#define SYS_GPE_ACTS_COP5_ACT 0x20000000
9923 +/** COP4 Status
9924 +    Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9925 +#define SYS_GPE_ACTS_COP4 0x10000000
9926 +/* The block is inactive.
9927 +#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */
9928 +/** The block is active. */
9929 +#define SYS_GPE_ACTS_COP4_ACT 0x10000000
9930 +/** COP3 Status
9931 +    Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9932 +#define SYS_GPE_ACTS_COP3 0x08000000
9933 +/* The block is inactive.
9934 +#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */
9935 +/** The block is active. */
9936 +#define SYS_GPE_ACTS_COP3_ACT 0x08000000
9937 +/** COP2 Status
9938 +    Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9939 +#define SYS_GPE_ACTS_COP2 0x04000000
9940 +/* The block is inactive.
9941 +#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */
9942 +/** The block is active. */
9943 +#define SYS_GPE_ACTS_COP2_ACT 0x04000000
9944 +/** COP1 Status
9945 +    Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9946 +#define SYS_GPE_ACTS_COP1 0x02000000
9947 +/* The block is inactive.
9948 +#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */
9949 +/** The block is active. */
9950 +#define SYS_GPE_ACTS_COP1_ACT 0x02000000
9951 +/** COP0 Status
9952 +    Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9953 +#define SYS_GPE_ACTS_COP0 0x01000000
9954 +/* The block is inactive.
9955 +#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */
9956 +/** The block is active. */
9957 +#define SYS_GPE_ACTS_COP0_ACT 0x01000000
9958 +/** PE5 Status
9959 +    Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9960 +#define SYS_GPE_ACTS_PE5 0x00200000
9961 +/* The block is inactive.
9962 +#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */
9963 +/** The block is active. */
9964 +#define SYS_GPE_ACTS_PE5_ACT 0x00200000
9965 +/** PE4 Status
9966 +    Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9967 +#define SYS_GPE_ACTS_PE4 0x00100000
9968 +/* The block is inactive.
9969 +#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */
9970 +/** The block is active. */
9971 +#define SYS_GPE_ACTS_PE4_ACT 0x00100000
9972 +/** PE3 Status
9973 +    Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9974 +#define SYS_GPE_ACTS_PE3 0x00080000
9975 +/* The block is inactive.
9976 +#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */
9977 +/** The block is active. */
9978 +#define SYS_GPE_ACTS_PE3_ACT 0x00080000
9979 +/** PE2 Status
9980 +    Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9981 +#define SYS_GPE_ACTS_PE2 0x00040000
9982 +/* The block is inactive.
9983 +#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */
9984 +/** The block is active. */
9985 +#define SYS_GPE_ACTS_PE2_ACT 0x00040000
9986 +/** PE1 Status
9987 +    Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9988 +#define SYS_GPE_ACTS_PE1 0x00020000
9989 +/* The block is inactive.
9990 +#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */
9991 +/** The block is active. */
9992 +#define SYS_GPE_ACTS_PE1_ACT 0x00020000
9993 +/** PE0 Status
9994 +    Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9995 +#define SYS_GPE_ACTS_PE0 0x00010000
9996 +/* The block is inactive.
9997 +#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */
9998 +/** The block is active. */
9999 +#define SYS_GPE_ACTS_PE0_ACT 0x00010000
10000 +/** ARB Status
10001 +    Shows the activation status of the ARB domain. This domain contains the Arbiter. */
10002 +#define SYS_GPE_ACTS_ARB 0x00002000
10003 +/* The block is inactive.
10004 +#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */
10005 +/** The block is active. */
10006 +#define SYS_GPE_ACTS_ARB_ACT 0x00002000
10007 +/** FSQM Status
10008 +    Shows the activation status of the FSQM domain. This domain contains the FSQM. */
10009 +#define SYS_GPE_ACTS_FSQM 0x00001000
10010 +/* The block is inactive.
10011 +#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */
10012 +/** The block is active. */
10013 +#define SYS_GPE_ACTS_FSQM_ACT 0x00001000
10014 +/** TMU Status
10015 +    Shows the activation status of the TMU domain. This domain contains the TMU. */
10016 +#define SYS_GPE_ACTS_TMU 0x00000800
10017 +/* The block is inactive.
10018 +#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */
10019 +/** The block is active. */
10020 +#define SYS_GPE_ACTS_TMU_ACT 0x00000800
10021 +/** MRG Status
10022 +    Shows the activation status of the MRG domain. This domain contains the Merger. */
10023 +#define SYS_GPE_ACTS_MRG 0x00000400
10024 +/* The block is inactive.
10025 +#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */
10026 +/** The block is active. */
10027 +#define SYS_GPE_ACTS_MRG_ACT 0x00000400
10028 +/** DISP Status
10029 +    Shows the activation status of the DISP domain. This domain contains the Dispatcher. */
10030 +#define SYS_GPE_ACTS_DISP 0x00000200
10031 +/* The block is inactive.
10032 +#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */
10033 +/** The block is active. */
10034 +#define SYS_GPE_ACTS_DISP_ACT 0x00000200
10035 +/** IQM Status
10036 +    Shows the activation status of the IQM domain. This domain contains the IQM. */
10037 +#define SYS_GPE_ACTS_IQM 0x00000100
10038 +/* The block is inactive.
10039 +#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */
10040 +/** The block is active. */
10041 +#define SYS_GPE_ACTS_IQM_ACT 0x00000100
10042 +/** CPUE Status
10043 +    Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10044 +#define SYS_GPE_ACTS_CPUE 0x00000080
10045 +/* The block is inactive.
10046 +#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */
10047 +/** The block is active. */
10048 +#define SYS_GPE_ACTS_CPUE_ACT 0x00000080
10049 +/** CPUI Status
10050 +    Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10051 +#define SYS_GPE_ACTS_CPUI 0x00000040
10052 +/* The block is inactive.
10053 +#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */
10054 +/** The block is active. */
10055 +#define SYS_GPE_ACTS_CPUI_ACT 0x00000040
10056 +/** GPONE Status
10057 +    Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10058 +#define SYS_GPE_ACTS_GPONE 0x00000020
10059 +/* The block is inactive.
10060 +#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */
10061 +/** The block is active. */
10062 +#define SYS_GPE_ACTS_GPONE_ACT 0x00000020
10063 +/** GPONI Status
10064 +    Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10065 +#define SYS_GPE_ACTS_GPONI 0x00000010
10066 +/* The block is inactive.
10067 +#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */
10068 +/** The block is active. */
10069 +#define SYS_GPE_ACTS_GPONI_ACT 0x00000010
10070 +/** LAN3 Status
10071 +    Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10072 +#define SYS_GPE_ACTS_LAN3 0x00000008
10073 +/* The block is inactive.
10074 +#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */
10075 +/** The block is active. */
10076 +#define SYS_GPE_ACTS_LAN3_ACT 0x00000008
10077 +/** LAN2 Status
10078 +    Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10079 +#define SYS_GPE_ACTS_LAN2 0x00000004
10080 +/* The block is inactive.
10081 +#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */
10082 +/** The block is active. */
10083 +#define SYS_GPE_ACTS_LAN2_ACT 0x00000004
10084 +/** LAN1 Status
10085 +    Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10086 +#define SYS_GPE_ACTS_LAN1 0x00000002
10087 +/* The block is inactive.
10088 +#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */
10089 +/** The block is active. */
10090 +#define SYS_GPE_ACTS_LAN1_ACT 0x00000002
10091 +/** LAN0 Status
10092 +    Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10093 +#define SYS_GPE_ACTS_LAN0 0x00000001
10094 +/* The block is inactive.
10095 +#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */
10096 +/** The block is active. */
10097 +#define SYS_GPE_ACTS_LAN0_ACT 0x00000001
10098 +
10099 +/* Fields of "Activation Register" */
10100 +/** Activate COP7
10101 +    Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10102 +#define SYS_GPE_ACT_COP7 0x80000000
10103 +/* No-Operation
10104 +#define SYS_GPE_ACT_COP7_NOP 0x00000000 */
10105 +/** Set */
10106 +#define SYS_GPE_ACT_COP7_SET 0x80000000
10107 +/** Activate COP6
10108 +    Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10109 +#define SYS_GPE_ACT_COP6 0x40000000
10110 +/* No-Operation
10111 +#define SYS_GPE_ACT_COP6_NOP 0x00000000 */
10112 +/** Set */
10113 +#define SYS_GPE_ACT_COP6_SET 0x40000000
10114 +/** Activate COP5
10115 +    Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10116 +#define SYS_GPE_ACT_COP5 0x20000000
10117 +/* No-Operation
10118 +#define SYS_GPE_ACT_COP5_NOP 0x00000000 */
10119 +/** Set */
10120 +#define SYS_GPE_ACT_COP5_SET 0x20000000
10121 +/** Activate COP4
10122 +    Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10123 +#define SYS_GPE_ACT_COP4 0x10000000
10124 +/* No-Operation
10125 +#define SYS_GPE_ACT_COP4_NOP 0x00000000 */
10126 +/** Set */
10127 +#define SYS_GPE_ACT_COP4_SET 0x10000000
10128 +/** Activate COP3
10129 +    Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10130 +#define SYS_GPE_ACT_COP3 0x08000000
10131 +/* No-Operation
10132 +#define SYS_GPE_ACT_COP3_NOP 0x00000000 */
10133 +/** Set */
10134 +#define SYS_GPE_ACT_COP3_SET 0x08000000
10135 +/** Activate COP2
10136 +    Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10137 +#define SYS_GPE_ACT_COP2 0x04000000
10138 +/* No-Operation
10139 +#define SYS_GPE_ACT_COP2_NOP 0x00000000 */
10140 +/** Set */
10141 +#define SYS_GPE_ACT_COP2_SET 0x04000000
10142 +/** Activate COP1
10143 +    Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10144 +#define SYS_GPE_ACT_COP1 0x02000000
10145 +/* No-Operation
10146 +#define SYS_GPE_ACT_COP1_NOP 0x00000000 */
10147 +/** Set */
10148 +#define SYS_GPE_ACT_COP1_SET 0x02000000
10149 +/** Activate COP0
10150 +    Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10151 +#define SYS_GPE_ACT_COP0 0x01000000
10152 +/* No-Operation
10153 +#define SYS_GPE_ACT_COP0_NOP 0x00000000 */
10154 +/** Set */
10155 +#define SYS_GPE_ACT_COP0_SET 0x01000000
10156 +/** Activate PE5
10157 +    Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10158 +#define SYS_GPE_ACT_PE5 0x00200000
10159 +/* No-Operation
10160 +#define SYS_GPE_ACT_PE5_NOP 0x00000000 */
10161 +/** Set */
10162 +#define SYS_GPE_ACT_PE5_SET 0x00200000
10163 +/** Activate PE4
10164 +    Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10165 +#define SYS_GPE_ACT_PE4 0x00100000
10166 +/* No-Operation
10167 +#define SYS_GPE_ACT_PE4_NOP 0x00000000 */
10168 +/** Set */
10169 +#define SYS_GPE_ACT_PE4_SET 0x00100000
10170 +/** Activate PE3
10171 +    Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10172 +#define SYS_GPE_ACT_PE3 0x00080000
10173 +/* No-Operation
10174 +#define SYS_GPE_ACT_PE3_NOP 0x00000000 */
10175 +/** Set */
10176 +#define SYS_GPE_ACT_PE3_SET 0x00080000
10177 +/** Activate PE2
10178 +    Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10179 +#define SYS_GPE_ACT_PE2 0x00040000
10180 +/* No-Operation
10181 +#define SYS_GPE_ACT_PE2_NOP 0x00000000 */
10182 +/** Set */
10183 +#define SYS_GPE_ACT_PE2_SET 0x00040000
10184 +/** Activate PE1
10185 +    Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10186 +#define SYS_GPE_ACT_PE1 0x00020000
10187 +/* No-Operation
10188 +#define SYS_GPE_ACT_PE1_NOP 0x00000000 */
10189 +/** Set */
10190 +#define SYS_GPE_ACT_PE1_SET 0x00020000
10191 +/** Activate PE0
10192 +    Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10193 +#define SYS_GPE_ACT_PE0 0x00010000
10194 +/* No-Operation
10195 +#define SYS_GPE_ACT_PE0_NOP 0x00000000 */
10196 +/** Set */
10197 +#define SYS_GPE_ACT_PE0_SET 0x00010000
10198 +/** Activate ARB
10199 +    Sets the activation flag of the ARB domain. This domain contains the Arbiter. */
10200 +#define SYS_GPE_ACT_ARB 0x00002000
10201 +/* No-Operation
10202 +#define SYS_GPE_ACT_ARB_NOP 0x00000000 */
10203 +/** Set */
10204 +#define SYS_GPE_ACT_ARB_SET 0x00002000
10205 +/** Activate FSQM
10206 +    Sets the activation flag of the FSQM domain. This domain contains the FSQM. */
10207 +#define SYS_GPE_ACT_FSQM 0x00001000
10208 +/* No-Operation
10209 +#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */
10210 +/** Set */
10211 +#define SYS_GPE_ACT_FSQM_SET 0x00001000
10212 +/** Activate TMU
10213 +    Sets the activation flag of the TMU domain. This domain contains the TMU. */
10214 +#define SYS_GPE_ACT_TMU 0x00000800
10215 +/* No-Operation
10216 +#define SYS_GPE_ACT_TMU_NOP 0x00000000 */
10217 +/** Set */
10218 +#define SYS_GPE_ACT_TMU_SET 0x00000800
10219 +/** Activate MRG
10220 +    Sets the activation flag of the MRG domain. This domain contains the Merger. */
10221 +#define SYS_GPE_ACT_MRG 0x00000400
10222 +/* No-Operation
10223 +#define SYS_GPE_ACT_MRG_NOP 0x00000000 */
10224 +/** Set */
10225 +#define SYS_GPE_ACT_MRG_SET 0x00000400
10226 +/** Activate DISP
10227 +    Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */
10228 +#define SYS_GPE_ACT_DISP 0x00000200
10229 +/* No-Operation
10230 +#define SYS_GPE_ACT_DISP_NOP 0x00000000 */
10231 +/** Set */
10232 +#define SYS_GPE_ACT_DISP_SET 0x00000200
10233 +/** Activate IQM
10234 +    Sets the activation flag of the IQM domain. This domain contains the IQM. */
10235 +#define SYS_GPE_ACT_IQM 0x00000100
10236 +/* No-Operation
10237 +#define SYS_GPE_ACT_IQM_NOP 0x00000000 */
10238 +/** Set */
10239 +#define SYS_GPE_ACT_IQM_SET 0x00000100
10240 +/** Activate CPUE
10241 +    Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10242 +#define SYS_GPE_ACT_CPUE 0x00000080
10243 +/* No-Operation
10244 +#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */
10245 +/** Set */
10246 +#define SYS_GPE_ACT_CPUE_SET 0x00000080
10247 +/** Activate CPUI
10248 +    Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10249 +#define SYS_GPE_ACT_CPUI 0x00000040
10250 +/* No-Operation
10251 +#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */
10252 +/** Set */
10253 +#define SYS_GPE_ACT_CPUI_SET 0x00000040
10254 +/** Activate GPONE
10255 +    Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10256 +#define SYS_GPE_ACT_GPONE 0x00000020
10257 +/* No-Operation
10258 +#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */
10259 +/** Set */
10260 +#define SYS_GPE_ACT_GPONE_SET 0x00000020
10261 +/** Activate GPONI
10262 +    Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10263 +#define SYS_GPE_ACT_GPONI 0x00000010
10264 +/* No-Operation
10265 +#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */
10266 +/** Set */
10267 +#define SYS_GPE_ACT_GPONI_SET 0x00000010
10268 +/** Activate LAN3
10269 +    Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10270 +#define SYS_GPE_ACT_LAN3 0x00000008
10271 +/* No-Operation
10272 +#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */
10273 +/** Set */
10274 +#define SYS_GPE_ACT_LAN3_SET 0x00000008
10275 +/** Activate LAN2
10276 +    Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10277 +#define SYS_GPE_ACT_LAN2 0x00000004
10278 +/* No-Operation
10279 +#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */
10280 +/** Set */
10281 +#define SYS_GPE_ACT_LAN2_SET 0x00000004
10282 +/** Activate LAN1
10283 +    Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10284 +#define SYS_GPE_ACT_LAN1 0x00000002
10285 +/* No-Operation
10286 +#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */
10287 +/** Set */
10288 +#define SYS_GPE_ACT_LAN1_SET 0x00000002
10289 +/** Activate LAN0
10290 +    Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10291 +#define SYS_GPE_ACT_LAN0 0x00000001
10292 +/* No-Operation
10293 +#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */
10294 +/** Set */
10295 +#define SYS_GPE_ACT_LAN0_SET 0x00000001
10296 +
10297 +/* Fields of "Deactivation Register" */
10298 +/** Deactivate COP7
10299 +    Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10300 +#define SYS_GPE_DEACT_COP7 0x80000000
10301 +/* No-Operation
10302 +#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */
10303 +/** Clear */
10304 +#define SYS_GPE_DEACT_COP7_CLR 0x80000000
10305 +/** Deactivate COP6
10306 +    Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10307 +#define SYS_GPE_DEACT_COP6 0x40000000
10308 +/* No-Operation
10309 +#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */
10310 +/** Clear */
10311 +#define SYS_GPE_DEACT_COP6_CLR 0x40000000
10312 +/** Deactivate COP5
10313 +    Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10314 +#define SYS_GPE_DEACT_COP5 0x20000000
10315 +/* No-Operation
10316 +#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */
10317 +/** Clear */
10318 +#define SYS_GPE_DEACT_COP5_CLR 0x20000000
10319 +/** Deactivate COP4
10320 +    Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10321 +#define SYS_GPE_DEACT_COP4 0x10000000
10322 +/* No-Operation
10323 +#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */
10324 +/** Clear */
10325 +#define SYS_GPE_DEACT_COP4_CLR 0x10000000
10326 +/** Deactivate COP3
10327 +    Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10328 +#define SYS_GPE_DEACT_COP3 0x08000000
10329 +/* No-Operation
10330 +#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */
10331 +/** Clear */
10332 +#define SYS_GPE_DEACT_COP3_CLR 0x08000000
10333 +/** Deactivate COP2
10334 +    Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10335 +#define SYS_GPE_DEACT_COP2 0x04000000
10336 +/* No-Operation
10337 +#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */
10338 +/** Clear */
10339 +#define SYS_GPE_DEACT_COP2_CLR 0x04000000
10340 +/** Deactivate COP1
10341 +    Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10342 +#define SYS_GPE_DEACT_COP1 0x02000000
10343 +/* No-Operation
10344 +#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */
10345 +/** Clear */
10346 +#define SYS_GPE_DEACT_COP1_CLR 0x02000000
10347 +/** Deactivate COP0
10348 +    Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10349 +#define SYS_GPE_DEACT_COP0 0x01000000
10350 +/* No-Operation
10351 +#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */
10352 +/** Clear */
10353 +#define SYS_GPE_DEACT_COP0_CLR 0x01000000
10354 +/** Deactivate PE5
10355 +    Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10356 +#define SYS_GPE_DEACT_PE5 0x00200000
10357 +/* No-Operation
10358 +#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */
10359 +/** Clear */
10360 +#define SYS_GPE_DEACT_PE5_CLR 0x00200000
10361 +/** Deactivate PE4
10362 +    Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10363 +#define SYS_GPE_DEACT_PE4 0x00100000
10364 +/* No-Operation
10365 +#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */
10366 +/** Clear */
10367 +#define SYS_GPE_DEACT_PE4_CLR 0x00100000
10368 +/** Deactivate PE3
10369 +    Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10370 +#define SYS_GPE_DEACT_PE3 0x00080000
10371 +/* No-Operation
10372 +#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */
10373 +/** Clear */
10374 +#define SYS_GPE_DEACT_PE3_CLR 0x00080000
10375 +/** Deactivate PE2
10376 +    Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10377 +#define SYS_GPE_DEACT_PE2 0x00040000
10378 +/* No-Operation
10379 +#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */
10380 +/** Clear */
10381 +#define SYS_GPE_DEACT_PE2_CLR 0x00040000
10382 +/** Deactivate PE1
10383 +    Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10384 +#define SYS_GPE_DEACT_PE1 0x00020000
10385 +/* No-Operation
10386 +#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */
10387 +/** Clear */
10388 +#define SYS_GPE_DEACT_PE1_CLR 0x00020000
10389 +/** Deactivate PE0
10390 +    Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10391 +#define SYS_GPE_DEACT_PE0 0x00010000
10392 +/* No-Operation
10393 +#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */
10394 +/** Clear */
10395 +#define SYS_GPE_DEACT_PE0_CLR 0x00010000
10396 +/** Deactivate ARB
10397 +    Clears the activation flag of the ARB domain. This domain contains the Arbiter. */
10398 +#define SYS_GPE_DEACT_ARB 0x00002000
10399 +/* No-Operation
10400 +#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */
10401 +/** Clear */
10402 +#define SYS_GPE_DEACT_ARB_CLR 0x00002000
10403 +/** Deactivate FSQM
10404 +    Clears the activation flag of the FSQM domain. This domain contains the FSQM. */
10405 +#define SYS_GPE_DEACT_FSQM 0x00001000
10406 +/* No-Operation
10407 +#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */
10408 +/** Clear */
10409 +#define SYS_GPE_DEACT_FSQM_CLR 0x00001000
10410 +/** Deactivate TMU
10411 +    Clears the activation flag of the TMU domain. This domain contains the TMU. */
10412 +#define SYS_GPE_DEACT_TMU 0x00000800
10413 +/* No-Operation
10414 +#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */
10415 +/** Clear */
10416 +#define SYS_GPE_DEACT_TMU_CLR 0x00000800
10417 +/** Deactivate MRG
10418 +    Clears the activation flag of the MRG domain. This domain contains the Merger. */
10419 +#define SYS_GPE_DEACT_MRG 0x00000400
10420 +/* No-Operation
10421 +#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */
10422 +/** Clear */
10423 +#define SYS_GPE_DEACT_MRG_CLR 0x00000400
10424 +/** Deactivate DISP
10425 +    Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */
10426 +#define SYS_GPE_DEACT_DISP 0x00000200
10427 +/* No-Operation
10428 +#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */
10429 +/** Clear */
10430 +#define SYS_GPE_DEACT_DISP_CLR 0x00000200
10431 +/** Deactivate IQM
10432 +    Clears the activation flag of the IQM domain. This domain contains the IQM. */
10433 +#define SYS_GPE_DEACT_IQM 0x00000100
10434 +/* No-Operation
10435 +#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */
10436 +/** Clear */
10437 +#define SYS_GPE_DEACT_IQM_CLR 0x00000100
10438 +/** Deactivate CPUE
10439 +    Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10440 +#define SYS_GPE_DEACT_CPUE 0x00000080
10441 +/* No-Operation
10442 +#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */
10443 +/** Clear */
10444 +#define SYS_GPE_DEACT_CPUE_CLR 0x00000080
10445 +/** Deactivate CPUI
10446 +    Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10447 +#define SYS_GPE_DEACT_CPUI 0x00000040
10448 +/* No-Operation
10449 +#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */
10450 +/** Clear */
10451 +#define SYS_GPE_DEACT_CPUI_CLR 0x00000040
10452 +/** Deactivate GPONE
10453 +    Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10454 +#define SYS_GPE_DEACT_GPONE 0x00000020
10455 +/* No-Operation
10456 +#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */
10457 +/** Clear */
10458 +#define SYS_GPE_DEACT_GPONE_CLR 0x00000020
10459 +/** Deactivate GPONI
10460 +    Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10461 +#define SYS_GPE_DEACT_GPONI 0x00000010
10462 +/* No-Operation
10463 +#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */
10464 +/** Clear */
10465 +#define SYS_GPE_DEACT_GPONI_CLR 0x00000010
10466 +/** Deactivate LAN3
10467 +    Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10468 +#define SYS_GPE_DEACT_LAN3 0x00000008
10469 +/* No-Operation
10470 +#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */
10471 +/** Clear */
10472 +#define SYS_GPE_DEACT_LAN3_CLR 0x00000008
10473 +/** Deactivate LAN2
10474 +    Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10475 +#define SYS_GPE_DEACT_LAN2 0x00000004
10476 +/* No-Operation
10477 +#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */
10478 +/** Clear */
10479 +#define SYS_GPE_DEACT_LAN2_CLR 0x00000004
10480 +/** Deactivate LAN1
10481 +    Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10482 +#define SYS_GPE_DEACT_LAN1 0x00000002
10483 +/* No-Operation
10484 +#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */
10485 +/** Clear */
10486 +#define SYS_GPE_DEACT_LAN1_CLR 0x00000002
10487 +/** Deactivate LAN0
10488 +    Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10489 +#define SYS_GPE_DEACT_LAN0 0x00000001
10490 +/* No-Operation
10491 +#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */
10492 +/** Clear */
10493 +#define SYS_GPE_DEACT_LAN0_CLR 0x00000001
10494 +
10495 +/* Fields of "Reboot Trigger Register" */
10496 +/** Reboot COP7
10497 +    Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10498 +#define SYS_GPE_RBT_COP7 0x80000000
10499 +/* No-Operation
10500 +#define SYS_GPE_RBT_COP7_NOP 0x00000000 */
10501 +/** Trigger */
10502 +#define SYS_GPE_RBT_COP7_TRIG 0x80000000
10503 +/** Reboot COP6
10504 +    Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10505 +#define SYS_GPE_RBT_COP6 0x40000000
10506 +/* No-Operation
10507 +#define SYS_GPE_RBT_COP6_NOP 0x00000000 */
10508 +/** Trigger */
10509 +#define SYS_GPE_RBT_COP6_TRIG 0x40000000
10510 +/** Reboot COP5
10511 +    Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10512 +#define SYS_GPE_RBT_COP5 0x20000000
10513 +/* No-Operation
10514 +#define SYS_GPE_RBT_COP5_NOP 0x00000000 */
10515 +/** Trigger */
10516 +#define SYS_GPE_RBT_COP5_TRIG 0x20000000
10517 +/** Reboot COP4
10518 +    Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10519 +#define SYS_GPE_RBT_COP4 0x10000000
10520 +/* No-Operation
10521 +#define SYS_GPE_RBT_COP4_NOP 0x00000000 */
10522 +/** Trigger */
10523 +#define SYS_GPE_RBT_COP4_TRIG 0x10000000
10524 +/** Reboot COP3
10525 +    Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10526 +#define SYS_GPE_RBT_COP3 0x08000000
10527 +/* No-Operation
10528 +#define SYS_GPE_RBT_COP3_NOP 0x00000000 */
10529 +/** Trigger */
10530 +#define SYS_GPE_RBT_COP3_TRIG 0x08000000
10531 +/** Reboot COP2
10532 +    Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10533 +#define SYS_GPE_RBT_COP2 0x04000000
10534 +/* No-Operation
10535 +#define SYS_GPE_RBT_COP2_NOP 0x00000000 */
10536 +/** Trigger */
10537 +#define SYS_GPE_RBT_COP2_TRIG 0x04000000
10538 +/** Reboot COP1
10539 +    Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10540 +#define SYS_GPE_RBT_COP1 0x02000000
10541 +/* No-Operation
10542 +#define SYS_GPE_RBT_COP1_NOP 0x00000000 */
10543 +/** Trigger */
10544 +#define SYS_GPE_RBT_COP1_TRIG 0x02000000
10545 +/** Reboot COP0
10546 +    Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10547 +#define SYS_GPE_RBT_COP0 0x01000000
10548 +/* No-Operation
10549 +#define SYS_GPE_RBT_COP0_NOP 0x00000000 */
10550 +/** Trigger */
10551 +#define SYS_GPE_RBT_COP0_TRIG 0x01000000
10552 +/** Reboot PE5
10553 +    Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10554 +#define SYS_GPE_RBT_PE5 0x00200000
10555 +/* No-Operation
10556 +#define SYS_GPE_RBT_PE5_NOP 0x00000000 */
10557 +/** Trigger */
10558 +#define SYS_GPE_RBT_PE5_TRIG 0x00200000
10559 +/** Reboot PE4
10560 +    Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10561 +#define SYS_GPE_RBT_PE4 0x00100000
10562 +/* No-Operation
10563 +#define SYS_GPE_RBT_PE4_NOP 0x00000000 */
10564 +/** Trigger */
10565 +#define SYS_GPE_RBT_PE4_TRIG 0x00100000
10566 +/** Reboot PE3
10567 +    Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10568 +#define SYS_GPE_RBT_PE3 0x00080000
10569 +/* No-Operation
10570 +#define SYS_GPE_RBT_PE3_NOP 0x00000000 */
10571 +/** Trigger */
10572 +#define SYS_GPE_RBT_PE3_TRIG 0x00080000
10573 +/** Reboot PE2
10574 +    Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10575 +#define SYS_GPE_RBT_PE2 0x00040000
10576 +/* No-Operation
10577 +#define SYS_GPE_RBT_PE2_NOP 0x00000000 */
10578 +/** Trigger */
10579 +#define SYS_GPE_RBT_PE2_TRIG 0x00040000
10580 +/** Reboot PE1
10581 +    Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10582 +#define SYS_GPE_RBT_PE1 0x00020000
10583 +/* No-Operation
10584 +#define SYS_GPE_RBT_PE1_NOP 0x00000000 */
10585 +/** Trigger */
10586 +#define SYS_GPE_RBT_PE1_TRIG 0x00020000
10587 +/** Reboot PE0
10588 +    Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10589 +#define SYS_GPE_RBT_PE0 0x00010000
10590 +/* No-Operation
10591 +#define SYS_GPE_RBT_PE0_NOP 0x00000000 */
10592 +/** Trigger */
10593 +#define SYS_GPE_RBT_PE0_TRIG 0x00010000
10594 +/** Reboot ARB
10595 +    Triggers a reboot of the ARB domain. This domain contains the Arbiter. */
10596 +#define SYS_GPE_RBT_ARB 0x00002000
10597 +/* No-Operation
10598 +#define SYS_GPE_RBT_ARB_NOP 0x00000000 */
10599 +/** Trigger */
10600 +#define SYS_GPE_RBT_ARB_TRIG 0x00002000
10601 +/** Reboot FSQM
10602 +    Triggers a reboot of the FSQM domain. This domain contains the FSQM. */
10603 +#define SYS_GPE_RBT_FSQM 0x00001000
10604 +/* No-Operation
10605 +#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */
10606 +/** Trigger */
10607 +#define SYS_GPE_RBT_FSQM_TRIG 0x00001000
10608 +/** Reboot TMU
10609 +    Triggers a reboot of the TMU domain. This domain contains the TMU. */
10610 +#define SYS_GPE_RBT_TMU 0x00000800
10611 +/* No-Operation
10612 +#define SYS_GPE_RBT_TMU_NOP 0x00000000 */
10613 +/** Trigger */
10614 +#define SYS_GPE_RBT_TMU_TRIG 0x00000800
10615 +/** Reboot MRG
10616 +    Triggers a reboot of the MRG domain. This domain contains the Merger. */
10617 +#define SYS_GPE_RBT_MRG 0x00000400
10618 +/* No-Operation
10619 +#define SYS_GPE_RBT_MRG_NOP 0x00000000 */
10620 +/** Trigger */
10621 +#define SYS_GPE_RBT_MRG_TRIG 0x00000400
10622 +/** Reboot DISP
10623 +    Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */
10624 +#define SYS_GPE_RBT_DISP 0x00000200
10625 +/* No-Operation
10626 +#define SYS_GPE_RBT_DISP_NOP 0x00000000 */
10627 +/** Trigger */
10628 +#define SYS_GPE_RBT_DISP_TRIG 0x00000200
10629 +/** Reboot IQM
10630 +    Triggers a reboot of the IQM domain. This domain contains the IQM. */
10631 +#define SYS_GPE_RBT_IQM 0x00000100
10632 +/* No-Operation
10633 +#define SYS_GPE_RBT_IQM_NOP 0x00000000 */
10634 +/** Trigger */
10635 +#define SYS_GPE_RBT_IQM_TRIG 0x00000100
10636 +/** Reboot CPUE
10637 +    Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10638 +#define SYS_GPE_RBT_CPUE 0x00000080
10639 +/* No-Operation
10640 +#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */
10641 +/** Trigger */
10642 +#define SYS_GPE_RBT_CPUE_TRIG 0x00000080
10643 +/** Reboot CPUI
10644 +    Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10645 +#define SYS_GPE_RBT_CPUI 0x00000040
10646 +/* No-Operation
10647 +#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */
10648 +/** Trigger */
10649 +#define SYS_GPE_RBT_CPUI_TRIG 0x00000040
10650 +/** Reboot GPONE
10651 +    Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10652 +#define SYS_GPE_RBT_GPONE 0x00000020
10653 +/* No-Operation
10654 +#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */
10655 +/** Trigger */
10656 +#define SYS_GPE_RBT_GPONE_TRIG 0x00000020
10657 +/** Reboot GPONI
10658 +    Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10659 +#define SYS_GPE_RBT_GPONI 0x00000010
10660 +/* No-Operation
10661 +#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */
10662 +/** Trigger */
10663 +#define SYS_GPE_RBT_GPONI_TRIG 0x00000010
10664 +/** Reboot LAN3
10665 +    Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10666 +#define SYS_GPE_RBT_LAN3 0x00000008
10667 +/* No-Operation
10668 +#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */
10669 +/** Trigger */
10670 +#define SYS_GPE_RBT_LAN3_TRIG 0x00000008
10671 +/** Reboot LAN2
10672 +    Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10673 +#define SYS_GPE_RBT_LAN2 0x00000004
10674 +/* No-Operation
10675 +#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */
10676 +/** Trigger */
10677 +#define SYS_GPE_RBT_LAN2_TRIG 0x00000004
10678 +/** Reboot LAN1
10679 +    Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10680 +#define SYS_GPE_RBT_LAN1 0x00000002
10681 +/* No-Operation
10682 +#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */
10683 +/** Trigger */
10684 +#define SYS_GPE_RBT_LAN1_TRIG 0x00000002
10685 +/** Reboot LAN0
10686 +    Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10687 +#define SYS_GPE_RBT_LAN0 0x00000001
10688 +/* No-Operation
10689 +#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */
10690 +/** Trigger */
10691 +#define SYS_GPE_RBT_LAN0_TRIG 0x00000001
10692 +
10693 +/* Fields of "Power Down Configuration Register" */
10694 +/** Enable Power Down COP7
10695 +    Ignore this bit as power-gating is not supported for this chip. */
10696 +#define SYS_GPE_PDCFG_COP7 0x80000000
10697 +/* Disable
10698 +#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */
10699 +/** Enable */
10700 +#define SYS_GPE_PDCFG_COP7_EN 0x80000000
10701 +/** Enable Power Down COP6
10702 +    Ignore this bit as power-gating is not supported for this chip. */
10703 +#define SYS_GPE_PDCFG_COP6 0x40000000
10704 +/* Disable
10705 +#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */
10706 +/** Enable */
10707 +#define SYS_GPE_PDCFG_COP6_EN 0x40000000
10708 +/** Enable Power Down COP5
10709 +    Ignore this bit as power-gating is not supported for this chip. */
10710 +#define SYS_GPE_PDCFG_COP5 0x20000000
10711 +/* Disable
10712 +#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */
10713 +/** Enable */
10714 +#define SYS_GPE_PDCFG_COP5_EN 0x20000000
10715 +/** Enable Power Down COP4
10716 +    Ignore this bit as power-gating is not supported for this chip. */
10717 +#define SYS_GPE_PDCFG_COP4 0x10000000
10718 +/* Disable
10719 +#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */
10720 +/** Enable */
10721 +#define SYS_GPE_PDCFG_COP4_EN 0x10000000
10722 +/** Enable Power Down COP3
10723 +    Ignore this bit as power-gating is not supported for this chip. */
10724 +#define SYS_GPE_PDCFG_COP3 0x08000000
10725 +/* Disable
10726 +#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */
10727 +/** Enable */
10728 +#define SYS_GPE_PDCFG_COP3_EN 0x08000000
10729 +/** Enable Power Down COP2
10730 +    Ignore this bit as power-gating is not supported for this chip. */
10731 +#define SYS_GPE_PDCFG_COP2 0x04000000
10732 +/* Disable
10733 +#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */
10734 +/** Enable */
10735 +#define SYS_GPE_PDCFG_COP2_EN 0x04000000
10736 +/** Enable Power Down COP1
10737 +    Ignore this bit as power-gating is not supported for this chip. */
10738 +#define SYS_GPE_PDCFG_COP1 0x02000000
10739 +/* Disable
10740 +#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */
10741 +/** Enable */
10742 +#define SYS_GPE_PDCFG_COP1_EN 0x02000000
10743 +/** Enable Power Down COP0
10744 +    Ignore this bit as power-gating is not supported for this chip. */
10745 +#define SYS_GPE_PDCFG_COP0 0x01000000
10746 +/* Disable
10747 +#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */
10748 +/** Enable */
10749 +#define SYS_GPE_PDCFG_COP0_EN 0x01000000
10750 +/** Enable Power Down PE5
10751 +    Ignore this bit as power-gating is not supported for this chip. */
10752 +#define SYS_GPE_PDCFG_PE5 0x00200000
10753 +/* Disable
10754 +#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */
10755 +/** Enable */
10756 +#define SYS_GPE_PDCFG_PE5_EN 0x00200000
10757 +/** Enable Power Down PE4
10758 +    Ignore this bit as power-gating is not supported for this chip. */
10759 +#define SYS_GPE_PDCFG_PE4 0x00100000
10760 +/* Disable
10761 +#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */
10762 +/** Enable */
10763 +#define SYS_GPE_PDCFG_PE4_EN 0x00100000
10764 +/** Enable Power Down PE3
10765 +    Ignore this bit as power-gating is not supported for this chip. */
10766 +#define SYS_GPE_PDCFG_PE3 0x00080000
10767 +/* Disable
10768 +#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */
10769 +/** Enable */
10770 +#define SYS_GPE_PDCFG_PE3_EN 0x00080000
10771 +/** Enable Power Down PE2
10772 +    Ignore this bit as power-gating is not supported for this chip. */
10773 +#define SYS_GPE_PDCFG_PE2 0x00040000
10774 +/* Disable
10775 +#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */
10776 +/** Enable */
10777 +#define SYS_GPE_PDCFG_PE2_EN 0x00040000
10778 +/** Enable Power Down PE1
10779 +    Ignore this bit as power-gating is not supported for this chip. */
10780 +#define SYS_GPE_PDCFG_PE1 0x00020000
10781 +/* Disable
10782 +#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */
10783 +/** Enable */
10784 +#define SYS_GPE_PDCFG_PE1_EN 0x00020000
10785 +/** Enable Power Down PE0
10786 +    Ignore this bit as power-gating is not supported for this chip. */
10787 +#define SYS_GPE_PDCFG_PE0 0x00010000
10788 +/* Disable
10789 +#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */
10790 +/** Enable */
10791 +#define SYS_GPE_PDCFG_PE0_EN 0x00010000
10792 +/** Enable Power Down ARB
10793 +    Ignore this bit as power-gating is not supported for this chip. */
10794 +#define SYS_GPE_PDCFG_ARB 0x00002000
10795 +/* Disable
10796 +#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */
10797 +/** Enable */
10798 +#define SYS_GPE_PDCFG_ARB_EN 0x00002000
10799 +/** Enable Power Down FSQM
10800 +    Ignore this bit as power-gating is not supported for this chip. */
10801 +#define SYS_GPE_PDCFG_FSQM 0x00001000
10802 +/* Disable
10803 +#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */
10804 +/** Enable */
10805 +#define SYS_GPE_PDCFG_FSQM_EN 0x00001000
10806 +/** Enable Power Down TMU
10807 +    Ignore this bit as power-gating is not supported for this chip. */
10808 +#define SYS_GPE_PDCFG_TMU 0x00000800
10809 +/* Disable
10810 +#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */
10811 +/** Enable */
10812 +#define SYS_GPE_PDCFG_TMU_EN 0x00000800
10813 +/** Enable Power Down MRG
10814 +    Ignore this bit as power-gating is not supported for this chip. */
10815 +#define SYS_GPE_PDCFG_MRG 0x00000400
10816 +/* Disable
10817 +#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */
10818 +/** Enable */
10819 +#define SYS_GPE_PDCFG_MRG_EN 0x00000400
10820 +/** Enable Power Down DISP
10821 +    Ignore this bit as power-gating is not supported for this chip. */
10822 +#define SYS_GPE_PDCFG_DISP 0x00000200
10823 +/* Disable
10824 +#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */
10825 +/** Enable */
10826 +#define SYS_GPE_PDCFG_DISP_EN 0x00000200
10827 +/** Enable Power Down IQM
10828 +    Ignore this bit as power-gating is not supported for this chip. */
10829 +#define SYS_GPE_PDCFG_IQM 0x00000100
10830 +/* Disable
10831 +#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */
10832 +/** Enable */
10833 +#define SYS_GPE_PDCFG_IQM_EN 0x00000100
10834 +/** Enable Power Down CPUE
10835 +    Ignore this bit as power-gating is not supported for this chip. */
10836 +#define SYS_GPE_PDCFG_CPUE 0x00000080
10837 +/* Disable
10838 +#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */
10839 +/** Enable */
10840 +#define SYS_GPE_PDCFG_CPUE_EN 0x00000080
10841 +/** Enable Power Down CPUI
10842 +    Ignore this bit as power-gating is not supported for this chip. */
10843 +#define SYS_GPE_PDCFG_CPUI 0x00000040
10844 +/* Disable
10845 +#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */
10846 +/** Enable */
10847 +#define SYS_GPE_PDCFG_CPUI_EN 0x00000040
10848 +/** Enable Power Down GPONE
10849 +    Ignore this bit as power-gating is not supported for this chip. */
10850 +#define SYS_GPE_PDCFG_GPONE 0x00000020
10851 +/* Disable
10852 +#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */
10853 +/** Enable */
10854 +#define SYS_GPE_PDCFG_GPONE_EN 0x00000020
10855 +/** Enable Power Down GPONI
10856 +    Ignore this bit as power-gating is not supported for this chip. */
10857 +#define SYS_GPE_PDCFG_GPONI 0x00000010
10858 +/* Disable
10859 +#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */
10860 +/** Enable */
10861 +#define SYS_GPE_PDCFG_GPONI_EN 0x00000010
10862 +/** Enable Power Down LAN3
10863 +    Ignore this bit as power-gating is not supported for this chip. */
10864 +#define SYS_GPE_PDCFG_LAN3 0x00000008
10865 +/* Disable
10866 +#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */
10867 +/** Enable */
10868 +#define SYS_GPE_PDCFG_LAN3_EN 0x00000008
10869 +/** Enable Power Down LAN2
10870 +    Ignore this bit as power-gating is not supported for this chip. */
10871 +#define SYS_GPE_PDCFG_LAN2 0x00000004
10872 +/* Disable
10873 +#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */
10874 +/** Enable */
10875 +#define SYS_GPE_PDCFG_LAN2_EN 0x00000004
10876 +/** Enable Power Down LAN1
10877 +    Ignore this bit as power-gating is not supported for this chip. */
10878 +#define SYS_GPE_PDCFG_LAN1 0x00000002
10879 +/* Disable
10880 +#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */
10881 +/** Enable */
10882 +#define SYS_GPE_PDCFG_LAN1_EN 0x00000002
10883 +/** Enable Power Down LAN0
10884 +    Ignore this bit as power-gating is not supported for this chip. */
10885 +#define SYS_GPE_PDCFG_LAN0 0x00000001
10886 +/* Disable
10887 +#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */
10888 +/** Enable */
10889 +#define SYS_GPE_PDCFG_LAN0_EN 0x00000001
10890 +
10891 +/* Fields of "Sleep Source Configuration Register" */
10892 +/** Sleep/Wakeup Source CPU
10893 +    Selects the CPU access signal as sleep/wakeup source. */
10894 +#define SYS_GPE_SSCFG_CPU 0x00020000
10895 +/* Not selected
10896 +#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */
10897 +/** Selected */
10898 +#define SYS_GPE_SSCFG_CPU_SEL 0x00020000
10899 +/** Sleep/Wakeup Source FSQM
10900 +    Selects the FSQM signal as sleep/wakeup source. */
10901 +#define SYS_GPE_SSCFG_FSQM 0x00008000
10902 +/* Not selected
10903 +#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */
10904 +/** Selected */
10905 +#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000
10906 +/** Sleep/Wakeup Source GPONT
10907 +    Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */
10908 +#define SYS_GPE_SSCFG_GPONT 0x00002000
10909 +/* Not selected
10910 +#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */
10911 +/** Selected */
10912 +#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000
10913 +/** Sleep/Wakeup Source GPONE
10914 +    Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */
10915 +#define SYS_GPE_SSCFG_GPONE 0x00001000
10916 +/* Not selected
10917 +#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */
10918 +/** Selected */
10919 +#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000
10920 +/** Sleep/Wakeup Source LAN3E
10921 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */
10922 +#define SYS_GPE_SSCFG_LAN3E 0x00000800
10923 +/* Not selected
10924 +#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */
10925 +/** Selected */
10926 +#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800
10927 +/** Sleep/Wakeup Source LAN2E
10928 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */
10929 +#define SYS_GPE_SSCFG_LAN2E 0x00000400
10930 +/* Not selected
10931 +#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */
10932 +/** Selected */
10933 +#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400
10934 +/** Sleep/Wakeup Source LAN1E
10935 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */
10936 +#define SYS_GPE_SSCFG_LAN1E 0x00000200
10937 +/* Not selected
10938 +#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */
10939 +/** Selected */
10940 +#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200
10941 +/** Sleep/Wakeup Source LAN0E
10942 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */
10943 +#define SYS_GPE_SSCFG_LAN0E 0x00000100
10944 +/* Not selected
10945 +#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */
10946 +/** Selected */
10947 +#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100
10948 +/** Sleep/Wakeup Source GPONI
10949 +    Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */
10950 +#define SYS_GPE_SSCFG_GPONI 0x00000010
10951 +/* Not selected
10952 +#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */
10953 +/** Selected */
10954 +#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010
10955 +/** Sleep/Wakeup Source LAN3I
10956 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */
10957 +#define SYS_GPE_SSCFG_LAN3I 0x00000008
10958 +/* Not selected
10959 +#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */
10960 +/** Selected */
10961 +#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008
10962 +/** Sleep/Wakeup Source LAN2I
10963 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */
10964 +#define SYS_GPE_SSCFG_LAN2I 0x00000004
10965 +/* Not selected
10966 +#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */
10967 +/** Selected */
10968 +#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004
10969 +/** Sleep/Wakeup Source LAN1I
10970 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */
10971 +#define SYS_GPE_SSCFG_LAN1I 0x00000002
10972 +/* Not selected
10973 +#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */
10974 +/** Selected */
10975 +#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002
10976 +/** Sleep/Wakeup Source LAN0I
10977 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */
10978 +#define SYS_GPE_SSCFG_LAN0I 0x00000001
10979 +/* Not selected
10980 +#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */
10981 +/** Selected */
10982 +#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001
10983 +
10984 +/* Fields of "Sleep Source Timer Register" */
10985 +/** Sleep Delay Value
10986 +    A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */
10987 +#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF
10988 +/** field offset */
10989 +#define SYS_GPE_SST_SDV_OFFSET 0
10990 +
10991 +/* Fields of "Sleep Destination Status Register" */
10992 +/** Shutoff COP7 on HW Sleep
10993 +    If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */
10994 +#define SYS_GPE_SDS_COP7 0x80000000
10995 +/* Not selected
10996 +#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */
10997 +/** Selected */
10998 +#define SYS_GPE_SDS_COP7_SEL 0x80000000
10999 +/** Shutoff COP6 on HW Sleep
11000 +    If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */
11001 +#define SYS_GPE_SDS_COP6 0x40000000
11002 +/* Not selected
11003 +#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */
11004 +/** Selected */
11005 +#define SYS_GPE_SDS_COP6_SEL 0x40000000
11006 +/** Shutoff COP5 on HW Sleep
11007 +    If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */
11008 +#define SYS_GPE_SDS_COP5 0x20000000
11009 +/* Not selected
11010 +#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */
11011 +/** Selected */
11012 +#define SYS_GPE_SDS_COP5_SEL 0x20000000
11013 +/** Shutoff COP4 on HW Sleep
11014 +    If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */
11015 +#define SYS_GPE_SDS_COP4 0x10000000
11016 +/* Not selected
11017 +#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */
11018 +/** Selected */
11019 +#define SYS_GPE_SDS_COP4_SEL 0x10000000
11020 +/** Shutoff COP3 on HW Sleep
11021 +    If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */
11022 +#define SYS_GPE_SDS_COP3 0x08000000
11023 +/* Not selected
11024 +#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */
11025 +/** Selected */
11026 +#define SYS_GPE_SDS_COP3_SEL 0x08000000
11027 +/** Shutoff COP2 on HW Sleep
11028 +    If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */
11029 +#define SYS_GPE_SDS_COP2 0x04000000
11030 +/* Not selected
11031 +#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */
11032 +/** Selected */
11033 +#define SYS_GPE_SDS_COP2_SEL 0x04000000
11034 +/** Shutoff COP1 on HW Sleep
11035 +    If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */
11036 +#define SYS_GPE_SDS_COP1 0x02000000
11037 +/* Not selected
11038 +#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */
11039 +/** Selected */
11040 +#define SYS_GPE_SDS_COP1_SEL 0x02000000
11041 +/** Shutoff COP0 on HW Sleep
11042 +    If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */
11043 +#define SYS_GPE_SDS_COP0 0x01000000
11044 +/* Not selected
11045 +#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */
11046 +/** Selected */
11047 +#define SYS_GPE_SDS_COP0_SEL 0x01000000
11048 +/** Shutoff PE5 on HW Sleep
11049 +    If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */
11050 +#define SYS_GPE_SDS_PE5 0x00200000
11051 +/* Not selected
11052 +#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */
11053 +/** Selected */
11054 +#define SYS_GPE_SDS_PE5_SEL 0x00200000
11055 +/** Shutoff PE4 on HW Sleep
11056 +    If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */
11057 +#define SYS_GPE_SDS_PE4 0x00100000
11058 +/* Not selected
11059 +#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */
11060 +/** Selected */
11061 +#define SYS_GPE_SDS_PE4_SEL 0x00100000
11062 +/** Shutoff PE3 on HW Sleep
11063 +    If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */
11064 +#define SYS_GPE_SDS_PE3 0x00080000
11065 +/* Not selected
11066 +#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */
11067 +/** Selected */
11068 +#define SYS_GPE_SDS_PE3_SEL 0x00080000
11069 +/** Shutoff PE2 on HW Sleep
11070 +    If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */
11071 +#define SYS_GPE_SDS_PE2 0x00040000
11072 +/* Not selected
11073 +#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */
11074 +/** Selected */
11075 +#define SYS_GPE_SDS_PE2_SEL 0x00040000
11076 +/** Shutoff PE1 on HW Sleep
11077 +    If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */
11078 +#define SYS_GPE_SDS_PE1 0x00020000
11079 +/* Not selected
11080 +#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */
11081 +/** Selected */
11082 +#define SYS_GPE_SDS_PE1_SEL 0x00020000
11083 +/** Shutoff PE0 on HW Sleep
11084 +    If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */
11085 +#define SYS_GPE_SDS_PE0 0x00010000
11086 +/* Not selected
11087 +#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */
11088 +/** Selected */
11089 +#define SYS_GPE_SDS_PE0_SEL 0x00010000
11090 +/** Shutoff ARB on HW Sleep
11091 +    If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */
11092 +#define SYS_GPE_SDS_ARB 0x00002000
11093 +/* Not selected
11094 +#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */
11095 +/** Selected */
11096 +#define SYS_GPE_SDS_ARB_SEL 0x00002000
11097 +/** Shutoff FSQM on HW Sleep
11098 +    If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */
11099 +#define SYS_GPE_SDS_FSQM 0x00001000
11100 +/* Not selected
11101 +#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */
11102 +/** Selected */
11103 +#define SYS_GPE_SDS_FSQM_SEL 0x00001000
11104 +/** Shutoff TMU on HW Sleep
11105 +    If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */
11106 +#define SYS_GPE_SDS_TMU 0x00000800
11107 +/* Not selected
11108 +#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */
11109 +/** Selected */
11110 +#define SYS_GPE_SDS_TMU_SEL 0x00000800
11111 +/** Shutoff MRG on HW Sleep
11112 +    If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */
11113 +#define SYS_GPE_SDS_MRG 0x00000400
11114 +/* Not selected
11115 +#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */
11116 +/** Selected */
11117 +#define SYS_GPE_SDS_MRG_SEL 0x00000400
11118 +/** Shutoff DISP on HW Sleep
11119 +    If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */
11120 +#define SYS_GPE_SDS_DISP 0x00000200
11121 +/* Not selected
11122 +#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */
11123 +/** Selected */
11124 +#define SYS_GPE_SDS_DISP_SEL 0x00000200
11125 +/** Shutoff IQM on HW Sleep
11126 +    If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */
11127 +#define SYS_GPE_SDS_IQM 0x00000100
11128 +/* Not selected
11129 +#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */
11130 +/** Selected */
11131 +#define SYS_GPE_SDS_IQM_SEL 0x00000100
11132 +/** Shutoff CPUE on HW Sleep
11133 +    If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */
11134 +#define SYS_GPE_SDS_CPUE 0x00000080
11135 +/* Not selected
11136 +#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */
11137 +/** Selected */
11138 +#define SYS_GPE_SDS_CPUE_SEL 0x00000080
11139 +/** Shutoff CPUI on HW Sleep
11140 +    If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */
11141 +#define SYS_GPE_SDS_CPUI 0x00000040
11142 +/* Not selected
11143 +#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */
11144 +/** Selected */
11145 +#define SYS_GPE_SDS_CPUI_SEL 0x00000040
11146 +/** Shutoff GPONE on HW Sleep
11147 +    If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
11148 +#define SYS_GPE_SDS_GPONE 0x00000020
11149 +/* Not selected
11150 +#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */
11151 +/** Selected */
11152 +#define SYS_GPE_SDS_GPONE_SEL 0x00000020
11153 +/** Shutoff GPONI on HW Sleep
11154 +    If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
11155 +#define SYS_GPE_SDS_GPONI 0x00000010
11156 +/* Not selected
11157 +#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */
11158 +/** Selected */
11159 +#define SYS_GPE_SDS_GPONI_SEL 0x00000010
11160 +/** Shutoff LAN3 on HW Sleep
11161 +    If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */
11162 +#define SYS_GPE_SDS_LAN3 0x00000008
11163 +/* Not selected
11164 +#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */
11165 +/** Selected */
11166 +#define SYS_GPE_SDS_LAN3_SEL 0x00000008
11167 +/** Shutoff LAN2 on HW Sleep
11168 +    If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */
11169 +#define SYS_GPE_SDS_LAN2 0x00000004
11170 +/* Not selected
11171 +#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */
11172 +/** Selected */
11173 +#define SYS_GPE_SDS_LAN2_SEL 0x00000004
11174 +/** Shutoff LAN1 on HW Sleep
11175 +    If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */
11176 +#define SYS_GPE_SDS_LAN1 0x00000002
11177 +/* Not selected
11178 +#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */
11179 +/** Selected */
11180 +#define SYS_GPE_SDS_LAN1_SEL 0x00000002
11181 +/** Shutoff LAN0 on HW Sleep
11182 +    If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */
11183 +#define SYS_GPE_SDS_LAN0 0x00000001
11184 +/* Not selected
11185 +#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */
11186 +/** Selected */
11187 +#define SYS_GPE_SDS_LAN0_SEL 0x00000001
11188 +
11189 +/* Fields of "Sleep Destination Set Register" */
11190 +/** Set Sleep Selection COP7
11191 +    Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
11192 +#define SYS_GPE_SDSET_COP7 0x80000000
11193 +/* No-Operation
11194 +#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */
11195 +/** Set */
11196 +#define SYS_GPE_SDSET_COP7_SET 0x80000000
11197 +/** Set Sleep Selection COP6
11198 +    Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
11199 +#define SYS_GPE_SDSET_COP6 0x40000000
11200 +/* No-Operation
11201 +#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */
11202 +/** Set */
11203 +#define SYS_GPE_SDSET_COP6_SET 0x40000000
11204 +/** Set Sleep Selection COP5
11205 +    Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
11206 +#define SYS_GPE_SDSET_COP5 0x20000000
11207 +/* No-Operation
11208 +#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */
11209 +/** Set */
11210 +#define SYS_GPE_SDSET_COP5_SET 0x20000000
11211 +/** Set Sleep Selection COP4
11212 +    Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
11213 +#define SYS_GPE_SDSET_COP4 0x10000000
11214 +/* No-Operation
11215 +#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */
11216 +/** Set */
11217 +#define SYS_GPE_SDSET_COP4_SET 0x10000000
11218 +/** Set Sleep Selection COP3
11219 +    Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
11220 +#define SYS_GPE_SDSET_COP3 0x08000000
11221 +/* No-Operation
11222 +#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */
11223 +/** Set */
11224 +#define SYS_GPE_SDSET_COP3_SET 0x08000000
11225 +/** Set Sleep Selection COP2
11226 +    Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
11227 +#define SYS_GPE_SDSET_COP2 0x04000000
11228 +/* No-Operation
11229 +#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */
11230 +/** Set */
11231 +#define SYS_GPE_SDSET_COP2_SET 0x04000000
11232 +/** Set Sleep Selection COP1
11233 +    Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
11234 +#define SYS_GPE_SDSET_COP1 0x02000000
11235 +/* No-Operation
11236 +#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */
11237 +/** Set */
11238 +#define SYS_GPE_SDSET_COP1_SET 0x02000000
11239 +/** Set Sleep Selection COP0
11240 +    Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
11241 +#define SYS_GPE_SDSET_COP0 0x01000000
11242 +/* No-Operation
11243 +#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */
11244 +/** Set */
11245 +#define SYS_GPE_SDSET_COP0_SET 0x01000000
11246 +/** Set Sleep Selection PE5
11247 +    Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
11248 +#define SYS_GPE_SDSET_PE5 0x00200000
11249 +/* No-Operation
11250 +#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */
11251 +/** Set */
11252 +#define SYS_GPE_SDSET_PE5_SET 0x00200000
11253 +/** Set Sleep Selection PE4
11254 +    Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
11255 +#define SYS_GPE_SDSET_PE4 0x00100000
11256 +/* No-Operation
11257 +#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */
11258 +/** Set */
11259 +#define SYS_GPE_SDSET_PE4_SET 0x00100000
11260 +/** Set Sleep Selection PE3
11261 +    Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
11262 +#define SYS_GPE_SDSET_PE3 0x00080000
11263 +/* No-Operation
11264 +#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */
11265 +/** Set */
11266 +#define SYS_GPE_SDSET_PE3_SET 0x00080000
11267 +/** Set Sleep Selection PE2
11268 +    Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
11269 +#define SYS_GPE_SDSET_PE2 0x00040000
11270 +/* No-Operation
11271 +#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */
11272 +/** Set */
11273 +#define SYS_GPE_SDSET_PE2_SET 0x00040000
11274 +/** Set Sleep Selection PE1
11275 +    Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
11276 +#define SYS_GPE_SDSET_PE1 0x00020000
11277 +/* No-Operation
11278 +#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */
11279 +/** Set */
11280 +#define SYS_GPE_SDSET_PE1_SET 0x00020000
11281 +/** Set Sleep Selection PE0
11282 +    Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
11283 +#define SYS_GPE_SDSET_PE0 0x00010000
11284 +/* No-Operation
11285 +#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */
11286 +/** Set */
11287 +#define SYS_GPE_SDSET_PE0_SET 0x00010000
11288 +/** Set Sleep Selection ARB
11289 +    Sets the selection bit for domain ARBThis domain contains the Arbiter. */
11290 +#define SYS_GPE_SDSET_ARB 0x00002000
11291 +/* No-Operation
11292 +#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */
11293 +/** Set */
11294 +#define SYS_GPE_SDSET_ARB_SET 0x00002000
11295 +/** Set Sleep Selection FSQM
11296 +    Sets the selection bit for domain FSQMThis domain contains the FSQM. */
11297 +#define SYS_GPE_SDSET_FSQM 0x00001000
11298 +/* No-Operation
11299 +#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */
11300 +/** Set */
11301 +#define SYS_GPE_SDSET_FSQM_SET 0x00001000
11302 +/** Set Sleep Selection TMU
11303 +    Sets the selection bit for domain TMUThis domain contains the TMU. */
11304 +#define SYS_GPE_SDSET_TMU 0x00000800
11305 +/* No-Operation
11306 +#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */
11307 +/** Set */
11308 +#define SYS_GPE_SDSET_TMU_SET 0x00000800
11309 +/** Set Sleep Selection MRG
11310 +    Sets the selection bit for domain MRGThis domain contains the Merger. */
11311 +#define SYS_GPE_SDSET_MRG 0x00000400
11312 +/* No-Operation
11313 +#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */
11314 +/** Set */
11315 +#define SYS_GPE_SDSET_MRG_SET 0x00000400
11316 +/** Set Sleep Selection DISP
11317 +    Sets the selection bit for domain DISPThis domain contains the Dispatcher. */
11318 +#define SYS_GPE_SDSET_DISP 0x00000200
11319 +/* No-Operation
11320 +#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */
11321 +/** Set */
11322 +#define SYS_GPE_SDSET_DISP_SET 0x00000200
11323 +/** Set Sleep Selection IQM
11324 +    Sets the selection bit for domain IQMThis domain contains the IQM. */
11325 +#define SYS_GPE_SDSET_IQM 0x00000100
11326 +/* No-Operation
11327 +#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */
11328 +/** Set */
11329 +#define SYS_GPE_SDSET_IQM_SET 0x00000100
11330 +/** Set Sleep Selection CPUE
11331 +    Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
11332 +#define SYS_GPE_SDSET_CPUE 0x00000080
11333 +/* No-Operation
11334 +#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */
11335 +/** Set */
11336 +#define SYS_GPE_SDSET_CPUE_SET 0x00000080
11337 +/** Set Sleep Selection CPUI
11338 +    Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
11339 +#define SYS_GPE_SDSET_CPUI 0x00000040
11340 +/* No-Operation
11341 +#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */
11342 +/** Set */
11343 +#define SYS_GPE_SDSET_CPUI_SET 0x00000040
11344 +/** Set Sleep Selection GPONE
11345 +    Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
11346 +#define SYS_GPE_SDSET_GPONE 0x00000020
11347 +/* No-Operation
11348 +#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */
11349 +/** Set */
11350 +#define SYS_GPE_SDSET_GPONE_SET 0x00000020
11351 +/** Set Sleep Selection GPONI
11352 +    Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
11353 +#define SYS_GPE_SDSET_GPONI 0x00000010
11354 +/* No-Operation
11355 +#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */
11356 +/** Set */
11357 +#define SYS_GPE_SDSET_GPONI_SET 0x00000010
11358 +/** Set Sleep Selection LAN3
11359 +    Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
11360 +#define SYS_GPE_SDSET_LAN3 0x00000008
11361 +/* No-Operation
11362 +#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */
11363 +/** Set */
11364 +#define SYS_GPE_SDSET_LAN3_SET 0x00000008
11365 +/** Set Sleep Selection LAN2
11366 +    Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
11367 +#define SYS_GPE_SDSET_LAN2 0x00000004
11368 +/* No-Operation
11369 +#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */
11370 +/** Set */
11371 +#define SYS_GPE_SDSET_LAN2_SET 0x00000004
11372 +/** Set Sleep Selection LAN1
11373 +    Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
11374 +#define SYS_GPE_SDSET_LAN1 0x00000002
11375 +/* No-Operation
11376 +#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */
11377 +/** Set */
11378 +#define SYS_GPE_SDSET_LAN1_SET 0x00000002
11379 +/** Set Sleep Selection LAN0
11380 +    Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
11381 +#define SYS_GPE_SDSET_LAN0 0x00000001
11382 +/* No-Operation
11383 +#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */
11384 +/** Set */
11385 +#define SYS_GPE_SDSET_LAN0_SET 0x00000001
11386 +
11387 +/* Fields of "Sleep Destination Clear Register" */
11388 +/** Clear Sleep Selection COP7
11389 +    Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
11390 +#define SYS_GPE_SDCLR_COP7 0x80000000
11391 +/* No-Operation
11392 +#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */
11393 +/** Clear */
11394 +#define SYS_GPE_SDCLR_COP7_CLR 0x80000000
11395 +/** Clear Sleep Selection COP6
11396 +    Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
11397 +#define SYS_GPE_SDCLR_COP6 0x40000000
11398 +/* No-Operation
11399 +#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */
11400 +/** Clear */
11401 +#define SYS_GPE_SDCLR_COP6_CLR 0x40000000
11402 +/** Clear Sleep Selection COP5
11403 +    Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
11404 +#define SYS_GPE_SDCLR_COP5 0x20000000
11405 +/* No-Operation
11406 +#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */
11407 +/** Clear */
11408 +#define SYS_GPE_SDCLR_COP5_CLR 0x20000000
11409 +/** Clear Sleep Selection COP4
11410 +    Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
11411 +#define SYS_GPE_SDCLR_COP4 0x10000000
11412 +/* No-Operation
11413 +#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */
11414 +/** Clear */
11415 +#define SYS_GPE_SDCLR_COP4_CLR 0x10000000
11416 +/** Clear Sleep Selection COP3
11417 +    Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
11418 +#define SYS_GPE_SDCLR_COP3 0x08000000
11419 +/* No-Operation
11420 +#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */
11421 +/** Clear */
11422 +#define SYS_GPE_SDCLR_COP3_CLR 0x08000000
11423 +/** Clear Sleep Selection COP2
11424 +    Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
11425 +#define SYS_GPE_SDCLR_COP2 0x04000000
11426 +/* No-Operation
11427 +#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */
11428 +/** Clear */
11429 +#define SYS_GPE_SDCLR_COP2_CLR 0x04000000
11430 +/** Clear Sleep Selection COP1
11431 +    Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
11432 +#define SYS_GPE_SDCLR_COP1 0x02000000
11433 +/* No-Operation
11434 +#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */
11435 +/** Clear */
11436 +#define SYS_GPE_SDCLR_COP1_CLR 0x02000000
11437 +/** Clear Sleep Selection COP0
11438 +    Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
11439 +#define SYS_GPE_SDCLR_COP0 0x01000000
11440 +/* No-Operation
11441 +#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */
11442 +/** Clear */
11443 +#define SYS_GPE_SDCLR_COP0_CLR 0x01000000
11444 +/** Clear Sleep Selection PE5
11445 +    Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
11446 +#define SYS_GPE_SDCLR_PE5 0x00200000
11447 +/* No-Operation
11448 +#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */
11449 +/** Clear */
11450 +#define SYS_GPE_SDCLR_PE5_CLR 0x00200000
11451 +/** Clear Sleep Selection PE4
11452 +    Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
11453 +#define SYS_GPE_SDCLR_PE4 0x00100000
11454 +/* No-Operation
11455 +#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */
11456 +/** Clear */
11457 +#define SYS_GPE_SDCLR_PE4_CLR 0x00100000
11458 +/** Clear Sleep Selection PE3
11459 +    Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
11460 +#define SYS_GPE_SDCLR_PE3 0x00080000
11461 +/* No-Operation
11462 +#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */
11463 +/** Clear */
11464 +#define SYS_GPE_SDCLR_PE3_CLR 0x00080000
11465 +/** Clear Sleep Selection PE2
11466 +    Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
11467 +#define SYS_GPE_SDCLR_PE2 0x00040000
11468 +/* No-Operation
11469 +#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */
11470 +/** Clear */
11471 +#define SYS_GPE_SDCLR_PE2_CLR 0x00040000
11472 +/** Clear Sleep Selection PE1
11473 +    Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
11474 +#define SYS_GPE_SDCLR_PE1 0x00020000
11475 +/* No-Operation
11476 +#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */
11477 +/** Clear */
11478 +#define SYS_GPE_SDCLR_PE1_CLR 0x00020000
11479 +/** Clear Sleep Selection PE0
11480 +    Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
11481 +#define SYS_GPE_SDCLR_PE0 0x00010000
11482 +/* No-Operation
11483 +#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */
11484 +/** Clear */
11485 +#define SYS_GPE_SDCLR_PE0_CLR 0x00010000
11486 +/** Clear Sleep Selection ARB
11487 +    Clears the selection bit for domain ARBThis domain contains the Arbiter. */
11488 +#define SYS_GPE_SDCLR_ARB 0x00002000
11489 +/* No-Operation
11490 +#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */
11491 +/** Clear */
11492 +#define SYS_GPE_SDCLR_ARB_CLR 0x00002000
11493 +/** Clear Sleep Selection FSQM
11494 +    Clears the selection bit for domain FSQMThis domain contains the FSQM. */
11495 +#define SYS_GPE_SDCLR_FSQM 0x00001000
11496 +/* No-Operation
11497 +#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */
11498 +/** Clear */
11499 +#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000
11500 +/** Clear Sleep Selection TMU
11501 +    Clears the selection bit for domain TMUThis domain contains the TMU. */
11502 +#define SYS_GPE_SDCLR_TMU 0x00000800
11503 +/* No-Operation
11504 +#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */
11505 +/** Clear */
11506 +#define SYS_GPE_SDCLR_TMU_CLR 0x00000800
11507 +/** Clear Sleep Selection MRG
11508 +    Clears the selection bit for domain MRGThis domain contains the Merger. */
11509 +#define SYS_GPE_SDCLR_MRG 0x00000400
11510 +/* No-Operation
11511 +#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */
11512 +/** Clear */
11513 +#define SYS_GPE_SDCLR_MRG_CLR 0x00000400
11514 +/** Clear Sleep Selection DISP
11515 +    Clears the selection bit for domain DISPThis domain contains the Dispatcher. */
11516 +#define SYS_GPE_SDCLR_DISP 0x00000200
11517 +/* No-Operation
11518 +#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */
11519 +/** Clear */
11520 +#define SYS_GPE_SDCLR_DISP_CLR 0x00000200
11521 +/** Clear Sleep Selection IQM
11522 +    Clears the selection bit for domain IQMThis domain contains the IQM. */
11523 +#define SYS_GPE_SDCLR_IQM 0x00000100
11524 +/* No-Operation
11525 +#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */
11526 +/** Clear */
11527 +#define SYS_GPE_SDCLR_IQM_CLR 0x00000100
11528 +/** Clear Sleep Selection CPUE
11529 +    Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
11530 +#define SYS_GPE_SDCLR_CPUE 0x00000080
11531 +/* No-Operation
11532 +#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */
11533 +/** Clear */
11534 +#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080
11535 +/** Clear Sleep Selection CPUI
11536 +    Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
11537 +#define SYS_GPE_SDCLR_CPUI 0x00000040
11538 +/* No-Operation
11539 +#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */
11540 +/** Clear */
11541 +#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040
11542 +/** Clear Sleep Selection GPONE
11543 +    Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
11544 +#define SYS_GPE_SDCLR_GPONE 0x00000020
11545 +/* No-Operation
11546 +#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */
11547 +/** Clear */
11548 +#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020
11549 +/** Clear Sleep Selection GPONI
11550 +    Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
11551 +#define SYS_GPE_SDCLR_GPONI 0x00000010
11552 +/* No-Operation
11553 +#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */
11554 +/** Clear */
11555 +#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010
11556 +/** Clear Sleep Selection LAN3
11557 +    Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
11558 +#define SYS_GPE_SDCLR_LAN3 0x00000008
11559 +/* No-Operation
11560 +#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */
11561 +/** Clear */
11562 +#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008
11563 +/** Clear Sleep Selection LAN2
11564 +    Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
11565 +#define SYS_GPE_SDCLR_LAN2 0x00000004
11566 +/* No-Operation
11567 +#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */
11568 +/** Clear */
11569 +#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004
11570 +/** Clear Sleep Selection LAN1
11571 +    Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
11572 +#define SYS_GPE_SDCLR_LAN1 0x00000002
11573 +/* No-Operation
11574 +#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */
11575 +/** Clear */
11576 +#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002
11577 +/** Clear Sleep Selection LAN0
11578 +    Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
11579 +#define SYS_GPE_SDCLR_LAN0 0x00000001
11580 +/* No-Operation
11581 +#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */
11582 +/** Clear */
11583 +#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001
11584 +
11585 +/* Fields of "IRNCS Capture Register" */
11586 +/** FSQM wakeup request
11587 +    The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11588 +#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000
11589 +/* Nothing
11590 +#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */
11591 +/** Write: Acknowledge the interrupt. */
11592 +#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000
11593 +/** Read: Interrupt occurred. */
11594 +#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000
11595 +/** GPONT wakeup request
11596 +    The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11597 +#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000
11598 +/* Nothing
11599 +#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */
11600 +/** Write: Acknowledge the interrupt. */
11601 +#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000
11602 +/** Read: Interrupt occurred. */
11603 +#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000
11604 +/** GPONE wakeup request
11605 +    The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11606 +#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000
11607 +/* Nothing
11608 +#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */
11609 +/** Write: Acknowledge the interrupt. */
11610 +#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000
11611 +/** Read: Interrupt occurred. */
11612 +#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000
11613 +/** LAN3E wakeup request
11614 +    The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11615 +#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000
11616 +/* Nothing
11617 +#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */
11618 +/** Write: Acknowledge the interrupt. */
11619 +#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000
11620 +/** Read: Interrupt occurred. */
11621 +#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000
11622 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
11623 +    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11624 +#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000
11625 +/* Nothing
11626 +#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */
11627 +/** Write: Acknowledge the interrupt. */
11628 +#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000
11629 +/** Read: Interrupt occurred. */
11630 +#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000
11631 +/** LAN1E wakeup request
11632 +    The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11633 +#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000
11634 +/* Nothing
11635 +#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */
11636 +/** Write: Acknowledge the interrupt. */
11637 +#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000
11638 +/** Read: Interrupt occurred. */
11639 +#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000
11640 +/** LAN0E wakeup request
11641 +    The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11642 +#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000
11643 +/* Nothing
11644 +#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */
11645 +/** Write: Acknowledge the interrupt. */
11646 +#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000
11647 +/** Read: Interrupt occurred. */
11648 +#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000
11649 +/** GPONI wakeup request
11650 +    The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11651 +#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000
11652 +/* Nothing
11653 +#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */
11654 +/** Write: Acknowledge the interrupt. */
11655 +#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000
11656 +/** Read: Interrupt occurred. */
11657 +#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000
11658 +/** LAN3I wakeup request
11659 +    The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11660 +#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000
11661 +/* Nothing
11662 +#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */
11663 +/** Write: Acknowledge the interrupt. */
11664 +#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000
11665 +/** Read: Interrupt occurred. */
11666 +#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000
11667 +/** LAN2I wakeup request
11668 +    The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11669 +#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000
11670 +/* Nothing
11671 +#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */
11672 +/** Write: Acknowledge the interrupt. */
11673 +#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000
11674 +/** Read: Interrupt occurred. */
11675 +#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000
11676 +/** LAN1I wakeup request
11677 +    The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11678 +#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000
11679 +/* Nothing
11680 +#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */
11681 +/** Write: Acknowledge the interrupt. */
11682 +#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000
11683 +/** Read: Interrupt occurred. */
11684 +#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000
11685 +/** LAN0I wakeup request
11686 +    The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11687 +#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000
11688 +/* Nothing
11689 +#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */
11690 +/** Write: Acknowledge the interrupt. */
11691 +#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000
11692 +/** Read: Interrupt occurred. */
11693 +#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000
11694 +/** FSQM sleep request
11695 +    The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11696 +#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000
11697 +/* Nothing
11698 +#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */
11699 +/** Write: Acknowledge the interrupt. */
11700 +#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000
11701 +/** Read: Interrupt occurred. */
11702 +#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000
11703 +/** GPONT sleep request
11704 +    The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11705 +#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000
11706 +/* Nothing
11707 +#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */
11708 +/** Write: Acknowledge the interrupt. */
11709 +#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000
11710 +/** Read: Interrupt occurred. */
11711 +#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000
11712 +/** GPONE sleep request
11713 +    The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11714 +#define SYS_GPE_IRNCSCR_GPONESR 0x00001000
11715 +/* Nothing
11716 +#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */
11717 +/** Write: Acknowledge the interrupt. */
11718 +#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000
11719 +/** Read: Interrupt occurred. */
11720 +#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000
11721 +/** LAN3E sleep request
11722 +    The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11723 +#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800
11724 +/* Nothing
11725 +#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */
11726 +/** Write: Acknowledge the interrupt. */
11727 +#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800
11728 +/** Read: Interrupt occurred. */
11729 +#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800
11730 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
11731 +    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11732 +#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400
11733 +/* Nothing
11734 +#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */
11735 +/** Write: Acknowledge the interrupt. */
11736 +#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400
11737 +/** Read: Interrupt occurred. */
11738 +#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400
11739 +/** LAN1E sleep request
11740 +    The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11741 +#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200
11742 +/* Nothing
11743 +#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */
11744 +/** Write: Acknowledge the interrupt. */
11745 +#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200
11746 +/** Read: Interrupt occurred. */
11747 +#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200
11748 +/** LAN0E sleep request
11749 +    The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11750 +#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100
11751 +/* Nothing
11752 +#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */
11753 +/** Write: Acknowledge the interrupt. */
11754 +#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100
11755 +/** Read: Interrupt occurred. */
11756 +#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100
11757 +/** GPONI sleep request
11758 +    The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11759 +#define SYS_GPE_IRNCSCR_GPONISR 0x00000010
11760 +/* Nothing
11761 +#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */
11762 +/** Write: Acknowledge the interrupt. */
11763 +#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010
11764 +/** Read: Interrupt occurred. */
11765 +#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010
11766 +/** LAN3I sleep request
11767 +    The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11768 +#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008
11769 +/* Nothing
11770 +#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */
11771 +/** Write: Acknowledge the interrupt. */
11772 +#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008
11773 +/** Read: Interrupt occurred. */
11774 +#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008
11775 +/** LAN2I sleep request
11776 +    The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11777 +#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004
11778 +/* Nothing
11779 +#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */
11780 +/** Write: Acknowledge the interrupt. */
11781 +#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004
11782 +/** Read: Interrupt occurred. */
11783 +#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004
11784 +/** LAN1I sleep request
11785 +    The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11786 +#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002
11787 +/* Nothing
11788 +#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */
11789 +/** Write: Acknowledge the interrupt. */
11790 +#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002
11791 +/** Read: Interrupt occurred. */
11792 +#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002
11793 +/** LAN0I sleep request
11794 +    The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11795 +#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001
11796 +/* Nothing
11797 +#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */
11798 +/** Write: Acknowledge the interrupt. */
11799 +#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001
11800 +/** Read: Interrupt occurred. */
11801 +#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001
11802 +
11803 +/* Fields of "IRNCS Interrupt Control Register" */
11804 +/** FSQM wakeup request
11805 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11806 +#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000
11807 +/** GPONT wakeup request
11808 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11809 +#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000
11810 +/** GPONE wakeup request
11811 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11812 +#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000
11813 +/** LAN3E wakeup request
11814 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11815 +#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000
11816 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
11817 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11818 +#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000
11819 +/** LAN1E wakeup request
11820 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11821 +#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000
11822 +/** LAN0E wakeup request
11823 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11824 +#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000
11825 +/** GPONI wakeup request
11826 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11827 +#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000
11828 +/** LAN3I wakeup request
11829 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11830 +#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000
11831 +/** LAN2I wakeup request
11832 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11833 +#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000
11834 +/** LAN1I wakeup request
11835 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11836 +#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000
11837 +/** LAN0I wakeup request
11838 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11839 +#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000
11840 +/** FSQM sleep request
11841 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11842 +#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000
11843 +/** GPONT sleep request
11844 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11845 +#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000
11846 +/** GPONE sleep request
11847 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11848 +#define SYS_GPE_IRNCSICR_GPONESR 0x00001000
11849 +/** LAN3E sleep request
11850 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11851 +#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800
11852 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
11853 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11854 +#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400
11855 +/** LAN1E sleep request
11856 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11857 +#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200
11858 +/** LAN0E sleep request
11859 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11860 +#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100
11861 +/** GPONI sleep request
11862 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11863 +#define SYS_GPE_IRNCSICR_GPONISR 0x00000010
11864 +/** LAN3I sleep request
11865 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11866 +#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008
11867 +/** LAN2I sleep request
11868 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11869 +#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004
11870 +/** LAN1I sleep request
11871 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11872 +#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002
11873 +/** LAN0I sleep request
11874 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
11875 +#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001
11876 +
11877 +/* Fields of "IRNCS Interrupt Enable Register" */
11878 +/** FSQM wakeup request
11879 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11880 +#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000
11881 +/* Disable
11882 +#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */
11883 +/** Enable */
11884 +#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000
11885 +/** GPONT wakeup request
11886 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11887 +#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000
11888 +/* Disable
11889 +#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */
11890 +/** Enable */
11891 +#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000
11892 +/** GPONE wakeup request
11893 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11894 +#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000
11895 +/* Disable
11896 +#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */
11897 +/** Enable */
11898 +#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000
11899 +/** LAN3E wakeup request
11900 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11901 +#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000
11902 +/* Disable
11903 +#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */
11904 +/** Enable */
11905 +#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000
11906 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
11907 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11908 +#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000
11909 +/* Disable
11910 +#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */
11911 +/** Enable */
11912 +#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000
11913 +/** LAN1E wakeup request
11914 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11915 +#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000
11916 +/* Disable
11917 +#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */
11918 +/** Enable */
11919 +#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000
11920 +/** LAN0E wakeup request
11921 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11922 +#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000
11923 +/* Disable
11924 +#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */
11925 +/** Enable */
11926 +#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000
11927 +/** GPONI wakeup request
11928 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11929 +#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000
11930 +/* Disable
11931 +#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */
11932 +/** Enable */
11933 +#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000
11934 +/** LAN3I wakeup request
11935 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11936 +#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000
11937 +/* Disable
11938 +#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */
11939 +/** Enable */
11940 +#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000
11941 +/** LAN2I wakeup request
11942 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11943 +#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000
11944 +/* Disable
11945 +#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */
11946 +/** Enable */
11947 +#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000
11948 +/** LAN1I wakeup request
11949 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11950 +#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000
11951 +/* Disable
11952 +#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */
11953 +/** Enable */
11954 +#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000
11955 +/** LAN0I wakeup request
11956 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11957 +#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000
11958 +/* Disable
11959 +#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */
11960 +/** Enable */
11961 +#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000
11962 +/** FSQM sleep request
11963 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11964 +#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000
11965 +/* Disable
11966 +#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */
11967 +/** Enable */
11968 +#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000
11969 +/** GPONT sleep request
11970 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11971 +#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000
11972 +/* Disable
11973 +#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */
11974 +/** Enable */
11975 +#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000
11976 +/** GPONE sleep request
11977 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11978 +#define SYS_GPE_IRNCSEN_GPONESR 0x00001000
11979 +/* Disable
11980 +#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */
11981 +/** Enable */
11982 +#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000
11983 +/** LAN3E sleep request
11984 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11985 +#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800
11986 +/* Disable
11987 +#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */
11988 +/** Enable */
11989 +#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800
11990 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
11991 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11992 +#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400
11993 +/* Disable
11994 +#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */
11995 +/** Enable */
11996 +#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400
11997 +/** LAN1E sleep request
11998 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
11999 +#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200
12000 +/* Disable
12001 +#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */
12002 +/** Enable */
12003 +#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200
12004 +/** LAN0E sleep request
12005 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12006 +#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100
12007 +/* Disable
12008 +#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */
12009 +/** Enable */
12010 +#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100
12011 +/** GPONI sleep request
12012 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12013 +#define SYS_GPE_IRNCSEN_GPONISR 0x00000010
12014 +/* Disable
12015 +#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */
12016 +/** Enable */
12017 +#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010
12018 +/** LAN3I sleep request
12019 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12020 +#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008
12021 +/* Disable
12022 +#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */
12023 +/** Enable */
12024 +#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008
12025 +/** LAN2I sleep request
12026 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12027 +#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004
12028 +/* Disable
12029 +#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */
12030 +/** Enable */
12031 +#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004
12032 +/** LAN1I sleep request
12033 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12034 +#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002
12035 +/* Disable
12036 +#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */
12037 +/** Enable */
12038 +#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002
12039 +/** LAN0I sleep request
12040 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12041 +#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001
12042 +/* Disable
12043 +#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */
12044 +/** Enable */
12045 +#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001
12046 +
12047 +/*! @} */ /* SYS_GPE_REGISTER */
12048 +
12049 +#endif /* _sys_gpe_reg_h */
12050 --- /dev/null
12051 +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
12052 @@ -0,0 +1,58 @@
12053 +/*
12054 + *  Lantiq FALCON specific CPU feature overrides
12055 + *
12056 + *  Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
12057 + *
12058 + *  This file was derived from: include/asm-mips/cpu-features.h
12059 + *     Copyright (C) 2003, 2004 Ralf Baechle
12060 + *     Copyright (C) 2004 Maciej W. Rozycki
12061 + *
12062 + *  This program is free software; you can redistribute it and/or modify it
12063 + *  under the terms of the GNU General Public License version 2 as published
12064 + *  by the Free Software Foundation.
12065 + *
12066 + */
12067 +#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
12068 +#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
12069 +
12070 +#define cpu_has_tlb            1
12071 +#define cpu_has_4kex           1
12072 +#define cpu_has_3k_cache       0
12073 +#define cpu_has_4k_cache       1
12074 +#define cpu_has_tx39_cache     0
12075 +#define cpu_has_sb1_cache      0
12076 +#define cpu_has_fpu            0
12077 +#define cpu_has_32fpr          0
12078 +#define cpu_has_counter                1
12079 +#define cpu_has_watch          1
12080 +#define cpu_has_divec          1
12081 +
12082 +#define cpu_has_prefetch       1
12083 +#define cpu_has_ejtag          1
12084 +#define cpu_has_llsc           1
12085 +
12086 +#define cpu_has_mips16         1
12087 +#define cpu_has_mdmx           0
12088 +#define cpu_has_mips3d         0
12089 +#define cpu_has_smartmips      0
12090 +
12091 +#define cpu_has_mips32r1       1
12092 +#define cpu_has_mips32r2       1
12093 +#define cpu_has_mips64r1       0
12094 +#define cpu_has_mips64r2       0
12095 +
12096 +#define cpu_has_dsp            1
12097 +#define cpu_has_mipsmt         1
12098 +
12099 +#define cpu_has_vint           1
12100 +#define cpu_has_veic           1
12101 +
12102 +#define cpu_has_64bits         0
12103 +#define cpu_has_64bit_zero_reg 0
12104 +#define cpu_has_64bit_gp_regs  0
12105 +#define cpu_has_64bit_addresses        0
12106 +
12107 +#define cpu_dcache_line_size() 32
12108 +#define cpu_icache_line_size() 32
12109 +
12110 +#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
12111 --- /dev/null
12112 +++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h
12113 @@ -0,0 +1,1520 @@
12114 +/******************************************************************************
12115 +
12116 +                               Copyright (c) 2010
12117 +                            Lantiq Deutschland GmbH
12118 +
12119 +  For licensing information, see the file 'LICENSE' in the root folder of
12120 +  this software module.
12121 +
12122 +******************************************************************************/
12123 +
12124 +#ifndef _ebu_reg_h
12125 +#define _ebu_reg_h
12126 +
12127 +/** \addtogroup EBU_REGISTER
12128 +   @{
12129 +*/
12130 +/* access macros */
12131 +#define ebu_r32(reg) reg_r32(&ebu->reg)
12132 +#define ebu_w32(val, reg) reg_w32(val, &ebu->reg)
12133 +#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg)
12134 +#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx)
12135 +#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx)
12136 +#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx)
12137 +#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx)
12138 +
12139 +
12140 +/** EBU register structure */
12141 +struct gpon_reg_ebu
12142 +{
12143 +   /** Reserved */
12144 +   unsigned int res_0[2]; /* 0x00000000 */
12145 +   /** Module ID Register
12146 +       Module type and version identifier */
12147 +   unsigned int modid; /* 0x00000008 */
12148 +   /** Module Control Register
12149 +       This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */
12150 +   unsigned int modcon; /* 0x0000000C */
12151 +   /** Bus Read Configuration Register0
12152 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12153 +   unsigned int busrcon0; /* 0x00000010 */
12154 +   /** Bus Read Parameters Register0 */
12155 +   unsigned int busrp0; /* 0x00000014 */
12156 +   /** Bus Write Configuration Register0
12157 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12158 +   unsigned int buswcon0; /* 0x00000018 */
12159 +   /** Bus Write Parameters Register0 */
12160 +   unsigned int buswp0; /* 0x0000001C */
12161 +   /** Bus Read Configuration Register1
12162 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12163 +   unsigned int busrcon1; /* 0x00000020 */
12164 +   /** Bus Read Parameters Register1 */
12165 +   unsigned int busrp1; /* 0x00000024 */
12166 +   /** Bus Write Configuration Register1
12167 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12168 +   unsigned int buswcon1; /* 0x00000028 */
12169 +   /** Bus Write Parameters Register1 */
12170 +   unsigned int buswp1; /* 0x0000002C */
12171 +   /** Reserved */
12172 +   unsigned int res_1[8]; /* 0x00000030 */
12173 +   /** Bus Protocol Configuration Extension Register 0 */
12174 +   unsigned int busconext0; /* 0x00000050 */
12175 +   /** Bus Protocol Configuration Extension Register 1 */
12176 +   unsigned int busconext1; /* 0x00000054 */
12177 +   /** Reserved */
12178 +   unsigned int res_2[10]; /* 0x00000058 */
12179 +   /** Serial Flash Configuration Register
12180 +       The content of this register configures the EBU's Serial Flash protocol engine. */
12181 +   unsigned int sfcon; /* 0x00000080 */
12182 +   /** Serial Flash Timing Register
12183 +       This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */
12184 +   unsigned int sftime; /* 0x00000084 */
12185 +   /** Serial Flash Status Register
12186 +       This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */
12187 +   unsigned int sfstat; /* 0x00000088 */
12188 +   /** Serial Flash Command Register
12189 +       When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */
12190 +   unsigned int sfcmd; /* 0x0000008C */
12191 +   /** Serial Flash Address Register
12192 +       This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */
12193 +   unsigned int sfaddr; /* 0x00000090 */
12194 +   /** Serial Flash Data Register
12195 +       This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */
12196 +   unsigned int sfdata; /* 0x00000094 */
12197 +   /** Serial Flash I/O Control Register
12198 +       This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */
12199 +   unsigned int sfio; /* 0x00000098 */
12200 +   /** Reserved */
12201 +   unsigned int res_3[25]; /* 0x0000009C */
12202 +};
12203 +
12204 +
12205 +/* Fields of "Module ID Register" */
12206 +/** Feature Select
12207 +    This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */
12208 +#define MODID_FSEL_MASK 0xE0000000
12209 +/** field offset */
12210 +#define MODID_FSEL_OFFSET 29
12211 +/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */
12212 +#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000
12213 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */
12214 +#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000
12215 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */
12216 +#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000
12217 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */
12218 +#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000
12219 +/** Serial Flash Support
12220 +    Indicates whether or not the support of Serial Flash devices is available. */
12221 +#define MODID_SF 0x10000000
12222 +/* Not Available
12223 +#define MODID_SF_NAV 0x00000000 */
12224 +/** Available */
12225 +#define MODID_SF_AV 0x10000000
12226 +/** AAD-mux Support
12227 +    Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */
12228 +#define MODID_AAD 0x08000000
12229 +/* Not Available
12230 +#define MODID_AAD_NAV 0x00000000 */
12231 +/** Available */
12232 +#define MODID_AAD_AV 0x08000000
12233 +/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */
12234 +#define MODID_DLL 0x04000000
12235 +/* Not Available
12236 +#define MODID_DLL_NAV 0x00000000 */
12237 +/** Available */
12238 +#define MODID_DLL_AV 0x04000000
12239 +/** Pad Multiplexing Scheme */
12240 +#define MODID_PMS_MASK 0x03000000
12241 +/** field offset */
12242 +#define MODID_PMS_OFFSET 24
12243 +/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */
12244 +#define MODID_PMS_PMS_CLASSIC 0x00000000
12245 +/** Revision
12246 +    Revision Number */
12247 +#define MODID_REV_MASK 0x000F0000
12248 +/** field offset */
12249 +#define MODID_REV_OFFSET 16
12250 +/** Module ID
12251 +    This field contains the EBU's unique peripheral ID. */
12252 +#define MODID_ID_MASK 0x0000FF00
12253 +/** field offset */
12254 +#define MODID_ID_OFFSET 8
12255 +/** Version
12256 +    This field gives the EBU version number. */
12257 +#define MODID_VERSION_MASK 0x000000FF
12258 +/** field offset */
12259 +#define MODID_VERSION_OFFSET 0
12260 +
12261 +/* Fields of "Module Control Register" */
12262 +/** Reserved */
12263 +#define MODCON_DLLUPDINT_MASK 0xC0000000
12264 +/** field offset */
12265 +#define MODCON_DLLUPDINT_OFFSET 30
12266 +/** Access Inhibit Acknowledge
12267 +    After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */
12268 +#define MODCON_AIA 0x02000000
12269 +/* no access restriction are active in the EBU subsystem
12270 +#define MODCON_AIA_NO_INHIBIT 0x00000000 */
12271 +/** accesses are restricted to selected (configuration) system bus port(s) */
12272 +#define MODCON_AIA_INHIBIT 0x02000000
12273 +/** Access Inhibit request
12274 +    Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */
12275 +#define MODCON_AI 0x01000000
12276 +/* no access restriction are active in the EBU subsystem
12277 +#define MODCON_AI_NO_INHIBIT 0x00000000 */
12278 +/** accesses are restricted to selected (configuration) system bus port(s) */
12279 +#define MODCON_AI_INHIBIT 0x01000000
12280 +/** Lock Timeout */
12281 +#define MODCON_LTO_MASK 0x00FF0000
12282 +/** field offset */
12283 +#define MODCON_LTO_OFFSET 16
12284 +/** Reserved */
12285 +#define MODCON_DDREN 0x00008000
12286 +/** Pad Drive Control
12287 +    Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12288 +#define MODCON_PEXT 0x00004000
12289 +/* Normal drive
12290 +#define MODCON_PEXT_NORMAL 0x00000000 */
12291 +/** Strong drive */
12292 +#define MODCON_PEXT_STRONG 0x00004000
12293 +/** Pad Slew Falling Edge Control
12294 +    Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12295 +#define MODCON_SLF 0x00002000
12296 +/* Slow slew rate
12297 +#define MODCON_SLF_SLOW 0x00000000 */
12298 +/** Fast slew rate */
12299 +#define MODCON_SLF_FAST 0x00002000
12300 +/** Pad Slew Rising Edge Control
12301 +    Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12302 +#define MODCON_SLR 0x00001000
12303 +/* Slow slew rate
12304 +#define MODCON_SLR_SLOW 0x00000000 */
12305 +/** Fast slew rate */
12306 +#define MODCON_SLR_FAST 0x00001000
12307 +/** Write Buffering Mode
12308 +    This bit controls when the EBU starts a new write burst transaction from the Memport interface. */
12309 +#define MODCON_WBM 0x00000040
12310 +/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect.
12311 +#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */
12312 +/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */
12313 +#define MODCON_WBM_START_WRITE_LATE 0x00000040
12314 +/** Reserved */
12315 +#define MODCON_SDCLKEN 0x00000020
12316 +/** Standby Mode Enable
12317 +    When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */
12318 +#define MODCON_STBYEN 0x00000010
12319 +/* Disable
12320 +#define MODCON_STBYEN_DIS 0x00000000 */
12321 +/** Enable */
12322 +#define MODCON_STBYEN_EN 0x00000010
12323 +/** Enable BFCLK1
12324 +    This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */
12325 +#define MODCON_BFCLK1EN 0x00000008
12326 +/* Disable
12327 +#define MODCON_BFCLK1EN_DIS 0x00000000 */
12328 +/** Enable */
12329 +#define MODCON_BFCLK1EN_EN 0x00000008
12330 +/** Ready/Busy Status Edge
12331 +    This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */
12332 +#define MODCON_STSEDGE 0x00000004
12333 +/** Ready/Busy Status
12334 +    This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */
12335 +#define MODCON_STS 0x00000002
12336 +/** External Bus Arbitration Mode
12337 +    This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */
12338 +#define MODCON_AM 0x00000001
12339 +/* The EBU does not own the bus (multi-master)
12340 +#define MODCON_AM_SHAREDBUS 0x00000000 */
12341 +/** The EBU owns the external bus. */
12342 +#define MODCON_AM_OWNBUS 0x00000001
12343 +
12344 +/* Fields of "Bus Read Configuration Register0" */
12345 +/** Device Type For Region
12346 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12347 +#define BUSRCON0_AGEN_MASK 0xF0000000
12348 +/** field offset */
12349 +#define BUSRCON0_AGEN_OFFSET 28
12350 +/** Muxed Asynchronous Type External Memory */
12351 +#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12352 +/** Muxed Burst Type External Memory */
12353 +#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12354 +/** NAND Flash (page optimised) */
12355 +#define BUSRCON0_AGEN_NAND_FLASH 0x20000000
12356 +/** Muxed Cellular RAM External Memory */
12357 +#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12358 +/** Demuxed Asynchronous Type External Memory */
12359 +#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12360 +/** Demuxed Burst Type External Memory */
12361 +#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12362 +/** Demuxed Page Mode External Memory */
12363 +#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12364 +/** Demuxed Cellular RAM External Memory */
12365 +#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12366 +/** Serial Flash */
12367 +#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
12368 +/** Device Addressing Mode
12369 +    t.b.d. */
12370 +#define BUSRCON0_PORTW_MASK 0x0C000000
12371 +/** field offset */
12372 +#define BUSRCON0_PORTW_OFFSET 26
12373 +/** 8-bit multiplexed */
12374 +#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
12375 +/** 16-bit multiplexed */
12376 +#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000
12377 +/** Twin, 16-bit multiplexed */
12378 +#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000
12379 +/** 32-bit multiplexed */
12380 +#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000
12381 +/** External Wait Control
12382 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12383 +#define BUSRCON0_WAIT_MASK 0x03000000
12384 +/** field offset */
12385 +#define BUSRCON0_WAIT_OFFSET 24
12386 +/** WAIT is ignored (default after reset). */
12387 +#define BUSRCON0_WAIT_OFF 0x00000000
12388 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
12389 +#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000
12390 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
12391 +#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000
12392 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
12393 +#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000
12394 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
12395 +#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
12396 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
12397 +#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000
12398 +/** Disable Burst Address Wrapping */
12399 +#define BUSRCON0_DBA 0x00800000
12400 +/** Reversed polarity at wait */
12401 +#define BUSRCON0_WAITINV 0x00400000
12402 +/* Low active.
12403 +#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */
12404 +/** High active */
12405 +#define BUSRCON0_WAITINV_ACTHI 0x00400000
12406 +/** Early ADV Enable for Synchronous Bursts */
12407 +#define BUSRCON0_EBSE 0x00200000
12408 +/* Low active.
12409 +#define BUSRCON0_EBSE_DELAYED 0x00000000 */
12410 +/** High active */
12411 +#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000
12412 +/** Early Control Signals for Synchronous Bursts */
12413 +#define BUSRCON0_ECSE 0x00100000
12414 +/* Low active.
12415 +#define BUSRCON0_ECSE_DELAYED 0x00000000 */
12416 +/** High active */
12417 +#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000
12418 +/** Synchronous Burst Buffer Mode Select */
12419 +#define BUSRCON0_FBBMSEL 0x00080000
12420 +/* FIXED_LENGTH
12421 +#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
12422 +/** CONTINUOUS */
12423 +#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000
12424 +/** Burst Length for Synchronous Burst */
12425 +#define BUSRCON0_FETBLEN_MASK 0x00070000
12426 +/** field offset */
12427 +#define BUSRCON0_FETBLEN_OFFSET 16
12428 +/** Up to 1 data cycle (default after reset). */
12429 +#define BUSRCON0_FETBLEN_SINGLE 0x00000000
12430 +/** Up to 2 data cycles. */
12431 +#define BUSRCON0_FETBLEN_BURST2 0x00010000
12432 +/** Up to 4 data cycles. */
12433 +#define BUSRCON0_FETBLEN_BURST4 0x00020000
12434 +/** Up to 8 data cycles. */
12435 +#define BUSRCON0_FETBLEN_BURST8 0x00030000
12436 +/** Up to 16 data cycles. */
12437 +#define BUSRCON0_FETBLEN_BURST16 0x00040000
12438 +/** Reserved
12439 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
12440 +#define BUSRCON0_NANDAMAP_MASK 0x0000C000
12441 +/** field offset */
12442 +#define BUSRCON0_NANDAMAP_OFFSET 14
12443 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12444 +#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000
12445 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12446 +#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
12447 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
12448 +#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000
12449 +/** Reserved for future use. Do not use or unpredictable results may occur. */
12450 +#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000
12451 +/** AAD-mux Protocol
12452 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
12453 +#define BUSRCON0_AADMUX 0x00002000
12454 +/* Muxed device is write accessed in AD-mux mode.
12455 +#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */
12456 +/** Muxed device is write accessed in AAD-mux mode. */
12457 +#define BUSRCON0_AADMUX_AAD_MUX 0x00002000
12458 +/** Asynchronous Address Phase */
12459 +#define BUSRCON0_AAP 0x00001000
12460 +/* Clock is enabled at beginning of access.
12461 +#define BUSRCON0_AAP_EARLY 0x00000000 */
12462 +/** Clock is enabled after address phase. */
12463 +#define BUSRCON0_AAP_LATE 0x00001000
12464 +/** Burst Flash Read Single Stage Synchronisation */
12465 +#define BUSRCON0_BFSSS 0x00000800
12466 +/* Two stages of synchronisation used.
12467 +#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */
12468 +/** Single stage of synchronisation used. */
12469 +#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800
12470 +/** Burst Flash Clock Feedback Enable */
12471 +#define BUSRCON0_FDBKEN 0x00000400
12472 +/* Disable
12473 +#define BUSRCON0_FDBKEN_DIS 0x00000000 */
12474 +/** Enable */
12475 +#define BUSRCON0_FDBKEN_EN 0x00000400
12476 +/** Auxiliary Chip Select Enable
12477 +    Not supported in GPON-EBU, field must be set to 0. */
12478 +#define BUSRCON0_CSA 0x00000200
12479 +/* Disable
12480 +#define BUSRCON0_CSA_DIS 0x00000000 */
12481 +/** Enable */
12482 +#define BUSRCON0_CSA_EN 0x00000200
12483 +/** Flash Non-Array Access Enable
12484 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
12485 +#define BUSRCON0_NAA 0x00000100
12486 +/* Disable
12487 +#define BUSRCON0_NAA_DIS 0x00000000 */
12488 +/** Enable */
12489 +#define BUSRCON0_NAA_EN 0x00000100
12490 +/** Module Enable */
12491 +#define BUSRCON0_ENABLE 0x00000001
12492 +/* Disable
12493 +#define BUSRCON0_ENABLE_DIS 0x00000000 */
12494 +/** Enable */
12495 +#define BUSRCON0_ENABLE_EN 0x00000001
12496 +
12497 +/* Fields of "Bus Read Parameters Register0" */
12498 +/** Address Cycles
12499 +    Number of cycles for address phase. */
12500 +#define BUSRP0_ADDRC_MASK 0xF0000000
12501 +/** field offset */
12502 +#define BUSRP0_ADDRC_OFFSET 28
12503 +/** Address Hold Cycles For Multiplexed Address
12504 +    Number of address hold cycles during multiplexed accesses. */
12505 +#define BUSRP0_ADHOLC_MASK 0x0F000000
12506 +/** field offset */
12507 +#define BUSRP0_ADHOLC_OFFSET 24
12508 +/** Programmed Command Delay Cycles
12509 +    Number of delay cycles during command delay phase. */
12510 +#define BUSRP0_CMDDELAY_MASK 0x00F00000
12511 +/** field offset */
12512 +#define BUSRP0_CMDDELAY_OFFSET 20
12513 +/** Extended Data */
12514 +#define BUSRP0_EXTDATA_MASK 0x000C0000
12515 +/** field offset */
12516 +#define BUSRP0_EXTDATA_OFFSET 18
12517 +/** External device outputs data every BFCLK cycle */
12518 +#define BUSRP0_EXTDATA_ONE 0x00000000
12519 +/** External device outputs data every 2nd BFCLK cycles */
12520 +#define BUSRP0_EXTDATA_TWO 0x00040000
12521 +/** External device outputs data every 4th BFCLK cycles */
12522 +#define BUSRP0_EXTDATA_FOUR 0x00080000
12523 +/** External device outputs data every 8th BFCLK cycles */
12524 +#define BUSRP0_EXTDATA_EIGHT 0x000C0000
12525 +/** Frequency of external clock at pin BFCLKO */
12526 +#define BUSRP0_EXTCLOCK_MASK 0x00030000
12527 +/** field offset */
12528 +#define BUSRP0_EXTCLOCK_OFFSET 16
12529 +/** Equal to ebu_clk frequency. */
12530 +#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000
12531 +/** 1/2 of ebu_clk frequency. */
12532 +#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000
12533 +/** 1/3 of ebu_clk frequency. */
12534 +#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000
12535 +/** 1/4 of ebu_clk frequency (default after reset). */
12536 +#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
12537 +/** Data Hold Cycles For read Accesses
12538 +    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
12539 +#define BUSRP0_DATAC_MASK 0x0000F000
12540 +/** field offset */
12541 +#define BUSRP0_DATAC_OFFSET 12
12542 +/** Programmed Wait States for read accesses
12543 +    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
12544 +#define BUSRP0_WAITRDC_MASK 0x00000F80
12545 +/** field offset */
12546 +#define BUSRP0_WAITRDC_OFFSET 7
12547 +/** Recovery Cycles After read Accesses, same CS
12548 +    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12549 +#define BUSRP0_RECOVC_MASK 0x00000070
12550 +/** field offset */
12551 +#define BUSRP0_RECOVC_OFFSET 4
12552 +/** Recovery Cycles After read Accesses, other CS
12553 +    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12554 +#define BUSRP0_DTACS_MASK 0x0000000F
12555 +/** field offset */
12556 +#define BUSRP0_DTACS_OFFSET 0
12557 +
12558 +/* Fields of "Bus Write Configuration Register0" */
12559 +/** Device Type For Region
12560 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12561 +#define BUSWCON0_AGEN_MASK 0xF0000000
12562 +/** field offset */
12563 +#define BUSWCON0_AGEN_OFFSET 28
12564 +/** Muxed Asynchronous Type External Memory */
12565 +#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12566 +/** Muxed Burst Type External Memory */
12567 +#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12568 +/** NAND Flash (page optimised) */
12569 +#define BUSWCON0_AGEN_NAND_FLASH 0x20000000
12570 +/** Muxed Cellular RAM External Memory */
12571 +#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12572 +/** Demuxed Asynchronous Type External Memory */
12573 +#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12574 +/** Demuxed Burst Type External Memory */
12575 +#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12576 +/** Demuxed Page Mode External Memory */
12577 +#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12578 +/** Demuxed Cellular RAM External Memory */
12579 +#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12580 +/** Serial Flash */
12581 +#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
12582 +/** Device Addressing Mode
12583 +    t.b.d. */
12584 +#define BUSWCON0_PORTW_MASK 0x0C000000
12585 +/** field offset */
12586 +#define BUSWCON0_PORTW_OFFSET 26
12587 +/** External Wait Control
12588 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12589 +#define BUSWCON0_WAIT_MASK 0x03000000
12590 +/** field offset */
12591 +#define BUSWCON0_WAIT_OFFSET 24
12592 +/** WAIT is ignored (default after reset). */
12593 +#define BUSWCON0_WAIT_OFF 0x00000000
12594 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
12595 +#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000
12596 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
12597 +#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000
12598 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
12599 +#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000
12600 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
12601 +#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
12602 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
12603 +#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000
12604 +/** Reserved */
12605 +#define BUSWCON0_LOCKCS 0x00800000
12606 +/** Reversed polarity at wait */
12607 +#define BUSWCON0_WAITINV 0x00400000
12608 +/* Low active.
12609 +#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */
12610 +/** High active */
12611 +#define BUSWCON0_WAITINV_ACTHI 0x00400000
12612 +/** Early ADV Enable for Synchronous Bursts */
12613 +#define BUSWCON0_EBSE 0x00200000
12614 +/* Low active.
12615 +#define BUSWCON0_EBSE_DELAYED 0x00000000 */
12616 +/** High active */
12617 +#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000
12618 +/** Early Control Signals for Synchronous Bursts */
12619 +#define BUSWCON0_ECSE 0x00100000
12620 +/* Low active.
12621 +#define BUSWCON0_ECSE_DELAYED 0x00000000 */
12622 +/** High active */
12623 +#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000
12624 +/** Synchronous Burst Buffer Mode Select */
12625 +#define BUSWCON0_FBBMSEL 0x00080000
12626 +/* FIXED_LENGTH
12627 +#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
12628 +/** CONTINUOUS */
12629 +#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000
12630 +/** Burst Length for Synchronous Burst */
12631 +#define BUSWCON0_FETBLEN_MASK 0x00070000
12632 +/** field offset */
12633 +#define BUSWCON0_FETBLEN_OFFSET 16
12634 +/** Up to 1 data cycle (default after reset). */
12635 +#define BUSWCON0_FETBLEN_SINGLE 0x00000000
12636 +/** Up to 2 data cycles. */
12637 +#define BUSWCON0_FETBLEN_BURST2 0x00010000
12638 +/** Up to 4 data cycles. */
12639 +#define BUSWCON0_FETBLEN_BURST4 0x00020000
12640 +/** Up to 8 data cycles. */
12641 +#define BUSWCON0_FETBLEN_BURST8 0x00030000
12642 +/** Up to 16 data cycles. */
12643 +#define BUSWCON0_FETBLEN_BURST16 0x00040000
12644 +/** Reserved
12645 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
12646 +#define BUSWCON0_NANDAMAP_MASK 0x0000C000
12647 +/** field offset */
12648 +#define BUSWCON0_NANDAMAP_OFFSET 14
12649 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12650 +#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000
12651 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12652 +#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
12653 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
12654 +#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000
12655 +/** Reserved for future use. Do not use or unpredictable results may occur. */
12656 +#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000
12657 +/** AAD-mux Protocol
12658 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
12659 +#define BUSWCON0_AADMUX 0x00002000
12660 +/* Muxed device is write accessed in AD-mux mode.
12661 +#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */
12662 +/** Muxed device is write accessed in AAD-mux mode. */
12663 +#define BUSWCON0_AADMUX_AAD_MUX 0x00002000
12664 +/** Asynchronous Address Phase */
12665 +#define BUSWCON0_AAP 0x00001000
12666 +/* Clock is enabled at beginning of access.
12667 +#define BUSWCON0_AAP_EARLY 0x00000000 */
12668 +/** Clock is enabled after address phase. */
12669 +#define BUSWCON0_AAP_LATE 0x00001000
12670 +/** Auxiliary Chip Select Enable
12671 +    Not supported in GPON-EBU, field must be set to 0. */
12672 +#define BUSWCON0_CSA 0x00000200
12673 +/* Disable
12674 +#define BUSWCON0_CSA_DIS 0x00000000 */
12675 +/** Enable */
12676 +#define BUSWCON0_CSA_EN 0x00000200
12677 +/** Flash Non-Array Access Enable
12678 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
12679 +#define BUSWCON0_NAA 0x00000100
12680 +/* Disable
12681 +#define BUSWCON0_NAA_DIS 0x00000000 */
12682 +/** Enable */
12683 +#define BUSWCON0_NAA_EN 0x00000100
12684 +/** Module Enable */
12685 +#define BUSWCON0_ENABLE 0x00000001
12686 +/* Disable
12687 +#define BUSWCON0_ENABLE_DIS 0x00000000 */
12688 +/** Enable */
12689 +#define BUSWCON0_ENABLE_EN 0x00000001
12690 +
12691 +/* Fields of "Bus Write Parameters Register0" */
12692 +/** Address Cycles
12693 +    Number of cycles for address phase. */
12694 +#define BUSWP0_ADDRC_MASK 0xF0000000
12695 +/** field offset */
12696 +#define BUSWP0_ADDRC_OFFSET 28
12697 +/** Address Hold Cycles For Multiplexed Address
12698 +    Number of address hold cycles during multiplexed accesses. */
12699 +#define BUSWP0_ADHOLC_MASK 0x0F000000
12700 +/** field offset */
12701 +#define BUSWP0_ADHOLC_OFFSET 24
12702 +/** Programmed Command Delay Cycles
12703 +    Number of delay cycles during command delay phase. */
12704 +#define BUSWP0_CMDDELAY_MASK 0x00F00000
12705 +/** field offset */
12706 +#define BUSWP0_CMDDELAY_OFFSET 20
12707 +/** Extended Data */
12708 +#define BUSWP0_EXTDATA_MASK 0x000C0000
12709 +/** field offset */
12710 +#define BUSWP0_EXTDATA_OFFSET 18
12711 +/** External device outputs data every BFCLK cycle */
12712 +#define BUSWP0_EXTDATA_ONE 0x00000000
12713 +/** External device outputs data every 2nd BFCLK cycles */
12714 +#define BUSWP0_EXTDATA_TWO 0x00040000
12715 +/** External device outputs data every 4th BFCLK cycles */
12716 +#define BUSWP0_EXTDATA_FOUR 0x00080000
12717 +/** External device outputs data every 8th BFCLK cycles */
12718 +#define BUSWP0_EXTDATA_EIGHT 0x000C0000
12719 +/** Frequency of external clock at pin BFCLKO */
12720 +#define BUSWP0_EXTCLOCK_MASK 0x00030000
12721 +/** field offset */
12722 +#define BUSWP0_EXTCLOCK_OFFSET 16
12723 +/** Equal to ebu_clk frequency. */
12724 +#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000
12725 +/** 1/2 of ebu_clk frequency. */
12726 +#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000
12727 +/** 1/3 of ebu_clk frequency. */
12728 +#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000
12729 +/** 1/4 of ebu_clk frequency (default after reset). */
12730 +#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
12731 +/** Data Hold Cycles For write Accesses
12732 +    Number of data hold cycles during write accesses. */
12733 +#define BUSWP0_DATAC_MASK 0x0000F000
12734 +/** field offset */
12735 +#define BUSWP0_DATAC_OFFSET 12
12736 +/** Programmed Wait States For write Accesses
12737 +    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
12738 +#define BUSWP0_WAITWDC_MASK 0x00000F80
12739 +/** field offset */
12740 +#define BUSWP0_WAITWDC_OFFSET 7
12741 +/** Recovery Cycles After write Accesses, same CS
12742 +    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
12743 +#define BUSWP0_RECOVC_MASK 0x00000070
12744 +/** field offset */
12745 +#define BUSWP0_RECOVC_OFFSET 4
12746 +/** Recovery Cycles After write Accesses, other CS
12747 +    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
12748 +#define BUSWP0_DTACS_MASK 0x0000000F
12749 +/** field offset */
12750 +#define BUSWP0_DTACS_OFFSET 0
12751 +
12752 +/* Fields of "Bus Read Configuration Register1" */
12753 +/** Device Type For Region
12754 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12755 +#define BUSRCON1_AGEN_MASK 0xF0000000
12756 +/** field offset */
12757 +#define BUSRCON1_AGEN_OFFSET 28
12758 +/** Muxed Asynchronous Type External Memory */
12759 +#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12760 +/** Muxed Burst Type External Memory */
12761 +#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12762 +/** NAND Flash (page optimised) */
12763 +#define BUSRCON1_AGEN_NAND_FLASH 0x20000000
12764 +/** Muxed Cellular RAM External Memory */
12765 +#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12766 +/** Demuxed Asynchronous Type External Memory */
12767 +#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12768 +/** Demuxed Burst Type External Memory */
12769 +#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12770 +/** Demuxed Page Mode External Memory */
12771 +#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12772 +/** Demuxed Cellular RAM External Memory */
12773 +#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12774 +/** Serial Flash */
12775 +#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000
12776 +/** Device Addressing Mode
12777 +    t.b.d. */
12778 +#define BUSRCON1_PORTW_MASK 0x0C000000
12779 +/** field offset */
12780 +#define BUSRCON1_PORTW_OFFSET 26
12781 +/** 8-bit multiplexed */
12782 +#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000
12783 +/** 16-bit multiplexed */
12784 +#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000
12785 +/** Twin, 16-bit multiplexed */
12786 +#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000
12787 +/** 32-bit multiplexed */
12788 +#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000
12789 +/** External Wait Control
12790 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12791 +#define BUSRCON1_WAIT_MASK 0x03000000
12792 +/** field offset */
12793 +#define BUSRCON1_WAIT_OFFSET 24
12794 +/** WAIT is ignored (default after reset). */
12795 +#define BUSRCON1_WAIT_OFF 0x00000000
12796 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
12797 +#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000
12798 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
12799 +#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000
12800 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
12801 +#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000
12802 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
12803 +#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
12804 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
12805 +#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000
12806 +/** Disable Burst Address Wrapping */
12807 +#define BUSRCON1_DBA 0x00800000
12808 +/** Reversed polarity at wait */
12809 +#define BUSRCON1_WAITINV 0x00400000
12810 +/* Low active.
12811 +#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */
12812 +/** High active */
12813 +#define BUSRCON1_WAITINV_ACTHI 0x00400000
12814 +/** Early ADV Enable for Synchronous Bursts */
12815 +#define BUSRCON1_EBSE 0x00200000
12816 +/* Low active.
12817 +#define BUSRCON1_EBSE_DELAYED 0x00000000 */
12818 +/** High active */
12819 +#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000
12820 +/** Early Control Signals for Synchronous Bursts */
12821 +#define BUSRCON1_ECSE 0x00100000
12822 +/* Low active.
12823 +#define BUSRCON1_ECSE_DELAYED 0x00000000 */
12824 +/** High active */
12825 +#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000
12826 +/** Synchronous Burst Buffer Mode Select */
12827 +#define BUSRCON1_FBBMSEL 0x00080000
12828 +/* FIXED_LENGTH
12829 +#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
12830 +/** CONTINUOUS */
12831 +#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000
12832 +/** Burst Length for Synchronous Burst */
12833 +#define BUSRCON1_FETBLEN_MASK 0x00070000
12834 +/** field offset */
12835 +#define BUSRCON1_FETBLEN_OFFSET 16
12836 +/** Up to 1 data cycle (default after reset). */
12837 +#define BUSRCON1_FETBLEN_SINGLE 0x00000000
12838 +/** Up to 2 data cycles. */
12839 +#define BUSRCON1_FETBLEN_BURST2 0x00010000
12840 +/** Up to 4 data cycles. */
12841 +#define BUSRCON1_FETBLEN_BURST4 0x00020000
12842 +/** Up to 8 data cycles. */
12843 +#define BUSRCON1_FETBLEN_BURST8 0x00030000
12844 +/** Up to 16 data cycles. */
12845 +#define BUSRCON1_FETBLEN_BURST16 0x00040000
12846 +/** Reserved
12847 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
12848 +#define BUSRCON1_NANDAMAP_MASK 0x0000C000
12849 +/** field offset */
12850 +#define BUSRCON1_NANDAMAP_OFFSET 14
12851 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12852 +#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000
12853 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12854 +#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
12855 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
12856 +#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000
12857 +/** Reserved for future use. Do not use or unpredictable results may occur. */
12858 +#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000
12859 +/** AAD-mux Protocol
12860 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
12861 +#define BUSRCON1_AADMUX 0x00002000
12862 +/* Muxed device is write accessed in AD-mux mode.
12863 +#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */
12864 +/** Muxed device is write accessed in AAD-mux mode. */
12865 +#define BUSRCON1_AADMUX_AAD_MUX 0x00002000
12866 +/** Asynchronous Address Phase */
12867 +#define BUSRCON1_AAP 0x00001000
12868 +/* Clock is enabled at beginning of access.
12869 +#define BUSRCON1_AAP_EARLY 0x00000000 */
12870 +/** Clock is enabled after address phase. */
12871 +#define BUSRCON1_AAP_LATE 0x00001000
12872 +/** Burst Flash Read Single Stage Synchronisation */
12873 +#define BUSRCON1_BFSSS 0x00000800
12874 +/* Two stages of synchronisation used.
12875 +#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */
12876 +/** Single stage of synchronisation used. */
12877 +#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800
12878 +/** Burst Flash Clock Feedback Enable */
12879 +#define BUSRCON1_FDBKEN 0x00000400
12880 +/* Disable
12881 +#define BUSRCON1_FDBKEN_DIS 0x00000000 */
12882 +/** Enable */
12883 +#define BUSRCON1_FDBKEN_EN 0x00000400
12884 +/** Auxiliary Chip Select Enable
12885 +    Not supported in GPON-EBU, field must be set to 0. */
12886 +#define BUSRCON1_CSA 0x00000200
12887 +/* Disable
12888 +#define BUSRCON1_CSA_DIS 0x00000000 */
12889 +/** Enable */
12890 +#define BUSRCON1_CSA_EN 0x00000200
12891 +/** Flash Non-Array Access Enable
12892 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
12893 +#define BUSRCON1_NAA 0x00000100
12894 +/* Disable
12895 +#define BUSRCON1_NAA_DIS 0x00000000 */
12896 +/** Enable */
12897 +#define BUSRCON1_NAA_EN 0x00000100
12898 +/** Module Enable */
12899 +#define BUSRCON1_ENABLE 0x00000001
12900 +/* Disable
12901 +#define BUSRCON1_ENABLE_DIS 0x00000000 */
12902 +/** Enable */
12903 +#define BUSRCON1_ENABLE_EN 0x00000001
12904 +
12905 +/* Fields of "Bus Read Parameters Register1" */
12906 +/** Address Cycles
12907 +    Number of cycles for address phase. */
12908 +#define BUSRP1_ADDRC_MASK 0xF0000000
12909 +/** field offset */
12910 +#define BUSRP1_ADDRC_OFFSET 28
12911 +/** Address Hold Cycles For Multiplexed Address
12912 +    Number of address hold cycles during multiplexed accesses. */
12913 +#define BUSRP1_ADHOLC_MASK 0x0F000000
12914 +/** field offset */
12915 +#define BUSRP1_ADHOLC_OFFSET 24
12916 +/** Programmed Command Delay Cycles
12917 +    Number of delay cycles during command delay phase. */
12918 +#define BUSRP1_CMDDELAY_MASK 0x00F00000
12919 +/** field offset */
12920 +#define BUSRP1_CMDDELAY_OFFSET 20
12921 +/** Extended Data */
12922 +#define BUSRP1_EXTDATA_MASK 0x000C0000
12923 +/** field offset */
12924 +#define BUSRP1_EXTDATA_OFFSET 18
12925 +/** External device outputs data every BFCLK cycle */
12926 +#define BUSRP1_EXTDATA_ONE 0x00000000
12927 +/** External device outputs data every 2nd BFCLK cycles */
12928 +#define BUSRP1_EXTDATA_TWO 0x00040000
12929 +/** External device outputs data every 4th BFCLK cycles */
12930 +#define BUSRP1_EXTDATA_FOUR 0x00080000
12931 +/** External device outputs data every 8th BFCLK cycles */
12932 +#define BUSRP1_EXTDATA_EIGHT 0x000C0000
12933 +/** Frequency of external clock at pin BFCLKO */
12934 +#define BUSRP1_EXTCLOCK_MASK 0x00030000
12935 +/** field offset */
12936 +#define BUSRP1_EXTCLOCK_OFFSET 16
12937 +/** Equal to ebu_clk frequency. */
12938 +#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000
12939 +/** 1/2 of ebu_clk frequency. */
12940 +#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000
12941 +/** 1/3 of ebu_clk frequency. */
12942 +#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000
12943 +/** 1/4 of ebu_clk frequency (default after reset). */
12944 +#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
12945 +/** Data Hold Cycles For read Accesses
12946 +    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
12947 +#define BUSRP1_DATAC_MASK 0x0000F000
12948 +/** field offset */
12949 +#define BUSRP1_DATAC_OFFSET 12
12950 +/** Programmed Wait States for read accesses
12951 +    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
12952 +#define BUSRP1_WAITRDC_MASK 0x00000F80
12953 +/** field offset */
12954 +#define BUSRP1_WAITRDC_OFFSET 7
12955 +/** Recovery Cycles After read Accesses, same CS
12956 +    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12957 +#define BUSRP1_RECOVC_MASK 0x00000070
12958 +/** field offset */
12959 +#define BUSRP1_RECOVC_OFFSET 4
12960 +/** Recovery Cycles After read Accesses, other CS
12961 +    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12962 +#define BUSRP1_DTACS_MASK 0x0000000F
12963 +/** field offset */
12964 +#define BUSRP1_DTACS_OFFSET 0
12965 +
12966 +/* Fields of "Bus Write Configuration Register1" */
12967 +/** Device Type For Region
12968 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12969 +#define BUSWCON1_AGEN_MASK 0xF0000000
12970 +/** field offset */
12971 +#define BUSWCON1_AGEN_OFFSET 28
12972 +/** Muxed Asynchronous Type External Memory */
12973 +#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12974 +/** Muxed Burst Type External Memory */
12975 +#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12976 +/** NAND Flash (page optimised) */
12977 +#define BUSWCON1_AGEN_NAND_FLASH 0x20000000
12978 +/** Muxed Cellular RAM External Memory */
12979 +#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12980 +/** Demuxed Asynchronous Type External Memory */
12981 +#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12982 +/** Demuxed Burst Type External Memory */
12983 +#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12984 +/** Demuxed Page Mode External Memory */
12985 +#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12986 +/** Demuxed Cellular RAM External Memory */
12987 +#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12988 +/** Serial Flash */
12989 +#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000
12990 +/** Device Addressing Mode
12991 +    t.b.d. */
12992 +#define BUSWCON1_PORTW_MASK 0x0C000000
12993 +/** field offset */
12994 +#define BUSWCON1_PORTW_OFFSET 26
12995 +/** External Wait Control
12996 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12997 +#define BUSWCON1_WAIT_MASK 0x03000000
12998 +/** field offset */
12999 +#define BUSWCON1_WAIT_OFFSET 24
13000 +/** WAIT is ignored (default after reset). */
13001 +#define BUSWCON1_WAIT_OFF 0x00000000
13002 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
13003 +#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000
13004 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
13005 +#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000
13006 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
13007 +#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000
13008 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
13009 +#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
13010 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
13011 +#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000
13012 +/** Reserved */
13013 +#define BUSWCON1_LOCKCS 0x00800000
13014 +/** Reversed polarity at wait */
13015 +#define BUSWCON1_WAITINV 0x00400000
13016 +/* Low active.
13017 +#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */
13018 +/** High active */
13019 +#define BUSWCON1_WAITINV_ACTHI 0x00400000
13020 +/** Early ADV Enable for Synchronous Bursts */
13021 +#define BUSWCON1_EBSE 0x00200000
13022 +/* Low active.
13023 +#define BUSWCON1_EBSE_DELAYED 0x00000000 */
13024 +/** High active */
13025 +#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000
13026 +/** Early Control Signals for Synchronous Bursts */
13027 +#define BUSWCON1_ECSE 0x00100000
13028 +/* Low active.
13029 +#define BUSWCON1_ECSE_DELAYED 0x00000000 */
13030 +/** High active */
13031 +#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000
13032 +/** Synchronous Burst Buffer Mode Select */
13033 +#define BUSWCON1_FBBMSEL 0x00080000
13034 +/* FIXED_LENGTH
13035 +#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
13036 +/** CONTINUOUS */
13037 +#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000
13038 +/** Burst Length for Synchronous Burst */
13039 +#define BUSWCON1_FETBLEN_MASK 0x00070000
13040 +/** field offset */
13041 +#define BUSWCON1_FETBLEN_OFFSET 16
13042 +/** Up to 1 data cycle (default after reset). */
13043 +#define BUSWCON1_FETBLEN_SINGLE 0x00000000
13044 +/** Up to 2 data cycles. */
13045 +#define BUSWCON1_FETBLEN_BURST2 0x00010000
13046 +/** Up to 4 data cycles. */
13047 +#define BUSWCON1_FETBLEN_BURST4 0x00020000
13048 +/** Up to 8 data cycles. */
13049 +#define BUSWCON1_FETBLEN_BURST8 0x00030000
13050 +/** Up to 16 data cycles. */
13051 +#define BUSWCON1_FETBLEN_BURST16 0x00040000
13052 +/** Reserved
13053 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
13054 +#define BUSWCON1_NANDAMAP_MASK 0x0000C000
13055 +/** field offset */
13056 +#define BUSWCON1_NANDAMAP_OFFSET 14
13057 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13058 +#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000
13059 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13060 +#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
13061 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
13062 +#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000
13063 +/** Reserved for future use. Do not use or unpredictable results may occur. */
13064 +#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000
13065 +/** AAD-mux Protocol
13066 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
13067 +#define BUSWCON1_AADMUX 0x00002000
13068 +/* Muxed device is write accessed in AD-mux mode.
13069 +#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */
13070 +/** Muxed device is write accessed in AAD-mux mode. */
13071 +#define BUSWCON1_AADMUX_AAD_MUX 0x00002000
13072 +/** Asynchronous Address Phase */
13073 +#define BUSWCON1_AAP 0x00001000
13074 +/* Clock is enabled at beginning of access.
13075 +#define BUSWCON1_AAP_EARLY 0x00000000 */
13076 +/** Clock is enabled after address phase. */
13077 +#define BUSWCON1_AAP_LATE 0x00001000
13078 +/** Auxiliary Chip Select Enable
13079 +    Not supported in GPON-EBU, field must be set to 0. */
13080 +#define BUSWCON1_CSA 0x00000200
13081 +/* Disable
13082 +#define BUSWCON1_CSA_DIS 0x00000000 */
13083 +/** Enable */
13084 +#define BUSWCON1_CSA_EN 0x00000200
13085 +/** Flash Non-Array Access Enable
13086 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
13087 +#define BUSWCON1_NAA 0x00000100
13088 +/* Disable
13089 +#define BUSWCON1_NAA_DIS 0x00000000 */
13090 +/** Enable */
13091 +#define BUSWCON1_NAA_EN 0x00000100
13092 +/** Module Enable */
13093 +#define BUSWCON1_ENABLE 0x00000001
13094 +/* Disable
13095 +#define BUSWCON1_ENABLE_DIS 0x00000000 */
13096 +/** Enable */
13097 +#define BUSWCON1_ENABLE_EN 0x00000001
13098 +
13099 +/* Fields of "Bus Write Parameters Register1" */
13100 +/** Address Cycles
13101 +    Number of cycles for address phase. */
13102 +#define BUSWP1_ADDRC_MASK 0xF0000000
13103 +/** field offset */
13104 +#define BUSWP1_ADDRC_OFFSET 28
13105 +/** Address Hold Cycles For Multiplexed Address
13106 +    Number of address hold cycles during multiplexed accesses. */
13107 +#define BUSWP1_ADHOLC_MASK 0x0F000000
13108 +/** field offset */
13109 +#define BUSWP1_ADHOLC_OFFSET 24
13110 +/** Programmed Command Delay Cycles
13111 +    Number of delay cycles during command delay phase. */
13112 +#define BUSWP1_CMDDELAY_MASK 0x00F00000
13113 +/** field offset */
13114 +#define BUSWP1_CMDDELAY_OFFSET 20
13115 +/** Extended Data */
13116 +#define BUSWP1_EXTDATA_MASK 0x000C0000
13117 +/** field offset */
13118 +#define BUSWP1_EXTDATA_OFFSET 18
13119 +/** External device outputs data every BFCLK cycle */
13120 +#define BUSWP1_EXTDATA_ONE 0x00000000
13121 +/** External device outputs data every 2nd BFCLK cycles */
13122 +#define BUSWP1_EXTDATA_TWO 0x00040000
13123 +/** External device outputs data every 4th BFCLK cycles */
13124 +#define BUSWP1_EXTDATA_FOUR 0x00080000
13125 +/** External device outputs data every 8th BFCLK cycles */
13126 +#define BUSWP1_EXTDATA_EIGHT 0x000C0000
13127 +/** Frequency of external clock at pin BFCLKO */
13128 +#define BUSWP1_EXTCLOCK_MASK 0x00030000
13129 +/** field offset */
13130 +#define BUSWP1_EXTCLOCK_OFFSET 16
13131 +/** Equal to ebu_clk frequency. */
13132 +#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000
13133 +/** 1/2 of ebu_clk frequency. */
13134 +#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000
13135 +/** 1/3 of ebu_clk frequency. */
13136 +#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000
13137 +/** 1/4 of ebu_clk frequency (default after reset). */
13138 +#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
13139 +/** Data Hold Cycles For write Accesses
13140 +    Number of data hold cycles during write accesses. */
13141 +#define BUSWP1_DATAC_MASK 0x0000F000
13142 +/** field offset */
13143 +#define BUSWP1_DATAC_OFFSET 12
13144 +/** Programmed Wait States For write Accesses
13145 +    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
13146 +#define BUSWP1_WAITWDC_MASK 0x00000F80
13147 +/** field offset */
13148 +#define BUSWP1_WAITWDC_OFFSET 7
13149 +/** Recovery Cycles After write Accesses, same CS
13150 +    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13151 +#define BUSWP1_RECOVC_MASK 0x00000070
13152 +/** field offset */
13153 +#define BUSWP1_RECOVC_OFFSET 4
13154 +/** Recovery Cycles After write Accesses, other CS
13155 +    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13156 +#define BUSWP1_DTACS_MASK 0x0000000F
13157 +/** field offset */
13158 +#define BUSWP1_DTACS_OFFSET 0
13159 +
13160 +/* Fields of "Bus Protocol Configuration Extension Register 0" */
13161 +/** Byte Control Mapping
13162 +    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
13163 +#define BUSCONEXT0_BCMAP_MASK 0x00030000
13164 +/** field offset */
13165 +#define BUSCONEXT0_BCMAP_OFFSET 16
13166 +/** No mirroring of byte enables. */
13167 +#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000
13168 +/** Asynchronous Early Write
13169 +    This bit is obsolete and must be set to 0 or unpredictable results may result. */
13170 +#define BUSCONEXT0_AEW 0x00008000
13171 +/** AAD-mux Consecutive Address Cycles
13172 +    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
13173 +#define BUSCONEXT0_ACAC 0x00004000
13174 +/* ADV is deasserted between high and low address phase.
13175 +#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */
13176 +/** ADV is not deasserted between high and low address phase. */
13177 +#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000
13178 +/** AAD-mux Write Address-to-Address Delay
13179 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
13180 +#define BUSCONEXT0_WAAC_MASK 0x00003800
13181 +/** field offset */
13182 +#define BUSCONEXT0_WAAC_OFFSET 11
13183 +/** AAD-mux Read Address-to-Address Delay
13184 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
13185 +#define BUSCONEXT0_RAAC_MASK 0x00000700
13186 +/** field offset */
13187 +#define BUSCONEXT0_RAAC_OFFSET 8
13188 +/** AAD-mux Paging Enable for CS0
13189 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13190 +#define BUSCONEXT0_PAGE_EN 0x00000080
13191 +/* Disable
13192 +#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */
13193 +/** Enable */
13194 +#define BUSCONEXT0_PAGE_EN_EN 0x00000080
13195 +/** AAD-mux Address Extension Bit Generation Mode
13196 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13197 +#define BUSCONEXT0_AEBM_MASK 0x00000070
13198 +/** field offset */
13199 +#define BUSCONEXT0_AEBM_OFFSET 4
13200 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
13201 +#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000
13202 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
13203 +#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010
13204 +/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
13205 +#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020
13206 +/** Do not use */
13207 +#define BUSCONEXT0_AEBM_reserved 0x00000030
13208 +/** A[15:14] in the high address cycle is set to 00B. */
13209 +#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040
13210 +/** A[15:14] in the high address cycle is set to 01B */
13211 +#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050
13212 +/** A[15:14] in the high address cycle is set to 10B */
13213 +#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060
13214 +/** A[15:14] in the high address cycle is set to 11B. */
13215 +#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070
13216 +/** Most Significant Address Bit of External Device
13217 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
13218 +#define BUSCONEXT0_AMSB_MASK 0x0000000F
13219 +/** field offset */
13220 +#define BUSCONEXT0_AMSB_OFFSET 0
13221 +
13222 +/* Fields of "Bus Protocol Configuration Extension Register 1" */
13223 +/** Byte Control Mapping
13224 +    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
13225 +#define BUSCONEXT1_BCMAP_MASK 0x00030000
13226 +/** field offset */
13227 +#define BUSCONEXT1_BCMAP_OFFSET 16
13228 +/** No mirroring of byte enables. */
13229 +#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000
13230 +/** Asynchronous Early Write
13231 +    This bit is obsolete and must be set to 0 or unpredictable results may result. */
13232 +#define BUSCONEXT1_AEW 0x00008000
13233 +/** AAD-mux Consecutive Address Cycles
13234 +    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
13235 +#define BUSCONEXT1_ACAC 0x00004000
13236 +/* ADV is deasserted between high and low address phase.
13237 +#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */
13238 +/** ADV is not deasserted between high and low address phase. */
13239 +#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000
13240 +/** AAD-mux Write Address-to-Address Delay
13241 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
13242 +#define BUSCONEXT1_WAAC_MASK 0x00003800
13243 +/** field offset */
13244 +#define BUSCONEXT1_WAAC_OFFSET 11
13245 +/** AAD-mux Read Address-to-Address Delay
13246 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
13247 +#define BUSCONEXT1_RAAC_MASK 0x00000700
13248 +/** field offset */
13249 +#define BUSCONEXT1_RAAC_OFFSET 8
13250 +/** AAD-mux Paging Enable for CS0
13251 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13252 +#define BUSCONEXT1_PAGE_EN 0x00000080
13253 +/* Disable
13254 +#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */
13255 +/** Enable */
13256 +#define BUSCONEXT1_PAGE_EN_EN 0x00000080
13257 +/** AAD-mux Address Extension Bit Generation Mode
13258 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13259 +#define BUSCONEXT1_AEBM_MASK 0x00000070
13260 +/** field offset */
13261 +#define BUSCONEXT1_AEBM_OFFSET 4
13262 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
13263 +#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000
13264 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
13265 +#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010
13266 +/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
13267 +#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020
13268 +/** Do not use */
13269 +#define BUSCONEXT1_AEBM_reserved 0x00000030
13270 +/** A[15:14] in the high address cycle is set to 00B. */
13271 +#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040
13272 +/** A[15:14] in the high address cycle is set to 01B */
13273 +#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050
13274 +/** A[15:14] in the high address cycle is set to 10B */
13275 +#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060
13276 +/** A[15:14] in the high address cycle is set to 11B. */
13277 +#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070
13278 +/** Most Significant Address Bit of External Device
13279 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
13280 +#define BUSCONEXT1_AMSB_MASK 0x0000000F
13281 +/** field offset */
13282 +#define BUSCONEXT1_AMSB_OFFSET 0
13283 +
13284 +/* Fields of "Serial Flash Configuration Register" */
13285 +/** Direct Access Device Port Width
13286 +    DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */
13287 +#define SFCON_DA_PORTW_MASK 0xE0000000
13288 +/** field offset */
13289 +#define SFCON_DA_PORTW_OFFSET 29
13290 +/** One signal line used in all phases of the transaction. */
13291 +#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000
13292 +/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */
13293 +#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000
13294 +/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
13295 +#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000
13296 +/** Two signal lines used in all phases of the transaction. */
13297 +#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000
13298 +/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */
13299 +#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000
13300 +/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
13301 +#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000
13302 +/** Four signal lines used in all phases of the transaction. */
13303 +#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000
13304 +/** for future use. */
13305 +#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000
13306 +/** Read Abort Enable
13307 +    If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */
13308 +#define SFCON_RD_ABORT_EN 0x10000000
13309 +/** Device Size
13310 +    Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */
13311 +#define SFCON_DEV_SIZE_MASK 0x0F000000
13312 +/** field offset */
13313 +#define SFCON_DEV_SIZE_OFFSET 24
13314 +/** 16 MBit device */
13315 +#define SFCON_DEV_SIZE_A20_0 0x00000000
13316 +/** 32 MBit device */
13317 +#define SFCON_DEV_SIZE_A21_0 0x01000000
13318 +/** 64 MBit device */
13319 +#define SFCON_DEV_SIZE_A22_0 0x02000000
13320 +/** 128 MBit device */
13321 +#define SFCON_DEV_SIZE_A23_0 0x03000000
13322 +/** 256 MBit device */
13323 +#define SFCON_DEV_SIZE_A24_0 0x04000000
13324 +/** 512 MBit device */
13325 +#define SFCON_DEV_SIZE_A25_0 0x05000000
13326 +/** 1 GBit device */
13327 +#define SFCON_DEV_SIZE_A26_0 0x06000000
13328 +/** 2 GBit device */
13329 +#define SFCON_DEV_SIZE_A27_0 0x07000000
13330 +/** 4 GBit device */
13331 +#define SFCON_DEV_SIZE_A28_0 0x08000000
13332 +/** 8 GBit device */
13333 +#define SFCON_DEV_SIZE_A29_0 0x09000000
13334 +/** 16 GBit device */
13335 +#define SFCON_DEV_SIZE_A30_0 0x0A000000
13336 +/** 32 GBit device */
13337 +#define SFCON_DEV_SIZE_A31_0 0x0B000000
13338 +/** Device Page Size
13339 +    Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */
13340 +#define SFCON_DPS_MASK 0x00C00000
13341 +/** field offset */
13342 +#define SFCON_DPS_OFFSET 22
13343 +/** Device page size is 256 Bytes */
13344 +#define SFCON_DPS_DPS_256 0x00000000
13345 +/** Device page size is 512 Bytes */
13346 +#define SFCON_DPS_DPS_512 0x00400000
13347 +/** Page Buffer Size
13348 +    Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */
13349 +#define SFCON_PB_SIZE_MASK 0x00300000
13350 +/** field offset */
13351 +#define SFCON_PB_SIZE_OFFSET 20
13352 +/** No read buffer is available/used. */
13353 +#define SFCON_PB_SIZE_NONE 0x00000000
13354 +/** 128 Bytes */
13355 +#define SFCON_PB_SIZE_SIZE_128 0x00100000
13356 +/** 256 Bytes */
13357 +#define SFCON_PB_SIZE_SIZE_256 0x00200000
13358 +/** Bidirectional Data Bus
13359 +    Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */
13360 +#define SFCON_BIDIR 0x00080000
13361 +/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read)
13362 +#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */
13363 +/** The Serial Flash interface uses a bidirectional data bus. */
13364 +#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000
13365 +/** No Busy Error termination
13366 +    By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */
13367 +#define SFCON_NO_BUSY_ERR 0x00040000
13368 +/** End-of-Busy Detection Mode
13369 +    Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */
13370 +#define SFCON_EOBDM_MASK 0x00030000
13371 +/** field offset */
13372 +#define SFCON_EOBDM_OFFSET 16
13373 +/** No read buffer is available/used. */
13374 +#define SFCON_EOBDM_SOFTWARE 0x00000000
13375 +/** Poll device status register (not supported yet) */
13376 +#define SFCON_EOBDM_POLL_SR 0x00010000
13377 +/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */
13378 +#define SFCON_EOBDM_POLL_RDY 0x00020000
13379 +/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */
13380 +#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000
13381 +/** Direct Access Keep Chip Select
13382 +    Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */
13383 +#define SFCON_DA_KEEP_CS 0x00008000
13384 +/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13385 +#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */
13386 +/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
13387 +#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000
13388 +/** Early Read Abort Enable
13389 +    When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */
13390 +#define SFCON_EARLY_ABORT 0x00004000
13391 +/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13392 +#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */
13393 +/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */
13394 +#define SFCON_EARLY_ABORT_ENABLE 0x00004000
13395 +/** Direct Access Address Length
13396 +    Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */
13397 +#define SFCON_DA_ALEN_MASK 0x00003000
13398 +/** field offset */
13399 +#define SFCON_DA_ALEN_OFFSET 12
13400 +/** 3 address bytes (bits 23:0 of the internal address) */
13401 +#define SFCON_DA_ALEN_THREE 0x00000000
13402 +/** Read Access Dummy Bytes
13403 +    This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */
13404 +#define SFCON_RD_DUMLEN_MASK 0x00000F00
13405 +/** field offset */
13406 +#define SFCON_RD_DUMLEN_OFFSET 8
13407 +/** Direct Read Access Command Opcode
13408 +    This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */
13409 +#define SFCON_RD_OPC_MASK 0x000000FF
13410 +/** field offset */
13411 +#define SFCON_RD_OPC_OFFSET 0
13412 +/** READ */
13413 +#define SFCON_RD_OPC_READ 0x00000003
13414 +/** FAST_READ */
13415 +#define SFCON_RD_OPC_FAST_READ 0x0000000B
13416 +
13417 +/* Fields of "Serial Flash Timing Register" */
13418 +/** CS Idle time
13419 +    This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */
13420 +#define SFTIME_CS_IDLE_MASK 0xF0000000
13421 +/** field offset */
13422 +#define SFTIME_CS_IDLE_OFFSET 28
13423 +/** 1 EBU clock cycles */
13424 +#define SFTIME_CS_IDLE_CLKC_0 0x00000000
13425 +/** 2 EBU clock cycles */
13426 +#define SFTIME_CS_IDLE_CLKC_1 0x10000000
13427 +/** 3 EBU clock cycles */
13428 +#define SFTIME_CS_IDLE_CLKC_2 0x20000000
13429 +/** 4 EBU clock cycles */
13430 +#define SFTIME_CS_IDLE_CLKC_3 0x30000000
13431 +/** 6 EBU clock cycles */
13432 +#define SFTIME_CS_IDLE_CLKC_4 0x40000000
13433 +/** 8 EBU clock cycles */
13434 +#define SFTIME_CS_IDLE_CLKC_5 0x50000000
13435 +/** 10 EBU clock cycles */
13436 +#define SFTIME_CS_IDLE_CLKC_6 0x60000000
13437 +/** 12 EBU clock cycles */
13438 +#define SFTIME_CS_IDLE_CLKC_7 0x70000000
13439 +/** 14 EBU clock cycles */
13440 +#define SFTIME_CS_IDLE_CLKC_8 0x80000000
13441 +/** 16 EBU clock cycles */
13442 +#define SFTIME_CS_IDLE_CLKC_9 0x90000000
13443 +/** 20 EBU clock cycles */
13444 +#define SFTIME_CS_IDLE_CLKC_10 0xA0000000
13445 +/** 24 EBU clock cycles */
13446 +#define SFTIME_CS_IDLE_CLKC_11 0xB0000000
13447 +/** 32 EBU clock cycles */
13448 +#define SFTIME_CS_IDLE_CLKC_12 0xC0000000
13449 +/** 40 EBU clock cycles */
13450 +#define SFTIME_CS_IDLE_CLKC_13 0xD0000000
13451 +/** 48 EBU clock cycles */
13452 +#define SFTIME_CS_IDLE_CLKC_14 0xE0000000
13453 +/** 64 EBU clock cycles */
13454 +#define SFTIME_CS_IDLE_CLKC_15 0xF0000000
13455 +/** CS Hold time
13456 +    This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */
13457 +#define SFTIME_CS_HOLD_MASK 0x0C000000
13458 +/** field offset */
13459 +#define SFTIME_CS_HOLD_OFFSET 26
13460 +/** CS Setup time
13461 +    This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */
13462 +#define SFTIME_CS_SETUP_MASK 0x03000000
13463 +/** field offset */
13464 +#define SFTIME_CS_SETUP_OFFSET 24
13465 +/** Write-to-Read Pause
13466 +    This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */
13467 +#define SFTIME_WR2RD_PAUSE_MASK 0x00300000
13468 +/** field offset */
13469 +#define SFTIME_WR2RD_PAUSE_OFFSET 20
13470 +/** Read Data Position
13471 +    This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */
13472 +#define SFTIME_RD_POS_MASK 0x000F0000
13473 +/** field offset */
13474 +#define SFTIME_RD_POS_OFFSET 16
13475 +/** SCK Fall-edge Position
13476 +    This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */
13477 +#define SFTIME_SCKF_POS_MASK 0x0000F000
13478 +/** field offset */
13479 +#define SFTIME_SCKF_POS_OFFSET 12
13480 +/** SCK Rise-edge Position
13481 +    This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */
13482 +#define SFTIME_SCKR_POS_MASK 0x00000F00
13483 +/** field offset */
13484 +#define SFTIME_SCKR_POS_OFFSET 8
13485 +/** SCK Feedback Clock Inversion
13486 +    If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */
13487 +#define SFTIME_SCK_FDBK_INV 0x00000040
13488 +/** SCK Clock Feedback
13489 +    If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */
13490 +#define SFTIME_SCK_FDBK_EN 0x00000020
13491 +/** Inverted SCK
13492 +    If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */
13493 +#define SFTIME_SCK_INV 0x00000010
13494 +/** SCK Period
13495 +    This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */
13496 +#define SFTIME_SCK_PER_MASK 0x0000000F
13497 +/** field offset */
13498 +#define SFTIME_SCK_PER_OFFSET 0
13499 +
13500 +/* Fields of "Serial Flash Status Register" */
13501 +/** Command Overwrite Error
13502 +    This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
13503 +#define SFSTAT_CMD_OVWRT_ERR 0x40000000
13504 +/** Command Error
13505 +    This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
13506 +#define SFSTAT_CMD_ERR 0x20000000
13507 +/** Access Command Pending
13508 +    If set, indicates that access from/to a Serial Flash device has not finished yet. */
13509 +#define SFSTAT_CMD_PEND 0x00400000
13510 +/** External Device Selected
13511 +    If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */
13512 +#define SFSTAT_SELECTED 0x00200000
13513 +/** Protocol Engine Active
13514 +    If set, indicates that the EBU's Serial Flash protocol engine is active. */
13515 +#define SFSTAT_ACTIVE 0x00100000
13516 +/** Page Buffer Invalidate
13517 +    When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */
13518 +#define SFSTAT_PB_INVALID 0x00010000
13519 +/** Page Buffer Update
13520 +    This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */
13521 +#define SFSTAT_PB_UPDATE 0x00002000
13522 +/** Page Buffer Valid
13523 +    This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */
13524 +#define SFSTAT_PB_VALID 0x00001000
13525 +/** Page Buffer Busy
13526 +    The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */
13527 +#define SFSTAT_PB_BUSY 0x00000100
13528 +/** Device Busy
13529 +    This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */
13530 +#define SFSTAT_BUSY 0x00000001
13531 +
13532 +/* Fields of "Serial Flash Command Register" */
13533 +/** Command Type
13534 +    This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */
13535 +#define SFCMD_CMDTYPE 0x80000000
13536 +/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device.
13537 +#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */
13538 +/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */
13539 +#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000
13540 +/** Device Port Width
13541 +    Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */
13542 +#define SFCMD_PORTW_MASK 0x70000000
13543 +/** field offset */
13544 +#define SFCMD_PORTW_OFFSET 28
13545 +/** Bidirectional Signal Lines
13546 +    If set selects bidirectional signal lines to be used for the data transfer. */
13547 +#define SFCMD_BIDIR 0x08000000
13548 +/** Chip Select
13549 +    This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */
13550 +#define SFCMD_CS_MASK 0x07000000
13551 +/** field offset */
13552 +#define SFCMD_CS_OFFSET 24
13553 +/** Disable Auto Address Increment
13554 +    By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */
13555 +#define SFCMD_DIS_AAI 0x00800000
13556 +/** Address Length
13557 +    Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */
13558 +#define SFCMD_ALEN_MASK 0x00700000
13559 +/** field offset */
13560 +#define SFCMD_ALEN_OFFSET 20
13561 +/** Dummy Phase Length
13562 +    Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */
13563 +#define SFCMD_DUMLEN_MASK 0x000F0000
13564 +/** field offset */
13565 +#define SFCMD_DUMLEN_OFFSET 16
13566 +/** Keep Chip Select
13567 +    Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */
13568 +#define SFCMD_KEEP_CS 0x00008000
13569 +/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13570 +#define SFCMD_KEEP_CS_DESELECT 0x00000000 */
13571 +/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
13572 +#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
13573 +/** Set Busy Flag
13574 +    If set, starting the command sets EBU_SFSTAT.busy. */
13575 +#define SFCMD_SET_BUSY 0x00004000
13576 +/** Ignore Busy
13577 +    By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */
13578 +#define SFCMD_IGNORE_BUSY 0x00002000
13579 +/** Skip Opcode
13580 +    If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */
13581 +#define SFCMD_SKIP_OPC 0x00001000
13582 +/** Data Length
13583 +    This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */
13584 +#define SFCMD_DLEN_MASK 0x00000E00
13585 +/** field offset */
13586 +#define SFCMD_DLEN_OFFSET 9
13587 +/** Direction
13588 +    Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */
13589 +#define SFCMD_DIR 0x00000100
13590 +/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA.
13591 +#define SFCMD_DIR_READ 0x00000000 */
13592 +/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */
13593 +#define SFCMD_DIR_WRITE 0x00000100
13594 +/** Command Opcode
13595 +    A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */
13596 +#define SFCMD_OPC_MASK 0x000000FF
13597 +/** field offset */
13598 +#define SFCMD_OPC_OFFSET 0
13599 +
13600 +/* Fields of "Serial Flash Address Register" */
13601 +/** Address
13602 +    Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
13603 +#define SFADDR_ADDR_MASK 0xFFFFFFFF
13604 +/** field offset */
13605 +#define SFADDR_ADDR_OFFSET 0
13606 +
13607 +/* Fields of "Serial Flash Data Register" */
13608 +/** Data Bytes
13609 +    Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
13610 +#define SFDATA_DATA_MASK 0xFFFFFFFF
13611 +/** field offset */
13612 +#define SFDATA_DATA_OFFSET 0
13613 +
13614 +/* Fields of "Serial Flash I/O Control Register" */
13615 +/** Start of Write Delay
13616 +    By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */
13617 +#define SFIO_SOWD_MASK 0x0000F000
13618 +/** field offset */
13619 +#define SFIO_SOWD_OFFSET 12
13620 +/** End of Write Delay
13621 +    This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */
13622 +#define SFIO_EOWD_MASK 0x00000F00
13623 +/** field offset */
13624 +#define SFIO_EOWD_OFFSET 8
13625 +/** Data Output
13626 +    The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */
13627 +#define SFIO_UNUSED_WD_MASK 0x0000000F
13628 +/** field offset */
13629 +#define SFIO_UNUSED_WD_OFFSET 0
13630 +
13631 +/*! @} */ /* EBU_REGISTER */
13632 +
13633 +#endif /* _ebu_reg_h */