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adm5120: convert to use the new mips multimachine stuff
[openwrt.git] / target / linux / coldfire / patches / 061-m5445x_rename_config.patch
1 From 778c1668df4a4c634fae8ef99a05120121cce838 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Wed, 18 Jun 2008 15:17:31 -0600
4 Subject: [PATCH] Convert CONFIG_M54455 to CONFIG_M5445X for clarity.
5
6 LTIBName: m5445x-rename-config
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 ---
9 arch/m68k/Kconfig | 50 ++++++++++++++++++++++++++++---------
10 arch/m68k/Makefile | 2 +-
11 arch/m68k/coldfire/Makefile | 2 +-
12 arch/m68k/coldfire/config.c | 33 +++++++++++++++----------
13 arch/m68k/coldfire/head.S | 23 ++++++++++-------
14 arch/m68k/coldfire/ints.c | 6 ++--
15 arch/m68k/kernel/dma.c | 4 +-
16 arch/m68k/kernel/setup.c | 2 +-
17 arch/m68k/mm/kmap.c | 2 +-
18 drivers/crypto/Kconfig | 12 ++++----
19 drivers/crypto/mcfcau-aes.c | 2 +-
20 drivers/crypto/mcfcau-des.c | 2 +-
21 drivers/crypto/mcfcau-md5.c | 2 +-
22 drivers/crypto/mcfcau-sha1.c | 2 +-
23 drivers/crypto/mcfcau.c | 2 +-
24 drivers/crypto/mcfcau.h | 2 +-
25 drivers/net/Kconfig | 2 +-
26 drivers/net/fec.c | 10 ++++----
27 drivers/net/fec.h | 2 +-
28 drivers/serial/mcfserial.c | 8 +++---
29 drivers/spi/coldfire_edma.c | 4 +-
30 drivers/spi/spi_coldfire.c | 2 +-
31 drivers/spi/ssi_audio.c | 2 +-
32 include/asm-m68k/cfcache.h | 2 +-
33 include/asm-m68k/coldfire.h | 4 +-
34 include/asm-m68k/coldfire_edma.h | 4 +-
35 include/asm-m68k/mcfsim.h | 2 +-
36 include/asm-m68k/mcfuart.h | 2 +-
37 include/asm-m68k/page_offset.h | 2 +-
38 include/asm-m68k/setup.h | 2 +-
39 30 files changed, 116 insertions(+), 80 deletions(-)
40
41 --- a/arch/m68k/Kconfig
42 +++ b/arch/m68k/Kconfig
43 @@ -56,7 +56,7 @@ config ARCH_MAY_HAVE_PC_FDC
44 default y
45
46 config NO_IOPORT
47 - def_bool !(M54455 || M547X_8X)
48 + def_bool !(M5445X || M547X_8X)
49
50 config NO_DMA
51 def_bool SUN3
52 @@ -143,7 +143,7 @@ config CFV4E
53
54 config MCD_DMA
55 bool "ColdFire MCD DMA support"
56 - depends on CFV4E
57 + depends on M547X_8X
58 default y
59 help
60 This enables support for the ColdFire 547x/548x family
61 @@ -177,7 +177,7 @@ config HADES
62 config PCI
63 bool
64 depends on HADES || M54455
65 - default y
66 + default n
67 help
68 Find out whether you have a PCI motherboard. PCI is the name of a
69 bus system, i.e. the way the CPU talks to the other stuff inside
70 @@ -325,11 +325,34 @@ config M68060
71 If you anticipate running this kernel on a computer with a MC68060
72 processor, say Y. Otherwise, say N.
73
74 -config M54455
75 - bool "MCF54455 support"
76 +config M5445X
77 + bool "MCF5445x support"
78 depends on COLDFIRE
79 help
80 - This option will add support for the MCF54455 processor with mmu.
81 + This option will add support for the MCF5445 processor with mmu.
82 +
83 +config M54451
84 + bool
85 + depends on M5445X
86 + default n
87 +
88 +config M54455
89 + bool
90 + depends on M5445X
91 + default n
92 +
93 +choice
94 + prompt "Model"
95 + depends on M5445X
96 + default M54451EVB
97 + config M54451EVB
98 + bool "M54451EVB"
99 + select M54451
100 + config M54455EVB
101 + bool "M54455EVB"
102 + select M54455
103 +endchoice
104 +
105
106 config M547X_8X
107 bool "MCF547x/MCF548x support"
108 @@ -393,7 +416,8 @@ endchoice
109
110 config MCFCLK
111 int
112 - default 266666666 if M54455
113 + default 266666666 if M54455EVB
114 + default 240000000 if M54451EVB
115 default 266000000 if M547X
116 default 200000000 if M548X
117 help
118 @@ -401,7 +425,7 @@ config MCFCLK
119
120 config MCF_USER_HALT
121 bool "Coldfire User Halt Enable"
122 - depends on M54455 || M547X_8X
123 + depends on M5445X || M547X_8X
124 default n
125 help
126 Enables the HALT instruction in User Mode.
127 @@ -420,19 +444,21 @@ config MMU_CFV4E
128 config SDRAM_BASE
129 hex
130 depends on COLDFIRE
131 - default 0x40000000 if M54455
132 + default 0x40000000 if M5445X
133 default 0x00000000 if M547X_8X
134
135 config SDRAM_SIZE
136 hex
137 depends on COLDFIRE
138 - default 0x0FFFFFFF if M54455
139 + default 0x08000000 if M54451EVB
140 + default 0x10000000 if M54455EVB
141 default 0x04000000 if M547X_8X
142
143 config NOR_FLASH_BASE
144 hex "NOR Flash Base Address"
145 - depends on M54455
146 - default 0x00000000
147 + depends on COLDFIRE
148 + default 0x00000000 if M54451EVB
149 + default 0x00000000 if M54455EVB
150
151 config M68KFPU_EMU
152 bool "Math emulation support (EXPERIMENTAL)"
153 --- a/arch/m68k/Makefile
154 +++ b/arch/m68k/Makefile
155 @@ -59,7 +59,7 @@ endif
156 endif
157 endif
158
159 -ifdef CONFIG_M54455
160 +ifdef CONFIG_M5445X
161 KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g
162 KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float
163 endif
164 --- a/arch/m68k/coldfire/Makefile
165 +++ b/arch/m68k/coldfire/Makefile
166 @@ -9,7 +9,7 @@ ifneq ($(strip $(CONFIG_USB) $(CONFIG_US
167 endif
168
169 obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o iomap.o
170 -obj-$(CONFIG_M54455) += mcf5445x-devices.o
171 +obj-$(CONFIG_M5445X) += mcf5445x-devices.o
172 obj-$(CONFIG_M547X_8X) += m547x_8x-devices.o
173 obj-$(CONFIG_M547X_8X) += mcf548x-devices.o
174 obj-$(CONFIG_MCD_DMA) += m547x_8x-dma.o
175 --- a/arch/m68k/coldfire/config.c
176 +++ b/arch/m68k/coldfire/config.c
177 @@ -35,14 +35,14 @@
178
179 #include <asm/mcfsim.h>
180
181 -#if defined(CONFIG_M54455)
182 +#if defined(CONFIG_M5445X)
183 #define UBOOT_EXTRA_CLOCKS
184 #elif defined(CONFIG_M547X_8X)
185 #define UBOOT_PCI
186 #endif
187 #include <asm/bootinfo.h>
188
189 -#ifdef CONFIG_M54455
190 +#ifdef CONFIG_M5445X
191 #include <asm/mcf5445x_intc.h>
192 #include <asm/mcf5445x_sdramc.h>
193 #include <asm/mcf5445x_fbcs.h>
194 @@ -132,8 +132,9 @@ int __init uboot_commandline(char *boota
195 /*
196 * This routine does things not done in the bootloader.
197 */
198 -#if defined(CONFIG_M54455)
199 -#define DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
200 +#if defined(CONFIG_M5445X)
201 +#define FOO_DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
202 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ ip=172.27.155.51:172.27.155.1"
203 #elif defined(CONFIG_M547X_8X)
204 #define DEFAULT_COMMAND_LINE "debug root=/dev/nfs rw nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.85:172.27.155.1"
205 #endif
206 @@ -143,14 +144,14 @@ asmlinkage void __init cf_early_init(voi
207
208 extern char _end;
209
210 -#if defined(CONFIG_M54455)
211 +#if defined(CONFIG_M5445X)
212 SET_VBR((void *)MCF_RAMBAR1);
213 #elif defined(CONFIG_M547X_8X)
214 SET_VBR((void *)MCF_RAMBAR0);
215 #endif
216
217 /* Mask all interrupts */
218 -#if defined(CONFIG_M54455)
219 +#if defined(CONFIG_M5445X)
220 MCF_INTC0_IMRL = 0xFFFFFFFF;
221 MCF_INTC0_IMRH = 0xFFFFFFFF;
222 MCF_INTC1_IMRL = 0xFFFFFFFF;
223 @@ -160,7 +161,7 @@ asmlinkage void __init cf_early_init(voi
224 MCF_IMRH = 0xFFFFFFFF;
225 #endif
226
227 -#if defined(CONFIG_M54455)
228 +#if defined(CONFIG_M5445X)
229 #if defined(CONFIG_NOR_FLASH_BASE)
230 MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
231 #else
232 @@ -171,9 +172,9 @@ asmlinkage void __init cf_early_init(voi
233 /* Init optional SDRAM chip select */
234 MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
235 #endif
236 -#endif /* CONFIG_M54455 */
237 +#endif /* CONFIG_M5445X */
238
239 -#if defined(CONFIG_M54455)
240 +#if defined(CONFIG_M5445X)
241 /* Setup SDRAM crossbar(XBS) priorities */
242 MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
243 MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
244 @@ -193,6 +194,7 @@ asmlinkage void __init cf_early_init(voi
245 m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
246 m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
247
248 +#if 0
249 if (!uboot_commandline(m68k_command_line)) {
250 #if defined(CONFIG_BOOTPARAM)
251 strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
252 @@ -200,6 +202,10 @@ asmlinkage void __init cf_early_init(voi
253 strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
254 #endif
255 }
256 +#endif
257 +/* JKM -- temporary! */
258 +strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
259 +/* JKM -- temporary! */
260
261 #if defined(CONFIG_BLK_DEV_INITRD)
262 /* add initrd image */
263 @@ -223,9 +229,10 @@ asmlinkage void __init cf_early_init(voi
264
265 /* Turn on caches via CACR, enable EUSP */
266 cacr_set(CACHE_INITIAL_MODE);
267 +
268 }
269
270 -#if defined(CONFIG_M54455)
271 +#if defined(CONFIG_M5445X)
272 void settimericr(unsigned int timer, unsigned int level)
273 {
274 volatile unsigned char *icrp;
275 @@ -256,7 +263,7 @@ void __init coldfire_trap_init(void)
276 int i = 0;
277 e_vector *vectors;
278
279 -#if defined(CONFIG_M54455)
280 +#if defined(CONFIG_M5445X)
281 vectors = (e_vector *)MCF_RAMBAR1;
282 #elif defined(CONFIG_M547X_8X)
283 vectors = (e_vector *)MCF_RAMBAR0;
284 @@ -281,7 +288,7 @@ void __init coldfire_trap_init(void)
285 vectors[32] = system_call;
286 }
287
288 -#if defined(CONFIG_M54455)
289 +#if defined(CONFIG_M5445X)
290
291 void coldfire_tick(void)
292 {
293 @@ -369,7 +376,7 @@ unsigned long coldfire_gettimeoffset(voi
294
295 void coldfire_reboot(void)
296 {
297 -#if defined(CONFIG_M54455)
298 +#if defined(CONFIG_M5445X)
299 /* disable interrupts and do a software reset */
300 asm("movew #0x2700, %%sr\n\t"
301 "moveb #0x80, %%d0\n\t"
302 --- a/arch/m68k/coldfire/head.S
303 +++ b/arch/m68k/coldfire/head.S
304 @@ -63,8 +63,8 @@
305 * None currently (mapped via TLBs)
306 */
307
308 -#if CONFIG_SDRAM_BASE != PAGE_BASE
309 -#if defined(CONFIG_M54455)
310 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
311 +#if defined(CONFIG_M5445X)
312 #if 0
313 #define ACR0_DEFAULT #0xA00FA048 /* ACR0 default value */
314 #endif
315 @@ -85,7 +85,11 @@
316 #endif
317
318 #else
319 -#if defined(CONFIG_M54455)
320 +#if defined(CONFIG_M5445X)
321 +#define ACR0_DEFAULT #0xF00FC040 /* ACR0 default value */
322 +#define ACR1_DEFAULT #0x400FA008 /* ACR1 default value */
323 +#define ACR2_DEFAULT #0x00000000 /* ACR2 default value */
324 +#define ACR3_DEFAULT #0x400FA008 /* ACR3 default value */
325 #elif defined(CONFIG_M547X_8X)
326 #define ACR0_DEFAULT #0xF00FC040 /* ACR0 default value */
327 #define ACR1_DEFAULT #0x000FA008 /* ACR1 default value */
328 @@ -280,7 +284,7 @@ ENTRY(__start)
329 subl %a0,%a0
330 movel %a0,%usp
331
332 -#if defined(CONFIG_M54455)
333 +#if defined(CONFIG_M5445X)
334 movel #(MCF_RAMBAR1 + 0x221), %d0
335 movec %d0, %rambar1
336 #elif defined(CONFIG_M547X_8X)
337 @@ -331,12 +335,11 @@ _loop_bss:
338 cmpl %a0,%a1
339 bne _loop_bss
340 #endif
341 -
342 /* If you change the memory size to another value make a matching
343 change in paging_init(cf-mmu.c) to zones_size[]. */
344
345 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
346 -#if defined(CONFIG_M54455)
347 +#if defined(CONFIG_M5445X)
348 /* Map 256MB as code */
349 mmu_map (PAGE_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
350 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC, MMUDR_SP, \
351 @@ -502,7 +505,7 @@ _loop_bss:
352 * enabled and we are executing in high memory.
353 */
354
355 -#if defined(CONFIG_M54455)
356 +#if defined(CONFIG_M5445X)
357 /* Map first 16 MB as code */
358 mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
359 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC, MMUDR_SP, 0, \
360 @@ -562,7 +565,7 @@ ENTRY(__running_high)
361
362 /* Unmap unity mappings */
363 #if CONFIG_SDRAM_BASE != PAGE_OFFSET
364 -#if defined(CONFIG_M54455)
365 +#if defined(CONFIG_M5445X)
366 mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
367 mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
368 #elif defined(CONFIG_M547X_8X)
369 @@ -599,9 +602,9 @@ func_start set_context,%d0,(1*4)
370 movec %d0,%asid
371 func_return set_context
372
373 -#ifdef CONFIG_M54455
374 +#ifdef CONFIG_M5445X
375 /*
376 - * set_fpga(addr,val) on the M54455EVB
377 + * set_fpga(addr,val) on the M5445X
378 *
379 * Map in 0x00000000 -> 0x0fffffff and then do the write.
380 */
381 --- a/arch/m68k/coldfire/ints.c
382 +++ b/arch/m68k/coldfire/ints.c
383 @@ -47,7 +47,7 @@ static int irq_depth[SYS_IRQS];
384 /*
385 * IRQ Controller
386 */
387 -#if defined(CONFIG_M54455)
388 +#if defined(CONFIG_M5445X)
389 void m5445x_irq_enable(unsigned int irq);
390 void m5445x_irq_disable(unsigned int irq);
391 static struct irq_controller m5445x_irq_controller = {
392 @@ -87,7 +87,7 @@ void __init init_IRQ(void)
393 {
394 int i;
395
396 -#if defined(CONFIG_M54455)
397 +#if defined(CONFIG_M5445X)
398 for (i = 0; i < SYS_IRQS; i++)
399 irq_controller[i] = &m5445x_irq_controller;
400 #elif defined(CONFIG_M547X_8X)
401 @@ -337,7 +337,7 @@ asmlinkage void handle_badint(struct pt_
402 }
403 EXPORT_SYMBOL(handle_badint);
404
405 -#ifdef CONFIG_M54455
406 +#ifdef CONFIG_M5445X
407 /*
408 * M5445X Implementation
409 */
410 --- a/arch/m68k/kernel/dma.c
411 +++ b/arch/m68k/kernel/dma.c
412 @@ -17,7 +17,7 @@
413 void *dma_alloc_coherent(struct device *dev, size_t size,
414 dma_addr_t *handle, gfp_t flag)
415 {
416 -#ifndef CONFIG_M54455
417 +#ifndef CONFIG_M5445X
418 struct page *page, **map;
419 pgprot_t pgprot;
420 void *addr;
421 @@ -75,7 +75,7 @@ void dma_free_coherent(struct device *de
422 void *addr, dma_addr_t handle)
423 {
424 pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
425 -#ifndef CONFIG_M54455
426 +#ifndef CONFIG_M5445X
427 vfree(addr);
428 #else
429 kfree(addr);
430 --- a/arch/m68k/kernel/setup.c
431 +++ b/arch/m68k/kernel/setup.c
432 @@ -519,7 +519,7 @@ int get_hardware_list(char *buffer)
433
434 void check_bugs(void)
435 {
436 -#if !defined(CONFIG_M68KFPU_EMU) && !defined(CONFIG_M54455)
437 +#if !defined(CONFIG_M68KFPU_EMU) && !defined(CONFIG_M5445X)
438 if (m68k_fputype == 0) {
439 printk(KERN_EMERG "*** YOU DO NOT HAVE A FLOATING POINT UNIT, "
440 "WHICH IS REQUIRED BY LINUX/M68K ***\n");
441 --- a/arch/m68k/mm/kmap.c
442 +++ b/arch/m68k/mm/kmap.c
443 @@ -133,7 +133,7 @@ void __iomem *__ioremap(unsigned long ph
444 }
445 #endif
446
447 -#ifdef CONFIG_M54455
448 +#ifdef CONFIG_M5445X
449 if (physaddr >= 0xf0000000) {
450 /*
451 * On the M5445x processors an ACR is setup to map
452 --- a/drivers/crypto/Kconfig
453 +++ b/drivers/crypto/Kconfig
454 @@ -62,15 +62,15 @@ config CRYPTO_DEV_GEODE
455
456 config CRYPTO_DEV_MCFCAU
457 bool "Support for Freescale Coldfire Cryptographic Acceleration Unit (CAU)"
458 - depends on M54455
459 + depends on M5445X
460 select CRYPTO_ALGAPI
461 help
462 The cryptographic acceleration unit (CAU) is a ColdFire coprocessor
463 implementing a set of specialized operations in hardware. For example, you can
464 - find it on MCF54455.
465 + find it on MCF5445X.
466
467 config CRYPTO_DEV_MCFCAU_DES
468 - tristate "DES and Triple DES cipher algorithms (MCF54455)"
469 + tristate "DES and Triple DES cipher algorithms (MCF5445X)"
470 depends on CRYPTO_DEV_MCFCAU
471 select CRYPTO_ALGAPI
472 select CRYPTO_BLKCIPHER
473 @@ -84,7 +84,7 @@ config CRYPTO_DEV_MCFCAU_DES
474 will be called mcfcau-des.
475
476 config CRYPTO_DEV_MCFCAU_AES
477 - tristate "AES cipher algorithm (MCF54455)"
478 + tristate "AES cipher algorithm (MCF5445X)"
479 depends on CRYPTO_DEV_MCFCAU
480 select CRYPTO_ALGAPI
481 select CRYPTO_BLKCIPHER
482 @@ -98,7 +98,7 @@ config CRYPTO_DEV_MCFCAU_AES
483 will be called mcfcau-aes.
484
485 config CRYPTO_DEV_MCFCAU_MD5
486 - tristate "MD5 digest algorithm (MCF54455)"
487 + tristate "MD5 digest algorithm (MCF5445X)"
488 depends on CRYPTO_DEV_MCFCAU
489 select CRYPTO_ALGAPI
490 help
491 @@ -111,7 +111,7 @@ config CRYPTO_DEV_MCFCAU_MD5
492 will be called mcfcau-md5.
493
494 config CRYPTO_DEV_MCFCAU_SHA1
495 - tristate "SHA1 digest algorithm (MCF54455)"
496 + tristate "SHA1 digest algorithm (MCF5445X)"
497 depends on CRYPTO_DEV_MCFCAU
498 select CRYPTO_ALGAPI
499 help
500 --- a/drivers/crypto/mcfcau-aes.c
501 +++ b/drivers/crypto/mcfcau-aes.c
502 @@ -5,7 +5,7 @@
503 * Author: Andrey Butok
504 * Copyright Freescale Semiconductor Inc. 2007
505 *
506 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
507 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
508 *
509 * This program is free software; you can redistribute it and/or modify it
510 * under the terms of the GNU General Public License as published by the
511 --- a/drivers/crypto/mcfcau-des.c
512 +++ b/drivers/crypto/mcfcau-des.c
513 @@ -5,7 +5,7 @@
514 * Author: Andrey Butok
515 * Copyright Freescale Semiconductor Inc. 2007
516 *
517 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
518 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
519 *
520 * This program is free software; you can redistribute it and/or modify it
521 * under the terms of the GNU General Public License as published by the
522 --- a/drivers/crypto/mcfcau-md5.c
523 +++ b/drivers/crypto/mcfcau-md5.c
524 @@ -5,7 +5,7 @@
525 * Author: Andrey Butok
526 * Copyright Freescale Semiconductor Inc. 2007
527 *
528 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
529 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
530 *
531 * This program is free software; you can redistribute it and/or modify it
532 * under the terms of the GNU General Public License as published by the
533 --- a/drivers/crypto/mcfcau-sha1.c
534 +++ b/drivers/crypto/mcfcau-sha1.c
535 @@ -5,7 +5,7 @@
536 * Author: Andrey Butok
537 * Copyright Freescale Semiconductor Inc. 2007
538 *
539 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
540 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
541 *
542 * This program is free software; you can redistribute it and/or modify it
543 * under the terms of the GNU General Public License as published by the
544 --- a/drivers/crypto/mcfcau.c
545 +++ b/drivers/crypto/mcfcau.c
546 @@ -5,7 +5,7 @@
547 * Author: Andrey Butok
548 * Copyright Freescale Semiconductor Inc. 2007
549 *
550 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
551 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
552 *
553 * This program is free software; you can redistribute it and/or modify it
554 * under the terms of the GNU General Public License as published by the
555 --- a/drivers/crypto/mcfcau.h
556 +++ b/drivers/crypto/mcfcau.h
557 @@ -5,7 +5,7 @@
558 * Author: Andrey Butok
559 * Copyright Freescale Semiconductor Inc. 2007
560 *
561 - * NOTE: You can find the ColdFire CAU module on MCF54455 and MCF52235.
562 + * NOTE: You can find the ColdFire CAU module on MCF5445X and MCF52235.
563 *
564 * This program is free software; you can redistribute it and/or modify it
565 * under the terms of the GNU General Public License as published by the
566 --- a/drivers/net/Kconfig
567 +++ b/drivers/net/Kconfig
568 @@ -1975,7 +1975,7 @@ config 68360_ENET
569
570 config FEC
571 bool "FEC ethernet controller (of ColdFire CPUs)"
572 - depends on M523x || M527x || M5272 || M528x || M520x || M54455
573 + depends on M523x || M527x || M5272 || M528x || M520x || M5445X
574 help
575 Say Y here if you want to use the built-in 10/100 Fast ethernet
576 controller on some Motorola ColdFire processors.
577 --- a/drivers/net/fec.c
578 +++ b/drivers/net/fec.c
579 @@ -52,7 +52,7 @@
580 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
581 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
582 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
583 - defined(CONFIG_M54455)
584 + defined(CONFIG_M5445X)
585
586 #include <asm/coldfire.h>
587 #include <asm/mcfsim.h>
588 @@ -84,7 +84,7 @@ static unsigned int fec_hw[] = {
589 (MCF_MBAR+0x30000),
590 #elif defined(CONFIG_M532x)
591 (MCF_MBAR+0xfc030000),
592 -#elif defined(CONFIG_M54455)
593 +#elif defined(CONFIG_M5445X)
594 (MCF_MBAR+0xfc030000),
595 #if defined(CONFIG_FEC2)
596 (MCF_MBAR+0xfc034000),
597 @@ -179,7 +179,7 @@ typedef struct {
598 * account when setting it.
599 */
600 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
601 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455)
602 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X)
603 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
604 #else
605 #define OPT_FRAME_SIZE 0
606 @@ -1831,9 +1831,9 @@ static void __inline__ fec_uncache(unsig
607
608 /* ------------------------------------------------------------------------- */
609
610 -#elif defined(CONFIG_M54455)
611 +#elif defined(CONFIG_M5445X)
612 /*
613 - * Code specific for M54455
614 + * Code specific for M5445X
615 */
616
617 static void __inline__ fec_request_intrs(struct net_device *dev)
618 --- a/drivers/net/fec.h
619 +++ b/drivers/net/fec.h
620 @@ -14,7 +14,7 @@
621 /****************************************************************************/
622
623 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
624 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455)
625 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X)
626 /*
627 * Just figures, Motorola would have to change the offsets for
628 * registers in the same peripheral device on different models
629 --- a/drivers/serial/mcfserial.c
630 +++ b/drivers/serial/mcfserial.c
631 @@ -69,7 +69,7 @@ struct timer_list mcfrs_timer_struct;
632 #define DEFAULT_CBAUD B38400
633 #elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || \
634 defined(CONFIG_M5329EVB) || defined(CONFIG_GILBARCO) || \
635 - defined(CONFIG_M54455) || defined(CONFIG_M547X_8X)
636 + defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X)
637 #define CONSOLE_BAUD_RATE 115200
638 #define DEFAULT_CBAUD B115200
639 #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
640 @@ -102,7 +102,7 @@ static struct tty_driver *mcfrs_serial_d
641 #undef SERIAL_DEBUG_FLOW
642
643 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
644 - defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455) || \
645 + defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M5445X) || \
646 defined(CONFIG_M547X_8X)
647 #define IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
648 #else
649 @@ -1630,7 +1630,7 @@ static void mcfrs_irqinit(struct mcf_ser
650 /* GPIOs also must be initalized, depends on board */
651 break;
652 }
653 -#elif defined(CONFIG_M54455)
654 +#elif defined(CONFIG_M5445X)
655 volatile unsigned char *uartp;
656 uartp = info->addr;
657 switch (info->line) {
658 @@ -2022,7 +2022,7 @@ struct console mcfrs_console = {
659
660 static int __init mcfrs_console_init(void)
661 {
662 -#if !(defined(CONFIG_M54455) || defined(CONFIG_M547X_8X))
663 +#if !(defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X))
664 register_console(&mcfrs_console);
665 #endif
666 return 0;
667 --- a/drivers/spi/coldfire_edma.c
668 +++ b/drivers/spi/coldfire_edma.c
669 @@ -20,10 +20,10 @@
670 #include <linux/cdev.h>
671 #include <linux/seq_file.h>
672 #include <linux/proc_fs.h>
673 -#ifdef CONFIG_M54455
674 +#ifdef CONFIG_M5445X
675 #include <asm/mcf5445x_edma.h>
676 #include <asm/mcf5445x_intc.h>
677 -#endif /* CONFIG_M54455 */
678 +#endif /* CONFIG_M5445X */
679 #include <asm/coldfire_edma.h>
680
681 /*
682 --- a/drivers/spi/spi_coldfire.c
683 +++ b/drivers/spi/spi_coldfire.c
684 @@ -57,7 +57,7 @@
685 #include <asm/mcfqspi.h>
686 #include <asm/coldfire.h>
687
688 -#if defined(CONFIG_M54455)
689 +#if defined(CONFIG_M5445X)
690 #include <asm/virtconvert.h>
691
692 #define SPI_DSPI
693 --- a/drivers/spi/ssi_audio.c
694 +++ b/drivers/spi/ssi_audio.c
695 @@ -25,7 +25,7 @@
696
697 #include <asm/coldfire.h>
698 #include <asm/coldfire_edma.h>
699 -#ifdef CONFIG_M54455
700 +#ifdef CONFIG_M5445X
701 #include <asm/mcf5445x_ssi.h>
702 #include <asm/mcf5445x_ccm.h>
703 #include <asm/mcf5445x_gpio.h>
704 --- a/include/asm-m68k/cfcache.h
705 +++ b/include/asm-m68k/cfcache.h
706 @@ -40,7 +40,7 @@
707 #define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
708 #define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
709
710 -#ifdef CONFIG_M54455
711 +#ifdef CONFIG_M5445X
712 /*
713 * M5445x Cache Configuration
714 * - cache line size is 16 bytes
715 --- a/include/asm-m68k/coldfire.h
716 +++ b/include/asm-m68k/coldfire.h
717 @@ -1,9 +1,9 @@
718 #ifndef _COLDFIRE_H_
719 #define _COLDFIRE_H_
720
721 -#if defined(CONFIG_M54455)
722 +#if defined(CONFIG_M5445X)
723 #define MCF_MBAR 0x0
724 -#define MCF_RAMBAR1 0x40000000
725 +#define MCF_RAMBAR1 0x80000000
726 #define MCF_SRAM 0x80000000
727 #elif defined(CONFIG_M547X_8X)
728 #define MCF_MBAR 0xF0000000
729 --- a/include/asm-m68k/coldfire_edma.h
730 +++ b/include/asm-m68k/coldfire_edma.h
731 @@ -20,14 +20,14 @@
732 #define EDMA_DRIVER_NAME "ColdFire-eDMA"
733 #define DMA_DEV_MINOR 1
734
735 -#ifdef CONFIG_M54455
736 +#ifdef CONFIG_M5445X
737 #define EDMA_INT_CHANNEL_BASE 8
738 #define EDMA_INT_CONTROLLER_BASE 64
739 #define EDMA_INT_BASE (EDMA_INT_CHANNEL_BASE + \
740 EDMA_INT_CONTROLLER_BASE)
741 #define EDMA_CHANNELS 16
742 #define EDMA_INT_ERR 16 /* edma error interrupt */
743 -#endif /* CONFIG_M54455 */
744 +#endif /* CONFIG_M5445X */
745
746 typedef irqreturn_t (*edma_irq_handler)(int, void *);
747 typedef void (*edma_error_handler)(int, void *);
748 --- a/include/asm-m68k/mcfsim.h
749 +++ b/include/asm-m68k/mcfsim.h
750 @@ -12,7 +12,7 @@
751 #include <asm/coldfire.h>
752 #endif
753
754 -#if defined(CONFIG_M54455)
755 +#if defined(CONFIG_M5445X)
756 #include <asm/mcf5445x_intc.h>
757 #include <asm/mcf5445x_gpio.h>
758 #include <asm/mcf5445x_i2c.h>
759 --- a/include/asm-m68k/mcfuart.h
760 +++ b/include/asm-m68k/mcfuart.h
761 @@ -15,7 +15,7 @@
762 * Define the base address of the UARTS within the MBAR address
763 * space.
764 */
765 -#if defined(CONFIG_M54455)
766 +#if defined(CONFIG_M5445X)
767 #include <asm/mcf5445x_intc.h>
768 #define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
769 #define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
770 --- a/include/asm-m68k/page_offset.h
771 +++ b/include/asm-m68k/page_offset.h
772 @@ -4,7 +4,7 @@
773 #if defined(CONFIG_SUN3)
774 #define PAGE_OFFSET_RAW 0x0E000000
775
776 -#elif defined(CONFIG_M54455) || defined(CONFIG_M547X_8X)
777 +#elif defined(CONFIG_M5445X) || defined(CONFIG_M547X_8X)
778 #define PHYS_OFFSET CONFIG_SDRAM_BASE
779 #define PAGE_OFFSET_RAW (PHYS_OFFSET)
780 /* #define PAGE_OFFSET_RAW 0xC0000000 */
781 --- a/include/asm-m68k/setup.h
782 +++ b/include/asm-m68k/setup.h
783 @@ -240,7 +240,7 @@ extern unsigned long m68k_machtype;
784 #define FPU_68040 (1<<FPUB_68040)
785 #define FPU_68060 (1<<FPUB_68060)
786 #define FPU_SUNFPA (1<<FPUB_SUNFPA)
787 -#ifndef CONFIG_M54455
788 +#ifndef CONFIG_M5445X
789 #define FPU_CFV4E (1<<FPUB_CFV4E)
790 #else
791 #define FPU_CFV4E 0
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