target/linux/brcm47xx/patches-2.6.23/622-ssb-cardbus-fixes.patch

   1 --- a/drivers/ssb/driver_pcicore.c
   2 +++ b/drivers/ssb/driver_pcicore.c
   3 @@ -11,6 +11,7 @@
   4  #include <linux/ssb/ssb.h>
   5  #include <linux/pci.h>
   6  #include <linux/delay.h>
   7 +#include <linux/ssb/ssb_embedded.h>
   8
   9  #include "ssb_private.h"
  10
  11 @@ -27,6 +28,18 @@
  12         ssb_write32(pc->dev, offset, value);
  13  }
  14
  15 +static inline
  16 +u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
  17 +{
  18 +       return ssb_read16(pc->dev, offset);
  19 +}
  20 +
  21 +static inline
  22 +void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
  23 +{
  24 +       ssb_write16(pc->dev, offset, value);
  25 +}
  26 +
  27  /**************************************************
  28   * Code for hostmode operation.
  29   **************************************************/
  30 @@ -123,8 +136,10 @@
  31         u32 addr = 0;
  32         u32 tmp;
  33
  34 -       if (unlikely(pc->cardbusmode && dev > 1))
  35 +       /* We do only have one cardbus device behind the bridge. */
  36 +       if (pc->cardbusmode && (dev >= 1))
  37                 goto out;
  38 +
  39         if (bus == 0) {
  40                 /* Type 0 transaction */
  41                 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
  42 @@ -324,7 +339,16 @@
  43         pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
  44         udelay(1); /* Assertion time demanded by the PCI standard */
  45
  46 -       /*TODO cardbus mode */
  47 +       if (pc->dev->bus->has_cardbus_slot) {
  48 +               ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
  49 +               pc->cardbusmode = 1;
  50 +               /* GPIO 1 resets the bridge */
  51 +               ssb_gpio_out(pc->dev->bus, 1, 1);
  52 +               ssb_gpio_outen(pc->dev->bus, 1, 1);
  53 +               pcicore_write16(pc, SSB_PCICORE_SPROM(0),
  54 +                               pcicore_read16(pc, SSB_PCICORE_SPROM(0))
  55 +                               | 0x0400);
  56 +       }
  57
  58         /* 64MB I/O window */
  59         pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
  60 --- a/drivers/ssb/main.c
  61 +++ b/drivers/ssb/main.c
  62 @@ -559,6 +559,7 @@
  63                 goto out;
  64         memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  65         memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  66 +       bus->has_cardbus_slot = iv.has_cardbus_slot;
  67  out:
  68         return err;
  69  }
  70 --- a/include/linux/ssb/ssb.h
  71 +++ b/include/linux/ssb/ssb.h
  72 @@ -282,6 +282,8 @@
  73         struct ssb_boardinfo boardinfo;
  74         /* Contents of the SPROM. */
  75         struct ssb_sprom sprom;
  76 +       /* If the board has a cardbus slot, this is set to true. */
  77 +       bool has_cardbus_slot;
  78
  79  #ifdef CONFIG_SSB_EMBEDDED
  80         /* Lock for GPIO register access. */
  81 @@ -299,8 +301,13 @@
  82
  83  /* The initialization-invariants. */
  84  struct ssb_init_invariants {
  85 +       /* Versioning information about the PCB. */
  86         struct ssb_boardinfo boardinfo;
  87 +       /* The SPROM information. That's either stored in an
  88 +        * EEPROM or NVRAM on the board. */
  89         struct ssb_sprom sprom;
  90 +       /* If the board has a cardbus slot, this is set to true. */
  91 +       bool has_cardbus_slot;
  92  };
  93  /* Type of function to fetch the invariants. */
  94  typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
  95 --- a/include/linux/ssb/ssb_driver_pci.h
  96 +++ b/include/linux/ssb/ssb_driver_pci.h
  97 @@ -51,6 +51,11 @@
  98  #define  SSB_PCICORE_SBTOPCI1_MASK     0xFC000000
  99  #define SSB_PCICORE_SBTOPCI2           0x0108  /* Backplane to PCI translation 2 (sbtopci2) */
 100  #define  SSB_PCICORE_SBTOPCI2_MASK     0xC0000000
 101 +#define SSB_PCICORE_PCICFG0            0x0400  /* PCI config space 0 (rev >= 8) */
 102 +#define SSB_PCICORE_PCICFG1            0x0500  /* PCI config space 1 (rev >= 8) */
 103 +#define SSB_PCICORE_PCICFG2            0x0600  /* PCI config space 2 (rev >= 8) */
 104 +#define SSB_PCICORE_PCICFG3            0x0700  /* PCI config space 3 (rev >= 8) */
 105 +#define SSB_PCICORE_SPROM(wordoffset)  (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
 106
 107  /* SBtoPCIx */
 108  #define SSB_PCICORE_SBTOPCI_MEM                0x00000000