atheros: fix up the wlan mac address if the board data is missing
[openwrt.git] / target / linux / ppc40x / patches / 006-magicboxv2.patch
1 --- /dev/null
2 +++ b/arch/powerpc/boot/cuboot-magicboxv2.c
3 @@ -0,0 +1,40 @@
4 +/*
5 + * Old U-boot compatibility for Magicbox v2
6 + *
7 + * Author: Imre Kaloz <kaloz@openwrt.org>
8 + *
9 + * This program is free software; you can redistribute it and/or modify it
10 + * under the terms of the GNU General Public License version 2 as published
11 + * by the Free Software Foundation.
12 + */
13 +
14 +#include "ops.h"
15 +#include "io.h"
16 +#include "dcr.h"
17 +#include "stdio.h"
18 +#include "4xx.h"
19 +#include "44x.h"
20 +#include "cuboot.h"
21 +
22 +#define TARGET_4xx
23 +#define TARGET_405EP
24 +#include "ppcboot.h"
25 +
26 +static bd_t bd;
27 +
28 +static void magicboxv2_fixups(void)
29 +{
30 + ibm405ep_fixup_clocks(25000000);
31 + ibm4xx_sdram_fixup_memsize();
32 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
33 +}
34 +
35 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
36 + unsigned long r6, unsigned long r7)
37 +{
38 + CUBOOT_INIT();
39 + platform_ops.fixups = magicboxv2_fixups;
40 + platform_ops.exit = ibm40x_dbcr_reset;
41 + fdt_init(_dtb_start);
42 + serial_console_init();
43 +}
44 --- /dev/null
45 +++ b/arch/powerpc/boot/dts/magicboxv2.dts
46 @@ -0,0 +1,250 @@
47 +/*
48 + * Device Tree Source for Magicbox v2
49 + *
50 + * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
51 + *
52 + * Based on walnut.dts
53 + *
54 + * This file is licensed under the terms of the GNU General Public
55 + * License version 2. This program is licensed "as is" without
56 + * any warranty of any kind, whether express or implied.
57 + */
58 +
59 +/dts-v1/;
60 +
61 +/ {
62 + #address-cells = <1>;
63 + #size-cells = <1>;
64 + model = "magicboxv2";
65 + compatible = "magicboxv2";
66 + dcr-parent = <&{/cpus/cpu@0}>;
67 +
68 + aliases {
69 + ethernet0 = &EMAC0;
70 + ethernet1 = &EMAC1;
71 + serial0 = &UART0;
72 + serial1 = &UART1;
73 + };
74 +
75 + cpus {
76 + #address-cells = <1>;
77 + #size-cells = <0>;
78 +
79 + cpu@0 {
80 + device_type = "cpu";
81 + model = "PowerPC,405EP";
82 + reg = <0x00000000>;
83 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
84 + timebase-frequency = <0>; /* Filled in by zImage */
85 + i-cache-line-size = <20>;
86 + d-cache-line-size = <20>;
87 + i-cache-size = <4000>;
88 + d-cache-size = <4000>;
89 + dcr-controller;
90 + dcr-access-method = "native";
91 + };
92 + };
93 +
94 + memory {
95 + device_type = "memory";
96 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
97 + };
98 +
99 + UIC0: interrupt-controller {
100 + compatible = "ibm,uic";
101 + interrupt-controller;
102 + cell-index = <0>;
103 + dcr-reg = <0x0c0 0x009>;
104 + #address-cells = <0>;
105 + #size-cells = <0>;
106 + #interrupt-cells = <2>;
107 + };
108 +
109 + plb {
110 + compatible = "ibm,plb3";
111 + #address-cells = <1>;
112 + #size-cells = <1>;
113 + ranges;
114 + clock-frequency = <0>; /* Filled in by zImage */
115 +
116 + SDRAM0: memory-controller {
117 + compatible = "ibm,sdram-405ep";
118 + dcr-reg = <0x010 0x002>;
119 + };
120 +
121 + MAL: mcmal {
122 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
123 + dcr-reg = <0x180 0x062>;
124 + num-tx-chans = <4>;
125 + num-rx-chans = <2>;
126 + interrupt-parent = <&UIC0>;
127 + interrupts = <
128 + 0xb 0x4 /* TXEOB */
129 + 0xc 0x4 /* RXEOB */
130 + 0xa 0x4 /* SERR */
131 + 0xd 0x4 /* TXDE */
132 + 0xe 0x4 /* RXDE */>;
133 + };
134 +
135 + POB0: opb {
136 + compatible = "ibm,opb-405ep", "ibm,opb";
137 + #address-cells = <1>;
138 + #size-cells = <1>;
139 + ranges = <0xef600000 0xef600000 0x00a00000>;
140 + dcr-reg = <0x0a0 0x005>;
141 + clock-frequency = <0>; /* Filled in by zImage */
142 +
143 + UART0: serial@ef600300 {
144 + device_type = "serial";
145 + compatible = "ns16550";
146 + reg = <0xef600300 0x00000008>;
147 + virtual-reg = <0xef600300>;
148 + clock-frequency = <0>; /* Filled in by zImage */
149 + current-speed = <115200>;
150 + interrupt-parent = <&UIC0>;
151 + interrupts = <0x0 0x4>;
152 + };
153 +
154 + UART1: serial@ef600400 {
155 + device_type = "serial";
156 + compatible = "ns16550";
157 + reg = <0xef600400 0x00000008>;
158 + virtual-reg = <0xef600400>;
159 + clock-frequency = <0>; /* Filled in by zImage */
160 + current-speed = <115200>;
161 + interrupt-parent = <&UIC0>;
162 + interrupts = <0x1 0x4>;
163 + };
164 +
165 + IIC: i2c@ef600500 {
166 + compatible = "ibm,iic-405ep", "ibm,iic";
167 + reg = <0xef600500 0x00000011>;
168 + interrupt-parent = <&UIC0>;
169 + interrupts = <0x2 0x4>;
170 + };
171 +
172 + GPIO: gpio@ef600700 {
173 + compatible = "ibm,gpio-405ep";
174 + reg = <0xef600700 0x00000020>;
175 + };
176 +
177 + EMAC0: ethernet@ef600800 {
178 + linux,network-index = <0x0>;
179 + device_type = "network";
180 + compatible = "ibm,emac-405ep", "ibm,emac";
181 + interrupt-parent = <&UIC0>;
182 + interrupts = <
183 + 0xf 0x4 /* Ethernet */
184 + 0x9 0x4 /* Ethernet Wake Up */>;
185 + local-mac-address = [000000000000]; /* Filled in by zImage */
186 + reg = <0xef600800 0x00000070>;
187 + mal-device = <&MAL>;
188 + mal-tx-channel = <0>;
189 + mal-rx-channel = <0>;
190 + cell-index = <0>;
191 + max-frame-size = <0x5dc>;
192 + rx-fifo-size = <0x1000>;
193 + tx-fifo-size = <0x800>;
194 + phy-mode = "mii";
195 + phy-map = <0x00000000>;
196 + };
197 + EMAC1: ethernet@ef600900 {
198 + linux,network-index = <0x1>;
199 + device_type = "network";
200 + compatible = "ibm,emac-405ep", "ibm,emac";
201 + interrupt-parent = <&UIC0>;
202 + interrupts = <
203 + 0x11 0x4 /* Ethernet */
204 + 0x09 0x4 /* Ethernet Wake Up */>;
205 + local-mac-address = [000000000000]; /* Filled in by zImage */
206 + reg = <0xef600900 0x00000070>;
207 + mal-device = <&MAL>;
208 + mal-tx-channel = <2>;
209 + mal-rx-channel = <1>;
210 + cell-index = <1>;
211 + max-frame-size = <0x5dc>;
212 + rx-fifo-size = <0x1000>;
213 + tx-fifo-size = <0x800>;
214 + mdio-device = <&EMAC0>;
215 + phy-mode = "mii";
216 + phy-map = <0x00000001>;
217 + };
218 +
219 + };
220 +
221 + EBC0: ebc {
222 + compatible = "ibm,ebc-405ep", "ibm,ebc";
223 + dcr-reg = <0x012 0x002>;
224 + #address-cells = <2>;
225 + #size-cells = <1>;
226 + /* The ranges property is supplied by the bootwrapper
227 + * and is based on the firmware's configuration of the
228 + * EBC bridge
229 + */
230 + clock-frequency = <0>; /* Filled in by zImage */
231 +
232 + nor_flash@ffc00000 {
233 + compatible = "cfi-flash";
234 + bank-width = <2>;
235 + reg = <0x00000000 0xffc00000 0x00400000>;
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 + partition@0 {
239 + label = "linux";
240 + reg = <0x0 0x3c0000>;
241 + };
242 + partition@100000 {
243 + label = "rootfs";
244 + reg = <0x100000 0x2c0000>;
245 + };
246 + partition@3c0000 {
247 + label = "u-boot";
248 + reg = <0x3c0000 0x30000>;
249 + read-only;
250 + };
251 + };
252 + };
253 +
254 + PCI0: pci@ec000000 {
255 + device_type = "pci";
256 + #interrupt-cells = <1>;
257 + #size-cells = <2>;
258 + #address-cells = <3>;
259 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
260 + primary;
261 + reg = <0xeec00000 0x00000008 /* Config space access */
262 + 0xeed80000 0x00000004 /* IACK */
263 + 0xeed80000 0x00000004 /* Special cycle */
264 + 0xef480000 0x00000040>; /* Internal registers */
265 +
266 + /* Outbound ranges, one memory and one IO,
267 + * later cannot be changed. Chip supports a second
268 + * IO range but we don't use it for now
269 + */
270 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
271 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
272 +
273 + /* Inbound 2GB range starting at 0 */
274 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
275 +
276 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
277 + interrupt-map = <
278 + /* IDSEL 1 */
279 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
280 +
281 + /* IDSEL 2 */
282 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
283 +
284 + /* IDSEL 3 */
285 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
286 +
287 + /* IDSEL 4 */
288 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
289 + >;
290 + };
291 + };
292 +
293 + chosen {
294 + linux,stdout-path = "/plb/opb/serial@ef600300";
295 + };
296 +};
297 --- a/arch/powerpc/boot/Makefile
298 +++ b/arch/powerpc/boot/Makefile
299 @@ -69,7 +69,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
300 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
301 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
302 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
303 - cuboot-acadia.c cuboot-magicboxv1.c
304 + cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
305 src-boot := $(src-wlib) $(src-plat) empty.c
306
307 src-boot := $(addprefix $(obj)/, $(src-boot))
308 @@ -214,6 +214,7 @@ image-$(CONFIG_EP405) += dtbImage.ep40
309 image-$(CONFIG_WALNUT) += treeImage.walnut
310 image-$(CONFIG_ACADIA) += cuImage.acadia
311 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
312 +image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
313
314 # Board ports in arch/powerpc/platform/44x/Kconfig
315 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
316 --- a/arch/powerpc/platforms/40x/Kconfig
317 +++ b/arch/powerpc/platforms/40x/Kconfig
318 @@ -51,6 +51,16 @@ config MAGICBOXV1
319 help
320 This option enables support for the Magicbox v1 board.
321
322 +config MAGICBOXV2
323 + bool "Magicbox v2"
324 + depends on 40x
325 + default n
326 + select PPC40x_SIMPLE
327 + select 405EP
328 + select PCI
329 + help
330 + This option enables support for the Magicbox v2 board.
331 +
332 config MAKALU
333 bool "Makalu"
334 depends on 40x
335 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
336 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
337 @@ -52,7 +52,8 @@ machine_device_initcall(ppc40x_simple, p
338 */
339 static char *board[] __initdata = {
340 "amcc,acadia",
341 - "magicboxv1"
342 + "magicboxv1",
343 + "magicboxv2",
344 };
345
346 static int __init ppc40x_probe(void)
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