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ar71xx/all0258n: fix partition layout
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
347 {
348 u32 t;
349
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
357 }
358
359 static void ag71xx_dma_reset(struct ag71xx *ag)
360 {
361 u32 val;
362 int i;
363
364 ag71xx_dump_dma_regs(ag);
365
366 /* stop RX and TX */
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
369
370 /*
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
373 */
374 mdelay(1);
375
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
379
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
384 }
385
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 if (val)
392 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
393 ag->dev->name, val);
394
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396
397 /* mask out reserved bits */
398 val &= ~0xff000000;
399
400 if (val)
401 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
402 ag->dev->name, val);
403
404 ag71xx_dump_dma_regs(ag);
405 }
406
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
409
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
417 FIFO_CFG4_VT)
418
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
425
426 static void ag71xx_hw_stop(struct ag71xx *ag)
427 {
428 /* disable all interrupts and stop the rx/tx engine */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
430 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
431 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
432 }
433
434 static void ag71xx_hw_setup(struct ag71xx *ag)
435 {
436 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
437
438 /* setup MAC configuration registers */
439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
440
441 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
442 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
443
444 /* setup max frame length */
445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
446
447 /* setup MII interface type */
448 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
449
450 /* setup FIFO configuration registers */
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
452 if (pdata->is_ar724x) {
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
455 } else {
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
458 }
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
461 }
462
463 static void ag71xx_hw_init(struct ag71xx *ag)
464 {
465 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
466 u32 reset_mask = pdata->reset_bit;
467
468 ag71xx_hw_stop(ag);
469
470 if (pdata->is_ar724x) {
471 u32 reset_phy = reset_mask;
472
473 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
474 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
475
476 ar71xx_device_stop(reset_phy);
477 mdelay(50);
478 ar71xx_device_start(reset_phy);
479 mdelay(200);
480 }
481
482 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
483 udelay(20);
484
485 ar71xx_device_stop(reset_mask);
486 mdelay(100);
487 ar71xx_device_start(reset_mask);
488 mdelay(200);
489
490 ag71xx_hw_setup(ag);
491
492 ag71xx_dma_reset(ag);
493 }
494
495 static void ag71xx_fast_reset(struct ag71xx *ag)
496 {
497 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
498 struct net_device *dev = ag->dev;
499 u32 reset_mask = pdata->reset_bit;
500 u32 rx_ds, tx_ds;
501 u32 mii_reg;
502
503 reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
504
505 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
506 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
507 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
508
509 ar71xx_device_stop(reset_mask);
510 udelay(10);
511 ar71xx_device_start(reset_mask);
512 udelay(10);
513
514 ag71xx_dma_reset(ag);
515 ag71xx_hw_setup(ag);
516
517 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
518 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
519 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
520
521 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
522 }
523
524 static void ag71xx_hw_start(struct ag71xx *ag)
525 {
526 /* start RX engine */
527 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
528
529 /* enable interrupts */
530 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
531 }
532
533 void ag71xx_link_adjust(struct ag71xx *ag)
534 {
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
536 u32 cfg2;
537 u32 ifctl;
538 u32 fifo5;
539 u32 mii_speed;
540
541 if (!ag->link) {
542 ag71xx_hw_stop(ag);
543 netif_carrier_off(ag->dev);
544 if (netif_msg_link(ag))
545 printk(KERN_INFO "%s: link down\n", ag->dev->name);
546 return;
547 }
548
549 if (pdata->is_ar724x)
550 ag71xx_fast_reset(ag);
551
552 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
553 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
554 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
555
556 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
557 ifctl &= ~(MAC_IFCTL_SPEED);
558
559 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
560 fifo5 &= ~FIFO_CFG5_BM;
561
562 switch (ag->speed) {
563 case SPEED_1000:
564 mii_speed = MII_CTRL_SPEED_1000;
565 cfg2 |= MAC_CFG2_IF_1000;
566 fifo5 |= FIFO_CFG5_BM;
567 break;
568 case SPEED_100:
569 mii_speed = MII_CTRL_SPEED_100;
570 cfg2 |= MAC_CFG2_IF_10_100;
571 ifctl |= MAC_IFCTL_SPEED;
572 break;
573 case SPEED_10:
574 mii_speed = MII_CTRL_SPEED_10;
575 cfg2 |= MAC_CFG2_IF_10_100;
576 break;
577 default:
578 BUG();
579 return;
580 }
581
582 if (pdata->is_ar91xx)
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
584 else if (pdata->is_ar724x)
585 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
586 else
587 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
588
589 if (pdata->set_pll)
590 pdata->set_pll(ag->speed);
591
592 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
593
594 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
595 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
596 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
597 ag71xx_hw_start(ag);
598
599 netif_carrier_on(ag->dev);
600 if (netif_msg_link(ag))
601 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
602 ag->dev->name,
603 ag71xx_speed_str(ag),
604 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
605
606 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
607 ag->dev->name,
608 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
609 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
611
612 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
613 ag->dev->name,
614 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
615 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
616 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
617
618 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
619 ag->dev->name,
620 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
621 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
622 ag71xx_mii_ctrl_rr(ag));
623 }
624
625 static int ag71xx_open(struct net_device *dev)
626 {
627 struct ag71xx *ag = netdev_priv(dev);
628 int ret;
629
630 ret = ag71xx_rings_init(ag);
631 if (ret)
632 goto err;
633
634 napi_enable(&ag->napi);
635
636 netif_carrier_off(dev);
637 ag71xx_phy_start(ag);
638
639 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
640 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
641
642 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
643
644 netif_start_queue(dev);
645
646 return 0;
647
648 err:
649 ag71xx_rings_cleanup(ag);
650 return ret;
651 }
652
653 static int ag71xx_stop(struct net_device *dev)
654 {
655 struct ag71xx *ag = netdev_priv(dev);
656 unsigned long flags;
657
658 netif_carrier_off(dev);
659 ag71xx_phy_stop(ag);
660
661 spin_lock_irqsave(&ag->lock, flags);
662
663 netif_stop_queue(dev);
664
665 ag71xx_hw_stop(ag);
666 ag71xx_dma_reset(ag);
667
668 napi_disable(&ag->napi);
669 del_timer_sync(&ag->oom_timer);
670
671 spin_unlock_irqrestore(&ag->lock, flags);
672
673 ag71xx_rings_cleanup(ag);
674
675 return 0;
676 }
677
678 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
679 struct net_device *dev)
680 {
681 struct ag71xx *ag = netdev_priv(dev);
682 struct ag71xx_ring *ring = &ag->tx_ring;
683 struct ag71xx_desc *desc;
684 dma_addr_t dma_addr;
685 int i;
686
687 i = ring->curr % ring->size;
688 desc = ring->buf[i].desc;
689
690 if (!ag71xx_desc_empty(desc))
691 goto err_drop;
692
693 if (ag71xx_has_ar8216(ag))
694 ag71xx_add_ar8216_header(ag, skb);
695
696 if (skb->len <= 0) {
697 DBG("%s: packet len is too small\n", ag->dev->name);
698 goto err_drop;
699 }
700
701 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
702 DMA_TO_DEVICE);
703
704 ring->buf[i].skb = skb;
705 ring->buf[i].timestamp = jiffies;
706
707 /* setup descriptor fields */
708 desc->data = (u32) dma_addr;
709 desc->ctrl = (skb->len & DESC_PKTLEN_M);
710
711 /* flush descriptor */
712 wmb();
713
714 ring->curr++;
715 if (ring->curr == (ring->dirty + ring->size)) {
716 DBG("%s: tx queue full\n", ag->dev->name);
717 netif_stop_queue(dev);
718 }
719
720 DBG("%s: packet injected into TX queue\n", ag->dev->name);
721
722 /* enable TX engine */
723 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
724
725 return NETDEV_TX_OK;
726
727 err_drop:
728 dev->stats.tx_dropped++;
729
730 dev_kfree_skb(skb);
731 return NETDEV_TX_OK;
732 }
733
734 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
735 {
736 struct ag71xx *ag = netdev_priv(dev);
737 int ret;
738
739 switch (cmd) {
740 case SIOCETHTOOL:
741 if (ag->phy_dev == NULL)
742 break;
743
744 spin_lock_irq(&ag->lock);
745 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
746 spin_unlock_irq(&ag->lock);
747 return ret;
748
749 case SIOCSIFHWADDR:
750 if (copy_from_user
751 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
752 return -EFAULT;
753 return 0;
754
755 case SIOCGIFHWADDR:
756 if (copy_to_user
757 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
758 return -EFAULT;
759 return 0;
760
761 case SIOCGMIIPHY:
762 case SIOCGMIIREG:
763 case SIOCSMIIREG:
764 if (ag->phy_dev == NULL)
765 break;
766
767 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
768
769 default:
770 break;
771 }
772
773 return -EOPNOTSUPP;
774 }
775
776 static void ag71xx_oom_timer_handler(unsigned long data)
777 {
778 struct net_device *dev = (struct net_device *) data;
779 struct ag71xx *ag = netdev_priv(dev);
780
781 napi_schedule(&ag->napi);
782 }
783
784 static void ag71xx_tx_timeout(struct net_device *dev)
785 {
786 struct ag71xx *ag = netdev_priv(dev);
787
788 if (netif_msg_tx_err(ag))
789 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
790
791 schedule_work(&ag->restart_work);
792 }
793
794 static void ag71xx_restart_work_func(struct work_struct *work)
795 {
796 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
797
798 if (ag71xx_get_pdata(ag)->is_ar724x) {
799 ag->link = 0;
800 ag71xx_link_adjust(ag);
801 return;
802 }
803
804 ag71xx_stop(ag->dev);
805 ag71xx_open(ag->dev);
806 }
807
808 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
809 {
810 u32 rx_sm, tx_sm, rx_fd;
811
812 if (likely(time_before(jiffies, timestamp + HZ/10)))
813 return false;
814
815 if (!netif_carrier_ok(ag->dev))
816 return false;
817
818 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
819 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
820 return true;
821
822 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
823 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
824 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
825 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
826 return true;
827
828 return false;
829 }
830
831 static int ag71xx_tx_packets(struct ag71xx *ag)
832 {
833 struct ag71xx_ring *ring = &ag->tx_ring;
834 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
835 int sent;
836
837 DBG("%s: processing TX ring\n", ag->dev->name);
838
839 sent = 0;
840 while (ring->dirty != ring->curr) {
841 unsigned int i = ring->dirty % ring->size;
842 struct ag71xx_desc *desc = ring->buf[i].desc;
843 struct sk_buff *skb = ring->buf[i].skb;
844
845 if (!ag71xx_desc_empty(desc)) {
846 if (pdata->is_ar7240 &&
847 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
848 schedule_work(&ag->restart_work);
849 break;
850 }
851
852 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
853
854 ag->dev->stats.tx_bytes += skb->len;
855 ag->dev->stats.tx_packets++;
856
857 dev_kfree_skb_any(skb);
858 ring->buf[i].skb = NULL;
859
860 ring->dirty++;
861 sent++;
862 }
863
864 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
865
866 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
867 netif_wake_queue(ag->dev);
868
869 return sent;
870 }
871
872 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
873 {
874 struct net_device *dev = ag->dev;
875 struct ag71xx_ring *ring = &ag->rx_ring;
876 int done = 0;
877
878 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
879 dev->name, limit, ring->curr, ring->dirty);
880
881 while (done < limit) {
882 unsigned int i = ring->curr % ring->size;
883 struct ag71xx_desc *desc = ring->buf[i].desc;
884 struct sk_buff *skb;
885 int pktlen;
886 int err = 0;
887
888 if (ag71xx_desc_empty(desc))
889 break;
890
891 if ((ring->dirty + ring->size) == ring->curr) {
892 ag71xx_assert(0);
893 break;
894 }
895
896 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
897
898 skb = ring->buf[i].skb;
899 pktlen = ag71xx_desc_pktlen(desc);
900 pktlen -= ETH_FCS_LEN;
901
902 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
903 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
904
905 dev->last_rx = jiffies;
906 dev->stats.rx_packets++;
907 dev->stats.rx_bytes += pktlen;
908
909 skb_put(skb, pktlen);
910 if (ag71xx_has_ar8216(ag))
911 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
912
913 if (err) {
914 dev->stats.rx_dropped++;
915 kfree_skb(skb);
916 } else {
917 skb->dev = dev;
918 skb->ip_summed = CHECKSUM_NONE;
919 if (ag->phy_dev) {
920 ag->phy_dev->netif_receive_skb(skb);
921 } else {
922 skb->protocol = eth_type_trans(skb, dev);
923 netif_receive_skb(skb);
924 }
925 }
926
927 ring->buf[i].skb = NULL;
928 done++;
929
930 ring->curr++;
931 }
932
933 ag71xx_ring_rx_refill(ag);
934
935 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
936 dev->name, ring->curr, ring->dirty, done);
937
938 return done;
939 }
940
941 static int ag71xx_poll(struct napi_struct *napi, int limit)
942 {
943 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
944 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
945 struct net_device *dev = ag->dev;
946 struct ag71xx_ring *rx_ring;
947 unsigned long flags;
948 u32 status;
949 int tx_done;
950 int rx_done;
951
952 pdata->ddr_flush();
953 tx_done = ag71xx_tx_packets(ag);
954
955 DBG("%s: processing RX ring\n", dev->name);
956 rx_done = ag71xx_rx_packets(ag, limit);
957
958 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
959
960 rx_ring = &ag->rx_ring;
961 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
962 goto oom;
963
964 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
965 if (unlikely(status & RX_STATUS_OF)) {
966 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
967 dev->stats.rx_fifo_errors++;
968
969 /* restart RX */
970 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
971 }
972
973 if (rx_done < limit) {
974 if (status & RX_STATUS_PR)
975 goto more;
976
977 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
978 if (status & TX_STATUS_PS)
979 goto more;
980
981 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
982 dev->name, rx_done, tx_done, limit);
983
984 napi_complete(napi);
985
986 /* enable interrupts */
987 spin_lock_irqsave(&ag->lock, flags);
988 ag71xx_int_enable(ag, AG71XX_INT_POLL);
989 spin_unlock_irqrestore(&ag->lock, flags);
990 return rx_done;
991 }
992
993 more:
994 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
995 dev->name, rx_done, tx_done, limit);
996 return rx_done;
997
998 oom:
999 if (netif_msg_rx_err(ag))
1000 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
1001
1002 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1003 napi_complete(napi);
1004 return 0;
1005 }
1006
1007 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1008 {
1009 struct net_device *dev = dev_id;
1010 struct ag71xx *ag = netdev_priv(dev);
1011 u32 status;
1012
1013 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1014 ag71xx_dump_intr(ag, "raw", status);
1015
1016 if (unlikely(!status))
1017 return IRQ_NONE;
1018
1019 if (unlikely(status & AG71XX_INT_ERR)) {
1020 if (status & AG71XX_INT_TX_BE) {
1021 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1022 dev_err(&dev->dev, "TX BUS error\n");
1023 }
1024 if (status & AG71XX_INT_RX_BE) {
1025 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1026 dev_err(&dev->dev, "RX BUS error\n");
1027 }
1028 }
1029
1030 if (likely(status & AG71XX_INT_POLL)) {
1031 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1032 DBG("%s: enable polling mode\n", dev->name);
1033 napi_schedule(&ag->napi);
1034 }
1035
1036 ag71xx_debugfs_update_int_stats(ag, status);
1037
1038 return IRQ_HANDLED;
1039 }
1040
1041 static void ag71xx_set_multicast_list(struct net_device *dev)
1042 {
1043 /* TODO */
1044 }
1045
1046 #ifdef CONFIG_NET_POLL_CONTROLLER
1047 /*
1048 * Polling 'interrupt' - used by things like netconsole to send skbs
1049 * without having to re-enable interrupts. It's not called while
1050 * the interrupt routine is executing.
1051 */
1052 static void ag71xx_netpoll(struct net_device *dev)
1053 {
1054 disable_irq(dev->irq);
1055 ag71xx_interrupt(dev->irq, dev);
1056 enable_irq(dev->irq);
1057 }
1058 #endif
1059
1060 static const struct net_device_ops ag71xx_netdev_ops = {
1061 .ndo_open = ag71xx_open,
1062 .ndo_stop = ag71xx_stop,
1063 .ndo_start_xmit = ag71xx_hard_start_xmit,
1064 .ndo_set_multicast_list = ag71xx_set_multicast_list,
1065 .ndo_do_ioctl = ag71xx_do_ioctl,
1066 .ndo_tx_timeout = ag71xx_tx_timeout,
1067 .ndo_change_mtu = eth_change_mtu,
1068 .ndo_set_mac_address = eth_mac_addr,
1069 .ndo_validate_addr = eth_validate_addr,
1070 #ifdef CONFIG_NET_POLL_CONTROLLER
1071 .ndo_poll_controller = ag71xx_netpoll,
1072 #endif
1073 };
1074
1075 static int __devinit ag71xx_probe(struct platform_device *pdev)
1076 {
1077 struct net_device *dev;
1078 struct resource *res;
1079 struct ag71xx *ag;
1080 struct ag71xx_platform_data *pdata;
1081 int err;
1082
1083 pdata = pdev->dev.platform_data;
1084 if (!pdata) {
1085 dev_err(&pdev->dev, "no platform data specified\n");
1086 err = -ENXIO;
1087 goto err_out;
1088 }
1089
1090 if (pdata->mii_bus_dev == NULL) {
1091 dev_err(&pdev->dev, "no MII bus device specified\n");
1092 err = -EINVAL;
1093 goto err_out;
1094 }
1095
1096 dev = alloc_etherdev(sizeof(*ag));
1097 if (!dev) {
1098 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1099 err = -ENOMEM;
1100 goto err_out;
1101 }
1102
1103 SET_NETDEV_DEV(dev, &pdev->dev);
1104
1105 ag = netdev_priv(dev);
1106 ag->pdev = pdev;
1107 ag->dev = dev;
1108 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1109 AG71XX_DEFAULT_MSG_ENABLE);
1110 spin_lock_init(&ag->lock);
1111
1112 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1113 if (!res) {
1114 dev_err(&pdev->dev, "no mac_base resource found\n");
1115 err = -ENXIO;
1116 goto err_out;
1117 }
1118
1119 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1120 if (!ag->mac_base) {
1121 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1122 err = -ENOMEM;
1123 goto err_free_dev;
1124 }
1125
1126 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1127 if (!res) {
1128 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1129 err = -ENXIO;
1130 goto err_unmap_base;
1131 }
1132
1133 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1134 if (!ag->mii_ctrl) {
1135 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1136 err = -ENOMEM;
1137 goto err_unmap_base;
1138 }
1139
1140 dev->irq = platform_get_irq(pdev, 0);
1141 err = request_irq(dev->irq, ag71xx_interrupt,
1142 IRQF_DISABLED,
1143 dev->name, dev);
1144 if (err) {
1145 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1146 goto err_unmap_mii_ctrl;
1147 }
1148
1149 dev->base_addr = (unsigned long)ag->mac_base;
1150 dev->netdev_ops = &ag71xx_netdev_ops;
1151 dev->ethtool_ops = &ag71xx_ethtool_ops;
1152
1153 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1154
1155 init_timer(&ag->oom_timer);
1156 ag->oom_timer.data = (unsigned long) dev;
1157 ag->oom_timer.function = ag71xx_oom_timer_handler;
1158
1159 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1160 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1161
1162 ag->stop_desc = dma_alloc_coherent(NULL,
1163 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1164
1165 if (!ag->stop_desc)
1166 goto err_free_irq;
1167
1168 ag->stop_desc->data = 0;
1169 ag->stop_desc->ctrl = 0;
1170 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1171
1172 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1173
1174 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1175
1176 err = register_netdev(dev);
1177 if (err) {
1178 dev_err(&pdev->dev, "unable to register net device\n");
1179 goto err_free_desc;
1180 }
1181
1182 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1183 dev->name, dev->base_addr, dev->irq);
1184
1185 ag71xx_dump_regs(ag);
1186
1187 ag71xx_hw_init(ag);
1188
1189 ag71xx_dump_regs(ag);
1190
1191 err = ag71xx_phy_connect(ag);
1192 if (err)
1193 goto err_unregister_netdev;
1194
1195 err = ag71xx_debugfs_init(ag);
1196 if (err)
1197 goto err_phy_disconnect;
1198
1199 platform_set_drvdata(pdev, dev);
1200
1201 return 0;
1202
1203 err_phy_disconnect:
1204 ag71xx_phy_disconnect(ag);
1205 err_unregister_netdev:
1206 unregister_netdev(dev);
1207 err_free_desc:
1208 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1209 ag->stop_desc_dma);
1210 err_free_irq:
1211 free_irq(dev->irq, dev);
1212 err_unmap_mii_ctrl:
1213 iounmap(ag->mii_ctrl);
1214 err_unmap_base:
1215 iounmap(ag->mac_base);
1216 err_free_dev:
1217 kfree(dev);
1218 err_out:
1219 platform_set_drvdata(pdev, NULL);
1220 return err;
1221 }
1222
1223 static int __devexit ag71xx_remove(struct platform_device *pdev)
1224 {
1225 struct net_device *dev = platform_get_drvdata(pdev);
1226
1227 if (dev) {
1228 struct ag71xx *ag = netdev_priv(dev);
1229
1230 ag71xx_debugfs_exit(ag);
1231 ag71xx_phy_disconnect(ag);
1232 unregister_netdev(dev);
1233 free_irq(dev->irq, dev);
1234 iounmap(ag->mii_ctrl);
1235 iounmap(ag->mac_base);
1236 kfree(dev);
1237 platform_set_drvdata(pdev, NULL);
1238 }
1239
1240 return 0;
1241 }
1242
1243 static struct platform_driver ag71xx_driver = {
1244 .probe = ag71xx_probe,
1245 .remove = __exit_p(ag71xx_remove),
1246 .driver = {
1247 .name = AG71XX_DRV_NAME,
1248 }
1249 };
1250
1251 static int __init ag71xx_module_init(void)
1252 {
1253 int ret;
1254
1255 ret = ag71xx_debugfs_root_init();
1256 if (ret)
1257 goto err_out;
1258
1259 ret = ag71xx_mdio_driver_init();
1260 if (ret)
1261 goto err_debugfs_exit;
1262
1263 ret = platform_driver_register(&ag71xx_driver);
1264 if (ret)
1265 goto err_mdio_exit;
1266
1267 return 0;
1268
1269 err_mdio_exit:
1270 ag71xx_mdio_driver_exit();
1271 err_debugfs_exit:
1272 ag71xx_debugfs_root_exit();
1273 err_out:
1274 return ret;
1275 }
1276
1277 static void __exit ag71xx_module_exit(void)
1278 {
1279 platform_driver_unregister(&ag71xx_driver);
1280 ag71xx_mdio_driver_exit();
1281 ag71xx_debugfs_root_exit();
1282 }
1283
1284 module_init(ag71xx_module_init);
1285 module_exit(ag71xx_module_exit);
1286
1287 MODULE_VERSION(AG71XX_DRV_VERSION);
1288 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1289 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1290 MODULE_LICENSE("GPL v2");
1291 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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