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[cavium-octeon] add missing patches
[openwrt.git] / target / linux / cavium-octeon / patches / 003_pci_pcie_support.patch
1 This patch adds support for PCI and PCIe to the base Cavium OCTEON
2 processor support.
3
4 Signed-off-by: David Daney <ddaney@caviumnetworks.com>
5 ---
6 arch/mips/Kconfig | 2 +
7 arch/mips/cavium-octeon/Makefile | 4 +
8 arch/mips/cavium-octeon/dma-octeon.c | 310 ++++++-
9 arch/mips/cavium-octeon/executive/Makefile | 2 +
10 .../cavium-octeon/executive/cvmx-helper-errata.c | 379 +++++++
11 .../cavium-octeon/executive/cvmx-helper-util.c | 502 ++++++++++
12 arch/mips/cavium-octeon/executive/cvmx-pcie.c | 1053 ++++++++++++++++++++
13 arch/mips/cavium-octeon/msi.c | 288 ++++++
14 arch/mips/cavium-octeon/octeon-irq.c | 2 +
15 arch/mips/cavium-octeon/pci-common.c | 137 +++
16 arch/mips/cavium-octeon/pci-common.h | 39 +
17 arch/mips/cavium-octeon/pci.c | 568 +++++++++++
18 arch/mips/cavium-octeon/pcie.c | 441 ++++++++
19 arch/mips/include/asm/octeon/cvmx-asm.h | 3 +-
20 arch/mips/include/asm/octeon/cvmx-helper-errata.h | 92 ++
21 arch/mips/include/asm/octeon/cvmx-helper-util.h | 266 +++++
22 arch/mips/include/asm/octeon/cvmx-packet.h | 16 +-
23 arch/mips/include/asm/octeon/cvmx-pcie.h | 284 ++++++
24 arch/mips/include/asm/octeon/cvmx-wqe.h | 422 ++++++++
25 arch/mips/include/asm/octeon/cvmx.h | 12 +
26 arch/mips/include/asm/octeon/octeon.h | 2 +
27 21 files changed, 4816 insertions(+), 8 deletions(-)
28 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
29 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-util.c
30 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-pcie.c
31 create mode 100644 arch/mips/cavium-octeon/msi.c
32 create mode 100644 arch/mips/cavium-octeon/pci-common.c
33 create mode 100644 arch/mips/cavium-octeon/pci-common.h
34 create mode 100644 arch/mips/cavium-octeon/pci.c
35 create mode 100644 arch/mips/cavium-octeon/pcie.c
36 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-errata.h
37 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-util.h
38 create mode 100644 arch/mips/include/asm/octeon/cvmx-pcie.h
39 create mode 100644 arch/mips/include/asm/octeon/cvmx-wqe.h
40
41 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
42 index ea2b262..f009496 100644
43 --- a/arch/mips/Kconfig
44 +++ b/arch/mips/Kconfig
45 @@ -620,6 +620,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
46 select SYS_HAS_EARLY_PRINTK
47 select CPU_CAVIUM_OCTEON
48 select SWAP_IO_SPACE
49 + select HW_HAS_PCI
50 + select ARCH_SUPPORTS_MSI
51 help
52 This option supports all of the Octeon reference boards from Cavium
53 Networks. It builds a kernel that dynamically determines the Octeon
54 diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
55 index 1c2a7fa..2b5f08f 100644
56 --- a/arch/mips/cavium-octeon/Makefile
57 +++ b/arch/mips/cavium-octeon/Makefile
58 @@ -14,3 +14,7 @@ obj-y += dma-octeon.o flash_setup.o
59 obj-y += octeon-memcpy.o
60
61 obj-$(CONFIG_SMP) += smp.o
62 +obj-$(CONFIG_PCI) += pci-common.o
63 +obj-$(CONFIG_PCI) += pci.o
64 +obj-$(CONFIG_PCI) += pcie.o
65 +obj-$(CONFIG_PCI_MSI) += msi.o
66 diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
67 index 01b1ef9..af3c26f 100644
68 --- a/arch/mips/cavium-octeon/dma-octeon.c
69 +++ b/arch/mips/cavium-octeon/dma-octeon.c
70 @@ -13,20 +13,326 @@
71 */
72 #include <linux/types.h>
73 #include <linux/mm.h>
74 +#include <linux/module.h>
75 +#include <linux/string.h>
76 +#include <linux/dma-mapping.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/scatterlist.h>
79 +
80 +#include <linux/cache.h>
81 +#include <linux/io.h>
82 +
83 +#include <asm/octeon/octeon.h>
84 +#include <asm/octeon/cvmx-npi-defs.h>
85 +#include <asm/octeon/cvmx-pci-defs.h>
86
87 #include <dma-coherence.h>
88
89 +#ifdef CONFIG_PCI
90 +#include "pci-common.h"
91 +#endif
92 +
93 +#define BAR2_PCI_ADDRESS 0x8000000000ul
94 +
95 +struct bar1_index_state {
96 + int16_t ref_count; /* Number of PCI mappings using this index */
97 + uint16_t address_bits; /* Upper bits of physical address. This is
98 + shifted 22 bits */
99 +};
100 +
101 +#ifdef CONFIG_PCI
102 +static DEFINE_SPINLOCK(bar1_lock);
103 +static struct bar1_index_state bar1_state[32];
104 +#endif
105 +
106 dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
107 {
108 +#ifndef CONFIG_PCI
109 /* Without PCI/PCIe this function can be called for Octeon internal
110 devices such as USB. These devices all support 64bit addressing */
111 mb();
112 return virt_to_phys(ptr);
113 +#else
114 + unsigned long flags;
115 + uint64_t dma_mask;
116 + int64_t start_index;
117 + dma_addr_t result = -1;
118 + uint64_t physical = virt_to_phys(ptr);
119 + int64_t index;
120 +
121 + mb();
122 + /*
123 + * Use the DMA masks to determine the allowed memory
124 + * region. For us it doesn't limit the actual memory, just the
125 + * address visible over PCI. Devices with limits need to use
126 + * lower indexed Bar1 entries.
127 + */
128 + if (dev) {
129 + dma_mask = dev->coherent_dma_mask;
130 + if (dev->dma_mask)
131 + dma_mask = *dev->dma_mask;
132 + } else
133 + dma_mask = 0xfffffffful;
134 +
135 + /*
136 + * Platform devices, such as the internal USB, skip all
137 + * translation and use Octeon physical addresses directly.
138 + */
139 + if (dev->bus == &platform_bus_type)
140 + return physical;
141 +
142 + switch (octeon_dma_bar_type) {
143 + case OCTEON_DMA_BAR_TYPE_PCIE:
144 + if (unlikely(physical < (16ul << 10)))
145 + panic("dma_map_single: Not allowed to map first 16KB."
146 + " It interferes with BAR0 special area\n");
147 + else if ((physical + size >= (256ul << 20)) &&
148 + (physical < (512ul << 20)))
149 + panic("dma_map_single: Not allowed to map bootbus\n");
150 + else if ((physical + size >= 0x400000000ull) &&
151 + physical < 0x410000000ull)
152 + panic("dma_map_single: "
153 + "Attempt to map illegal memory address 0x%lx\n",
154 + physical);
155 + else if (physical >= 0x420000000ull)
156 + panic("dma_map_single: "
157 + "Attempt to map illegal memory address 0x%lx\n",
158 + physical);
159 + else if ((physical + size >=
160 + (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
161 + && physical < (4ull<<30))
162 + pr_warning("dma_map_single: Warning: "
163 + "Mapping memory address that might "
164 + "conflict with devices 0x%lx-0x%lx\n",
165 + physical, physical+size-1);
166 + /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
167 + if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
168 + result = physical - 0x400000000ull;
169 + else
170 + result = physical;
171 + if (((result+size-1) & dma_mask) != result+size-1)
172 + panic("dma_map_single: Attempt to map address "
173 + "0x%lx-0x%lx, which can't be accessed according "
174 + "to the dma mask 0x%lx\n",
175 + physical, physical+size-1, dma_mask);
176 + goto done;
177 +
178 + case OCTEON_DMA_BAR_TYPE_BIG:
179 +#ifdef CONFIG_64BIT
180 + /* If the device supports 64bit addressing, then use BAR2 */
181 + if (dma_mask > BAR2_PCI_ADDRESS) {
182 + result = physical + BAR2_PCI_ADDRESS;
183 + goto done;
184 + }
185 +#endif
186 + if (unlikely(physical < (4ul << 10))) {
187 + panic("dma_map_single: Not allowed to map first 4KB. "
188 + "It interferes with BAR0 special area\n");
189 + } else if (physical < (256ul << 20)) {
190 + if (unlikely(physical + size > (256ul << 20)))
191 + panic("dma_map_single: Requested memory spans "
192 + "Bar0 0:256MB and bootbus\n");
193 + result = physical;
194 + goto done;
195 + } else if (unlikely(physical < (512ul << 20))) {
196 + panic("dma_map_single: Not allowed to map bootbus\n");
197 + } else if (physical < (2ul << 30)) {
198 + if (unlikely(physical + size > (2ul << 30)))
199 + panic("dma_map_single: Requested memory spans "
200 + "Bar0 512MB:2GB and BAR1\n");
201 + result = physical;
202 + goto done;
203 + } else if (physical < (2ul << 30) + (128 << 20)) {
204 + /* Fall through */
205 + } else if (physical <
206 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
207 + if (unlikely
208 + (physical + size >
209 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
210 + panic("dma_map_single: Requested memory "
211 + "extends past Bar1 (4GB-%luMB)\n",
212 + OCTEON_PCI_BAR1_HOLE_SIZE);
213 + result = physical;
214 + goto done;
215 + } else if ((physical >= 0x410000000ull) &&
216 + (physical < 0x420000000ull)) {
217 + if (unlikely(physical + size > 0x420000000ull))
218 + panic("dma_map_single: Requested memory spans "
219 + "non existant memory\n");
220 + /* BAR0 fixed mapping 256MB:512MB ->
221 + * 16GB+256MB:16GB+512MB */
222 + result = physical - 0x400000000ull;
223 + goto done;
224 + } else {
225 + /* Continued below switch statement */
226 + }
227 + break;
228 +
229 + case OCTEON_DMA_BAR_TYPE_SMALL:
230 +#ifdef CONFIG_64BIT
231 + /* If the device supports 64bit addressing, then use BAR2 */
232 + if (dma_mask > BAR2_PCI_ADDRESS) {
233 + result = physical + BAR2_PCI_ADDRESS;
234 + goto done;
235 + }
236 +#endif
237 + /* Continued below switch statement */
238 + break;
239 +
240 + default:
241 + panic("dma_map_single: Invalid octeon_dma_bar_type\n");
242 + }
243 +
244 + /* Don't allow mapping to span multiple Bar entries. The hardware guys
245 + won't guarantee that DMA across boards work */
246 + if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
247 + panic("dma_map_single: "
248 + "Requested memory spans more than one Bar1 entry\n");
249 +
250 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
251 + start_index = 31;
252 + else if (unlikely(dma_mask < (1ul << 27)))
253 + start_index = (dma_mask >> 22);
254 + else
255 + start_index = 31;
256 +
257 + /* Only one processor can access the Bar register at once */
258 + spin_lock_irqsave(&bar1_lock, flags);
259 +
260 + /* Look through Bar1 for existing mapping that will work */
261 + for (index = start_index; index >= 0; index--) {
262 + if ((bar1_state[index].address_bits == physical >> 22) &&
263 + (bar1_state[index].ref_count)) {
264 + /* An existing mapping will work, use it */
265 + bar1_state[index].ref_count++;
266 + if (unlikely(bar1_state[index].ref_count < 0))
267 + panic("dma_map_single: "
268 + "Bar1[%d] reference count overflowed\n",
269 + (int) index);
270 + result = (index << 22) | (physical & ((1 << 22) - 1));
271 + /* Large BAR1 is offset at 2GB */
272 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
273 + result += 2ul << 30;
274 + goto done_unlock;
275 + }
276 + }
277 +
278 + /* No existing mappings, look for a free entry */
279 + for (index = start_index; index >= 0; index--) {
280 + if (unlikely(bar1_state[index].ref_count == 0)) {
281 + union cvmx_pci_bar1_indexx bar1_index;
282 + /* We have a free entry, use it */
283 + bar1_state[index].ref_count = 1;
284 + bar1_state[index].address_bits = physical >> 22;
285 + bar1_index.u32 = 0;
286 + /* Address bits[35:22] sent to L2C */
287 + bar1_index.s.addr_idx = physical >> 22;
288 + /* Don't put PCI accesses in L2. */
289 + bar1_index.s.ca = 1;
290 + /* Endian Swap Mode */
291 + bar1_index.s.end_swp = 1;
292 + /* Set '1' when the selected address range is valid. */
293 + bar1_index.s.addr_v = 1;
294 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
295 + bar1_index.u32);
296 + /* An existing mapping will work, use it */
297 + result = (index << 22) | (physical & ((1 << 22) - 1));
298 + /* Large BAR1 is offset at 2GB */
299 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
300 + result += 2ul << 30;
301 + goto done_unlock;
302 + }
303 + }
304 +
305 + pr_err("dma_map_single: "
306 + "Can't find empty BAR1 index for physical mapping 0x%llx\n",
307 + (unsigned long long) physical);
308 +
309 +done_unlock:
310 + spin_unlock_irqrestore(&bar1_lock, flags);
311 +done:
312 + pr_debug("dma_map_single 0x%lx->0x%lx\n", physical, result);
313 + return result;
314 +#endif
315 }
316
317 void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
318 {
319 - /* Without PCI/PCIe this function can be called for Octeon internal
320 - * devices such as USB. These devices all support 64bit addressing */
321 +#ifndef CONFIG_PCI
322 + /*
323 + * Without PCI/PCIe this function can be called for Octeon internal
324 + * devices such as USB. These devices all support 64bit addressing.
325 + */
326 + return;
327 +#else
328 + unsigned long flags;
329 + uint64_t index;
330 +
331 + /*
332 + * Platform devices, such as the internal USB, skip all
333 + * translation and use Octeon physical addresses directly.
334 + */
335 + if (dev->bus == &platform_bus_type)
336 + return;
337 +
338 + switch (octeon_dma_bar_type) {
339 + case OCTEON_DMA_BAR_TYPE_PCIE:
340 + /* Nothing to do, all mappings are static */
341 + goto done;
342 +
343 + case OCTEON_DMA_BAR_TYPE_BIG:
344 +#ifdef CONFIG_64BIT
345 + /* Nothing to do for addresses using BAR2 */
346 + if (dma_addr >= BAR2_PCI_ADDRESS)
347 + goto done;
348 +#endif
349 + if (unlikely(dma_addr < (4ul << 10)))
350 + panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
351 + dma_addr);
352 + else if (dma_addr < (2ul << 30))
353 + /* Nothing to do for addresses using BAR0 */
354 + goto done;
355 + else if (dma_addr < (2ul << 30) + (128ul << 20))
356 + /* Need to unmap, fall through */
357 + index = (dma_addr - (2ul << 30)) >> 22;
358 + else if (dma_addr <
359 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
360 + goto done; /* Nothing to do for the rest of BAR1 */
361 + else
362 + panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
363 + dma_addr);
364 + /* Continued below switch statement */
365 + break;
366 +
367 + case OCTEON_DMA_BAR_TYPE_SMALL:
368 +#ifdef CONFIG_64BIT
369 + /* Nothing to do for addresses using BAR2 */
370 + if (dma_addr >= BAR2_PCI_ADDRESS)
371 + goto done;
372 +#endif
373 + index = dma_addr >> 22;
374 + /* Continued below switch statement */
375 + break;
376 +
377 + default:
378 + panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
379 + }
380 +
381 + if (unlikely(index > 31))
382 + panic("dma_unmap_single: "
383 + "Attempt to unmap an invalid address (0x%llx)\n",
384 + (unsigned long long) dma_addr);
385 +
386 + spin_lock_irqsave(&bar1_lock, flags);
387 + bar1_state[index].ref_count--;
388 + if (bar1_state[index].ref_count == 0)
389 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
390 + else if (unlikely(bar1_state[index].ref_count < 0))
391 + panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
392 + (int) index);
393 + spin_unlock_irqrestore(&bar1_lock, flags);
394 +done:
395 + pr_debug("dma_unmap_single 0x%lx\n", dma_addr);
396 return;
397 +#endif
398 }
399 diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
400 index 80d6cb2..9b470dd 100644
401 --- a/arch/mips/cavium-octeon/executive/Makefile
402 +++ b/arch/mips/cavium-octeon/executive/Makefile
403 @@ -11,3 +11,5 @@
404
405 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
406
407 +obj-$(CONFIG_PCI) += cvmx-pcie.o
408 +obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-util.o
409 diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
410 new file mode 100644
411 index 0000000..98822c1
412 --- /dev/null
413 +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
414 @@ -0,0 +1,379 @@
415 +/***********************license start***************
416 + * Author: Cavium Networks
417 + *
418 + * Contact: support@caviumnetworks.com
419 + * This file is part of the OCTEON SDK
420 + *
421 + * Copyright (c) 2003-2008 Cavium Networks
422 + *
423 + * This file is free software; you can redistribute it and/or modify
424 + * it under the terms of the GNU General Public License, Version 2, as
425 + * published by the Free Software Foundation.
426 + *
427 + * This file is distributed in the hope that it will be useful, but
428 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
429 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
430 + * NONINFRINGEMENT. See the GNU General Public License for more
431 + * details.
432 + *
433 + * You should have received a copy of the GNU General Public License
434 + * along with this file; if not, write to the Free Software
435 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
436 + * or visit http://www.gnu.org/licenses/.
437 + *
438 + * This file may also be available under a different license from Cavium.
439 + * Contact Cavium Networks for more information
440 + ***********************license end**************************************/
441 +
442 +/**
443 + *
444 + * Fixes and workaround for Octeon chip errata. This file
445 + * contains functions called by cvmx-helper to workaround known
446 + * chip errata. For the most part, code doesn't need to call
447 + * these functions directly.
448 + *
449 + */
450 +#include <asm/octeon/octeon.h>
451 +
452 +#include <asm/octeon/cvmx-helper-util.h>
453 +
454 +#ifdef CVMX_ENABLE_PKO_FUNCTIONS
455 +
456 +/**
457 + * @INTERNAL
458 + * Function to adjust internal IPD pointer alignments
459 + *
460 + * Returns 0 on success
461 + * !0 on failure
462 + */
463 +int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
464 +{
465 +#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \
466 + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_FIRST_MBUFF_SKIP)
467 +#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \
468 + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
469 +#define FIX_IPD_OUTPORT 0
470 + /* Ports 0-15 are interface 0, 16-31 are interface 1 */
471 +#define INTERFACE(port) (port >> 4)
472 +#define INDEX(port) (port & 0xf)
473 + uint64_t *p64;
474 + cvmx_pko_command_word0_t pko_command;
475 + cvmx_buf_ptr_t g_buffer, pkt_buffer;
476 + cvmx_wqe_t *work;
477 + int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
478 + cvmx_gmxx_prtx_cfg_t gmx_cfg;
479 + int retry_cnt;
480 + int retry_loop_cnt;
481 + int mtu;
482 + int i;
483 + cvmx_helper_link_info_t link_info;
484 +
485 + /* Save values for restore at end */
486 + uint64_t prtx_cfg =
487 + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT),
488 + INTERFACE(FIX_IPD_OUTPORT)));
489 + uint64_t tx_ptr_en =
490 + cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
491 + uint64_t rx_ptr_en =
492 + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
493 + uint64_t rxx_jabber =
494 + cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT),
495 + INTERFACE(FIX_IPD_OUTPORT)));
496 + uint64_t frame_max =
497 + cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT),
498 + INTERFACE(FIX_IPD_OUTPORT)));
499 +
500 + /* Configure port to gig FDX as required for loopback mode */
501 + cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
502 +
503 + /*
504 + * Disable reception on all ports so if traffic is present it
505 + * will not interfere.
506 + */
507 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
508 +
509 + cvmx_wait(100000000ull);
510 +
511 + for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
512 + retry_cnt = 100000;
513 + wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
514 + pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
515 + wqe_pcnt &= 0x7f;
516 +
517 + num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
518 +
519 + if (num_segs == 0)
520 + goto fix_ipd_exit;
521 +
522 + num_segs += 1;
523 +
524 + size =
525 + FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES +
526 + ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
527 + (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
528 +
529 + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),
530 + 1 << INDEX(FIX_IPD_OUTPORT));
531 + CVMX_SYNC;
532 +
533 + g_buffer.u64 = 0;
534 + g_buffer.s.addr =
535 + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
536 + if (g_buffer.s.addr == 0) {
537 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
538 + "allocation failure.\n");
539 + goto fix_ipd_exit;
540 + }
541 +
542 + g_buffer.s.pool = CVMX_FPA_WQE_POOL;
543 + g_buffer.s.size = num_segs;
544 +
545 + pkt_buffer.u64 = 0;
546 + pkt_buffer.s.addr =
547 + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
548 + if (pkt_buffer.s.addr == 0) {
549 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
550 + "allocation failure.\n");
551 + goto fix_ipd_exit;
552 + }
553 + pkt_buffer.s.i = 1;
554 + pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
555 + pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
556 +
557 + p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr);
558 + p64[0] = 0xffffffffffff0000ull;
559 + p64[1] = 0x08004510ull;
560 + p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull;
561 + p64[3] = 0x3a5fc0a81073c0a8ull;
562 +
563 + for (i = 0; i < num_segs; i++) {
564 + if (i > 0)
565 + pkt_buffer.s.size =
566 + FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
567 +
568 + if (i == (num_segs - 1))
569 + pkt_buffer.s.i = 0;
570 +
571 + *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr +
572 + 8 * i) = pkt_buffer.u64;
573 + }
574 +
575 + /* Build the PKO command */
576 + pko_command.u64 = 0;
577 + pko_command.s.segs = num_segs;
578 + pko_command.s.total_bytes = size;
579 + pko_command.s.dontfree = 0;
580 + pko_command.s.gather = 1;
581 +
582 + gmx_cfg.u64 =
583 + cvmx_read_csr(CVMX_GMXX_PRTX_CFG
584 + (INDEX(FIX_IPD_OUTPORT),
585 + INTERFACE(FIX_IPD_OUTPORT)));
586 + gmx_cfg.s.en = 1;
587 + cvmx_write_csr(CVMX_GMXX_PRTX_CFG
588 + (INDEX(FIX_IPD_OUTPORT),
589 + INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
590 + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
591 + 1 << INDEX(FIX_IPD_OUTPORT));
592 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
593 + 1 << INDEX(FIX_IPD_OUTPORT));
594 +
595 + mtu =
596 + cvmx_read_csr(CVMX_GMXX_RXX_JABBER
597 + (INDEX(FIX_IPD_OUTPORT),
598 + INTERFACE(FIX_IPD_OUTPORT)));
599 + cvmx_write_csr(CVMX_GMXX_RXX_JABBER
600 + (INDEX(FIX_IPD_OUTPORT),
601 + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
602 + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
603 + (INDEX(FIX_IPD_OUTPORT),
604 + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
605 +
606 +#if CVMX_PKO_USE_FAU_FOR_OUTPUT_QUEUES
607 + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
608 + cvmx_pko_get_base_queue
609 + (FIX_IPD_OUTPORT),
610 + CVMX_PKO_LOCK_NONE);
611 + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
612 + cvmx_pko_get_base_queue
613 + (FIX_IPD_OUTPORT), pko_command,
614 + g_buffer, CVMX_PKO_LOCK_NONE);
615 +#else
616 + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
617 + cvmx_pko_get_base_queue
618 + (FIX_IPD_OUTPORT),
619 + CVMX_PKO_LOCK_CMD_QUEUE);
620 + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
621 + cvmx_pko_get_base_queue
622 + (FIX_IPD_OUTPORT), pko_command,
623 + g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
624 +#endif
625 + CVMX_SYNC;
626 +
627 + do {
628 + work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
629 + retry_cnt--;
630 + } while ((work == NULL) && (retry_cnt > 0));
631 +
632 + if (!retry_cnt)
633 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
634 + "get_work() timeout occured.\n");
635 +
636 + /* Free packet */
637 + if (work)
638 + cvmx_helper_free_packet_data(work);
639 + }
640 +
641 +fix_ipd_exit:
642 +
643 + /* Return CSR configs to saved values */
644 + cvmx_write_csr(CVMX_GMXX_PRTX_CFG
645 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
646 + prtx_cfg);
647 + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
648 + tx_ptr_en);
649 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
650 + rx_ptr_en);
651 + cvmx_write_csr(CVMX_GMXX_RXX_JABBER
652 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
653 + rxx_jabber);
654 + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
655 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
656 + frame_max);
657 + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
658 + /* Set link to down so autonegotiation will set it up again */
659 + link_info.u64 = 0;
660 + cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
661 +
662 + /*
663 + * Bring the link back up as autonegotiation is not done in
664 + * user applications.
665 + */
666 + cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
667 +
668 + CVMX_SYNC;
669 + if (num_segs)
670 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
671 +
672 + return !!num_segs;
673 +
674 +}
675 +
676 +/**
677 + * @INTERNAL
678 + * Workaround ASX setup errata with CN38XX pass1
679 + *
680 + * @interface: Interface to setup
681 + * @port: Port to setup (0..3)
682 + * @cpu_clock_hz:
683 + * Chip frequency in Hertz
684 + *
685 + * Returns Zero on success, negative on failure
686 + */
687 +int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
688 +{
689 + /* Set hi water mark as per errata GMX-4 */
690 + if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
691 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
692 + else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
693 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
694 + else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
695 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
696 + else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
697 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
698 + else
699 + cvmx_dprintf("Illegal clock frequency (%d). "
700 + "CVMX_ASXX_TX_HI_WATERX not set\n",
701 + cpu_clock_hz);
702 + return 0;
703 +}
704 +
705 +/**
706 + * This function needs to be called on all Octeon chips with
707 + * errata PKI-100.
708 + *
709 + * The Size field is 8 too large in WQE and next pointers
710 + *
711 + * The Size field generated by IPD is 8 larger than it should
712 + * be. The Size field is <55:40> of both:
713 + * - WORD3 in the work queue entry, and
714 + * - the next buffer pointer (which precedes the packet data
715 + * in each buffer).
716 + *
717 + * @work: Work queue entry to fix
718 + * Returns Zero on success. Negative on failure
719 + */
720 +int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
721 +{
722 + uint64_t number_buffers = work->word2.s.bufs;
723 +
724 + /* We only need to do this if the work has buffers */
725 + if (number_buffers) {
726 + cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
727 + /* Check for errata PKI-100 */
728 + if ((buffer_ptr.s.pool == 0) &&
729 + (((uint64_t) buffer_ptr.s.size +
730 + ((uint64_t) buffer_ptr.s.back << 7) +
731 + ((uint64_t) buffer_ptr.s.addr & 0x7F)) !=
732 + (CVMX_FPA_PACKET_POOL_SIZE + 8))) {
733 + /* fix is not needed */
734 + return 0;
735 + }
736 + /* Decrement the work packet pointer */
737 + buffer_ptr.s.size -= 8;
738 + work->packet_ptr = buffer_ptr;
739 +
740 + /*
741 + * Now loop through decrementing the size for each
742 + * additional buffer.
743 + */
744 + while (--number_buffers) {
745 + /* Chain pointers are 8 bytes before the data */
746 + cvmx_buf_ptr_t *ptr =
747 + (cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
748 + buffer_ptr = *ptr;
749 + buffer_ptr.s.size -= 8;
750 + *ptr = buffer_ptr;
751 + }
752 + }
753 + /*
754 + * Make sure that these write go out before other operations
755 + * such as FPA frees.
756 + */
757 + CVMX_SYNCWS;
758 + return 0;
759 +}
760 +
761 +#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
762 +
763 +/**
764 + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
765 + * 1 doesn't work properly. The following code disables 2nd order
766 + * CDR for the specified QLM.
767 + *
768 + * @qlm: QLM to disable 2nd order CDR for.
769 + */
770 +void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
771 +{
772 + int lane;
773 + cvmx_helper_qlm_jtag_init();
774 + /* We need to load all four lanes of the QLM, a total of 1072 bits */
775 + for (lane = 0; lane < 4; lane++) {
776 + /*
777 + * Each lane has 268 bits. We need to set
778 + * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
779 + * 1. All other bits are zero. Bits go in LSB first,
780 + * so start off with the zeros for bits <63:0>.
781 + */
782 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
783 + /* cfg_cdr_incx<67:64>=3 */
784 + cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
785 + /* Zeros for bits <76:68> */
786 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
787 + /* cfg_cdr_secord<77>=1 */
788 + cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
789 + /* Zeros for bits <267:78> */
790 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
791 + }
792 + cvmx_helper_qlm_jtag_update(qlm);
793 +}
794 diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
795 new file mode 100644
796 index 0000000..dc0087c
797 --- /dev/null
798 +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
799 @@ -0,0 +1,502 @@
800 +/***********************license start***************
801 + * Author: Cavium Networks
802 + *
803 + * Contact: support@caviumnetworks.com
804 + * This file is part of the OCTEON SDK
805 + *
806 + * Copyright (c) 2003-2008 Cavium Networks
807 + *
808 + * This file is free software; you can redistribute it and/or modify
809 + * it under the terms of the GNU General Public License, Version 2, as
810 + * published by the Free Software Foundation.
811 + *
812 + * This file is distributed in the hope that it will be useful, but
813 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
814 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
815 + * NONINFRINGEMENT. See the GNU General Public License for more
816 + * details.
817 + *
818 + * You should have received a copy of the GNU General Public License
819 + * along with this file; if not, write to the Free Software
820 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
821 + * or visit http://www.gnu.org/licenses/.
822 + *
823 + * This file may also be available under a different license from Cavium.
824 + * Contact Cavium Networks for more information
825 + ***********************license end**************************************/
826 +
827 +/**
828 + *
829 + * Small helper utilities.
830 + *
831 + */
832 +
833 +#include <asm/octeon/octeon.h>
834 +
835 +#include <asm/octeon/cvmx-helper-util.h>
836 +
837 +#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
838 +
839 +/**
840 + * Get the version of the CVMX libraries.
841 + *
842 + * Returns Version string. Note this buffer is allocated statically
843 + * and will be shared by all callers.
844 + */
845 +const char *cvmx_helper_get_version(void)
846 +{
847 + return OCTEON_SDK_VERSION_STRING;
848 +}
849 +
850 +/**
851 + * Convert a interface mode into a human readable string
852 + *
853 + * @mode: Mode to convert
854 + *
855 + * Returns String
856 + */
857 +const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
858 + mode)
859 +{
860 + switch (mode) {
861 + case CVMX_HELPER_INTERFACE_MODE_DISABLED:
862 + return "DISABLED";
863 + case CVMX_HELPER_INTERFACE_MODE_RGMII:
864 + return "RGMII";
865 + case CVMX_HELPER_INTERFACE_MODE_GMII:
866 + return "GMII";
867 + case CVMX_HELPER_INTERFACE_MODE_SPI:
868 + return "SPI";
869 + case CVMX_HELPER_INTERFACE_MODE_PCIE:
870 + return "PCIE";
871 + case CVMX_HELPER_INTERFACE_MODE_XAUI:
872 + return "XAUI";
873 + case CVMX_HELPER_INTERFACE_MODE_SGMII:
874 + return "SGMII";
875 + case CVMX_HELPER_INTERFACE_MODE_PICMG:
876 + return "PICMG";
877 + case CVMX_HELPER_INTERFACE_MODE_NPI:
878 + return "NPI";
879 + case CVMX_HELPER_INTERFACE_MODE_LOOP:
880 + return "LOOP";
881 + }
882 + return "UNKNOWN";
883 +}
884 +
885 +/**
886 + * Debug routine to dump the packet structure to the console
887 + *
888 + * @work: Work queue entry containing the packet to dump
889 + */
890 +int cvmx_helper_dump_packet(cvmx_wqe_t *work)
891 +{
892 + uint64_t count;
893 + uint64_t remaining_bytes;
894 + cvmx_buf_ptr_t buffer_ptr;
895 + uint64_t start_of_buffer;
896 + uint8_t *data_address;
897 + uint8_t *end_of_data;
898 +
899 + cvmx_dprintf("Packet Length: %u\n", work->len);
900 + cvmx_dprintf(" Input Port: %u\n", work->ipprt);
901 + cvmx_dprintf(" QoS: %u\n", work->qos);
902 + cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
903 +
904 + if (work->word2.s.bufs == 0) {
905 + cvmx_ipd_wqe_fpa_queue_t wqe_pool;
906 + wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
907 + buffer_ptr.u64 = 0;
908 + buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
909 + buffer_ptr.s.size = 128;
910 + buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
911 + if (cvmx_likely(!work->word2.s.not_IP)) {
912 + if (work->word2.s.is_v6)
913 + buffer_ptr.s.addr += 2;
914 + else
915 + buffer_ptr.s.addr += 6;
916 + }
917 + } else
918 + buffer_ptr = work->packet_ptr;
919 + remaining_bytes = work->len;
920 +
921 + while (remaining_bytes) {
922 + start_of_buffer =
923 + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
924 + cvmx_dprintf(" Buffer Start:%llx\n",
925 + (unsigned long long)start_of_buffer);
926 + cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
927 + cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
928 + cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
929 + cvmx_dprintf(" Buffer Data: %llx\n",
930 + (unsigned long long)buffer_ptr.s.addr);
931 + cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
932 +
933 + cvmx_dprintf("\t\t");
934 + data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
935 + end_of_data = data_address + buffer_ptr.s.size;
936 + count = 0;
937 + while (data_address < end_of_data) {
938 + if (remaining_bytes == 0)
939 + break;
940 + else
941 + remaining_bytes--;
942 + cvmx_dprintf("%02x", (unsigned int)*data_address);
943 + data_address++;
944 + if (remaining_bytes && (count == 7)) {
945 + cvmx_dprintf("\n\t\t");
946 + count = 0;
947 + } else
948 + count++;
949 + }
950 + cvmx_dprintf("\n");
951 +
952 + if (remaining_bytes)
953 + buffer_ptr =
954 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.
955 + addr - 8);
956 + }
957 + return 0;
958 +}
959 +
960 +/**
961 + * Setup Random Early Drop on a specific input queue
962 + *
963 + * @queue: Input queue to setup RED on (0-7)
964 + * @pass_thresh:
965 + * Packets will begin slowly dropping when there are less than
966 + * this many packet buffers free in FPA 0.
967 + * @drop_thresh:
968 + * All incomming packets will be dropped when there are less
969 + * than this many free packet buffers in FPA 0.
970 + * Returns Zero on success. Negative on failure
971 + */
972 +int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
973 +{
974 + cvmx_ipd_qos_red_marks_t red_marks;
975 + cvmx_ipd_red_quex_param_t red_param;
976 +
977 + /*
978 + * Set RED to begin dropping packets when there are
979 + * pass_thresh buffers left. It will linearly drop more
980 + * packets until reaching drop_thresh buffers.
981 + */
982 + red_marks.u64 = 0;
983 + red_marks.s.drop = drop_thresh;
984 + red_marks.s.pass = pass_thresh;
985 + cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
986 +
987 + /* Use the actual queue 0 counter, not the average */
988 + red_param.u64 = 0;
989 + red_param.s.prb_con =
990 + (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
991 + red_param.s.avg_con = 1;
992 + red_param.s.new_con = 255;
993 + red_param.s.use_pcnt = 1;
994 + cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
995 + return 0;
996 +}
997 +
998 +/**
999 + * Setup Random Early Drop to automatically begin dropping packets.
1000 + *
1001 + * @pass_thresh:
1002 + * Packets will begin slowly dropping when there are less than
1003 + * this many packet buffers free in FPA 0.
1004 + * @drop_thresh:
1005 + * All incomming packets will be dropped when there are less
1006 + * than this many free packet buffers in FPA 0.
1007 + * Returns Zero on success. Negative on failure
1008 + */
1009 +int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1010 +{
1011 + cvmx_ipd_portx_bp_page_cnt_t page_cnt;
1012 + cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
1013 + cvmx_ipd_red_port_enable_t red_port_enable;
1014 + int queue;
1015 + int interface;
1016 + int port;
1017 +
1018 + /* Disable backpressure based on queued buffers. It needs SW support */
1019 + page_cnt.u64 = 0;
1020 + page_cnt.s.bp_enb = 0;
1021 + page_cnt.s.page_cnt = 100;
1022 + for (interface = 0; interface < 2; interface++) {
1023 + for (port = cvmx_helper_get_first_ipd_port(interface);
1024 + port < cvmx_helper_get_last_ipd_port(interface); port++)
1025 + cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
1026 + page_cnt.u64);
1027 + }
1028 +
1029 + for (queue = 0; queue < 8; queue++)
1030 + cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
1031 +
1032 + /* Shutoff the dropping based on the per port page count. SW isn't
1033 + decrementing it right now */
1034 + ipd_bp_prt_red_end.u64 = 0;
1035 + ipd_bp_prt_red_end.s.prt_enb = 0;
1036 + cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
1037 +
1038 + red_port_enable.u64 = 0;
1039 + red_port_enable.s.prt_enb = 0xfffffffffull;
1040 + red_port_enable.s.avg_dly = 10000;
1041 + red_port_enable.s.prb_dly = 10000;
1042 + cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
1043 +
1044 + return 0;
1045 +}
1046 +
1047 +/**
1048 + * Setup the common GMX settings that determine the number of
1049 + * ports. These setting apply to almost all configurations of all
1050 + * chips.
1051 + *
1052 + * @interface: Interface to configure
1053 + * @num_ports: Number of ports on the interface
1054 + *
1055 + * Returns Zero on success, negative on failure
1056 + */
1057 +int __cvmx_helper_setup_gmx(int interface, int num_ports)
1058 +{
1059 + cvmx_gmxx_tx_prts_t gmx_tx_prts;
1060 + cvmx_gmxx_rx_prts_t gmx_rx_prts;
1061 + cvmx_pko_reg_gmx_port_mode_t pko_mode;
1062 +
1063 + /* Tell GMX the number of TX ports on this interface */
1064 + gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
1065 + gmx_tx_prts.s.prts = num_ports;
1066 + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
1067 +
1068 + /*
1069 + * Tell GMX the number of RX ports on this interface. This only
1070 + * applies to *GMII and XAUI ports.
1071 + */
1072 + if (cvmx_helper_interface_get_mode(interface) ==
1073 + CVMX_HELPER_INTERFACE_MODE_RGMII
1074 + || cvmx_helper_interface_get_mode(interface) ==
1075 + CVMX_HELPER_INTERFACE_MODE_SGMII
1076 + || cvmx_helper_interface_get_mode(interface) ==
1077 + CVMX_HELPER_INTERFACE_MODE_GMII
1078 + || cvmx_helper_interface_get_mode(interface) ==
1079 + CVMX_HELPER_INTERFACE_MODE_XAUI) {
1080 + if (num_ports > 4) {
1081 + cvmx_dprintf("__cvmx_helper_setup_gmx: "
1082 + "Illegal num_ports\n");
1083 + return -1;
1084 + }
1085 +
1086 + gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
1087 + gmx_rx_prts.s.prts = num_ports;
1088 + cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
1089 + }
1090 +
1091 + /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX and 31XX */
1092 + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
1093 + || OCTEON_IS_MODEL(OCTEON_CN50XX))
1094 + return 0;
1095 +
1096 + /* Tell PKO the number of ports on this interface */
1097 + pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
1098 + if (interface == 0) {
1099 + if (num_ports == 1)
1100 + pko_mode.s.mode0 = 4;
1101 + else if (num_ports == 2)
1102 + pko_mode.s.mode0 = 3;
1103 + else if (num_ports <= 4)
1104 + pko_mode.s.mode0 = 2;
1105 + else if (num_ports <= 8)
1106 + pko_mode.s.mode0 = 1;
1107 + else
1108 + pko_mode.s.mode0 = 0;
1109 + } else {
1110 + if (num_ports == 1)
1111 + pko_mode.s.mode1 = 4;
1112 + else if (num_ports == 2)
1113 + pko_mode.s.mode1 = 3;
1114 + else if (num_ports <= 4)
1115 + pko_mode.s.mode1 = 2;
1116 + else if (num_ports <= 8)
1117 + pko_mode.s.mode1 = 1;
1118 + else
1119 + pko_mode.s.mode1 = 0;
1120 + }
1121 + cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
1122 + return 0;
1123 +}
1124 +
1125 +/**
1126 + * Returns the IPD/PKO port number for a port on the given
1127 + * interface.
1128 + *
1129 + * @interface: Interface to use
1130 + * @port: Port on the interface
1131 + *
1132 + * Returns IPD/PKO port number
1133 + */
1134 +int cvmx_helper_get_ipd_port(int interface, int port)
1135 +{
1136 + switch (interface) {
1137 + case 0:
1138 + return port;
1139 + case 1:
1140 + return port + 16;
1141 + case 2:
1142 + return port + 32;
1143 + case 3:
1144 + return port + 36;
1145 + }
1146 + return -1;
1147 +}
1148 +
1149 +#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
1150 +
1151 +/**
1152 + * Returns the interface number for an IPD/PKO port number.
1153 + *
1154 + * @ipd_port: IPD/PKO port number
1155 + *
1156 + * Returns Interface number
1157 + */
1158 +int cvmx_helper_get_interface_num(int ipd_port)
1159 +{
1160 + if (ipd_port < 16)
1161 + return 0;
1162 + else if (ipd_port < 32)
1163 + return 1;
1164 + else if (ipd_port < 36)
1165 + return 2;
1166 + else if (ipd_port < 40)
1167 + return 3;
1168 + else
1169 + cvmx_dprintf("cvmx_helper_get_interface_num: "
1170 + "Illegal IPD port number\n");
1171 +
1172 + return -1;
1173 +}
1174 +
1175 +/**
1176 + * Returns the interface index number for an IPD/PKO port
1177 + * number.
1178 + *
1179 + * @ipd_port: IPD/PKO port number
1180 + *
1181 + * Returns Interface index number
1182 + */
1183 +int cvmx_helper_get_interface_index_num(int ipd_port)
1184 +{
1185 + if (ipd_port < 32)
1186 + return ipd_port & 15;
1187 + else if (ipd_port < 36)
1188 + return ipd_port & 3;
1189 + else if (ipd_port < 40)
1190 + return ipd_port & 3;
1191 + else
1192 + cvmx_dprintf("cvmx_helper_get_interface_index_num: "
1193 + "Illegal IPD port number\n");
1194 +
1195 + return -1;
1196 +}
1197 +
1198 +/**
1199 + * Initialize the internal QLM JTAG logic to allow programming
1200 + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
1201 + * These functions should only be used at the direction of Cavium
1202 + * Networks. Programming incorrect values into the JTAG chain
1203 + * can cause chip damage.
1204 + */
1205 +void cvmx_helper_qlm_jtag_init(void)
1206 +{
1207 + union cvmx_ciu_qlm_jtgc jtgc;
1208 + int clock_div = 0;
1209 + int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
1210 + divisor = (divisor - 1) >> 2;
1211 + /* Convert the divisor into a power of 2 shift */
1212 + CVMX_CLZ(clock_div, divisor);
1213 + clock_div = 32 - clock_div;
1214 +
1215 + /*
1216 + * Clock divider for QLM JTAG operations. eclk is divided by
1217 + * 2^(CLK_DIV + 2).
1218 + */
1219 + jtgc.u64 = 0;
1220 + jtgc.s.clk_div = clock_div;
1221 + jtgc.s.mux_sel = 0;
1222 + if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1223 + jtgc.s.bypass = 0x3;
1224 + else
1225 + jtgc.s.bypass = 0xf;
1226 + cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
1227 + cvmx_read_csr(CVMX_CIU_QLM_JTGC);
1228 +}
1229 +
1230 +/**
1231 + * Write up to 32bits into the QLM jtag chain. Bits are shifted
1232 + * into the MSB and out the LSB, so you should shift in the low
1233 + * order bits followed by the high order bits. The JTAG chain is
1234 + * 4 * 268 bits long, or 1072.
1235 + *
1236 + * @qlm: QLM to shift value into
1237 + * @bits: Number of bits to shift in (1-32).
1238 + * @data: Data to shift in. Bit 0 enters the chain first, followed by
1239 + * bit 1, etc.
1240 + *
1241 + * Returns The low order bits of the JTAG chain that shifted out of the
1242 + * circle.
1243 + */
1244 +uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
1245 +{
1246 + union cvmx_ciu_qlm_jtgd jtgd;
1247 + jtgd.u64 = 0;
1248 + jtgd.s.shift = 1;
1249 + jtgd.s.shft_cnt = bits - 1;
1250 + jtgd.s.shft_reg = data;
1251 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1252 + jtgd.s.select = 1 << qlm;
1253 + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1254 + do {
1255 + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1256 + } while (jtgd.s.shift);
1257 + return jtgd.s.shft_reg >> (32 - bits);
1258 +}
1259 +
1260 +/**
1261 + * Shift long sequences of zeros into the QLM JTAG chain. It is
1262 + * common to need to shift more than 32 bits of zeros into the
1263 + * chain. This function is a convience wrapper around
1264 + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
1265 + * zeros at a time.
1266 + *
1267 + * @qlm: QLM to shift zeros into
1268 + * @bits:
1269 + */
1270 +void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
1271 +{
1272 + while (bits > 0) {
1273 + int n = bits;
1274 + if (n > 32)
1275 + n = 32;
1276 + cvmx_helper_qlm_jtag_shift(qlm, n, 0);
1277 + bits -= n;
1278 + }
1279 +}
1280 +
1281 +/**
1282 + * Program the QLM JTAG chain into all lanes of the QLM. You must
1283 + * have already shifted in 268*4, or 1072 bits into the JTAG
1284 + * chain. Updating invalid values can possibly cause chip damage.
1285 + *
1286 + * @qlm: QLM to program
1287 + */
1288 +void cvmx_helper_qlm_jtag_update(int qlm)
1289 +{
1290 + union cvmx_ciu_qlm_jtgd jtgd;
1291 +
1292 + /* Update the new data */
1293 + jtgd.u64 = 0;
1294 + jtgd.s.update = 1;
1295 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1296 + jtgd.s.select = 1 << qlm;
1297 + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1298 + do {
1299 + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1300 + } while (jtgd.s.update);
1301 +}
1302 diff --git a/arch/mips/cavium-octeon/executive/cvmx-pcie.c b/arch/mips/cavium-octeon/executive/cvmx-pcie.c
1303 new file mode 100644
1304 index 0000000..710f21f
1305 --- /dev/null
1306 +++ b/arch/mips/cavium-octeon/executive/cvmx-pcie.c
1307 @@ -0,0 +1,1053 @@
1308 +/***********************license start***************
1309 + * Author: Cavium Networks
1310 + *
1311 + * Contact: support@caviumnetworks.com
1312 + * This file is part of the OCTEON SDK
1313 + *
1314 + * Copyright (c) 2003-2008 Cavium Networks
1315 + *
1316 + * This file is free software; you can redistribute it and/or modify
1317 + * it under the terms of the GNU General Public License, Version 2, as
1318 + * published by the Free Software Foundation.
1319 + *
1320 + * This file is distributed in the hope that it will be useful, but
1321 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1322 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1323 + * NONINFRINGEMENT. See the GNU General Public License for more
1324 + * details.
1325 + *
1326 + * You should have received a copy of the GNU General Public License
1327 + * along with this file; if not, write to the Free Software
1328 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1329 + * 02110-1301 USA or visit http://www.gnu.org/licenses/.
1330 + *
1331 + * This file may also be available under a different license from Cavium.
1332 + * Contact Cavium Networks for more information
1333 + ***********************license end**************************************/
1334 +
1335 +/**
1336 + *
1337 + * Interface to PCIe as a host(RC) or target(EP)
1338 + *
1339 + */
1340 +#include <linux/delay.h>
1341 +#include <asm/byteorder.h>
1342 +
1343 +#include <asm/octeon/octeon.h>
1344 +#include <asm/octeon/cvmx-npei-defs.h>
1345 +#include <asm/octeon/cvmx-pciercx-defs.h>
1346 +#include <asm/octeon/cvmx-pescx-defs.h>
1347 +#include <asm/octeon/cvmx-pexp-defs.h>
1348 +#include <asm/octeon/cvmx-pcieep-defs.h>
1349 +#include <asm/octeon/cvmx-helper-errata.h>
1350 +#include <asm/octeon/cvmx-pcie.h>
1351 +
1352 +/**
1353 + * Return the Core virtual base address for PCIe IO access. IOs are
1354 + * read/written as an offset from this address.
1355 + *
1356 + * @pcie_port: PCIe port the IO is for
1357 + *
1358 + * Returns 64bit Octeon IO base address for read/write
1359 + */
1360 +uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
1361 +{
1362 + union cvmx_pcie_address pcie_addr;
1363 + pcie_addr.u64 = 0;
1364 + pcie_addr.io.upper = 0;
1365 + pcie_addr.io.io = 1;
1366 + pcie_addr.io.did = 3;
1367 + pcie_addr.io.subdid = 2;
1368 + pcie_addr.io.es = 1;
1369 + pcie_addr.io.port = pcie_port;
1370 + return pcie_addr.u64;
1371 +}
1372 +
1373 +/**
1374 + * Size of the IO address region returned at address
1375 + * cvmx_pcie_get_io_base_address()
1376 + *
1377 + * @pcie_port: PCIe port the IO is for
1378 + *
1379 + * Returns Size of the IO window
1380 + */
1381 +uint64_t cvmx_pcie_get_io_size(int pcie_port)
1382 +{
1383 + return 1ull << 32;
1384 +}
1385 +
1386 +/**
1387 + * Return the Core virtual base address for PCIe MEM access. Memory is
1388 + * read/written as an offset from this address.
1389 + *
1390 + * @pcie_port: PCIe port the IO is for
1391 + *
1392 + * Returns 64bit Octeon IO base address for read/write
1393 + */
1394 +uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
1395 +{
1396 + union cvmx_pcie_address pcie_addr;
1397 + pcie_addr.u64 = 0;
1398 + pcie_addr.mem.upper = 0;
1399 + pcie_addr.mem.io = 1;
1400 + pcie_addr.mem.did = 3;
1401 + pcie_addr.mem.subdid = 3 + pcie_port;
1402 + return pcie_addr.u64;
1403 +}
1404 +
1405 +/**
1406 + * Size of the Mem address region returned at address
1407 + * cvmx_pcie_get_mem_base_address()
1408 + *
1409 + * @pcie_port: PCIe port the IO is for
1410 + *
1411 + * Returns Size of the Mem window
1412 + */
1413 +uint64_t cvmx_pcie_get_mem_size(int pcie_port)
1414 +{
1415 + return 1ull << 36;
1416 +}
1417 +
1418 +/**
1419 + * Initialize the RC config space CSRs
1420 + *
1421 + * @pcie_port: PCIe port to initialize
1422 + */
1423 +static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
1424 +{
1425 + union cvmx_pciercx_cfg030 pciercx_cfg030;
1426 + union cvmx_npei_ctl_status2 npei_ctl_status2;
1427 + union cvmx_pciercx_cfg070 pciercx_cfg070;
1428 + union cvmx_pciercx_cfg001 pciercx_cfg001;
1429 + union cvmx_pciercx_cfg032 pciercx_cfg032;
1430 + union cvmx_pciercx_cfg006 pciercx_cfg006;
1431 + union cvmx_pciercx_cfg008 pciercx_cfg008;
1432 + union cvmx_pciercx_cfg009 pciercx_cfg009;
1433 + union cvmx_pciercx_cfg010 pciercx_cfg010;
1434 + union cvmx_pciercx_cfg011 pciercx_cfg011;
1435 + union cvmx_pciercx_cfg035 pciercx_cfg035;
1436 + union cvmx_pciercx_cfg075 pciercx_cfg075;
1437 + union cvmx_pciercx_cfg034 pciercx_cfg034;
1438 +
1439 + /* Max Payload Size (PCIE*_CFG030[MPS]) */
1440 + /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
1441 + /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
1442 + /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
1443 + pciercx_cfg030.u32 =
1444 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
1445 + /*
1446 + * Max payload size = 128 bytes for best Octeon DMA
1447 + * performance.
1448 + */
1449 + pciercx_cfg030.s.mps = 0;
1450 + /*
1451 + * Max read request size = 128 bytes for best Octeon DMA
1452 + * performance.
1453 + */
1454 + pciercx_cfg030.s.mrrs = 0;
1455 + /* Enable relaxed ordering. */
1456 + pciercx_cfg030.s.ro_en = 1;
1457 + /* Enable no snoop. */
1458 + pciercx_cfg030.s.ns_en = 1;
1459 + /* Correctable error reporting enable. */
1460 + pciercx_cfg030.s.ce_en = 1;
1461 + /* Non-fatal error reporting enable. */
1462 + pciercx_cfg030.s.nfe_en = 1;
1463 + /* Fatal error reporting enable. */
1464 + pciercx_cfg030.s.fe_en = 1;
1465 + /* Unsupported request reporting enable. */
1466 + pciercx_cfg030.s.ur_en = 1;
1467 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
1468 + pciercx_cfg030.u32);
1469 +
1470 + /*
1471 + * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
1472 + * PCIE*_CFG030[MPS]
1473 + *
1474 + * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
1475 + * exceed PCIE*_CFG030[MRRS].
1476 + */
1477 + npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
1478 + /* Max payload size = 128 bytes for best Octeon DMA performance */
1479 + npei_ctl_status2.s.mps = 0;
1480 + /* Max read request size = 128 bytes for best Octeon DMA performance */
1481 + npei_ctl_status2.s.mrrs = 0;
1482 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
1483 +
1484 + /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
1485 + pciercx_cfg070.u32 =
1486 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
1487 + pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
1488 + pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
1489 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
1490 + pciercx_cfg070.u32);
1491 +
1492 + /*
1493 + * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
1494 + * always be set.
1495 + *
1496 + * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
1497 + * Message Enable (PCIE*_CFG001[SEE])
1498 + */
1499 + pciercx_cfg001.u32 =
1500 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
1501 + pciercx_cfg001.s.msae = 1; /* Memory space enable. */
1502 + pciercx_cfg001.s.me = 1; /* Bus master enable. */
1503 + pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
1504 + pciercx_cfg001.s.see = 1; /* SERR# enable */
1505 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
1506 + pciercx_cfg001.u32);
1507 +
1508 + /* Advanced Error Recovery Message Enables */
1509 + /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
1510 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
1511 + /* Use CVMX_PCIERCX_CFG067 hardware default */
1512 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
1513 +
1514 + /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
1515 + pciercx_cfg032.u32 =
1516 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1517 + pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
1518 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
1519 + pciercx_cfg032.u32);
1520 +
1521 + /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
1522 +
1523 + /*
1524 + * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
1525 + * cvmx_pcie_rc_initialize_link()
1526 + *
1527 + * Primary Bus Number (PCIERCn_CFG006[PBNUM])
1528 + *
1529 + * We set the primary bus number to 1 so IDT bridges are
1530 + * happy. They don't like zero.
1531 + */
1532 + pciercx_cfg006.u32 = 0;
1533 + pciercx_cfg006.s.pbnum = 1;
1534 + pciercx_cfg006.s.sbnum = 1;
1535 + pciercx_cfg006.s.subbnum = 1;
1536 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
1537 + pciercx_cfg006.u32);
1538 +
1539 + /*
1540 + * Memory-mapped I/O BAR (PCIERCn_CFG008)
1541 + * Most applications should disable the memory-mapped I/O BAR by
1542 + * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
1543 + */
1544 + pciercx_cfg008.u32 = 0;
1545 + pciercx_cfg008.s.mb_addr = 0x100;
1546 + pciercx_cfg008.s.ml_addr = 0;
1547 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
1548 + pciercx_cfg008.u32);
1549 +
1550 + /*
1551 + * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
1552 + * Most applications should disable the prefetchable BAR by setting
1553 + * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
1554 + * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
1555 + */
1556 + pciercx_cfg009.u32 =
1557 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
1558 + pciercx_cfg010.u32 =
1559 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
1560 + pciercx_cfg011.u32 =
1561 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
1562 + pciercx_cfg009.s.lmem_base = 0x100;
1563 + pciercx_cfg009.s.lmem_limit = 0;
1564 + pciercx_cfg010.s.umem_base = 0x100;
1565 + pciercx_cfg011.s.umem_limit = 0;
1566 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
1567 + pciercx_cfg009.u32);
1568 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
1569 + pciercx_cfg010.u32);
1570 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
1571 + pciercx_cfg011.u32);
1572 +
1573 + /*
1574 + * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
1575 + * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
1576 + */
1577 + pciercx_cfg035.u32 =
1578 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
1579 + /* System error on correctable error enable. */
1580 + pciercx_cfg035.s.secee = 1;
1581 + /* System error on fatal error enable. */
1582 + pciercx_cfg035.s.sefee = 1;
1583 + /* System error on non-fatal error enable. */
1584 + pciercx_cfg035.s.senfee = 1;
1585 + /* PME interrupt enable. */
1586 + pciercx_cfg035.s.pmeie = 1;
1587 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
1588 + pciercx_cfg035.u32);
1589 +
1590 + /*
1591 + * Advanced Error Recovery Interrupt Enables
1592 + * (PCIERCn_CFG075[CERE,NFERE,FERE])
1593 + */
1594 + pciercx_cfg075.u32 =
1595 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
1596 + /* Correctable error reporting enable. */
1597 + pciercx_cfg075.s.cere = 1;
1598 + /* Non-fatal error reporting enable. */
1599 + pciercx_cfg075.s.nfere = 1;
1600 + /* Fatal error reporting enable. */
1601 + pciercx_cfg075.s.fere = 1;
1602 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
1603 + pciercx_cfg075.u32);
1604 +
1605 + /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
1606 + * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
1607 + */
1608 + pciercx_cfg034.u32 =
1609 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
1610 + /* Hot-plug interrupt enable. */
1611 + pciercx_cfg034.s.hpint_en = 1;
1612 + /* Data Link Layer state changed enable */
1613 + pciercx_cfg034.s.dlls_en = 1;
1614 + /* Command completed interrupt enable. */
1615 + pciercx_cfg034.s.ccint_en = 1;
1616 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
1617 + pciercx_cfg034.u32);
1618 +}
1619 +
1620 +/**
1621 + * Initialize a host mode PCIe link. This function takes a PCIe
1622 + * port from reset to a link up state. Software can then begin
1623 + * configuring the rest of the link.
1624 + *
1625 + * @pcie_port: PCIe port to initialize
1626 + *
1627 + * Returns Zero on success
1628 + */
1629 +static int __cvmx_pcie_rc_initialize_link(int pcie_port)
1630 +{
1631 + uint64_t start_cycle;
1632 + union cvmx_pescx_ctl_status pescx_ctl_status;
1633 + union cvmx_pciercx_cfg452 pciercx_cfg452;
1634 + union cvmx_pciercx_cfg032 pciercx_cfg032;
1635 + union cvmx_pciercx_cfg448 pciercx_cfg448;
1636 +
1637 + /* Set the lane width */
1638 + pciercx_cfg452.u32 =
1639 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
1640 + pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1641 + if (pescx_ctl_status.s.qlm_cfg == 0) {
1642 + /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
1643 + pciercx_cfg452.s.lme = 0xf;
1644 + } else {
1645 + /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
1646 + pciercx_cfg452.s.lme = 0x7;
1647 + }
1648 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
1649 + pciercx_cfg452.u32);
1650 +
1651 + /*
1652 + * CN52XX pass 1.x has an errata where length mismatches on UR
1653 + * responses can cause bus errors on 64bit memory
1654 + * reads. Turning off length error checking fixes this.
1655 + */
1656 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1657 + union cvmx_pciercx_cfg455 pciercx_cfg455;
1658 + pciercx_cfg455.u32 =
1659 + cvmx_pcie_cfgx_read(pcie_port,
1660 + CVMX_PCIERCX_CFG455(pcie_port));
1661 + pciercx_cfg455.s.m_cpl_len_err = 1;
1662 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
1663 + pciercx_cfg455.u32);
1664 + }
1665 +
1666 + /* Lane swap needs to be manually enabled for CN52XX */
1667 + if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
1668 + pescx_ctl_status.s.lane_swp = 1;
1669 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
1670 + pescx_ctl_status.u64);
1671 + }
1672 +
1673 + /* Bring up the link */
1674 + pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1675 + pescx_ctl_status.s.lnk_enb = 1;
1676 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
1677 +
1678 + /*
1679 + * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
1680 + * be disabled.
1681 + */
1682 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
1683 + __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
1684 +
1685 + /* Wait for the link to come up */
1686 + cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
1687 + start_cycle = cvmx_get_cycle();
1688 + do {
1689 + if (cvmx_get_cycle() - start_cycle >
1690 + 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
1691 + cvmx_dprintf("PCIe: Port %d link timeout\n",
1692 + pcie_port);
1693 + return -1;
1694 + }
1695 + cvmx_wait(10000);
1696 + pciercx_cfg032.u32 =
1697 + cvmx_pcie_cfgx_read(pcie_port,
1698 + CVMX_PCIERCX_CFG032(pcie_port));
1699 + } while (pciercx_cfg032.s.dlla == 0);
1700 +
1701 + /* Display the link status */
1702 + cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
1703 + pciercx_cfg032.s.nlw);
1704 +
1705 + /*
1706 + * Update the Replay Time Limit. Empirically, some PCIe
1707 + * devices take a little longer to respond than expected under
1708 + * load. As a workaround for this we configure the Replay Time
1709 + * Limit to the value expected for a 512 byte MPS instead of
1710 + * our actual 256 byte MPS. The numbers below are directly
1711 + * from the PCIe spec table 3-4.
1712 + */
1713 + pciercx_cfg448.u32 =
1714 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1715 + switch (pciercx_cfg032.s.nlw) {
1716 + case 1: /* 1 lane */
1717 + pciercx_cfg448.s.rtl = 1677;
1718 + break;
1719 + case 2: /* 2 lanes */
1720 + pciercx_cfg448.s.rtl = 867;
1721 + break;
1722 + case 4: /* 4 lanes */
1723 + pciercx_cfg448.s.rtl = 462;
1724 + break;
1725 + case 8: /* 8 lanes */
1726 + pciercx_cfg448.s.rtl = 258;
1727 + break;
1728 + }
1729 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
1730 + pciercx_cfg448.u32);
1731 +
1732 + return 0;
1733 +}
1734 +
1735 +/**
1736 + * Initialize a PCIe port for use in host(RC) mode. It doesn't
1737 + * enumerate the bus.
1738 + *
1739 + * @pcie_port: PCIe port to initialize
1740 + *
1741 + * Returns Zero on success
1742 + */
1743 +int cvmx_pcie_rc_initialize(int pcie_port)
1744 +{
1745 + int i;
1746 + union cvmx_ciu_soft_prst ciu_soft_prst;
1747 + union cvmx_pescx_bist_status pescx_bist_status;
1748 + union cvmx_pescx_bist_status2 pescx_bist_status2;
1749 + union cvmx_npei_ctl_status npei_ctl_status;
1750 + union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
1751 + union cvmx_npei_mem_access_subidx mem_access_subid;
1752 + union cvmx_npei_dbg_data npei_dbg_data;
1753 + union cvmx_pescx_ctl_status2 pescx_ctl_status2;
1754 +
1755 + /*
1756 + * Make sure we aren't trying to setup a target mode interface
1757 + * in host mode.
1758 + */
1759 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1760 + if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
1761 + cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
1762 + "on port0, but port0 is not in host mode\n");
1763 + return -1;
1764 + }
1765 +
1766 + /*
1767 + * Make sure a CN52XX isn't trying to bring up port 1 when it
1768 + * is disabled.
1769 + */
1770 + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1771 + npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1772 + if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
1773 + cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
1774 + "called on port1, but port1 is disabled\n");
1775 + return -1;
1776 + }
1777 + }
1778 +
1779 + /*
1780 + * PCIe switch arbitration mode. '0' == fixed priority NPEI,
1781 + * PCIe0, then PCIe1. '1' == round robin.
1782 + */
1783 + npei_ctl_status.s.arb = 1;
1784 + /* Allow up to 0x20 config retries */
1785 + npei_ctl_status.s.cfg_rtry = 0x20;
1786 + /*
1787 + * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
1788 + * don't reset.
1789 + */
1790 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1791 + npei_ctl_status.s.p0_ntags = 0x20;
1792 + npei_ctl_status.s.p1_ntags = 0x20;
1793 + }
1794 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
1795 +
1796 + /* Bring the PCIe out of reset */
1797 + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
1798 + /*
1799 + * The EBH5200 board swapped the PCIe reset lines on
1800 + * the board. As a workaround for this bug, we bring
1801 + * both PCIe ports out of reset at the same time
1802 + * instead of on separate calls. So for port 0, we
1803 + * bring both out of reset and do nothing on port 1.
1804 + */
1805 + if (pcie_port == 0) {
1806 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1807 + /*
1808 + * After a chip reset the PCIe will also be in
1809 + * reset. If it isn't, most likely someone is
1810 + * trying to init it again without a proper
1811 + * PCIe reset.
1812 + */
1813 + if (ciu_soft_prst.s.soft_prst == 0) {
1814 + /* Reset the ports */
1815 + ciu_soft_prst.s.soft_prst = 1;
1816 + cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1817 + ciu_soft_prst.u64);
1818 + ciu_soft_prst.u64 =
1819 + cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1820 + ciu_soft_prst.s.soft_prst = 1;
1821 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1822 + ciu_soft_prst.u64);
1823 + /* Wait until pcie resets the ports. */
1824 + udelay(2000);
1825 + }
1826 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1827 + ciu_soft_prst.s.soft_prst = 0;
1828 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1829 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1830 + ciu_soft_prst.s.soft_prst = 0;
1831 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1832 + }
1833 + } else {
1834 + /*
1835 + * The normal case: The PCIe ports are completely
1836 + * separate and can be brought out of reset
1837 + * independently.
1838 + */
1839 + if (pcie_port)
1840 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1841 + else
1842 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1843 + /*
1844 + * After a chip reset the PCIe will also be in
1845 + * reset. If it isn't, most likely someone is trying
1846 + * to init it again without a proper PCIe reset.
1847 + */
1848 + if (ciu_soft_prst.s.soft_prst == 0) {
1849 + /* Reset the port */
1850 + ciu_soft_prst.s.soft_prst = 1;
1851 + if (pcie_port)
1852 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1853 + ciu_soft_prst.u64);
1854 + else
1855 + cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1856 + ciu_soft_prst.u64);
1857 + /* Wait until pcie resets the ports. */
1858 + udelay(2000);
1859 + }
1860 + if (pcie_port) {
1861 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1862 + ciu_soft_prst.s.soft_prst = 0;
1863 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1864 + } else {
1865 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1866 + ciu_soft_prst.s.soft_prst = 0;
1867 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1868 + }
1869 + }
1870 +
1871 + /*
1872 + * Wait for PCIe reset to complete. Due to errata PCIE-700, we
1873 + * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
1874 + * fixed number of cycles.
1875 + */
1876 + cvmx_wait(400000);
1877 +
1878 + /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
1879 + CN52XX, so we only probe it on newer chips */
1880 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
1881 + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1882 + /* Clear PCLK_RUN so we can check if the clock is running */
1883 + pescx_ctl_status2.u64 =
1884 + cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1885 + pescx_ctl_status2.s.pclk_run = 1;
1886 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
1887 + pescx_ctl_status2.u64);
1888 + /*
1889 + * Now that we cleared PCLK_RUN, wait for it to be set
1890 + * again telling us the clock is running.
1891 + */
1892 + if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
1893 + union cvmx_pescx_ctl_status2,
1894 + pclk_run, ==, 1, 10000)) {
1895 + cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
1896 + pcie_port);
1897 + return -1;
1898 + }
1899 + }
1900 +
1901 + /*
1902 + * Check and make sure PCIe came out of reset. If it doesn't
1903 + * the board probably hasn't wired the clocks up and the
1904 + * interface should be skipped.
1905 + */
1906 + pescx_ctl_status2.u64 =
1907 + cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1908 + if (pescx_ctl_status2.s.pcierst) {
1909 + cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
1910 + pcie_port);
1911 + return -1;
1912 + }
1913 +
1914 + /*
1915 + * Check BIST2 status. If any bits are set skip this interface. This
1916 + * is an attempt to catch PCIE-813 on pass 1 parts.
1917 + */
1918 + pescx_bist_status2.u64 =
1919 + cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
1920 + if (pescx_bist_status2.u64) {
1921 + cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
1922 + "port isn't hooked up, skipping.\n",
1923 + pcie_port);
1924 + return -1;
1925 + }
1926 +
1927 + /* Check BIST status */
1928 + pescx_bist_status.u64 =
1929 + cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
1930 + if (pescx_bist_status.u64)
1931 + cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
1932 + pcie_port, CAST64(pescx_bist_status.u64));
1933 +
1934 + /* Initialize the config space CSRs */
1935 + __cvmx_pcie_rc_initialize_config_space(pcie_port);
1936 +
1937 + /* Bring the link up */
1938 + if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
1939 + cvmx_dprintf
1940 + ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
1941 + return -1;
1942 + }
1943 +
1944 + /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1945 + npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
1946 + /* Allow 16 words to combine */
1947 + npei_mem_access_ctl.s.max_word = 0;
1948 + /* Wait up to 127 cycles for more data */
1949 + npei_mem_access_ctl.s.timer = 127;
1950 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
1951 +
1952 + /* Setup Mem access SubDIDs */
1953 + mem_access_subid.u64 = 0;
1954 + /* Port the request is sent to. */
1955 + mem_access_subid.s.port = pcie_port;
1956 + /* Due to an errata on pass 1 chips, no merging is allowed. */
1957 + mem_access_subid.s.nmerge = 1;
1958 + /* Endian-swap for Reads. */
1959 + mem_access_subid.s.esr = 1;
1960 + /* Endian-swap for Writes. */
1961 + mem_access_subid.s.esw = 1;
1962 + /* No Snoop for Reads. */
1963 + mem_access_subid.s.nsr = 1;
1964 + /* No Snoop for Writes. */
1965 + mem_access_subid.s.nsw = 1;
1966 + /* Disable Relaxed Ordering for Reads. */
1967 + mem_access_subid.s.ror = 0;
1968 + /* Disable Relaxed Ordering for Writes. */
1969 + mem_access_subid.s.row = 0;
1970 + /* PCIe Adddress Bits <63:34>. */
1971 + mem_access_subid.s.ba = 0;
1972 +
1973 + /*
1974 + * Setup mem access 12-15 for port 0, 16-19 for port 1,
1975 + * supplying 36 bits of address space.
1976 + */
1977 + for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1978 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
1979 + mem_access_subid.u64);
1980 + /* Set each SUBID to extend the addressable range */
1981 + mem_access_subid.s.ba += 1;
1982 + }
1983 +
1984 + /*
1985 + * Disable the peer to peer forwarding register. This must be
1986 + * setup by the OS after it enumerates the bus and assigns
1987 + * addresses to the PCIe busses.
1988 + */
1989 + for (i = 0; i < 4; i++) {
1990 + cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
1991 + cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
1992 + }
1993 +
1994 + /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1995 + cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
1996 +
1997 + /*
1998 + * Disable Octeon's BAR1. It isn't needed in RC mode since
1999 + * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
2000 + * the 2nd 256MB of memory.
2001 + */
2002 + cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
2003 +
2004 + /*
2005 + * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
2006 + * precedence where they overlap. It also overlaps with the
2007 + * device addresses, so make sure the peer to peer forwarding
2008 + * is set right.
2009 + */
2010 + cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
2011 +
2012 + /*
2013 + * Setup BAR2 attributes
2014 + *
2015 + * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
2016 + * - PTLP_RO,CTLP_RO should normally be set (except for debug).
2017 + * - WAIT_COM=0 will likely work for all applications.
2018 + *
2019 + * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
2020 + */
2021 + if (pcie_port) {
2022 + union cvmx_npei_ctl_port1 npei_ctl_port;
2023 + npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
2024 + npei_ctl_port.s.bar2_enb = 1;
2025 + npei_ctl_port.s.bar2_esx = 1;
2026 + npei_ctl_port.s.bar2_cax = 0;
2027 + npei_ctl_port.s.ptlp_ro = 1;
2028 + npei_ctl_port.s.ctlp_ro = 1;
2029 + npei_ctl_port.s.wait_com = 0;
2030 + npei_ctl_port.s.waitl_com = 0;
2031 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
2032 + } else {
2033 + union cvmx_npei_ctl_port0 npei_ctl_port;
2034 + npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
2035 + npei_ctl_port.s.bar2_enb = 1;
2036 + npei_ctl_port.s.bar2_esx = 1;
2037 + npei_ctl_port.s.bar2_cax = 0;
2038 + npei_ctl_port.s.ptlp_ro = 1;
2039 + npei_ctl_port.s.ctlp_ro = 1;
2040 + npei_ctl_port.s.wait_com = 0;
2041 + npei_ctl_port.s.waitl_com = 0;
2042 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
2043 + }
2044 + return 0;
2045 +}
2046 +
2047 +/**
2048 + * Shutdown a PCIe port and put it in reset
2049 + *
2050 + * @pcie_port: PCIe port to shutdown
2051 + *
2052 + * Returns Zero on success
2053 + */
2054 +int cvmx_pcie_rc_shutdown(int pcie_port)
2055 +{
2056 + /* Wait for all pending operations to complete */
2057 + if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port),
2058 + union cvmx_pescx_cpl_lut_valid,
2059 + tag, ==, 0, 2000))
2060 + cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
2061 +
2062 + /* Force reset */
2063 + if (pcie_port) {
2064 + union cvmx_ciu_soft_prst ciu_soft_prst;
2065 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
2066 + ciu_soft_prst.s.soft_prst = 1;
2067 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
2068 + } else {
2069 + union cvmx_ciu_soft_prst ciu_soft_prst;
2070 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
2071 + ciu_soft_prst.s.soft_prst = 1;
2072 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
2073 + }
2074 + return 0;
2075 +}
2076 +
2077 +/**
2078 + * Build a PCIe config space request address for a device
2079 + *
2080 + * @pcie_port: PCIe port to access
2081 + * @bus: Sub bus
2082 + * @dev: Device ID
2083 + * @fn: Device sub function
2084 + * @reg: Register to access
2085 + *
2086 + * Returns 64bit Octeon IO address
2087 + */
2088 +static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
2089 + int dev, int fn, int reg)
2090 +{
2091 + union cvmx_pcie_address pcie_addr;
2092 + union cvmx_pciercx_cfg006 pciercx_cfg006;
2093 +
2094 + pciercx_cfg006.u32 =
2095 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
2096 + if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
2097 + return 0;
2098 +
2099 + pcie_addr.u64 = 0;
2100 + pcie_addr.config.upper = 2;
2101 + pcie_addr.config.io = 1;
2102 + pcie_addr.config.did = 3;
2103 + pcie_addr.config.subdid = 1;
2104 + pcie_addr.config.es = 1;
2105 + pcie_addr.config.port = pcie_port;
2106 + pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
2107 + pcie_addr.config.bus = bus;
2108 + pcie_addr.config.dev = dev;
2109 + pcie_addr.config.func = fn;
2110 + pcie_addr.config.reg = reg;
2111 + return pcie_addr.u64;
2112 +}
2113 +
2114 +/**
2115 + * Read 8bits from a Device's config space
2116 + *
2117 + * @pcie_port: PCIe port the device is on
2118 + * @bus: Sub bus
2119 + * @dev: Device ID
2120 + * @fn: Device sub function
2121 + * @reg: Register to access
2122 + *
2123 + * Returns Result of the read
2124 + */
2125 +uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
2126 + int fn, int reg)
2127 +{
2128 + uint64_t address =
2129 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2130 + if (address)
2131 + return cvmx_read64_uint8(address);
2132 + else
2133 + return 0xff;
2134 +}
2135 +
2136 +/**
2137 + * Read 16bits from a Device's config space
2138 + *
2139 + * @pcie_port: PCIe port the device is on
2140 + * @bus: Sub bus
2141 + * @dev: Device ID
2142 + * @fn: Device sub function
2143 + * @reg: Register to access
2144 + *
2145 + * Returns Result of the read
2146 + */
2147 +uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
2148 + int reg)
2149 +{
2150 + uint64_t address =
2151 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2152 + if (address)
2153 + return le16_to_cpu(cvmx_read64_uint16(address));
2154 + else
2155 + return 0xffff;
2156 +}
2157 +
2158 +/**
2159 + * Read 32bits from a Device's config space
2160 + *
2161 + * @pcie_port: PCIe port the device is on
2162 + * @bus: Sub bus
2163 + * @dev: Device ID
2164 + * @fn: Device sub function
2165 + * @reg: Register to access
2166 + *
2167 + * Returns Result of the read
2168 + */
2169 +uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
2170 + int reg)
2171 +{
2172 + uint64_t address =
2173 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2174 + if (address)
2175 + return le32_to_cpu(cvmx_read64_uint32(address));
2176 + else
2177 + return 0xffffffff;
2178 +}
2179 +
2180 +/**
2181 + * Write 8bits to a Device's config space
2182 + *
2183 + * @pcie_port: PCIe port the device is on
2184 + * @bus: Sub bus
2185 + * @dev: Device ID
2186 + * @fn: Device sub function
2187 + * @reg: Register to access
2188 + * @val: Value to write
2189 + */
2190 +void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
2191 + int reg, uint8_t val)
2192 +{
2193 + uint64_t address =
2194 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2195 + if (address)
2196 + cvmx_write64_uint8(address, val);
2197 +}
2198 +
2199 +/**
2200 + * Write 16bits to a Device's config space
2201 + *
2202 + * @pcie_port: PCIe port the device is on
2203 + * @bus: Sub bus
2204 + * @dev: Device ID
2205 + * @fn: Device sub function
2206 + * @reg: Register to access
2207 + * @val: Value to write
2208 + */
2209 +void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
2210 + int reg, uint16_t val)
2211 +{
2212 + uint64_t address =
2213 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2214 + if (address)
2215 + cvmx_write64_uint16(address, cpu_to_le16(val));
2216 +}
2217 +
2218 +/**
2219 + * Write 32bits to a Device's config space
2220 + *
2221 + * @pcie_port: PCIe port the device is on
2222 + * @bus: Sub bus
2223 + * @dev: Device ID
2224 + * @fn: Device sub function
2225 + * @reg: Register to access
2226 + * @val: Value to write
2227 + */
2228 +void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
2229 + int reg, uint32_t val)
2230 +{
2231 + uint64_t address =
2232 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2233 + if (address)
2234 + cvmx_write64_uint32(address, cpu_to_le32(val));
2235 +}
2236 +
2237 +/**
2238 + * Read a PCIe config space register indirectly. This is used for
2239 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2240 + *
2241 + * @pcie_port: PCIe port to read from
2242 + * @cfg_offset: Address to read
2243 + *
2244 + * Returns Value read
2245 + */
2246 +uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
2247 +{
2248 + union cvmx_pescx_cfg_rd pescx_cfg_rd;
2249 + pescx_cfg_rd.u64 = 0;
2250 + pescx_cfg_rd.s.addr = cfg_offset;
2251 + cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
2252 + pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
2253 + return pescx_cfg_rd.s.data;
2254 +}
2255 +
2256 +/**
2257 + * Write a PCIe config space register indirectly. This is used for
2258 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2259 + *
2260 + * @pcie_port: PCIe port to write to
2261 + * @cfg_offset: Address to write
2262 + * @val: Value to write
2263 + */
2264 +void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
2265 +{
2266 + union cvmx_pescx_cfg_wr pescx_cfg_wr;
2267 + pescx_cfg_wr.u64 = 0;
2268 + pescx_cfg_wr.s.addr = cfg_offset;
2269 + pescx_cfg_wr.s.data = val;
2270 + cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
2271 +}
2272 +
2273 +/**
2274 + * Initialize a PCIe port for use in target(EP) mode.
2275 + *
2276 + * Returns Zero on success
2277 + */
2278 +int cvmx_pcie_ep_initialize(void)
2279 +{
2280 + int pcie_port = 0;
2281 + union cvmx_npei_ctl_status npei_ctl_status;
2282 + union cvmx_pciercx_cfg030 pciercx_cfg030;
2283 + union cvmx_npei_ctl_status2 npei_ctl_status2;
2284 + union cvmx_npei_mem_access_subidx mem_access_subid;
2285 +
2286 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
2287 + if (npei_ctl_status.s.host_mode)
2288 + return -1;
2289 +
2290 + /* Enable bus master and memory */
2291 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEP_CFG001, 0x6);
2292 +
2293 + /*
2294 + * Max Payload Size (PCIE*_CFG030[MPS])
2295 + * Max Read Request Size (PCIE*_CFG030[MRRS])
2296 + * Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN]
2297 + * Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN])
2298 + */
2299 + pciercx_cfg030.u32 =
2300 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
2301 + /* Max payload size = 128 bytes (Limit of most PCs) */
2302 + pciercx_cfg030.s.mps = 0;
2303 + /*
2304 + * Max read request size = 128 bytes for best Octeon DMA
2305 + * performance.
2306 + */
2307 + pciercx_cfg030.s.mrrs = 0;
2308 + /* Enable relaxed ordering. */
2309 + pciercx_cfg030.s.ro_en = 1;
2310 + /* Enable no snoop. */
2311 + pciercx_cfg030.s.ns_en = 1;
2312 + /* Correctable error reporting enable. */
2313 + pciercx_cfg030.s.ce_en = 1;
2314 + /* Non-fatal error reporting enable. */
2315 + pciercx_cfg030.s.nfe_en = 1;
2316 + /* Fatal error reporting enable. */
2317 + pciercx_cfg030.s.fe_en = 1;
2318 + /* Unsupported request reporting enable. */
2319 + pciercx_cfg030.s.ur_en = 1;
2320 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
2321 + pciercx_cfg030.u32);
2322 +
2323 + /*
2324 + * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
2325 + * PCIE*_CFG030[MPS]
2326 + *
2327 + * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
2328 + * exceed PCIE*_CFG030[MRRS]
2329 + */
2330 + npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
2331 + /* Max payload size = 128 bytes (Limit of most PCs) */
2332 + npei_ctl_status2.s.mps = 0;
2333 + /* Max read request size = 128 bytes for best Octeon DMA performance */
2334 + npei_ctl_status2.s.mrrs = 0;
2335 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
2336 +
2337 + /* Setup Mem access SubDID 12 to access Host memory */
2338 + mem_access_subid.u64 = 0;
2339 + /* Port the request is sent to. */
2340 + mem_access_subid.s.port = pcie_port;
2341 + /* Merging is allowed in this window. */
2342 + mem_access_subid.s.nmerge = 1;
2343 + /* Endian-swap for Reads. */
2344 + mem_access_subid.s.esr = 0;
2345 + /* Endian-swap for Writes. */
2346 + mem_access_subid.s.esw = 0;
2347 + /* No Snoop for Reads. */
2348 + mem_access_subid.s.nsr = 1;
2349 + /* No Snoop for Writes. */
2350 + mem_access_subid.s.nsw = 1;
2351 + /* Disable Relaxed Ordering for Reads. */
2352 + mem_access_subid.s.ror = 0;
2353 + /* Disable Relaxed Ordering for Writes. */
2354 + mem_access_subid.s.row = 0;
2355 + /* PCIe Adddress Bits <63:34>. */
2356 + mem_access_subid.s.ba = 0;
2357 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(12),
2358 + mem_access_subid.u64);
2359 + return 0;
2360 +}
2361 diff --git a/arch/mips/cavium-octeon/msi.c b/arch/mips/cavium-octeon/msi.c
2362 new file mode 100644
2363 index 0000000..964b03b
2364 --- /dev/null
2365 +++ b/arch/mips/cavium-octeon/msi.c
2366 @@ -0,0 +1,288 @@
2367 +/*
2368 + * This file is subject to the terms and conditions of the GNU General Public
2369 + * License. See the file "COPYING" in the main directory of this archive
2370 + * for more details.
2371 + *
2372 + * Copyright (C) 2005-2007 Cavium Networks
2373 + */
2374 +#include <linux/kernel.h>
2375 +#include <linux/init.h>
2376 +#include <linux/msi.h>
2377 +#include <linux/spinlock.h>
2378 +#include <linux/interrupt.h>
2379 +
2380 +#include <asm/octeon/octeon.h>
2381 +#include <asm/octeon/cvmx-npi-defs.h>
2382 +#include <asm/octeon/cvmx-pci-defs.h>
2383 +#include <asm/octeon/cvmx-npei-defs.h>
2384 +#include <asm/octeon/cvmx-pexp-defs.h>
2385 +
2386 +#include "pci-common.h"
2387 +
2388 +/*
2389 + * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
2390 + * in use.
2391 + */
2392 +static uint64_t msi_free_irq_bitmask;
2393 +
2394 +/*
2395 + * Each bit in msi_multiple_irq_bitmask tells that the device using
2396 + * this bit in msi_free_irq_bitmask is also using the next bit. This
2397 + * is used so we can disable all of the MSI interrupts when a device
2398 + * uses multiple.
2399 + */
2400 +static uint64_t msi_multiple_irq_bitmask;
2401 +
2402 +/*
2403 + * This lock controls updates to msi_free_irq_bitmask and
2404 + * msi_multiple_irq_bitmask.
2405 + */
2406 +static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
2407 +
2408 +
2409 +/**
2410 + * Called when a driver request MSI interrupts instead of the
2411 + * legacy INT A-D. This routine will allocate multiple interrupts
2412 + * for MSI devices that support them. A device can override this by
2413 + * programming the MSI control bits [6:4] before calling
2414 + * pci_enable_msi().
2415 + *
2416 + * @param dev Device requesting MSI interrupts
2417 + * @param desc MSI descriptor
2418 + *
2419 + * Returns 0 on success.
2420 + */
2421 +int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2422 +{
2423 + struct msi_msg msg;
2424 + uint16_t control;
2425 + int configured_private_bits;
2426 + int request_private_bits;
2427 + int irq;
2428 + int irq_step;
2429 + uint64_t search_mask;
2430 +
2431 + /*
2432 + * Read the MSI config to figure out how many IRQs this device
2433 + * wants. Most devices only want 1, which will give
2434 + * configured_private_bits and request_private_bits equal 0.
2435 + */
2436 + pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2437 + &control);
2438 +
2439 + /*
2440 + * If the number of private bits has been configured then use
2441 + * that value instead of the requested number. This gives the
2442 + * driver the chance to override the number of interrupts
2443 + * before calling pci_enable_msi().
2444 + */
2445 + configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
2446 + if (configured_private_bits == 0) {
2447 + /* Nothing is configured, so use the hardware requested size */
2448 + request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
2449 + } else {
2450 + /*
2451 + * Use the number of configured bits, assuming the
2452 + * driver wanted to override the hardware request
2453 + * value.
2454 + */
2455 + request_private_bits = configured_private_bits;
2456 + }
2457 +
2458 + /*
2459 + * The PCI 2.3 spec mandates that there are at most 32
2460 + * interrupts. If this device asks for more, only give it one.
2461 + */
2462 + if (request_private_bits > 5)
2463 + request_private_bits = 0;
2464 +
2465 +try_only_one:
2466 + /*
2467 + * The IRQs have to be aligned on a power of two based on the
2468 + * number being requested.
2469 + */
2470 + irq_step = 1 << request_private_bits;
2471 +
2472 + /* Mask with one bit for each IRQ */
2473 + search_mask = (1 << irq_step) - 1;
2474 +
2475 + /*
2476 + * We're going to search msi_free_irq_bitmask_lock for zero
2477 + * bits. This represents an MSI interrupt number that isn't in
2478 + * use.
2479 + */
2480 + spin_lock(&msi_free_irq_bitmask_lock);
2481 + for (irq = 0; irq < 64; irq += irq_step) {
2482 + if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
2483 + msi_free_irq_bitmask |= search_mask << irq;
2484 + msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
2485 + break;
2486 + }
2487 + }
2488 + spin_unlock(&msi_free_irq_bitmask_lock);
2489 +
2490 + /* Make sure the search for available interrupts didn't fail */
2491 + if (irq >= 64) {
2492 + if (request_private_bits) {
2493 + pr_err("arch_setup_msi_irq: Unable to find %d free "
2494 + "interrupts, trying just one",
2495 + 1 << request_private_bits);
2496 + request_private_bits = 0;
2497 + goto try_only_one;
2498 + } else
2499 + panic("arch_setup_msi_irq: Unable to find a free MSI "
2500 + "interrupt");
2501 + }
2502 +
2503 + /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
2504 + irq += OCTEON_IRQ_MSI_BIT0;
2505 +
2506 + switch (octeon_dma_bar_type) {
2507 + case OCTEON_DMA_BAR_TYPE_SMALL:
2508 + /* When not using big bar, Bar 0 is based at 128MB */
2509 + msg.address_lo =
2510 + ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
2511 + msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
2512 + case OCTEON_DMA_BAR_TYPE_BIG:
2513 + /* When using big bar, Bar 0 is based at 0 */
2514 + msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
2515 + msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
2516 + break;
2517 + case OCTEON_DMA_BAR_TYPE_PCIE:
2518 + /* When using PCIe, Bar 0 is based at 0 */
2519 + /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
2520 + msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
2521 + msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
2522 + break;
2523 + default:
2524 + panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
2525 + }
2526 + msg.data = irq - OCTEON_IRQ_MSI_BIT0;
2527 +
2528 + /* Update the number of IRQs the device has available to it */
2529 + control &= ~PCI_MSI_FLAGS_QSIZE;
2530 + control |= request_private_bits << 4;
2531 + pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2532 + control);
2533 +
2534 + set_irq_msi(irq, desc);
2535 + write_msi_msg(irq, &msg);
2536 + return 0;
2537 +}
2538 +
2539 +
2540 +/**
2541 + * Called when a device no longer needs its MSI interrupts. All
2542 + * MSI interrupts for the device are freed.
2543 + *
2544 + * @irq: The devices first irq number. There may be multple in sequence.
2545 + */
2546 +void arch_teardown_msi_irq(unsigned int irq)
2547 +{
2548 + int number_irqs;
2549 + uint64_t bitmask;
2550 +
2551 + if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
2552 + panic("arch_teardown_msi_irq: Attempted to teardown illegal "
2553 + "MSI interrupt (%d)", irq);
2554 + irq -= OCTEON_IRQ_MSI_BIT0;
2555 +
2556 + /*
2557 + * Count the number of IRQs we need to free by looking at the
2558 + * msi_multiple_irq_bitmask. Each bit set means that the next
2559 + * IRQ is also owned by this device.
2560 + */
2561 + number_irqs = 0;
2562 + while ((irq+number_irqs < 64) &&
2563 + (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
2564 + number_irqs++;
2565 + number_irqs++;
2566 + /* Mask with one bit for each IRQ */
2567 + bitmask = (1 << number_irqs) - 1;
2568 + /* Shift the mask to the correct bit location */
2569 + bitmask <<= irq;
2570 + if ((msi_free_irq_bitmask & bitmask) != bitmask)
2571 + panic("arch_teardown_msi_irq: Attempted to teardown MSI "
2572 + "interrupt (%d) not in use", irq);
2573 +
2574 + /* Checks are done, update the in use bitmask */
2575 + spin_lock(&msi_free_irq_bitmask_lock);
2576 + msi_free_irq_bitmask &= ~bitmask;
2577 + msi_multiple_irq_bitmask &= ~bitmask;
2578 + spin_unlock(&msi_free_irq_bitmask_lock);
2579 +}
2580 +
2581 +
2582 +/**
2583 + * Called by the interrupt handling code when an MSI interrupt
2584 + * occurs.
2585 + *
2586 + * @param cpl
2587 + * @param dev_id
2588 + *
2589 + * @return
2590 + */
2591 +static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
2592 +{
2593 + uint64_t msi_bits;
2594 + int irq;
2595 +
2596 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
2597 + msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
2598 + else
2599 + msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
2600 + irq = fls64(msi_bits);
2601 + if (irq) {
2602 + irq += OCTEON_IRQ_MSI_BIT0 - 1;
2603 + if (irq_desc[irq].action) {
2604 + do_IRQ(irq);
2605 + return IRQ_HANDLED;
2606 + } else {
2607 + pr_err("Spurious MSI interrupt %d\n", irq);
2608 + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2609 + /* These chips have PCIe */
2610 + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
2611 + 1ull << (irq -
2612 + OCTEON_IRQ_MSI_BIT0));
2613 + } else {
2614 + /* These chips have PCI */
2615 + cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
2616 + 1ull << (irq -
2617 + OCTEON_IRQ_MSI_BIT0));
2618 + }
2619 + }
2620 + }
2621 + return IRQ_NONE;
2622 +}
2623 +
2624 +
2625 +/**
2626 + * Initializes the MSI interrupt handling code
2627 + *
2628 + * @return
2629 + */
2630 +int octeon_msi_initialize(void)
2631 +{
2632 + int r;
2633 + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2634 + r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2635 + IRQF_SHARED,
2636 + "MSI[0:63]", octeon_msi_interrupt);
2637 + } else if (octeon_is_pci_host()) {
2638 + r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2639 + IRQF_SHARED,
2640 + "MSI[0:15]", octeon_msi_interrupt);
2641 + r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
2642 + IRQF_SHARED,
2643 + "MSI[16:31]", octeon_msi_interrupt);
2644 + r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
2645 + IRQF_SHARED,
2646 + "MSI[32:47]", octeon_msi_interrupt);
2647 + r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
2648 + IRQF_SHARED,
2649 + "MSI[48:63]", octeon_msi_interrupt);
2650 + }
2651 + return 0;
2652 +}
2653 +
2654 +subsys_initcall(octeon_msi_initialize);
2655 diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
2656 index 788d588..3d7be84 100644
2657 --- a/arch/mips/cavium-octeon/octeon-irq.c
2658 +++ b/arch/mips/cavium-octeon/octeon-irq.c
2659 @@ -10,6 +10,8 @@
2660 #include <linux/hardirq.h>
2661
2662 #include <asm/octeon/octeon.h>
2663 +#include <asm/octeon/cvmx-pexp-defs.h>
2664 +#include <asm/octeon/cvmx-npi-defs.h>
2665
2666 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
2667 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
2668 diff --git a/arch/mips/cavium-octeon/pci-common.c b/arch/mips/cavium-octeon/pci-common.c
2669 new file mode 100644
2670 index 0000000..cd029f8
2671 --- /dev/null
2672 +++ b/arch/mips/cavium-octeon/pci-common.c
2673 @@ -0,0 +1,137 @@
2674 +/*
2675 + * This file is subject to the terms and conditions of the GNU General Public
2676 + * License. See the file "COPYING" in the main directory of this archive
2677 + * for more details.
2678 + *
2679 + * Copyright (C) 2005-2007 Cavium Networks
2680 + */
2681 +#include <linux/kernel.h>
2682 +#include <linux/init.h>
2683 +#include <linux/pci.h>
2684 +#include <linux/interrupt.h>
2685 +#include <linux/time.h>
2686 +#include <linux/delay.h>
2687 +#include "pci-common.h"
2688 +
2689 +typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2690 +enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
2691 +
2692 +/**
2693 + * Map a PCI device to the appropriate interrupt line
2694 + *
2695 + * @param dev The Linux PCI device structure for the device to map
2696 + * @param slot The slot number for this device on __BUS 0__. Linux
2697 + * enumerates through all the bridges and figures out the
2698 + * slot on Bus 0 where this device eventually hooks to.
2699 + * @param pin The PCI interrupt pin read from the device, then swizzled
2700 + * as it goes through each bridge.
2701 + * @return Interrupt number for the device
2702 + */
2703 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
2704 +{
2705 + if (octeon_pcibios_map_irq)
2706 + return octeon_pcibios_map_irq(dev, slot, pin);
2707 + else
2708 + panic("octeon_pcibios_map_irq doesn't point to a "
2709 + "pcibios_map_irq() function");
2710 +}
2711 +
2712 +
2713 +/**
2714 + * Called to perform platform specific PCI setup
2715 + *
2716 + * @param dev
2717 + * @return
2718 + */
2719 +int pcibios_plat_dev_init(struct pci_dev *dev)
2720 +{
2721 + uint16_t config;
2722 + uint32_t dconfig;
2723 + int pos;
2724 + /*
2725 + * Force the Cache line setting to 64 bytes. The standard
2726 + * Linux bus scan doesn't seem to set it. Octeon really has
2727 + * 128 byte lines, but Intel bridges get really upset if you
2728 + * try and set values above 64 bytes. Value is specified in
2729 + * 32bit words.
2730 + */
2731 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
2732 + /* Set latency timers for all devices */
2733 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
2734 +
2735 + /* Enable reporting System errors and parity errors on all devices */
2736 + /* Enable parity checking and error reporting */
2737 + pci_read_config_word(dev, PCI_COMMAND, &config);
2738 + config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2739 + pci_write_config_word(dev, PCI_COMMAND, config);
2740 +
2741 + if (dev->subordinate) {
2742 + /* Set latency timers on sub bridges */
2743 + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
2744 + /* More bridge error detection */
2745 + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
2746 + config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
2747 + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
2748 + }
2749 +
2750 + /* Enable the PCIe normal error reporting */
2751 + pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2752 + if (pos) {
2753 + /* Update Device Control */
2754 + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
2755 + /* Correctable Error Reporting */
2756 + config |= PCI_EXP_DEVCTL_CERE;
2757 + /* Non-Fatal Error Reporting */
2758 + config |= PCI_EXP_DEVCTL_NFERE;
2759 + /* Fatal Error Reporting */
2760 + config |= PCI_EXP_DEVCTL_FERE;
2761 + /* Unsupported Request */
2762 + config |= PCI_EXP_DEVCTL_URRE;
2763 + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
2764 + }
2765 +
2766 + /* Find the Advanced Error Reporting capability */
2767 + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
2768 + if (pos) {
2769 + /* Clear Uncorrectable Error Status */
2770 + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2771 + &dconfig);
2772 + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2773 + dconfig);
2774 + /* Enable reporting of all uncorrectable errors */
2775 + /* Uncorrectable Error Mask - turned on bits disable errors */
2776 + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
2777 + /*
2778 + * Leave severity at HW default. This only controls if
2779 + * errors are reported as uncorrectable or
2780 + * correctable, not if the error is reported.
2781 + */
2782 + /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
2783 + /* Clear Correctable Error Status */
2784 + pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
2785 + pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
2786 + /* Enable reporting of all correctable errors */
2787 + /* Correctable Error Mask - turned on bits disable errors */
2788 + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
2789 + /* Advanced Error Capabilities */
2790 + pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
2791 + /* ECRC Generation Enable */
2792 + if (config & PCI_ERR_CAP_ECRC_GENC)
2793 + config |= PCI_ERR_CAP_ECRC_GENE;
2794 + /* ECRC Check Enable */
2795 + if (config & PCI_ERR_CAP_ECRC_CHKC)
2796 + config |= PCI_ERR_CAP_ECRC_CHKE;
2797 + pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
2798 + /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
2799 + /* Report all errors to the root complex */
2800 + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
2801 + PCI_ERR_ROOT_CMD_COR_EN |
2802 + PCI_ERR_ROOT_CMD_NONFATAL_EN |
2803 + PCI_ERR_ROOT_CMD_FATAL_EN);
2804 + /* Clear the Root status register */
2805 + pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
2806 + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
2807 + }
2808 +
2809 + return 0;
2810 +}
2811 diff --git a/arch/mips/cavium-octeon/pci-common.h b/arch/mips/cavium-octeon/pci-common.h
2812 new file mode 100644
2813 index 0000000..74ae799
2814 --- /dev/null
2815 +++ b/arch/mips/cavium-octeon/pci-common.h
2816 @@ -0,0 +1,39 @@
2817 +/*
2818 + * This file is subject to the terms and conditions of the GNU General Public
2819 + * License. See the file "COPYING" in the main directory of this archive
2820 + * for more details.
2821 + *
2822 + * Copyright (C) 2005-2007 Cavium Networks
2823 + */
2824 +#ifndef __OCTEON_PCI_COMMON_H__
2825 +#define __OCTEON_PCI_COMMON_H__
2826 +
2827 +#include <linux/pci.h>
2828 +
2829 +/* Some PCI cards require delays when accessing config space. */
2830 +#define PCI_CONFIG_SPACE_DELAY 10000
2831 +
2832 +/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
2833 + Octeon specific version pointed to by this variable. This function needs to
2834 + change for PCI or PCIe based hosts */
2835 +extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2836 +
2837 +/* The following defines are only used when octeon_dma_bar_type =
2838 + OCTEON_DMA_BAR_TYPE_BIG */
2839 +#define OCTEON_PCI_BAR1_HOLE_BITS 5
2840 +#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
2841 +
2842 +enum octeon_dma_bar_type {
2843 + OCTEON_DMA_BAR_TYPE_INVALID,
2844 + OCTEON_DMA_BAR_TYPE_SMALL,
2845 + OCTEON_DMA_BAR_TYPE_BIG,
2846 + OCTEON_DMA_BAR_TYPE_PCIE
2847 +};
2848 +
2849 +/**
2850 + * This is a variable to tell the DMA mapping system in dma-octeon.c
2851 + * how to map PCI DMA addresses.
2852 + */
2853 +extern enum octeon_dma_bar_type octeon_dma_bar_type;
2854 +
2855 +#endif
2856 diff --git a/arch/mips/cavium-octeon/pci.c b/arch/mips/cavium-octeon/pci.c
2857 new file mode 100644
2858 index 0000000..67c0ff5
2859 --- /dev/null
2860 +++ b/arch/mips/cavium-octeon/pci.c
2861 @@ -0,0 +1,568 @@
2862 +/*
2863 + * This file is subject to the terms and conditions of the GNU General Public
2864 + * License. See the file "COPYING" in the main directory of this archive
2865 + * for more details.
2866 + *
2867 + * Copyright (C) 2005-2007 Cavium Networks
2868 + */
2869 +#include <linux/kernel.h>
2870 +#include <linux/init.h>
2871 +#include <linux/pci.h>
2872 +#include <linux/interrupt.h>
2873 +#include <linux/time.h>
2874 +#include <linux/delay.h>
2875 +
2876 +#include <asm/time.h>
2877 +
2878 +#include <asm/octeon/octeon.h>
2879 +#include <asm/octeon/cvmx-npi-defs.h>
2880 +#include <asm/octeon/cvmx-pci-defs.h>
2881 +
2882 +#include "pci-common.h"
2883 +
2884 +#define USE_OCTEON_INTERNAL_ARBITER
2885 +
2886 +/*
2887 + * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
2888 + * addresses. Use PCI endian swapping 1 so no address swapping is
2889 + * necessary. The Linux io routines will endian swap the data.
2890 + */
2891 +#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
2892 +#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
2893 +
2894 +/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
2895 +#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
2896 +
2897 +/**
2898 + * This is the bit decoding used for the Octeon PCI controller addresses
2899 + */
2900 +union octeon_pci_address {
2901 + uint64_t u64;
2902 + struct {
2903 + uint64_t upper:2;
2904 + uint64_t reserved:13;
2905 + uint64_t io:1;
2906 + uint64_t did:5;
2907 + uint64_t subdid:3;
2908 + uint64_t reserved2:4;
2909 + uint64_t endian_swap:2;
2910 + uint64_t reserved3:10;
2911 + uint64_t bus:8;
2912 + uint64_t dev:5;
2913 + uint64_t func:3;
2914 + uint64_t reg:8;
2915 + } s;
2916 +};
2917 +
2918 +/**
2919 + * Return the mapping of PCI device number to IRQ line. Each
2920 + * character in the return string represents the interrupt
2921 + * line for the device at that position. Device 1 maps to the
2922 + * first character, etc. The characters A-D are used for PCI
2923 + * interrupts.
2924 + *
2925 + * Returns PCI interrupt mapping
2926 + */
2927 +const char *octeon_get_pci_interrupts(void)
2928 +{
2929 + /*
2930 + * Returning an empty string causes the interrupts to be
2931 + * routed based on the PCI specification. From the PCI spec:
2932 + *
2933 + * INTA# of Device Number 0 is connected to IRQW on the system
2934 + * board. (Device Number has no significance regarding being
2935 + * located on the system board or in a connector.) INTA# of
2936 + * Device Number 1 is connected to IRQX on the system
2937 + * board. INTA# of Device Number 2 is connected to IRQY on the
2938 + * system board. INTA# of Device Number 3 is connected to IRQZ
2939 + * on the system board. The table below describes how each
2940 + * agent's INTx# lines are connected to the system board
2941 + * interrupt lines. The following equation can be used to
2942 + * determine to which INTx# signal on the system board a given
2943 + * device's INTx# line(s) is connected.
2944 + *
2945 + * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
2946 + * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
2947 + * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
2948 + * INTD# = 3)
2949 + */
2950 + switch (octeon_bootinfo->board_type) {
2951 + case CVMX_BOARD_TYPE_NAO38:
2952 + /* This is really the NAC38 */
2953 + return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
2954 + case CVMX_BOARD_TYPE_THUNDER:
2955 + return "";
2956 + case CVMX_BOARD_TYPE_EBH3000:
2957 + return "";
2958 + case CVMX_BOARD_TYPE_EBH3100:
2959 + case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
2960 + case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
2961 + return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
2962 + case CVMX_BOARD_TYPE_BBGW_REF:
2963 + return "AABCD";
2964 + default:
2965 + return "";
2966 + }
2967 +}
2968 +
2969 +/**
2970 + * Map a PCI device to the appropriate interrupt line
2971 + *
2972 + * @dev: The Linux PCI device structure for the device to map
2973 + * @slot: The slot number for this device on __BUS 0__. Linux
2974 + * enumerates through all the bridges and figures out the
2975 + * slot on Bus 0 where this device eventually hooks to.
2976 + * @pin: The PCI interrupt pin read from the device, then swizzled
2977 + * as it goes through each bridge.
2978 + * Returns Interrupt number for the device
2979 + */
2980 +int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
2981 + u8 slot, u8 pin)
2982 +{
2983 + int irq_num;
2984 + const char *interrupts;
2985 + int dev_num;
2986 +
2987 + /* Get the board specific interrupt mapping */
2988 + interrupts = octeon_get_pci_interrupts();
2989 +
2990 + dev_num = dev->devfn >> 3;
2991 + if (dev_num < strlen(interrupts))
2992 + irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
2993 + OCTEON_IRQ_PCI_INT0;
2994 + else
2995 + irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
2996 + return irq_num;
2997 +}
2998 +
2999 +
3000 +/**
3001 + * Read a value from configuration space
3002 + *
3003 + */
3004 +static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
3005 + int reg, int size, u32 *val)
3006 +{
3007 + union octeon_pci_address pci_addr;
3008 +
3009 + pci_addr.u64 = 0;
3010 + pci_addr.s.upper = 2;
3011 + pci_addr.s.io = 1;
3012 + pci_addr.s.did = 3;
3013 + pci_addr.s.subdid = 1;
3014 + pci_addr.s.endian_swap = 1;
3015 + pci_addr.s.bus = bus->number;
3016 + pci_addr.s.dev = devfn >> 3;
3017 + pci_addr.s.func = devfn & 0x7;
3018 + pci_addr.s.reg = reg;
3019 +
3020 +#if PCI_CONFIG_SPACE_DELAY
3021 + udelay(PCI_CONFIG_SPACE_DELAY);
3022 +#endif
3023 + switch (size) {
3024 + case 4:
3025 + *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
3026 + return PCIBIOS_SUCCESSFUL;
3027 + case 2:
3028 + *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
3029 + return PCIBIOS_SUCCESSFUL;
3030 + case 1:
3031 + *val = cvmx_read64_uint8(pci_addr.u64);
3032 + return PCIBIOS_SUCCESSFUL;
3033 + }
3034 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3035 +}
3036 +
3037 +
3038 +/**
3039 + * Write a value to PCI configuration space
3040 + *
3041 + * @bus:
3042 + * @devfn:
3043 + * @reg:
3044 + * @size:
3045 + * @val:
3046 + * Returns
3047 + */
3048 +static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
3049 + int reg, int size, u32 val)
3050 +{
3051 + union octeon_pci_address pci_addr;
3052 +
3053 + pci_addr.u64 = 0;
3054 + pci_addr.s.upper = 2;
3055 + pci_addr.s.io = 1;
3056 + pci_addr.s.did = 3;
3057 + pci_addr.s.subdid = 1;
3058 + pci_addr.s.endian_swap = 1;
3059 + pci_addr.s.bus = bus->number;
3060 + pci_addr.s.dev = devfn >> 3;
3061 + pci_addr.s.func = devfn & 0x7;
3062 + pci_addr.s.reg = reg;
3063 +
3064 +#if PCI_CONFIG_SPACE_DELAY
3065 + udelay(PCI_CONFIG_SPACE_DELAY);
3066 +#endif
3067 + switch (size) {
3068 + case 4:
3069 + cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
3070 + return PCIBIOS_SUCCESSFUL;
3071 + case 2:
3072 + cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
3073 + return PCIBIOS_SUCCESSFUL;
3074 + case 1:
3075 + cvmx_write64_uint8(pci_addr.u64, val);
3076 + return PCIBIOS_SUCCESSFUL;
3077 + }
3078 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3079 +}
3080 +
3081 +
3082 +static struct pci_ops octeon_pci_ops = {
3083 + octeon_read_config,
3084 + octeon_write_config,
3085 +};
3086 +
3087 +static struct resource octeon_pci_mem_resource = {
3088 + .start = 0,
3089 + .end = 0,
3090 + .name = "Octeon PCI MEM",
3091 + .flags = IORESOURCE_MEM,
3092 +};
3093 +
3094 +/*
3095 + * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
3096 + * bridge
3097 + */
3098 +static struct resource octeon_pci_io_resource = {
3099 + .start = 0x4000,
3100 + .end = OCTEON_PCI_IOSPACE_SIZE - 1,
3101 + .name = "Octeon PCI IO",
3102 + .flags = IORESOURCE_IO,
3103 +};
3104 +
3105 +static struct pci_controller octeon_pci_controller = {
3106 + .pci_ops = &octeon_pci_ops,
3107 + .mem_resource = &octeon_pci_mem_resource,
3108 + .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
3109 + .io_resource = &octeon_pci_io_resource,
3110 + .io_offset = 0,
3111 + .io_map_base = OCTEON_PCI_IOSPACE_BASE,
3112 +};
3113 +
3114 +
3115 +/**
3116 + * Low level initialize the Octeon PCI controller
3117 + *
3118 + * Returns
3119 + */
3120 +static void octeon_pci_initialize(void)
3121 +{
3122 + union cvmx_pci_cfg01 cfg01;
3123 + union cvmx_npi_ctl_status ctl_status;
3124 + union cvmx_pci_ctl_status_2 ctl_status_2;
3125 + union cvmx_pci_cfg19 cfg19;
3126 + union cvmx_pci_cfg16 cfg16;
3127 + union cvmx_pci_cfg22 cfg22;
3128 + union cvmx_pci_cfg56 cfg56;
3129 +
3130 + /* Reset the PCI Bus */
3131 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
3132 + cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3133 +
3134 + udelay(2000); /* Hold PCI reset for 2 ms */
3135 +
3136 + ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
3137 + ctl_status.s.max_word = 1;
3138 + ctl_status.s.timer = 1;
3139 + cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
3140 +
3141 + /* Deassert PCI reset and advertize PCX Host Mode Device Capability
3142 + (64b) */
3143 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
3144 + cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3145 +
3146 + udelay(2000); /* Wait 2 ms after deasserting PCI reset */
3147 +
3148 + ctl_status_2.u32 = 0;
3149 + ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
3150 + before any PCI reads. */
3151 + ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
3152 + ctl_status_2.s.bar2_enb = 1;
3153 + ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
3154 + ctl_status_2.s.bar2_esx = 1;
3155 + ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
3156 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3157 + /* BAR1 hole */
3158 + ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
3159 + ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
3160 + ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
3161 + ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
3162 + ctl_status_2.s.bb1 = 1; /* BAR1 is big */
3163 + ctl_status_2.s.bb0 = 1; /* BAR0 is big */
3164 + }
3165 +
3166 + octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
3167 + udelay(2000); /* Wait 2 ms before doing PCI reads */
3168 +
3169 + ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
3170 + pr_notice("PCI Status: %s %s-bit\n",
3171 + ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
3172 + ctl_status_2.s.ap_64ad ? "64" : "32");
3173 +
3174 + if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
3175 + union cvmx_pci_cnt_reg cnt_reg_start;
3176 + union cvmx_pci_cnt_reg cnt_reg_end;
3177 + unsigned long cycles, pci_clock;
3178 +
3179 + cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3180 + cycles = read_c0_cvmcount();
3181 + udelay(1000);
3182 + cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3183 + cycles = read_c0_cvmcount() - cycles;
3184 + pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
3185 + (cycles / (mips_hpt_frequency / 1000000));
3186 + pr_notice("PCI Clock: %lu MHz\n", pci_clock);
3187 + }
3188 +
3189 + /*
3190 + * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
3191 + * in PCI-X mode to allow four oustanding splits. Otherwise,
3192 + * should not change from its reset value. Don't write PCI_CFG19
3193 + * in PCI mode (0x82000001 reset value), write it to 0x82000004
3194 + * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
3195 + * MRBCM -> must be one.
3196 + */
3197 + if (ctl_status_2.s.ap_pcix) {
3198 + cfg19.u32 = 0;
3199 + /*
3200 + * Target Delayed/Split request outstanding maximum
3201 + * count. [1..31] and 0=32. NOTE: If the user
3202 + * programs these bits beyond the Designed Maximum
3203 + * outstanding count, then the designed maximum table
3204 + * depth will be used instead. No additional
3205 + * Deferred/Split transactions will be accepted if
3206 + * this outstanding maximum count is
3207 + * reached. Furthermore, no additional deferred/split
3208 + * transactions will be accepted if the I/O delay/ I/O
3209 + * Split Request outstanding maximum is reached.
3210 + */
3211 + cfg19.s.tdomc = 4;
3212 + /*
3213 + * Master Deferred Read Request Outstanding Max Count
3214 + * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
3215 + * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
3216 + * 5 2 110 6 3 111 7 3 For example, if these bits are
3217 + * programmed to 100, the core can support 2 DAC
3218 + * cycles, 4 SAC cycles or a combination of 1 DAC and
3219 + * 2 SAC cycles. NOTE: For the PCI-X maximum
3220 + * outstanding split transactions, refer to
3221 + * CRE0[22:20].
3222 + */
3223 + cfg19.s.mdrrmc = 2;
3224 + /*
3225 + * Master Request (Memory Read) Byte Count/Byte Enable
3226 + * select. 0 = Byte Enables valid. In PCI mode, a
3227 + * burst transaction cannot be performed using Memory
3228 + * Read command=4?h6. 1 = DWORD Byte Count valid
3229 + * (default). In PCI Mode, the memory read byte
3230 + * enables are automatically generated by the
3231 + * core. Note: N3 Master Request transaction sizes are
3232 + * always determined through the
3233 + * am_attr[<35:32>|<7:0>] field.
3234 + */
3235 + cfg19.s.mrbcm = 1;
3236 + octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
3237 + }
3238 +
3239 +
3240 + cfg01.u32 = 0;
3241 + cfg01.s.msae = 1; /* Memory Space Access Enable */
3242 + cfg01.s.me = 1; /* Master Enable */
3243 + cfg01.s.pee = 1; /* PERR# Enable */
3244 + cfg01.s.see = 1; /* System Error Enable */
3245 + cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
3246 +
3247 + octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
3248 +
3249 +#ifdef USE_OCTEON_INTERNAL_ARBITER
3250 + /*
3251 + * When OCTEON is a PCI host, most systems will use OCTEON's
3252 + * internal arbiter, so must enable it before any PCI/PCI-X
3253 + * traffic can occur.
3254 + */
3255 + {
3256 + union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
3257 +
3258 + pci_int_arb_cfg.u64 = 0;
3259 + pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
3260 + cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
3261 + }
3262 +#endif /* USE_OCTEON_INTERNAL_ARBITER */
3263 +
3264 + /*
3265 + * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
3266 + * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
3267 + * 1..7.
3268 + */
3269 + cfg16.u32 = 0;
3270 + cfg16.s.mltd = 1; /* Master Latency Timer Disable */
3271 + octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
3272 +
3273 + /*
3274 + * Should be written to 0x4ff00. MTTV -> must be zero.
3275 + * FLUSH -> must be 1. MRV -> should be 0xFF.
3276 + */
3277 + cfg22.u32 = 0;
3278 + /* Master Retry Value [1..255] and 0=infinite */
3279 + cfg22.s.mrv = 0xff;
3280 + /*
3281 + * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
3282 + * N3K operation.
3283 + */
3284 + cfg22.s.flush = 1;
3285 + octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
3286 +
3287 + /*
3288 + * MOST Indicates the maximum number of outstanding splits (in -1
3289 + * notation) when OCTEON is in PCI-X mode. PCI-X performance is
3290 + * affected by the MOST selection. Should generally be written
3291 + * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
3292 + * depending on the desired MOST of 3, 2, 1, or 0, respectively.
3293 + */
3294 + cfg56.u32 = 0;
3295 + cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
3296 + cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
3297 + cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
3298 + cfg56.s.roe = 1; /* Relaxed Ordering Enable */
3299 + cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
3300 + [0=512B,1=1024B,2=2048B,3=4096B] */
3301 + cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
3302 + .. 7=32] */
3303 +
3304 + octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
3305 +
3306 + /*
3307 + * Affects PCI performance when OCTEON services reads to its
3308 + * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
3309 + * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
3310 + * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
3311 + * these values need to be changed so they won't possibly prefetch off
3312 + * of the end of memory if PCI is DMAing a buffer at the end of
3313 + * memory. Note that these values differ from their reset values.
3314 + */
3315 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
3316 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
3317 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
3318 +}
3319 +
3320 +
3321 +/**
3322 + * Initialize the Octeon PCI controller
3323 + *
3324 + * Returns
3325 + */
3326 +static int __init octeon_pci_setup(void)
3327 +{
3328 + union cvmx_npi_mem_access_subidx mem_access;
3329 + int index;
3330 +
3331 + /* Only these chips have PCI */
3332 + if (octeon_has_feature(OCTEON_FEATURE_PCIE))
3333 + return 0;
3334 +
3335 + /* Point pcibios_map_irq() to the PCI version of it */
3336 + octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
3337 +
3338 + /* Only use the big bars on chips that support it */
3339 + if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
3340 + OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
3341 + OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
3342 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
3343 + else
3344 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
3345 +
3346 + /* PCI I/O and PCI MEM values */
3347 + set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
3348 + ioport_resource.start = 0;
3349 + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
3350 + if (!octeon_is_pci_host()) {
3351 + pr_notice("Not in host mode, PCI Controller not initialized\n");
3352 + return 0;
3353 + }
3354 +
3355 + pr_notice("%s Octeon big bar support\n",
3356 + (octeon_dma_bar_type ==
3357 + OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
3358 +
3359 + octeon_pci_initialize();
3360 +
3361 + mem_access.u64 = 0;
3362 + mem_access.s.esr = 1; /* Endian-Swap on read. */
3363 + mem_access.s.esw = 1; /* Endian-Swap on write. */
3364 + mem_access.s.nsr = 0; /* No-Snoop on read. */
3365 + mem_access.s.nsw = 0; /* No-Snoop on write. */
3366 + mem_access.s.ror = 0; /* Relax Read on read. */
3367 + mem_access.s.row = 0; /* Relax Order on write. */
3368 + mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
3369 + cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
3370 +
3371 + /*
3372 + * Remap the Octeon BAR 2 above all 32 bit devices
3373 + * (0x8000000000ul). This is done here so it is remapped
3374 + * before the readl()'s below. We don't want BAR2 overlapping
3375 + * with BAR0/BAR1 during these reads.
3376 + */
3377 + octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
3378 + octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
3379 +
3380 + /* Disable the BAR1 movable mappings */
3381 + for (index = 0; index < 32; index++)
3382 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
3383 +
3384 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3385 + /* Remap the Octeon BAR 0 to 0-2GB */
3386 + octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
3387 + octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3388 +
3389 + /*
3390 + * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
3391 + * BAR 1 hole).
3392 + */
3393 + octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
3394 + octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3395 +
3396 + /* Devices go after BAR1 */
3397 + octeon_pci_mem_resource.start =
3398 + OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
3399 + (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3400 + octeon_pci_mem_resource.end =
3401 + octeon_pci_mem_resource.start + (1ul << 30);
3402 + } else {
3403 + /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
3404 + octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
3405 + octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3406 +
3407 + /* Remap the Octeon BAR 1 to map 0-128MB */
3408 + octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
3409 + octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3410 +
3411 + /* Devices go after BAR0 */
3412 + octeon_pci_mem_resource.start =
3413 + OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
3414 + (4ul << 10);
3415 + octeon_pci_mem_resource.end =
3416 + octeon_pci_mem_resource.start + (1ul << 30);
3417 + }
3418 +
3419 + register_pci_controller(&octeon_pci_controller);
3420 +
3421 + /*
3422 + * Clear any errors that might be pending from before the bus
3423 + * was setup properly.
3424 + */
3425 + cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
3426 + return 0;
3427 +}
3428 +
3429 +arch_initcall(octeon_pci_setup);
3430 diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/cavium-octeon/pcie.c
3431 new file mode 100644
3432 index 0000000..cb6662c
3433 --- /dev/null
3434 +++ b/arch/mips/cavium-octeon/pcie.c
3435 @@ -0,0 +1,441 @@
3436 +/*
3437 + * This file is subject to the terms and conditions of the GNU General Public
3438 + * License. See the file "COPYING" in the main directory of this archive
3439 + * for more details.
3440 + *
3441 + * Copyright (C) 2007, 2008 Cavium Networks
3442 + */
3443 +#include <linux/kernel.h>
3444 +#include <linux/init.h>
3445 +#include <linux/pci.h>
3446 +#include <linux/interrupt.h>
3447 +#include <linux/time.h>
3448 +#include <linux/delay.h>
3449 +
3450 +#include <asm/octeon/octeon.h>
3451 +#include <asm/octeon/cvmx-pcie.h>
3452 +#include <asm/octeon/cvmx-npei-defs.h>
3453 +#include <asm/octeon/cvmx-pexp-defs.h>
3454 +
3455 +#include "pci-common.h"
3456 +
3457 +/**
3458 + * Map a PCI device to the appropriate interrupt line
3459 + *
3460 + * @param dev The Linux PCI device structure for the device to map
3461 + * @param slot The slot number for this device on __BUS 0__. Linux
3462 + * enumerates through all the bridges and figures out the
3463 + * slot on Bus 0 where this device eventually hooks to.
3464 + * @param pin The PCI interrupt pin read from the device, then swizzled
3465 + * as it goes through each bridge.
3466 + * @return Interrupt number for the device
3467 + */
3468 +int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
3469 + u8 slot, u8 pin)
3470 +{
3471 + /*
3472 + * The EBH5600 board with the PCI to PCIe bridge mistakenly
3473 + * wires the first slot for both device id 2 and interrupt
3474 + * A. According to the PCI spec, device id 2 should be C. The
3475 + * following kludge attempts to fix this.
3476 + */
3477 + if (strstr(octeon_board_type_string(), "EBH5600") &&
3478 + dev->bus && dev->bus->parent) {
3479 + /*
3480 + * Iterate all the way up the device chain and find
3481 + * the root bus.
3482 + */
3483 + while (dev->bus && dev->bus->parent)
3484 + dev = to_pci_dev(dev->bus->bridge);
3485 + /* If the root bus is number 0 and the PEX 8114 is the
3486 + * root, assume we are behind the miswired bus. We
3487 + * need to correct the swizzle level by two. Yuck.
3488 + */
3489 + if ((dev->bus->number == 0) &&
3490 + (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
3491 + /*
3492 + * The pin field is one based, not zero. We
3493 + * need to swizzle it by minus two.
3494 + */
3495 + pin = ((pin - 3) & 3) + 1;
3496 + }
3497 + }
3498 + /*
3499 + * The -1 is because pin starts with one, not zero. It might
3500 + * be that this equation needs to include the slot number, but
3501 + * I don't have hardware to check that against.
3502 + */
3503 + return pin - 1 + OCTEON_IRQ_PCI_INT0;
3504 +}
3505 +
3506 +/**
3507 + * Read a value from configuration space
3508 + *
3509 + * @param bus
3510 + * @param devfn
3511 + * @param reg
3512 + * @param size
3513 + * @param val
3514 + * @return
3515 + */
3516 +static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
3517 + unsigned int devfn, int reg, int size,
3518 + u32 *val)
3519 +{
3520 + union octeon_cvmemctl cvmmemctl;
3521 + union octeon_cvmemctl cvmmemctl_save;
3522 + int bus_number = bus->number;
3523 +
3524 + /*
3525 + * We need to force the bus number to be zero on the root
3526 + * bus. Linux numbers the 2nd root bus to start after all
3527 + * buses on root 0.
3528 + */
3529 + if (bus->parent == NULL)
3530 + bus_number = 0;
3531 +
3532 + /*
3533 + * PCIe only has a single device connected to Octeon. It is
3534 + * always device ID 0. Don't bother doing reads for other
3535 + * device IDs on the first segment.
3536 + */
3537 + if ((bus_number == 0) && (devfn >> 3 != 0))
3538 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3539 +
3540 + /*
3541 + * The following is a workaround for the CN57XX, CN56XX,
3542 + * CN55XX, and CN54XX errata with PCIe config reads from non
3543 + * existent devices. These chips will hang the PCIe link if a
3544 + * config read is performed that causes a UR response.
3545 + */
3546 + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3547 + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
3548 + /*
3549 + * For our EBH5600 board, port 0 has a bridge with two
3550 + * PCI-X slots. We need a new special checks to make
3551 + * sure we only probe valid stuff. The PCIe->PCI-X
3552 + * bridge only respondes to device ID 0, function
3553 + * 0-1
3554 + */
3555 + if ((bus_number == 0) && (devfn >= 2))
3556 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3557 + /*
3558 + * The PCI-X slots are device ID 2,3. Choose one of
3559 + * the below "if" blocks based on what is plugged into
3560 + * the board.
3561 + */
3562 +#if 1
3563 + /* Use this option if you aren't using either slot */
3564 + if (bus_number == 1)
3565 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3566 +#elif 0
3567 + /*
3568 + * Use this option if you are using the first slot but
3569 + * not the second.
3570 + */
3571 + if ((bus_number == 1) && (devfn >> 3 != 2))
3572 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3573 +#elif 0
3574 + /*
3575 + * Use this option if you are using the second slot
3576 + * but not the first.
3577 + */
3578 + if ((bus_number == 1) && (devfn >> 3 != 3))
3579 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3580 +#elif 0
3581 + /* Use this opion if you are using both slots */
3582 + if ((bus_number == 1) &&
3583 + !((devfn == (2 << 3)) || (devfn == (3 << 3))))
3584 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3585 +#endif
3586 +
3587 + /*
3588 + * The following #if gives a more complicated
3589 + * example. This is the required checks for running a
3590 + * Nitrox CN16XX-NHBX in the slot of the EBH5600. This
3591 + * card has a PLX PCIe bridge with four Nitrox PLX
3592 + * parts behind it.
3593 + */
3594 +#if 0
3595 + /* PLX bridge with 4 ports */
3596 + if ((bus_number == 3) &&
3597 + !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
3598 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3599 + /* Nitrox behind PLX 1 */
3600 + if ((bus_number == 4) && (devfn >> 3 != 0))
3601 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3602 + /* Nitrox behind PLX 2 */
3603 + if ((bus_number == 5) && (devfn >> 3 != 0))
3604 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3605 + /* Nitrox behind PLX 3 */
3606 + if ((bus_number == 6) && (devfn >> 3 != 0))
3607 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3608 + /* Nitrox behind PLX 4 */
3609 + if ((bus_number == 7) && (devfn >> 3 != 0))
3610 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3611 +#endif
3612 + /*
3613 + * Shorten the DID timeout so bus errors for PCIe
3614 + * config reads from non existent devices happen
3615 + * faster. This allows us to continue booting even if
3616 + * the above "if" checks are wrong. Once one of these
3617 + * errors happens, the PCIe port is dead.
3618 + */
3619 + cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
3620 + cvmmemctl.u64 = cvmmemctl_save.u64;
3621 + cvmmemctl.s.didtto = 2;
3622 + __write_64bit_c0_register($11, 7, cvmmemctl.u64);
3623 + }
3624 +
3625 + switch (size) {
3626 + case 4:
3627 + *val = cvmx_pcie_config_read32(pcie_port, bus_number,
3628 + devfn >> 3, devfn & 0x7, reg);
3629 + break;
3630 + case 2:
3631 + *val = cvmx_pcie_config_read16(pcie_port, bus_number,
3632 + devfn >> 3, devfn & 0x7, reg);
3633 + break;
3634 + case 1:
3635 + *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
3636 + devfn & 0x7, reg);
3637 + break;
3638 + default:
3639 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3640 + }
3641 +
3642 + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3643 + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
3644 + __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
3645 + return PCIBIOS_SUCCESSFUL;
3646 +}
3647 +
3648 +static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
3649 + int reg, int size, u32 *val)
3650 +{
3651 + return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
3652 +}
3653 +
3654 +static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
3655 + int reg, int size, u32 *val)
3656 +{
3657 + return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
3658 +}
3659 +
3660 +
3661 +
3662 +/**
3663 + * Write a value to PCI configuration space
3664 + *
3665 + * @param bus
3666 + * @param devfn
3667 + * @param reg
3668 + * @param size
3669 + * @param val
3670 + * @return
3671 + */
3672 +static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
3673 + unsigned int devfn, int reg,
3674 + int size, u32 val)
3675 +{
3676 + int bus_number = bus->number;
3677 + /*
3678 + * We need to force the bus number to be zero on the root
3679 + * bus. Linux numbers the 2nd root bus to start after all
3680 + * busses on root 0.
3681 + */
3682 + if (bus->parent == NULL)
3683 + bus_number = 0;
3684 +
3685 + switch (size) {
3686 + case 4:
3687 + cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
3688 + devfn & 0x7, reg, val);
3689 + return PCIBIOS_SUCCESSFUL;
3690 + case 2:
3691 + cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
3692 + devfn & 0x7, reg, val);
3693 + return PCIBIOS_SUCCESSFUL;
3694 + case 1:
3695 + cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
3696 + devfn & 0x7, reg, val);
3697 + return PCIBIOS_SUCCESSFUL;
3698 + }
3699 +#if PCI_CONFIG_SPACE_DELAY
3700 + udelay(PCI_CONFIG_SPACE_DELAY);
3701 +#endif
3702 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3703 +}
3704 +
3705 +static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
3706 + int reg, int size, u32 val)
3707 +{
3708 + return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
3709 +}
3710 +
3711 +static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
3712 + int reg, int size, u32 val)
3713 +{
3714 + return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
3715 +}
3716 +
3717 +static struct pci_ops octeon_pcie0_ops = {
3718 + octeon_pcie0_read_config,
3719 + octeon_pcie0_write_config,
3720 +};
3721 +
3722 +static struct resource octeon_pcie0_mem_resource = {
3723 + .name = "Octeon PCIe0 MEM",
3724 + .flags = IORESOURCE_MEM,
3725 +};
3726 +
3727 +static struct resource octeon_pcie0_io_resource = {
3728 + .name = "Octeon PCIe0 IO",
3729 + .flags = IORESOURCE_IO,
3730 +};
3731 +
3732 +static struct pci_controller octeon_pcie0_controller = {
3733 + .pci_ops = &octeon_pcie0_ops,
3734 + .mem_resource = &octeon_pcie0_mem_resource,
3735 + .io_resource = &octeon_pcie0_io_resource,
3736 +};
3737 +
3738 +static struct pci_ops octeon_pcie1_ops = {
3739 + octeon_pcie1_read_config,
3740 + octeon_pcie1_write_config,
3741 +};
3742 +
3743 +static struct resource octeon_pcie1_mem_resource = {
3744 + .name = "Octeon PCIe1 MEM",
3745 + .flags = IORESOURCE_MEM,
3746 +};
3747 +
3748 +static struct resource octeon_pcie1_io_resource = {
3749 + .name = "Octeon PCIe1 IO",
3750 + .flags = IORESOURCE_IO,
3751 +};
3752 +
3753 +static struct pci_controller octeon_pcie1_controller = {
3754 + .pci_ops = &octeon_pcie1_ops,
3755 + .mem_resource = &octeon_pcie1_mem_resource,
3756 + .io_resource = &octeon_pcie1_io_resource,
3757 +};
3758 +
3759 +
3760 +/**
3761 + * Initialize the Octeon PCIe controllers
3762 + *
3763 + * @return
3764 + */
3765 +static int __init octeon_pcie_setup(void)
3766 +{
3767 + union cvmx_npei_ctl_status npei_ctl_status;
3768 + int result;
3769 +
3770 + /* These chips don't have PCIe */
3771 + if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
3772 + return 0;
3773 +
3774 + /* Point pcibios_map_irq() to the PCIe version of it */
3775 + octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
3776 +
3777 + /* Use the PCIe based DMA mappings */
3778 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
3779 +
3780 + /*
3781 + * PCIe I/O range. It is based on port 0 but includes up until
3782 + * port 1's end.
3783 + */
3784 + set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
3785 + ioport_resource.start = 0;
3786 + ioport_resource.end =
3787 + cvmx_pcie_get_io_base_address(1) -
3788 + cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
3789 +
3790 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
3791 + if (npei_ctl_status.s.host_mode) {
3792 + pr_notice("PCIe: Initializing port 0\n");
3793 + result = cvmx_pcie_rc_initialize(0);
3794 + if (result == 0) {
3795 + /* Memory offsets are physical addresses */
3796 + octeon_pcie0_controller.mem_offset =
3797 + cvmx_pcie_get_mem_base_address(0);
3798 + /* IO offsets are Mips virtual addresses */
3799 + octeon_pcie0_controller.io_map_base =
3800 + CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
3801 + (0));
3802 + octeon_pcie0_controller.io_offset = 0;
3803 + /*
3804 + * To keep things similar to PCI, we start
3805 + * device addresses at the same place as PCI
3806 + * uisng big bar support. This normally
3807 + * translates to 4GB-256MB, which is the same
3808 + * as most x86 PCs.
3809 + */
3810 + octeon_pcie0_controller.mem_resource->start =
3811 + cvmx_pcie_get_mem_base_address(0) +
3812 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3813 + octeon_pcie0_controller.mem_resource->end =
3814 + cvmx_pcie_get_mem_base_address(0) +
3815 + cvmx_pcie_get_mem_size(0) - 1;
3816 + /*
3817 + * Ports must be above 16KB for the ISA bus
3818 + * filtering in the PCI-X to PCI bridge.
3819 + */
3820 + octeon_pcie0_controller.io_resource->start = 4 << 10;
3821 + octeon_pcie0_controller.io_resource->end =
3822 + cvmx_pcie_get_io_size(0) - 1;
3823 + register_pci_controller(&octeon_pcie0_controller);
3824 + }
3825 + } else {
3826 + pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
3827 + }
3828 +
3829 + /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
3830 + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
3831 + union cvmx_npei_dbg_data npei_dbg_data;
3832 + npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
3833 + if (npei_dbg_data.cn52xx.qlm0_link_width)
3834 + return 0;
3835 + }
3836 +
3837 + pr_notice("PCIe: Initializing port 1\n");
3838 + result = cvmx_pcie_rc_initialize(1);
3839 + if (result == 0) {
3840 + /* Memory offsets are physical addresses */
3841 + octeon_pcie1_controller.mem_offset =
3842 + cvmx_pcie_get_mem_base_address(1);
3843 + /* IO offsets are Mips virtual addresses */
3844 + octeon_pcie1_controller.io_map_base =
3845 + CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
3846 + octeon_pcie1_controller.io_offset =
3847 + cvmx_pcie_get_io_base_address(1) -
3848 + cvmx_pcie_get_io_base_address(0);
3849 + /*
3850 + * To keep things similar to PCI, we start device
3851 + * addresses at the same place as PCI uisng big bar
3852 + * support. This normally translates to 4GB-256MB,
3853 + * which is the same as most x86 PCs.
3854 + */
3855 + octeon_pcie1_controller.mem_resource->start =
3856 + cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
3857 + (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3858 + octeon_pcie1_controller.mem_resource->end =
3859 + cvmx_pcie_get_mem_base_address(1) +
3860 + cvmx_pcie_get_mem_size(1) - 1;
3861 + /*
3862 + * Ports must be above 16KB for the ISA bus filtering
3863 + * in the PCI-X to PCI bridge.
3864 + */
3865 + octeon_pcie1_controller.io_resource->start =
3866 + cvmx_pcie_get_io_base_address(1) -
3867 + cvmx_pcie_get_io_base_address(0);
3868 + octeon_pcie1_controller.io_resource->end =
3869 + octeon_pcie1_controller.io_resource->start +
3870 + cvmx_pcie_get_io_size(1) - 1;
3871 + register_pci_controller(&octeon_pcie1_controller);
3872 + }
3873 + return 0;
3874 +}
3875 +
3876 +arch_initcall(octeon_pcie_setup);
3877 diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
3878 index b21d3fc..093bcaf 100644
3879 --- a/arch/mips/include/asm/octeon/cvmx-asm.h
3880 +++ b/arch/mips/include/asm/octeon/cvmx-asm.h
3881 @@ -119,7 +119,8 @@
3882 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3883 #define CVMX_DPOP(result, input) \
3884 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3885 -
3886 +#define CVMX_CLZ(result, input) \
3887 + asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3888 /* some new cop0-like stuff */
3889 #define CVMX_RDHWR(result, regstr) \
3890 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
3891 diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
3892 new file mode 100644
3893 index 0000000..ce5deea
3894 --- /dev/null
3895 +++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
3896 @@ -0,0 +1,92 @@
3897 +/***********************license start***************
3898 + * Author: Cavium Networks
3899 + *
3900 + * Contact: support@caviumnetworks.com
3901 + * This file is part of the OCTEON SDK
3902 + *
3903 + * Copyright (c) 2003-2008 Cavium Networks
3904 + *
3905 + * This file is free software; you can redistribute it and/or modify
3906 + * it under the terms of the GNU General Public License, Version 2, as
3907 + * published by the Free Software Foundation.
3908 + *
3909 + * This file is distributed in the hope that it will be useful, but
3910 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
3911 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3912 + * NONINFRINGEMENT. See the GNU General Public License for more
3913 + * details.
3914 + *
3915 + * You should have received a copy of the GNU General Public License
3916 + * along with this file; if not, write to the Free Software
3917 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3918 + * or visit http://www.gnu.org/licenses/.
3919 + *
3920 + * This file may also be available under a different license from Cavium.
3921 + * Contact Cavium Networks for more information
3922 + ***********************license end**************************************/
3923 +
3924 +/**
3925 + * @file
3926 + *
3927 + * Fixes and workaround for Octeon chip errata. This file
3928 + * contains functions called by cvmx-helper to workaround known
3929 + * chip errata. For the most part, code doesn't need to call
3930 + * these functions directly.
3931 + *
3932 + */
3933 +#ifndef __CVMX_HELPER_ERRATA_H__
3934 +#define __CVMX_HELPER_ERRATA_H__
3935 +
3936 +
3937 +#include "cvmx-wqe.h"
3938 +
3939 +/**
3940 + * @INTERNAL
3941 + * Function to adjust internal IPD pointer alignments
3942 + *
3943 + * Returns 0 on success
3944 + * !0 on failure
3945 + */
3946 +extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
3947 +
3948 +/**
3949 + * @INTERNAL
3950 + * Workaround ASX setup errata with CN38XX pass1
3951 + *
3952 + * @interface: Interface to setup
3953 + * @port: Port to setup (0..3)
3954 + * @cpu_clock_hz:
3955 + * Chip frequency in Hertz
3956 + *
3957 + * Returns Zero on success, negative on failure
3958 + */
3959 +extern int __cvmx_helper_errata_asx_pass1(int interface, int port,
3960 + int cpu_clock_hz);
3961 +
3962 +/**
3963 + * This function needs to be called on all Octeon chips with
3964 + * errata PKI-100.
3965 + *
3966 + * The Size field is 8 too large in WQE and next pointers
3967 + *
3968 + * The Size field generated by IPD is 8 larger than it should
3969 + * be. The Size field is <55:40> of both:
3970 + * - WORD3 in the work queue entry, and
3971 + * - the next buffer pointer (which precedes the packet data
3972 + * in each buffer).
3973 + *
3974 + * @work: Work queue entry to fix
3975 + * Returns Zero on success. Negative on failure
3976 + */
3977 +extern int cvmx_helper_fix_ipd_packet_chain(struct cvmx_wqe *work);
3978 +
3979 +/**
3980 + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
3981 + * 1 doesn't work properly. The following code disables 2nd order
3982 + * CDR for the specified QLM.
3983 + *
3984 + * @qlm: QLM to disable 2nd order CDR for.
3985 + */
3986 +extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
3987 +
3988 +#endif
3989 diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
3990 new file mode 100644
3991 index 0000000..d720217
3992 --- /dev/null
3993 +++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
3994 @@ -0,0 +1,266 @@
3995 +/***********************license start***************
3996 + * Author: Cavium Networks
3997 + *
3998 + * Contact: support@caviumnetworks.com
3999 + * This file is part of the OCTEON SDK
4000 + *
4001 + * Copyright (c) 2003-2008 Cavium Networks
4002 + *
4003 + * This file is free software; you can redistribute it and/or modify
4004 + * it under the terms of the GNU General Public License, Version 2, as
4005 + * published by the Free Software Foundation.
4006 + *
4007 + * This file is distributed in the hope that it will be useful, but
4008 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4009 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4010 + * NONINFRINGEMENT. See the GNU General Public License for more
4011 + * details.
4012 + *
4013 + * You should have received a copy of the GNU General Public License
4014 + * along with this file; if not, write to the Free Software
4015 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4016 + * or visit http://www.gnu.org/licenses/.
4017 + *
4018 + * This file may also be available under a different license from Cavium.
4019 + * Contact Cavium Networks for more information
4020 + ***********************license end**************************************/
4021 +
4022 +/**
4023 + *
4024 + * Small helper utilities.
4025 + *
4026 + */
4027 +
4028 +#ifndef __CVMX_HELPER_UTIL_H__
4029 +#define __CVMX_HELPER_UTIL_H__
4030 +
4031 +#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
4032 +
4033 +/**
4034 + * Convert a interface mode into a human readable string
4035 + *
4036 + * @mode: Mode to convert
4037 + *
4038 + * Returns String
4039 + */
4040 +extern const char
4041 + *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
4042 +
4043 +/**
4044 + * Debug routine to dump the packet structure to the console
4045 + *
4046 + * @work: Work queue entry containing the packet to dump
4047 + * Returns
4048 + */
4049 +extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
4050 +
4051 +/**
4052 + * Setup Random Early Drop on a specific input queue
4053 + *
4054 + * @queue: Input queue to setup RED on (0-7)
4055 + * @pass_thresh:
4056 + * Packets will begin slowly dropping when there are less than
4057 + * this many packet buffers free in FPA 0.
4058 + * @drop_thresh:
4059 + * All incomming packets will be dropped when there are less
4060 + * than this many free packet buffers in FPA 0.
4061 + * Returns Zero on success. Negative on failure
4062 + */
4063 +extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
4064 + int drop_thresh);
4065 +
4066 +/**
4067 + * Setup Random Early Drop to automatically begin dropping packets.
4068 + *
4069 + * @pass_thresh:
4070 + * Packets will begin slowly dropping when there are less than
4071 + * this many packet buffers free in FPA 0.
4072 + * @drop_thresh:
4073 + * All incomming packets will be dropped when there are less
4074 + * than this many free packet buffers in FPA 0.
4075 + * Returns Zero on success. Negative on failure
4076 + */
4077 +extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
4078 +
4079 +/**
4080 + * Get the version of the CVMX libraries.
4081 + *
4082 + * Returns Version string. Note this buffer is allocated statically
4083 + * and will be shared by all callers.
4084 + */
4085 +extern const char *cvmx_helper_get_version(void);
4086 +
4087 +/**
4088 + * @INTERNAL
4089 + * Setup the common GMX settings that determine the number of
4090 + * ports. These setting apply to almost all configurations of all
4091 + * chips.
4092 + *
4093 + * @interface: Interface to configure
4094 + * @num_ports: Number of ports on the interface
4095 + *
4096 + * Returns Zero on success, negative on failure
4097 + */
4098 +extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
4099 +
4100 +/**
4101 + * Returns the IPD/PKO port number for a port on the given
4102 + * interface.
4103 + *
4104 + * @interface: Interface to use
4105 + * @port: Port on the interface
4106 + *
4107 + * Returns IPD/PKO port number
4108 + */
4109 +extern int cvmx_helper_get_ipd_port(int interface, int port);
4110 +
4111 +/**
4112 + * Returns the IPD/PKO port number for the first port on the given
4113 + * interface.
4114 + *
4115 + * @interface: Interface to use
4116 + *
4117 + * Returns IPD/PKO port number
4118 + */
4119 +static inline int cvmx_helper_get_first_ipd_port(int interface)
4120 +{
4121 + return cvmx_helper_get_ipd_port(interface, 0);
4122 +}
4123 +
4124 +/**
4125 + * Returns the IPD/PKO port number for the last port on the given
4126 + * interface.
4127 + *
4128 + * @interface: Interface to use
4129 + *
4130 + * Returns IPD/PKO port number
4131 + */
4132 +static inline int cvmx_helper_get_last_ipd_port(int interface)
4133 +{
4134 + extern int cvmx_helper_ports_on_interface(int interface);
4135 +
4136 + return cvmx_helper_get_first_ipd_port(interface) +
4137 + cvmx_helper_ports_on_interface(interface) - 1;
4138 +}
4139 +
4140 +/**
4141 + * Free the packet buffers contained in a work queue entry.
4142 + * The work queue entry is not freed.
4143 + *
4144 + * @work: Work queue entry with packet to free
4145 + */
4146 +static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
4147 +{
4148 + uint64_t number_buffers;
4149 + cvmx_buf_ptr_t buffer_ptr;
4150 + cvmx_buf_ptr_t next_buffer_ptr;
4151 + uint64_t start_of_buffer;
4152 +
4153 + number_buffers = work->word2.s.bufs;
4154 + if (number_buffers == 0)
4155 + return;
4156 + buffer_ptr = work->packet_ptr;
4157 +
4158 + /*
4159 + * Since the number of buffers is not zero, we know this is
4160 + * not a dynamic short packet. We need to check if it is a
4161 + * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
4162 + * true, we need to free all buffers except for the first
4163 + * one. The caller doesn't expect their WQE pointer to be
4164 + * freed.
4165 + */
4166 + start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4167 + if (cvmx_ptr_to_phys(work) == start_of_buffer) {
4168 + next_buffer_ptr =
4169 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4170 + buffer_ptr = next_buffer_ptr;
4171 + number_buffers--;
4172 + }
4173 +
4174 + while (number_buffers--) {
4175 + /*
4176 + * Remember the back pointer is in cache lines, not
4177 + * 64bit words.
4178 + */
4179 + start_of_buffer =
4180 + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4181 + /*
4182 + * Read pointer to next buffer before we free the
4183 + * current buffer.
4184 + */
4185 + next_buffer_ptr =
4186 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4187 + cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
4188 + buffer_ptr.s.pool, 0);
4189 + buffer_ptr = next_buffer_ptr;
4190 + }
4191 +}
4192 +
4193 +#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
4194 +
4195 +/**
4196 + * Returns the interface number for an IPD/PKO port number.
4197 + *
4198 + * @ipd_port: IPD/PKO port number
4199 + *
4200 + * Returns Interface number
4201 + */
4202 +extern int cvmx_helper_get_interface_num(int ipd_port);
4203 +
4204 +/**
4205 + * Returns the interface index number for an IPD/PKO port
4206 + * number.
4207 + *
4208 + * @ipd_port: IPD/PKO port number
4209 + *
4210 + * Returns Interface index number
4211 + */
4212 +extern int cvmx_helper_get_interface_index_num(int ipd_port);
4213 +
4214 +/**
4215 + * Initialize the internal QLM JTAG logic to allow programming
4216 + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
4217 + * These functions should only be used at the direction of Cavium
4218 + * Networks. Programming incorrect values into the JTAG chain
4219 + * can cause chip damage.
4220 + */
4221 +extern void cvmx_helper_qlm_jtag_init(void);
4222 +
4223 +/**
4224 + * Write up to 32bits into the QLM jtag chain. Bits are shifted
4225 + * into the MSB and out the LSB, so you should shift in the low
4226 + * order bits followed by the high order bits. The JTAG chain is
4227 + * 4 * 268 bits long, or 1072.
4228 + *
4229 + * @qlm: QLM to shift value into
4230 + * @bits: Number of bits to shift in (1-32).
4231 + * @data: Data to shift in. Bit 0 enters the chain first, followed by
4232 + * bit 1, etc.
4233 + *
4234 + * Returns The low order bits of the JTAG chain that shifted out of the
4235 + * circle.
4236 + */
4237 +extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
4238 +
4239 +/**
4240 + * Shift long sequences of zeros into the QLM JTAG chain. It is
4241 + * common to need to shift more than 32 bits of zeros into the
4242 + * chain. This function is a convience wrapper around
4243 + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
4244 + * zeros at a time.
4245 + *
4246 + * @qlm: QLM to shift zeros into
4247 + * @bits:
4248 + */
4249 +extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
4250 +
4251 +/**
4252 + * Program the QLM JTAG chain into all lanes of the QLM. You must
4253 + * have already shifted in 268*4, or 1072 bits into the JTAG
4254 + * chain. Updating invalid values can possibly cause chip damage.
4255 + *
4256 + * @qlm: QLM to program
4257 + */
4258 +extern void cvmx_helper_qlm_jtag_update(int qlm);
4259 +
4260 +#endif /* __CVMX_HELPER_H__ */
4261 diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
4262 index 38aefa1..1cb3419 100644
4263 --- a/arch/mips/include/asm/octeon/cvmx-packet.h
4264 +++ b/arch/mips/include/asm/octeon/cvmx-packet.h
4265 @@ -25,7 +25,8 @@
4266 * Contact Cavium Networks for more information
4267 ***********************license end**************************************/
4268
4269 -/*
4270 +/**
4271 + *
4272 * Packet buffer defines.
4273 */
4274
4275 @@ -39,18 +40,23 @@ union cvmx_buf_ptr {
4276 void *ptr;
4277 uint64_t u64;
4278 struct {
4279 - /* if set, invert the "free" pick of the overall
4280 + /*
4281 + * If set, invert the "free" pick of the overall
4282 * packet. HW always sets this bit to 0 on inbound
4283 - * packet */
4284 + * packet.
4285 + */
4286 uint64_t i:1;
4287
4288 - /* Indicates the amount to back up to get to the
4289 + /*
4290 + * Indicates the amount to back up to get to the
4291 * buffer start in cache lines. In most cases this is
4292 * less than one complete cache line, so the value is
4293 - * zero */
4294 + * zero.
4295 + */
4296 uint64_t back:4;
4297 /* The pool that the buffer came from / goes to */
4298 uint64_t pool:3;
4299 +
4300 /* The size of the segment pointed to by addr (in bytes) */
4301 uint64_t size:16;
4302 /* Pointer to the first byte of the data, NOT buffer */
4303 diff --git a/arch/mips/include/asm/octeon/cvmx-pcie.h b/arch/mips/include/asm/octeon/cvmx-pcie.h
4304 new file mode 100644
4305 index 0000000..55a5ac1
4306 --- /dev/null
4307 +++ b/arch/mips/include/asm/octeon/cvmx-pcie.h
4308 @@ -0,0 +1,284 @@
4309 +/***********************license start***************
4310 + * Author: Cavium Networks
4311 + *
4312 + * Contact: support@caviumnetworks.com
4313 + * This file is part of the OCTEON SDK
4314 + *
4315 + * Copyright (c) 2003-2008 Cavium Networks
4316 + *
4317 + * This file is free software; you can redistribute it and/or modify
4318 + * it under the terms of the GNU General Public License, Version 2, as
4319 + * published by the Free Software Foundation.
4320 + *
4321 + * This file is distributed in the hope that it will be useful, but
4322 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4323 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4324 + * NONINFRINGEMENT. See the GNU General Public License for more
4325 + * details.
4326 + *
4327 + * You should have received a copy of the GNU General Public License
4328 + * along with this file; if not, write to the Free Software
4329 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4330 + * or visit http://www.gnu.org/licenses/.
4331 + *
4332 + * This file may also be available under a different license from Cavium.
4333 + * Contact Cavium Networks for more information
4334 + ***********************license end**************************************/
4335 +
4336 +/**
4337 + * @file
4338 + *
4339 + * Interface to PCIe as a host(RC) or target(EP)
4340 + *
4341 + */
4342 +
4343 +#ifndef __CVMX_PCIE_H__
4344 +#define __CVMX_PCIE_H__
4345 +
4346 +union cvmx_pcie_address {
4347 + uint64_t u64;
4348 + struct {
4349 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4350 + uint64_t reserved_49_61:13; /* Must be zero */
4351 + uint64_t io:1; /* 1 for IO space access */
4352 + uint64_t did:5; /* PCIe DID = 3 */
4353 + uint64_t subdid:3; /* PCIe SubDID = 1 */
4354 + uint64_t reserved_36_39:4; /* Must be zero */
4355 + uint64_t es:2; /* Endian swap = 1 */
4356 + uint64_t port:2; /* PCIe port 0,1 */
4357 + uint64_t reserved_29_31:3; /* Must be zero */
4358 + /*
4359 + * Selects the type of the configuration request (0 = type 0,
4360 + * 1 = type 1).
4361 + */
4362 + uint64_t ty:1;
4363 + /* Target bus number sent in the ID in the request. */
4364 + uint64_t bus:8;
4365 + /*
4366 + * Target device number sent in the ID in the
4367 + * request. Note that Dev must be zero for type 0
4368 + * configuration requests.
4369 + */
4370 + uint64_t dev:5;
4371 + /* Target function number sent in the ID in the request. */
4372 + uint64_t func:3;
4373 + /*
4374 + * Selects a register in the configuration space of
4375 + * the target.
4376 + */
4377 + uint64_t reg:12;
4378 + } config;
4379 + struct {
4380 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4381 + uint64_t reserved_49_61:13; /* Must be zero */
4382 + uint64_t io:1; /* 1 for IO space access */
4383 + uint64_t did:5; /* PCIe DID = 3 */
4384 + uint64_t subdid:3; /* PCIe SubDID = 2 */
4385 + uint64_t reserved_36_39:4; /* Must be zero */
4386 + uint64_t es:2; /* Endian swap = 1 */
4387 + uint64_t port:2; /* PCIe port 0,1 */
4388 + uint64_t address:32; /* PCIe IO address */
4389 + } io;
4390 + struct {
4391 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4392 + uint64_t reserved_49_61:13; /* Must be zero */
4393 + uint64_t io:1; /* 1 for IO space access */
4394 + uint64_t did:5; /* PCIe DID = 3 */
4395 + uint64_t subdid:3; /* PCIe SubDID = 3-6 */
4396 + uint64_t reserved_36_39:4; /* Must be zero */
4397 + uint64_t address:36; /* PCIe Mem address */
4398 + } mem;
4399 +};
4400 +
4401 +/**
4402 + * Return the Core virtual base address for PCIe IO access. IOs are
4403 + * read/written as an offset from this address.
4404 + *
4405 + * @pcie_port: PCIe port the IO is for
4406 + *
4407 + * Returns 64bit Octeon IO base address for read/write
4408 + */
4409 +uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
4410 +
4411 +/**
4412 + * Size of the IO address region returned at address
4413 + * cvmx_pcie_get_io_base_address()
4414 + *
4415 + * @pcie_port: PCIe port the IO is for
4416 + *
4417 + * Returns Size of the IO window
4418 + */
4419 +uint64_t cvmx_pcie_get_io_size(int pcie_port);
4420 +
4421 +/**
4422 + * Return the Core virtual base address for PCIe MEM access. Memory is
4423 + * read/written as an offset from this address.
4424 + *
4425 + * @pcie_port: PCIe port the IO is for
4426 + *
4427 + * Returns 64bit Octeon IO base address for read/write
4428 + */
4429 +uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
4430 +
4431 +/**
4432 + * Size of the Mem address region returned at address
4433 + * cvmx_pcie_get_mem_base_address()
4434 + *
4435 + * @pcie_port: PCIe port the IO is for
4436 + *
4437 + * Returns Size of the Mem window
4438 + */
4439 +uint64_t cvmx_pcie_get_mem_size(int pcie_port);
4440 +
4441 +/**
4442 + * Initialize a PCIe port for use in host(RC) mode. It doesn't
4443 + * enumerate the bus.
4444 + *
4445 + * @pcie_port: PCIe port to initialize
4446 + *
4447 + * Returns Zero on success
4448 + */
4449 +int cvmx_pcie_rc_initialize(int pcie_port);
4450 +
4451 +/**
4452 + * Shutdown a PCIe port and put it in reset
4453 + *
4454 + * @pcie_port: PCIe port to shutdown
4455 + *
4456 + * Returns Zero on success
4457 + */
4458 +int cvmx_pcie_rc_shutdown(int pcie_port);
4459 +
4460 +/**
4461 + * Read 8bits from a Device's config space
4462 + *
4463 + * @pcie_port: PCIe port the device is on
4464 + * @bus: Sub bus
4465 + * @dev: Device ID
4466 + * @fn: Device sub function
4467 + * @reg: Register to access
4468 + *
4469 + * Returns Result of the read
4470 + */
4471 +uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn,
4472 + int reg);
4473 +
4474 +/**
4475 + * Read 16bits from a Device's config space
4476 + *
4477 + * @pcie_port: PCIe port the device is on
4478 + * @bus: Sub bus
4479 + * @dev: Device ID
4480 + * @fn: Device sub function
4481 + * @reg: Register to access
4482 + *
4483 + * Returns Result of the read
4484 + */
4485 +uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
4486 + int reg);
4487 +
4488 +/**
4489 + * Read 32bits from a Device's config space
4490 + *
4491 + * @pcie_port: PCIe port the device is on
4492 + * @bus: Sub bus
4493 + * @dev: Device ID
4494 + * @fn: Device sub function
4495 + * @reg: Register to access
4496 + *
4497 + * Returns Result of the read
4498 + */
4499 +uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
4500 + int reg);
4501 +
4502 +/**
4503 + * Write 8bits to a Device's config space
4504 + *
4505 + * @pcie_port: PCIe port the device is on
4506 + * @bus: Sub bus
4507 + * @dev: Device ID
4508 + * @fn: Device sub function
4509 + * @reg: Register to access
4510 + * @val: Value to write
4511 + */
4512 +void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg,
4513 + uint8_t val);
4514 +
4515 +/**
4516 + * Write 16bits to a Device's config space
4517 + *
4518 + * @pcie_port: PCIe port the device is on
4519 + * @bus: Sub bus
4520 + * @dev: Device ID
4521 + * @fn: Device sub function
4522 + * @reg: Register to access
4523 + * @val: Value to write
4524 + */
4525 +void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg,
4526 + uint16_t val);
4527 +
4528 +/**
4529 + * Write 32bits to a Device's config space
4530 + *
4531 + * @pcie_port: PCIe port the device is on
4532 + * @bus: Sub bus
4533 + * @dev: Device ID
4534 + * @fn: Device sub function
4535 + * @reg: Register to access
4536 + * @val: Value to write
4537 + */
4538 +void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg,
4539 + uint32_t val);
4540 +
4541 +/**
4542 + * Read a PCIe config space register indirectly. This is used for
4543 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4544 + *
4545 + * @pcie_port: PCIe port to read from
4546 + * @cfg_offset: Address to read
4547 + *
4548 + * Returns Value read
4549 + */
4550 +uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
4551 +
4552 +/**
4553 + * Write a PCIe config space register indirectly. This is used for
4554 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4555 + *
4556 + * @pcie_port: PCIe port to write to
4557 + * @cfg_offset: Address to write
4558 + * @val: Value to write
4559 + */
4560 +void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
4561 +
4562 +/**
4563 + * Write a 32bit value to the Octeon NPEI register space
4564 + *
4565 + * @address: Address to write to
4566 + * @val: Value to write
4567 + */
4568 +static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
4569 +{
4570 + cvmx_write64_uint32(address ^ 4, val);
4571 + cvmx_read64_uint32(address ^ 4);
4572 +}
4573 +
4574 +/**
4575 + * Read a 32bit value from the Octeon NPEI register space
4576 + *
4577 + * @address: Address to read
4578 + * Returns The result
4579 + */
4580 +static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
4581 +{
4582 + return cvmx_read64_uint32(address ^ 4);
4583 +}
4584 +
4585 +/**
4586 + * Initialize a PCIe port for use in target(EP) mode.
4587 + *
4588 + * Returns Zero on success
4589 + */
4590 +int cvmx_pcie_ep_initialize(void);
4591 +
4592 +#endif
4593 diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
4594 new file mode 100644
4595 index 0000000..fadc700
4596 --- /dev/null
4597 +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
4598 @@ -0,0 +1,422 @@
4599 +/***********************license start***************
4600 + * Author: Cavium Networks
4601 + *
4602 + * Contact: support@caviumnetworks.com
4603 + * This file is part of the OCTEON SDK
4604 + *
4605 + * Copyright (c) 2003-2008 Cavium Networks
4606 + *
4607 + * This file is free software; you can redistribute it and/or modify
4608 + * it under the terms of the GNU General Public License, Version 2, as
4609 + * published by the Free Software Foundation.
4610 + *
4611 + * This file is distributed in the hope that it will be useful, but
4612 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4613 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4614 + * NONINFRINGEMENT. See the GNU General Public License for more
4615 + * details.
4616 + *
4617 + * You should have received a copy of the GNU General Public License
4618 + * along with this file; if not, write to the Free Software
4619 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4620 + * or visit http://www.gnu.org/licenses/.
4621 + *
4622 + * This file may also be available under a different license from Cavium.
4623 + * Contact Cavium Networks for more information
4624 + ***********************license end**************************************/
4625 +
4626 +/**
4627 + *
4628 + * This header file defines the work queue entry (wqe) data structure.
4629 + * Since this is a commonly used structure that depends on structures
4630 + * from several hardware blocks, those definitions have been placed
4631 + * in this file to create a single point of definition of the wqe
4632 + * format.
4633 + *
4634 + * Data structures are still named according to the block that they
4635 + * relate to.
4636 + *
4637 + */
4638 +
4639 +#ifndef __CVMX_WQE_H__
4640 +#define __CVMX_WQE_H__
4641 +
4642 +#include "cvmx-packet.h"
4643 +
4644 +#define OCT_TAG_TYPE_STRING(x) ( \
4645 + { \
4646 + const char *r; \
4647 + switch (x) { \
4648 + case CVMX_POW_TAG_TYPE_ORDERED: \
4649 + r = "ORDERED"; \
4650 + break; \
4651 + case CVMX_POW_TAG_TYPE_ATOMIC: \
4652 + r = "ATOMIC"; \
4653 + break; \
4654 + case CVMX_POW_TAG_TYPE_NULL: \
4655 + r = "NULL"; \
4656 + break; \
4657 + default: \
4658 + r = "NULL_NULL"; \
4659 + break; \
4660 + } \
4661 + r; \
4662 + })
4663 +
4664 +/**
4665 + * HW decode / err_code in work queue entry
4666 + */
4667 +union cvmx_pip_wqe_word2{
4668 + uint64_t u64;
4669 +
4670 + /* Use this struct if the hardware determines that the packet is IP */
4671 + struct {
4672 + /* HW sets this to the number of buffers used by this packet */
4673 + uint64_t bufs:8;
4674 + /* HW sets to the number of L2 bytes prior to the IP */
4675 + uint64_t ip_offset:8;
4676 + /* Set to 1 if we found VLAN in the L2 */
4677 + uint64_t vlan_valid:1;
4678 + uint64_t unassigned:2;
4679 + /* HW sets to the VLAN CFI flag (valid when vlan_valid) */
4680 + uint64_t vlan_cfi:1;
4681 + /* HW sets to the VLAN_ID field (valid when vlan_valid) */
4682 + uint64_t vlan_id:12;
4683 +
4684 + uint64_t unassigned2:12;
4685 + /* The packet needs to be decompressed */
4686 + uint64_t dec_ipcomp:1;
4687 + /* The packet is either TCP or UDP */
4688 + uint64_t tcp_or_udp:1;
4689 + /* The packet needs to be decrypted (ESP or AH) */
4690 + uint64_t dec_ipsec:1;
4691 + /* The packet is IPv6 */
4692 + uint64_t is_v6:1;
4693 +
4694 + /*
4695 + * rcv_error, not_IP, IP_exc, is_frag, L4_error,
4696 + * software, etc.
4697 + */
4698 +
4699 + /*
4700 + * Reserved for software use, hardware will clear on
4701 + * packet creation.
4702 + */
4703 + uint64_t software:1;
4704 + /* exceptional conditions below. */
4705 +
4706 + /*
4707 + * The receive interface hardware detected an L4 error
4708 + * (only applies if !is_frag) (only applies if
4709 + * !rcv_error && !not_IP && !IP_exc && !is_frag)
4710 + * failure indicated in err_code below, decode:
4711 + *
4712 + * - 1 = Malformed L4
4713 + *
4714 + * - 2 = L4 Checksum Error: the L4 checksum value is
4715 + *
4716 + * - 3 = UDP Length Error: The UDP length field would
4717 + * make the UDP data longer than what remains in
4718 + * the IP packet (as defined by the IP header
4719 + * length field).
4720 + *
4721 + * - 4 = Bad L4 Port: either the source or destination
4722 + * TCP/UDP port is 0.
4723 + *
4724 + * - 8 = TCP FIN Only: the packet is TCP and only the
4725 + * FIN flag set.
4726 + *
4727 + * - 9 = TCP No Flags: the packet is TCP and no flags
4728 + * are set.
4729 + *
4730 + * - 10 = TCP FIN RST: the packet is TCP and both FIN
4731 + * and RST are set.
4732 + *
4733 + * - 11 = TCP SYN URG: the packet is TCP and both SYN
4734 + * and URG are set.
4735 + *
4736 + * - 12 = TCP SYN RST: the packet is TCP and both SYN
4737 + * and RST are set.
4738 + *
4739 + * - 13 = TCP SYN FIN: the packet is TCP and both SYN
4740 + * and FIN are set.
4741 + *
4742 + */
4743 + uint64_t L4_error:1;
4744 + /* Set if the packet is a fragment */
4745 + uint64_t is_frag:1;
4746 +
4747 + /*
4748 + * The receive interface hardware detected an IP error
4749 + * / exception (only applies if !rcv_error && !not_IP)
4750 + * failure indicated in err_code below, decode:
4751 + *
4752 + * - 1 = Not IP: the IP version field is neither 4 nor
4753 + * 6.
4754 + *
4755 + * - 2 = IPv4 Header Checksum Error: the IPv4 header
4756 + * has a checksum violation.
4757 + *
4758 + * - 3 = IP Malformed Header: the packet is not long
4759 + * enough to contain the IP header.
4760 + *
4761 + * - 4 = IP Malformed: the packet is not long enough
4762 + * to contain the bytes indicated by the IP
4763 + * header. Pad is allowed.
4764 + *
4765 + * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
4766 + * Hop Count field are zero.
4767 + *
4768 + * - 6 = IP Options.
4769 + */
4770 + uint64_t IP_exc:1;
4771 + /*
4772 + * Set if the hardware determined that the packet is a
4773 + * broadcast.
4774 + */
4775 + uint64_t is_bcast:1;
4776 + /*
4777 + * Set if the hardware determined that the packet is a
4778 + * multi-cast.
4779 + */
4780 + uint64_t is_mcast:1;
4781 + /*
4782 + * Set if the packet may not be IP (must be zero in
4783 + * this case).
4784 + */
4785 + uint64_t not_IP:1;
4786 + /*
4787 + * The receive interface hardware detected a receive
4788 + * error (must be zero in this case)
4789 + *
4790 + * lower err_code = first-level descriptor of the work
4791 + *
4792 + * zero for packet submitted by hardware that isn't on
4793 + * the slow path.
4794 + */
4795 + uint64_t rcv_error:1;
4796 +
4797 + /* Type is cvmx_pip_err_t */
4798 + uint64_t err_code:8;
4799 + } s;
4800 +
4801 + /* Use this to get at the 16 vlan bits */
4802 + struct {
4803 + uint64_t unused1:16;
4804 + uint64_t vlan:16;
4805 + uint64_t unused2:32;
4806 + } svlan;
4807 +
4808 + /*
4809 + * Use this struct if the hardware could not determine that
4810 + * the packet is ip.
4811 + */
4812 + struct {
4813 + /* HW sets this to the number of buffers used by this packet. */
4814 + uint64_t bufs:8;
4815 + uint64_t unused:8;
4816 + /* Set to 1 if we found VLAN in the L2. */
4817 + uint64_t vlan_valid:1;
4818 + uint64_t unassigned:2;
4819 + /* HW sets to the VLAN CFI flag (valid when vlan_valid). */
4820 + uint64_t vlan_cfi:1;
4821 + /* HW sets to the VLAN_ID field (valid when vlan_valid). */
4822 + uint64_t vlan_id:12;
4823 +
4824 + uint64_t unassigned2:16;
4825 + /*
4826 + * Reserved for software use, hardware will clear on
4827 + * packet creation.
4828 + */
4829 + uint64_t software:1;
4830 + uint64_t unassigned3:1;
4831 + /* Set if the hardware determined that the packet is rarp. */
4832 + uint64_t is_rarp:1;
4833 + /* Set if the hardware determined that the packet is arp. */
4834 + uint64_t is_arp:1;
4835 + /*
4836 + * Set if the hardware determined that the packet is a
4837 + * broadcast.
4838 + */
4839 + uint64_t is_bcast:1;
4840 + /*
4841 + * Set if the hardware determined that the packet is a
4842 + * multi-cast.
4843 + */
4844 + uint64_t is_mcast:1;
4845 + /*
4846 + * Set if the packet may not be IP (must be one in
4847 + * this case).
4848 + */
4849 + uint64_t not_IP:1;
4850 + /*
4851 + * The receive interface hardware detected a receive
4852 + * error. Failure indicated in err_code below, decode:
4853 + *
4854 + * - 1 = partial error: a packet was partially
4855 + * received, but internal buffering / bandwidth
4856 + * was not adequate to receive the entire
4857 + * packet.
4858 + *
4859 + * - 2 = jabber error: the RGMII packet was too large
4860 + * and is truncated.
4861 + *
4862 + * - 3 = overrun error: the RGMII packet is longer
4863 + * than allowed and had an FCS error.
4864 + *
4865 + * - 4 = oversize error: the RGMII packet is longer
4866 + * than allowed.
4867 + *
4868 + * - 5 = alignment error: the RGMII packet is not an
4869 + * integer number of bytes and had an FCS error
4870 + * (100M and 10M only).
4871 + *
4872 + * - 6 = fragment error: the RGMII packet is shorter
4873 + * than allowed and had an FCS error.
4874 + *
4875 + * - 7 = GMX FCS error: the RGMII packet had an FCS
4876 + * error.
4877 + *
4878 + * - 8 = undersize error: the RGMII packet is shorter
4879 + * than allowed.
4880 + *
4881 + * - 9 = extend error: the RGMII packet had an extend
4882 + * error.
4883 + *
4884 + * - 10 = length mismatch error: the RGMII packet had
4885 + * a length that did not match the length field
4886 + * in the L2 HDR.
4887 + *
4888 + * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
4889 + * packet had one or more data reception errors
4890 + * (RXERR) or the SPI4 packet had one or more
4891 + * DIP4 errors.
4892 + *
4893 + * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
4894 + * packet was not large enough to cover the
4895 + * skipped bytes or the SPI4 packet was
4896 + * terminated with an About EOPS.
4897 + *
4898 + * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
4899 + * RGMII packet had a studder error (data not
4900 + * repeated - 10/100M only) or the SPI4 packet
4901 + * was sent to an NXA.
4902 + *
4903 + * - 16 = FCS error: a SPI4.2 packet had an FCS error.
4904 + *
4905 + * - 17 = Skip error: a packet was not large enough to
4906 + * cover the skipped bytes.
4907 + *
4908 + * - 18 = L2 header malformed: the packet is not long
4909 + * enough to contain the L2
4910 + */
4911 +
4912 + /*
4913 + * lower err_code = first-level descriptor of the
4914 + * work.
4915 + *
4916 + * zero for packet submitted by hardware that isn't on
4917 + * the slow path.
4918 + */
4919 + uint64_t rcv_error:1;
4920 +
4921 + /* Type is cvmx_pip_err_t (union, so can't use directly. */
4922 + uint64_t err_code:8;
4923 + } snoip;
4924 +
4925 +};
4926 +
4927 +/**
4928 + * Work queue entry format
4929 + *
4930 + * must be 8-byte aligned
4931 + */
4932 +struct cvmx_wqe {
4933 +
4934 + /*****************************************************************
4935 + * WORD 0
4936 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4937 + */
4938 +
4939 + /**
4940 + * raw chksum result generated by the HW
4941 + */
4942 + uint16_t hw_chksum;
4943 + /**
4944 + * Field unused by hardware - available for software
4945 + */
4946 + uint8_t unused;
4947 + /**
4948 + * Next pointer used by hardware for list maintenance.
4949 + * May be written/read by HW before the work queue
4950 + * entry is scheduled to a PP
4951 + * (Only 36 bits used in Octeon 1)
4952 + */
4953 + uint64_t next_ptr:40;
4954 +
4955 + /*****************************************************************
4956 + * WORD 1
4957 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4958 + */
4959 +
4960 + /**
4961 + * HW sets to the total number of bytes in the packet
4962 + */
4963 + uint64_t len:16;
4964 + /**
4965 + * HW sets this to input physical port
4966 + */
4967 + uint64_t ipprt:6;
4968 +
4969 + /**
4970 + * HW sets this to what it thought the priority of the input packet was
4971 + */
4972 + uint64_t qos:3;
4973 +
4974 + /**
4975 + * the group that the work queue entry will be scheduled to
4976 + */
4977 + uint64_t grp:4;
4978 + /**
4979 + * the type of the tag (ORDERED, ATOMIC, NULL)
4980 + */
4981 + uint64_t tag_type:3;
4982 + /**
4983 + * the synchronization/ordering tag
4984 + */
4985 + uint64_t tag:32;
4986 +
4987 + /**
4988 + * WORD 2 HW WRITE: the following 64-bits are filled in by
4989 + * hardware when a packet arrives This indicates a variety of
4990 + * status and error conditions.
4991 + */
4992 + union cvmx_pip_wqe_word2 word2;
4993 +
4994 + /**
4995 + * Pointer to the first segment of the packet.
4996 + */
4997 + union cvmx_buf_ptr packet_ptr;
4998 +
4999 + /**
5000 + * HW WRITE: octeon will fill in a programmable amount from the
5001 + * packet, up to (at most, but perhaps less) the amount
5002 + * needed to fill the work queue entry to 128 bytes
5003 + * If the packet is recognized to be IP, the hardware starts (except that
5004 + * the IPv4 header is padded for appropriate alignment) writing here where
5005 + * the IP header starts.
5006 + * If the packet is not recognized to be IP, the hardware starts writing
5007 + * the beginning of the packet here.
5008 + */
5009 + uint8_t packet_data[96];
5010 +
5011 + /**
5012 + * If desired, SW can make the work Q entry any length. For the
5013 + * purposes of discussion here, Assume 128B always, as this is all that
5014 + * the hardware deals with.
5015 + *
5016 + */
5017 +
5018 +} CVMX_CACHE_LINE_ALIGNED;
5019 +
5020 +#endif /* __CVMX_WQE_H__ */
5021 diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
5022 index 03fddfa..e31e3fe 100644
5023 --- a/arch/mips/include/asm/octeon/cvmx.h
5024 +++ b/arch/mips/include/asm/octeon/cvmx.h
5025 @@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(void)
5026 }
5027
5028 /**
5029 + * Wait for the specified number of cycle
5030 + *
5031 + */
5032 +static inline void cvmx_wait(uint64_t cycles)
5033 +{
5034 + uint64_t done = cvmx_get_cycle() + cycles;
5035 +
5036 + while (cvmx_get_cycle() < done)
5037 + ; /* Spin */
5038 +}
5039 +
5040 +/**
5041 * Reads a chip global cycle counter. This counts CPU cycles since
5042 * chip reset. The counter is 64 bit.
5043 * This register does not exist on CN38XX pass 1 silicion
5044 diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
5045 index edc6760..cac9b1a 100644
5046 --- a/arch/mips/include/asm/octeon/octeon.h
5047 +++ b/arch/mips/include/asm/octeon/octeon.h
5048 @@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
5049 return cvmx_read64_uint32(address ^ 4);
5050 }
5051
5052 +extern struct cvmx_bootinfo *octeon_bootinfo;
5053 +
5054 #endif /* __ASM_OCTEON_OCTEON_H */
5055 --
5056 1.5.6.5
5057
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