1 /**************************************************************************
3 * BRIEF MODULE DESCRIPTION
4 * Driver for the IDT RC32434 on-chip ethernet controller.
6 * Copyright 2004 IDT Inc. (rischelp@idt.com)
7 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 **************************************************************************
33 * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
39 **************************************************************************
42 #include <linux/autoconf.h>
43 #include <linux/module.h>
44 #include <linux/kernel.h>
45 #include <linux/moduleparam.h>
46 #include <linux/sched.h>
47 #include <linux/ctype.h>
48 #include <linux/types.h>
49 #include <linux/fcntl.h>
50 #include <linux/interrupt.h>
51 #include <linux/ptrace.h>
52 #include <linux/init.h>
53 #include <linux/ioport.h>
54 #include <linux/proc_fs.h>
56 #include <linux/slab.h>
57 #include <linux/string.h>
58 #include <linux/delay.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/skbuff.h>
62 #include <linux/errno.h>
63 #include <linux/platform_device.h>
64 #include <asm/bootinfo.h>
65 #include <asm/system.h>
66 #include <asm/bitops.h>
67 #include <asm/pgtable.h>
68 #include <asm/segment.h>
72 #include <asm/rc32434/rb.h>
73 #include "rc32434_eth.h"
75 #define DRIVER_VERSION "(mar2904)"
77 #define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
79 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
81 #define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
82 ((dev)->dev_addr[3] << 16) | \
83 ((dev)->dev_addr[4] << 8) | \
86 #define MII_CLOCK 1250000 /* no more than 2.5MHz */
87 #define CONFIG_IDT_USE_NAPI 1
90 static inline void rc32434_abort_tx(struct net_device
*dev
)
92 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
93 rc32434_abort_dma(dev
, lp
->tx_dma_regs
);
97 static inline void rc32434_abort_rx(struct net_device
*dev
)
99 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
100 rc32434_abort_dma(dev
, lp
->rx_dma_regs
);
104 static inline void rc32434_start_tx(struct rc32434_local
*lp
, volatile DMAD_t td
)
106 rc32434_start_dma(lp
->tx_dma_regs
, CPHYSADDR(td
));
109 static inline void rc32434_start_rx(struct rc32434_local
*lp
, volatile DMAD_t rd
)
111 rc32434_start_dma(lp
->rx_dma_regs
, CPHYSADDR(rd
));
114 static inline void rc32434_chain_tx(struct rc32434_local
*lp
, volatile DMAD_t td
)
116 rc32434_chain_dma(lp
->tx_dma_regs
, CPHYSADDR(td
));
119 static inline void rc32434_chain_rx(struct rc32434_local
*lp
, volatile DMAD_t rd
)
121 rc32434_chain_dma(lp
->rx_dma_regs
, CPHYSADDR(rd
));
124 #ifdef RC32434_PROC_DEBUG
125 static int rc32434_read_proc(char *buf
, char **start
, off_t fpos
,
126 int length
, int *eof
, void *data
)
128 struct net_device
*dev
= (struct net_device
*)data
;
129 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
132 /* print out header */
133 len
+= sprintf(buf
+ len
, "\n\tKorina Ethernet Debug\n\n");
134 len
+= sprintf (buf
+ len
,
135 "DMA halt count = %10d, DMA run count = %10d\n",
136 lp
->dma_halt_cnt
, lp
->dma_run_cnt
);
145 if ((len
-= fpos
) > length
)
156 * Restart the RC32434 ethernet controller.
158 static int rc32434_restart(struct net_device
*dev
)
160 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
165 disable_irq(lp
->rx_irq
);
166 disable_irq(lp
->tx_irq
);
167 #ifdef RC32434_REVISION
168 disable_irq(lp
->ovr_irq
);
170 disable_irq(lp
->und_irq
);
172 /* Mask F E bit in Tx DMA */
173 __raw_writel(__raw_readl(&lp
->tx_dma_regs
->dmasm
) | DMASM_f_m
| DMASM_e_m
, &lp
->tx_dma_regs
->dmasm
);
174 /* Mask D H E bit in Rx DMA */
175 __raw_writel(__raw_readl(&lp
->rx_dma_regs
->dmasm
) | DMASM_d_m
| DMASM_h_m
| DMASM_e_m
, &lp
->rx_dma_regs
->dmasm
);
178 rc32434_multicast_list(dev
);
180 enable_irq(lp
->und_irq
);
181 #ifdef RC32434_REVISION
182 enable_irq(lp
->ovr_irq
);
184 enable_irq(lp
->tx_irq
);
185 enable_irq(lp
->rx_irq
);
190 static int rc32434_probe(struct platform_device
*pdev
)
192 struct korina_device
*bif
= (struct korina_device
*) pdev
->dev
.platform_data
;
193 struct rc32434_local
*lp
= NULL
;
194 struct net_device
*dev
= NULL
;
198 dev
= alloc_etherdev(sizeof(struct rc32434_local
));
200 ERR("Korina_eth: alloc_etherdev failed\n");
204 platform_set_drvdata(pdev
, dev
);
205 SET_NETDEV_DEV(dev
, &pdev
->dev
);
208 memcpy(dev
->dev_addr
, bif
->mac
, 6);
210 /* Initialize the device structure. */
211 if (dev
->priv
== NULL
) {
212 lp
= (struct rc32434_local
*)kmalloc(sizeof(*lp
), GFP_KERNEL
);
213 memset(lp
, 0, sizeof(struct rc32434_local
));
216 lp
= (struct rc32434_local
*)dev
->priv
;
219 lp
->rx_irq
= platform_get_irq_byname(pdev
, "korina_rx");
220 lp
->tx_irq
= platform_get_irq_byname(pdev
, "korina_tx");
221 lp
->ovr_irq
= platform_get_irq_byname(pdev
, "korina_ovr");
222 lp
->und_irq
= platform_get_irq_byname(pdev
, "korina_und");
224 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "korina_regs");
225 dev
->base_addr
= r
->start
;
226 lp
->eth_regs
= ioremap_nocache(r
->start
, r
->end
- r
->start
);
228 ERR("Can't remap eth registers\n");
233 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "korina_dma_rx");
234 lp
->rx_dma_regs
= ioremap_nocache(r
->start
, r
->end
- r
->start
);
235 if (!lp
->rx_dma_regs
) {
236 ERR("Can't remap Rx DMA registers\n");
241 r
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "korina_dma_tx");
242 lp
->tx_dma_regs
= ioremap_nocache(r
->start
, r
->end
- r
->start
);
243 if (!lp
->tx_dma_regs
) {
244 ERR("Can't remap Tx DMA registers\n");
249 #ifdef RC32434_PROC_DEBUG
250 lp
->ps
= create_proc_read_entry (bif
->name
, 0, proc_net
,
251 rc32434_read_proc
, dev
);
254 lp
->td_ring
= (DMAD_t
)kmalloc(TD_RING_SIZE
+ RD_RING_SIZE
, GFP_KERNEL
);
256 ERR("Can't allocate descriptors\n");
261 dma_cache_inv((unsigned long)(lp
->td_ring
), TD_RING_SIZE
+ RD_RING_SIZE
);
263 /* now convert TD_RING pointer to KSEG1 */
264 lp
->td_ring
= (DMAD_t
)KSEG1ADDR(lp
->td_ring
);
265 lp
->rd_ring
= &lp
->td_ring
[RC32434_NUM_TDS
];
268 spin_lock_init(&lp
->lock
);
270 /* just use the rx dma irq */
271 dev
->irq
= lp
->rx_irq
;
276 dev
->open
= rc32434_open
;
277 dev
->stop
= rc32434_close
;
278 dev
->hard_start_xmit
= rc32434_send_packet
;
279 dev
->get_stats
= rc32434_get_stats
;
280 dev
->set_multicast_list
= &rc32434_multicast_list
;
281 dev
->tx_timeout
= rc32434_tx_timeout
;
282 dev
->watchdog_timeo
= RC32434_TX_TIMEOUT
;
284 netif_napi_add(dev
, &lp
->napi
, rc32434_poll
, 64);
285 lp
->tx_tasklet
= kmalloc(sizeof(struct tasklet_struct
), GFP_KERNEL
);
286 tasklet_init(lp
->tx_tasklet
, rc32434_tx_tasklet
, (unsigned long)dev
);
288 if ((err
= register_netdev(dev
))) {
289 printk(KERN_ERR
"rc32434 ethernet. Cannot register net device %d\n", err
);
295 INFO("Rx IRQ %d, Tx IRQ %d, ", lp
->rx_irq
, lp
->tx_irq
);
296 for (i
= 0; i
< 6; i
++) {
297 printk("%2.2x", dev
->dev_addr
[i
]);
306 rc32434_cleanup_module();
307 ERR(" failed. Returns %d\n", retval
);
312 static int rc32434_remove(struct platform_device
*pdev
)
314 struct korina_device
*bif
= (struct korina_device
*) pdev
->dev
.platform_data
;
316 if (bif
->dev
!= NULL
) {
317 struct rc32434_local
*lp
= (struct rc32434_local
*)bif
->dev
->priv
;
320 iounmap((void*)lp
->eth_regs
);
322 iounmap((void*)lp
->rx_dma_regs
);
324 iounmap((void*)lp
->tx_dma_regs
);
326 kfree((void*)KSEG0ADDR(lp
->td_ring
));
328 #ifdef RC32434_PROC_DEBUG
330 remove_proc_entry(bif
->name
, proc_net
);
336 platform_set_drvdata(pdev
, NULL
);
337 unregister_netdev(bif
->dev
);
338 free_netdev(bif
->dev
);
345 static int rc32434_open(struct net_device
*dev
)
347 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
350 if (rc32434_init(dev
)) {
351 ERR("Error: cannot open the Ethernet device\n");
355 /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
356 if (request_irq(lp
->rx_irq
, &rc32434_rx_dma_interrupt
,
357 IRQF_SHARED
| IRQF_DISABLED
,
358 "Korina ethernet Rx", dev
)) {
359 ERR(": unable to get Rx DMA IRQ %d\n",
363 if (request_irq(lp
->tx_irq
, &rc32434_tx_dma_interrupt
,
364 IRQF_SHARED
| IRQF_DISABLED
,
365 "Korina ethernet Tx", dev
)) {
366 ERR(": unable to get Tx DMA IRQ %d\n",
368 free_irq(lp
->rx_irq
, dev
);
372 #ifdef RC32434_REVISION
373 /* Install handler for overrun error. */
374 if (request_irq(lp
->ovr_irq
, &rc32434_ovr_interrupt
,
375 IRQF_SHARED
| IRQF_DISABLED
,
376 "Ethernet Overflow", dev
)) {
377 ERR(": unable to get OVR IRQ %d\n",
379 free_irq(lp
->rx_irq
, dev
);
380 free_irq(lp
->tx_irq
, dev
);
385 /* Install handler for underflow error. */
386 if (request_irq(lp
->und_irq
, &rc32434_und_interrupt
,
387 IRQF_SHARED
| IRQF_DISABLED
,
388 "Ethernet Underflow", dev
)) {
389 ERR(": unable to get UND IRQ %d\n",
391 free_irq(lp
->rx_irq
, dev
);
392 free_irq(lp
->tx_irq
, dev
);
393 #ifdef RC32434_REVISION
394 free_irq(lp
->ovr_irq
, dev
);
406 static int rc32434_close(struct net_device
*dev
)
408 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
411 /* Disable interrupts */
412 disable_irq(lp
->rx_irq
);
413 disable_irq(lp
->tx_irq
);
414 #ifdef RC32434_REVISION
415 disable_irq(lp
->ovr_irq
);
417 disable_irq(lp
->und_irq
);
419 tmp
= __raw_readl(&lp
->tx_dma_regs
->dmasm
);
420 tmp
= tmp
| DMASM_f_m
| DMASM_e_m
;
421 __raw_writel(tmp
, &lp
->tx_dma_regs
->dmasm
);
423 tmp
= __raw_readl(&lp
->rx_dma_regs
->dmasm
);
424 tmp
= tmp
| DMASM_d_m
| DMASM_h_m
| DMASM_e_m
;
425 __raw_writel(tmp
, &lp
->rx_dma_regs
->dmasm
);
427 free_irq(lp
->rx_irq
, dev
);
428 free_irq(lp
->tx_irq
, dev
);
429 #ifdef RC32434_REVISION
430 free_irq(lp
->ovr_irq
, dev
);
432 free_irq(lp
->und_irq
, dev
);
437 /* transmit packet */
438 static int rc32434_send_packet(struct sk_buff
*skb
, struct net_device
*dev
)
440 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
446 spin_lock_irqsave(&lp
->lock
, flags
);
448 td
= &lp
->td_ring
[lp
->tx_chain_tail
];
450 /* stop queue when full, drop pkts if queue already full */
451 if(lp
->tx_count
>= (RC32434_NUM_TDS
- 2)) {
454 if(lp
->tx_count
== (RC32434_NUM_TDS
- 2)) {
455 netif_stop_queue(dev
);
458 lp
->stats
.tx_dropped
++;
459 dev_kfree_skb_any(skb
);
460 spin_unlock_irqrestore(&lp
->lock
, flags
);
467 lp
->tx_skb
[lp
->tx_chain_tail
] = skb
;
470 dma_cache_wback((u32
)skb
->data
, skb
->len
);
472 /* Setup the transmit descriptor. */
473 dma_cache_inv((u32
) td
, sizeof(*td
));
474 td
->ca
= CPHYSADDR(skb
->data
);
476 if(__raw_readl(&(lp
->tx_dma_regs
->dmandptr
)) == 0) {
477 if( lp
->tx_chain_status
== empty
) {
478 td
->control
= DMA_COUNT(length
) |DMAD_cof_m
|DMAD_iof_m
; /* Update tail */
479 lp
->tx_chain_tail
= (lp
->tx_chain_tail
+ 1) & RC32434_TDS_MASK
; /* Move tail */
480 __raw_writel(CPHYSADDR(&lp
->td_ring
[lp
->tx_chain_head
]), &(lp
->tx_dma_regs
->dmandptr
)); /* Write to NDPTR */
481 lp
->tx_chain_head
= lp
->tx_chain_tail
; /* Move head to tail */
484 td
->control
= DMA_COUNT(length
) |DMAD_cof_m
|DMAD_iof_m
; /* Update tail */
485 lp
->td_ring
[(lp
->tx_chain_tail
-1)& RC32434_TDS_MASK
].control
&= ~(DMAD_cof_m
); /* Link to prev */
486 lp
->td_ring
[(lp
->tx_chain_tail
-1)& RC32434_TDS_MASK
].link
= CPHYSADDR(td
); /* Link to prev */
487 lp
->tx_chain_tail
= (lp
->tx_chain_tail
+ 1) & RC32434_TDS_MASK
; /* Move tail */
488 __raw_writel(CPHYSADDR(&lp
->td_ring
[lp
->tx_chain_head
]), &(lp
->tx_dma_regs
->dmandptr
)); /* Write to NDPTR */
489 lp
->tx_chain_head
= lp
->tx_chain_tail
; /* Move head to tail */
490 lp
->tx_chain_status
= empty
;
494 if( lp
->tx_chain_status
== empty
) {
495 td
->control
= DMA_COUNT(length
) |DMAD_cof_m
|DMAD_iof_m
; /* Update tail */
496 lp
->tx_chain_tail
= (lp
->tx_chain_tail
+ 1) & RC32434_TDS_MASK
; /* Move tail */
497 lp
->tx_chain_status
= filled
;
500 td
->control
= DMA_COUNT(length
) |DMAD_cof_m
|DMAD_iof_m
; /* Update tail */
501 lp
->td_ring
[(lp
->tx_chain_tail
-1)& RC32434_TDS_MASK
].control
&= ~(DMAD_cof_m
); /* Link to prev */
502 lp
->td_ring
[(lp
->tx_chain_tail
-1)& RC32434_TDS_MASK
].link
= CPHYSADDR(td
); /* Link to prev */
503 lp
->tx_chain_tail
= (lp
->tx_chain_tail
+ 1) & RC32434_TDS_MASK
; /* Move tail */
506 dma_cache_wback((u32
) td
, sizeof(*td
));
508 dev
->trans_start
= jiffies
;
510 spin_unlock_irqrestore(&lp
->lock
, flags
);
516 /* Ethernet MII-PHY Handler */
517 static void rc32434_mii_handler(unsigned long data
)
519 struct net_device
*dev
= (struct net_device
*)data
;
520 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
522 unsigned long duplex_status
;
523 int port_addr
= (lp
->rx_irq
== 0x2c? 1:0) << 8;
525 spin_lock_irqsave(&lp
->lock
, flags
);
527 /* Two ports are using the same MII, the difference is the PHY address */
528 __raw_writel(0, &rc32434_eth0_regs
->miimcfg
);
529 __raw_writel(0, &rc32434_eth0_regs
->miimcmd
);
530 __raw_writel(port_addr
|0x05, &rc32434_eth0_regs
->miimaddr
);
531 __raw_writel(MIIMCMD_scn_m
, &rc32434_eth0_regs
->miimcmd
);
532 while(__raw_readl(&rc32434_eth0_regs
->miimind
) & MIIMIND_nv_m
);
534 ERR("irq:%x port_addr:%x RDD:%x\n",
535 lp
->rx_irq
, port_addr
, __raw_readl(&rc32434_eth0_regs
->miimrdd
));
536 duplex_status
= (__raw_readl(&rc32434_eth0_regs
->miimrdd
) & 0x140)? ETHMAC2_fd_m
: 0;
537 if(duplex_status
!= lp
->duplex_mode
) {
538 ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status
? "Full":"Half", lp
->rx_irq
== 0x2c? 1:0);
539 lp
->duplex_mode
= duplex_status
;
540 rc32434_restart(dev
);
543 lp
->mii_phy_timer
.expires
= jiffies
+ 10 * HZ
;
544 add_timer(&lp
->mii_phy_timer
);
546 spin_unlock_irqrestore(&lp
->lock
, flags
);
550 #ifdef RC32434_REVISION
551 /* Ethernet Rx Overflow interrupt */
553 rc32434_ovr_interrupt(int irq
, void *dev_id
)
555 struct net_device
*dev
= (struct net_device
*)dev_id
;
556 struct rc32434_local
*lp
;
558 irqreturn_t retval
= IRQ_NONE
;
562 lp
= (struct rc32434_local
*)dev
->priv
;
563 spin_lock(&lp
->lock
);
564 ovr
= __raw_readl(&lp
->eth_regs
->ethintfc
);
566 if(ovr
& ETHINTFC_ovr_m
) {
567 netif_stop_queue(dev
);
570 __raw_writel((ovr
& ~ETHINTFC_ovr_m
), &lp
->eth_regs
->ethintfc
);
572 /* Restart interface */
573 rc32434_restart(dev
);
574 retval
= IRQ_HANDLED
;
576 spin_unlock(&lp
->lock
);
584 /* Ethernet Tx Underflow interrupt */
586 rc32434_und_interrupt(int irq
, void *dev_id
)
588 struct net_device
*dev
= (struct net_device
*)dev_id
;
589 struct rc32434_local
*lp
;
591 irqreturn_t retval
= IRQ_NONE
;
595 lp
= (struct rc32434_local
*)dev
->priv
;
597 spin_lock(&lp
->lock
);
599 und
= __raw_readl(&lp
->eth_regs
->ethintfc
);
601 if(und
& ETHINTFC_und_m
) {
602 netif_stop_queue(dev
);
604 __raw_writel((und
& ~ETHINTFC_und_m
), &lp
->eth_regs
->ethintfc
);
606 /* Restart interface */
607 rc32434_restart(dev
);
608 retval
= IRQ_HANDLED
;
611 spin_unlock(&lp
->lock
);
617 /* Ethernet Rx DMA interrupt */
619 rc32434_rx_dma_interrupt(int irq
, void *dev_id
)
621 struct net_device
*dev
= (struct net_device
*)dev_id
;
622 struct rc32434_local
* lp
;
623 volatile u32 dmas
,dmasm
;
628 lp
= (struct rc32434_local
*)dev
->priv
;
630 spin_lock(&lp
->lock
);
631 dmas
= __raw_readl(&lp
->rx_dma_regs
->dmas
);
632 if(dmas
& (DMAS_d_m
|DMAS_h_m
|DMAS_e_m
)) {
633 /* Mask D H E bit in Rx DMA */
634 dmasm
= __raw_readl(&lp
->rx_dma_regs
->dmasm
);
635 __raw_writel(dmasm
| (DMASM_d_m
| DMASM_h_m
| DMASM_e_m
), &lp
->rx_dma_regs
->dmasm
);
637 netif_rx_schedule_prep(dev
, &lp
->napi
);
640 ERR(": DMA error\n");
642 retval
= IRQ_HANDLED
;
647 spin_unlock(&lp
->lock
);
651 static int rc32434_poll(struct napi_struct
*napi
, int budget
)
653 struct rc32434_local
* lp
= container_of(napi
, struct rc32434_local
, napi
);
654 struct net_device
*dev
= lp
->dev
;
655 volatile DMAD_t rd
= &lp
->rd_ring
[lp
->rx_next_done
];
656 struct sk_buff
*skb
, *skb_new
;
658 u32 devcs
, count
, pkt_len
, pktuncrc_len
;
661 int rx_work_limit
= min(budget
, 64);
663 dma_cache_inv((u32
)rd
, sizeof(*rd
));
664 while ( (count
= RC32434_RBSIZE
- (u32
)DMA_COUNT(rd
->control
)) != 0) {
665 if(--rx_work_limit
<0)
669 /* init the var. used for the later operations within the while loop */
672 pkt_len
= RCVPKT_LENGTH(devcs
);
673 skb
= lp
->rx_skb
[lp
->rx_next_done
];
676 lp
->stats
.rx_errors
++;
677 lp
->stats
.rx_dropped
++;
679 else if ((devcs
& ( ETHRX_ld_m
)) != ETHRX_ld_m
) {
680 /* check that this is a whole packet */
681 /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
682 lp
->stats
.rx_errors
++;
683 lp
->stats
.rx_dropped
++;
685 else if ( (devcs
& ETHRX_rok_m
) ) {
688 /* must be the (first and) last descriptor then */
689 pkt_buf
= (u8
*)lp
->rx_skb
[lp
->rx_next_done
]->data
;
691 pktuncrc_len
= pkt_len
- 4;
692 /* invalidate the cache */
693 dma_cache_inv((unsigned long)pkt_buf
, pktuncrc_len
);
695 /* Malloc up new buffer. */
696 skb_new
= dev_alloc_skb(RC32434_RBSIZE
+ 2);
698 if (skb_new
!= NULL
){
700 skb_put(skb
, pktuncrc_len
);
702 skb
->protocol
= eth_type_trans(skb
, dev
);
704 /* pass the packet to upper layers */
705 netif_receive_skb(skb
);
707 dev
->last_rx
= jiffies
;
708 lp
->stats
.rx_packets
++;
709 lp
->stats
.rx_bytes
+= pktuncrc_len
;
711 if (IS_RCV_MP(devcs
))
712 lp
->stats
.multicast
++;
715 skb_reserve(skb_new
, 2);
718 lp
->rx_skb
[lp
->rx_next_done
] = skb_new
;
721 ERR("no memory, dropping rx packet.\n");
722 lp
->stats
.rx_errors
++;
723 lp
->stats
.rx_dropped
++;
729 /* This should only happen if we enable accepting broken packets */
730 lp
->stats
.rx_errors
++;
731 lp
->stats
.rx_dropped
++;
733 /* add statistics counters */
734 if (IS_RCV_CRC_ERR(devcs
)) {
735 DBG(2, "RX CRC error\n");
736 lp
->stats
.rx_crc_errors
++;
738 else if (IS_RCV_LOR_ERR(devcs
)) {
739 DBG(2, "RX LOR error\n");
740 lp
->stats
.rx_length_errors
++;
742 else if (IS_RCV_LE_ERR(devcs
)) {
743 DBG(2, "RX LE error\n");
744 lp
->stats
.rx_length_errors
++;
746 else if (IS_RCV_OVR_ERR(devcs
)) {
747 lp
->stats
.rx_over_errors
++;
749 else if (IS_RCV_CV_ERR(devcs
)) {
751 DBG(2, "RX CV error\n");
752 lp
->stats
.rx_frame_errors
++;
754 else if (IS_RCV_CES_ERR(devcs
)) {
755 DBG(2, "RX Preamble error\n");
761 /* restore descriptor's curr_addr */
763 rd
->ca
= CPHYSADDR(skb_new
->data
);
765 rd
->ca
= CPHYSADDR(skb
->data
);
767 rd
->control
= DMA_COUNT(RC32434_RBSIZE
) |DMAD_cod_m
|DMAD_iod_m
;
768 lp
->rd_ring
[(lp
->rx_next_done
-1)& RC32434_RDS_MASK
].control
&= ~(DMAD_cod_m
);
770 lp
->rx_next_done
= (lp
->rx_next_done
+ 1) & RC32434_RDS_MASK
;
771 dma_cache_wback((u32
)rd
, sizeof(*rd
));
772 rd
= &lp
->rd_ring
[lp
->rx_next_done
];
773 __raw_writel( ~DMAS_d_m
, &lp
->rx_dma_regs
->dmas
);
776 if(rx_work_limit
< 0)
779 dmas
= __raw_readl(&lp
->rx_dma_regs
->dmas
);
781 if(dmas
& DMAS_h_m
) {
782 __raw_writel( ~(DMAS_h_m
| DMAS_e_m
), &lp
->rx_dma_regs
->dmas
);
783 #ifdef RC32434_PROC_DEBUG
787 skb
= lp
->rx_skb
[lp
->rx_next_done
];
788 rd
->ca
= CPHYSADDR(skb
->data
);
789 dma_cache_wback((u32
)rd
, sizeof(*rd
));
790 rc32434_chain_rx(lp
,rd
);
793 netif_rx_complete(dev
, &lp
->napi
);
794 /* Enable D H E bit in Rx DMA */
795 __raw_writel(__raw_readl(&lp
->rx_dma_regs
->dmasm
) & ~(DMASM_d_m
| DMASM_h_m
|DMASM_e_m
), &lp
->rx_dma_regs
->dmasm
);
803 /* Ethernet Tx DMA interrupt */
805 rc32434_tx_dma_interrupt(int irq
, void *dev_id
)
807 struct net_device
*dev
= (struct net_device
*)dev_id
;
808 struct rc32434_local
*lp
;
809 volatile u32 dmas
,dmasm
;
814 lp
= (struct rc32434_local
*)dev
->priv
;
816 spin_lock(&lp
->lock
);
818 dmas
= __raw_readl(&lp
->tx_dma_regs
->dmas
);
820 if (dmas
& (DMAS_f_m
| DMAS_e_m
)) {
821 dmasm
= __raw_readl(&lp
->tx_dma_regs
->dmasm
);
822 /* Mask F E bit in Tx DMA */
823 __raw_writel(dmasm
| (DMASM_f_m
| DMASM_e_m
), &lp
->tx_dma_regs
->dmasm
);
825 tasklet_hi_schedule(lp
->tx_tasklet
);
827 if(lp
->tx_chain_status
== filled
&& (__raw_readl(&(lp
->tx_dma_regs
->dmandptr
)) == 0)) {
828 __raw_writel(CPHYSADDR(&lp
->td_ring
[lp
->tx_chain_head
]), &(lp
->tx_dma_regs
->dmandptr
));
829 lp
->tx_chain_status
= empty
;
830 lp
->tx_chain_head
= lp
->tx_chain_tail
;
831 dev
->trans_start
= jiffies
;
835 ERR(": DMA error\n");
837 retval
= IRQ_HANDLED
;
842 spin_unlock(&lp
->lock
);
848 static void rc32434_tx_tasklet(unsigned long tx_data_dev
)
850 struct net_device
*dev
= (struct net_device
*)tx_data_dev
;
851 struct rc32434_local
* lp
= (struct rc32434_local
*)dev
->priv
;
852 volatile DMAD_t td
= &lp
->td_ring
[lp
->tx_next_done
];
857 spin_lock_irqsave(&lp
->lock
, flags
);
859 /* process all desc that are done */
860 while(IS_DMA_FINISHED(td
->control
)) {
861 if(lp
->tx_full
== 1) {
862 netif_wake_queue(dev
);
866 devcs
= lp
->td_ring
[lp
->tx_next_done
].devcs
;
867 if ((devcs
& (ETHTX_fd_m
| ETHTX_ld_m
)) != (ETHTX_fd_m
| ETHTX_ld_m
)) {
868 lp
->stats
.tx_errors
++;
869 lp
->stats
.tx_dropped
++;
871 /* should never happen */
872 DBG(1, __FUNCTION__
": split tx ignored\n");
874 else if (IS_TX_TOK(devcs
)) {
875 lp
->stats
.tx_packets
++;
876 lp
->stats
.tx_bytes
+=lp
->tx_skb
[lp
->tx_next_done
]->len
;
879 lp
->stats
.tx_errors
++;
880 lp
->stats
.tx_dropped
++;
883 if (IS_TX_UND_ERR(devcs
))
884 lp
->stats
.tx_fifo_errors
++;
886 /* oversized frame */
887 if (IS_TX_OF_ERR(devcs
))
888 lp
->stats
.tx_aborted_errors
++;
890 /* excessive deferrals */
891 if (IS_TX_ED_ERR(devcs
))
892 lp
->stats
.tx_carrier_errors
++;
894 /* collisions: medium busy */
895 if (IS_TX_EC_ERR(devcs
))
896 lp
->stats
.collisions
++;
899 if (IS_TX_LC_ERR(devcs
))
900 lp
->stats
.tx_window_errors
++;
904 /* We must always free the original skb */
905 if (lp
->tx_skb
[lp
->tx_next_done
] != NULL
) {
906 dev_kfree_skb_any(lp
->tx_skb
[lp
->tx_next_done
]);
907 lp
->tx_skb
[lp
->tx_next_done
] = NULL
;
910 lp
->td_ring
[lp
->tx_next_done
].control
= DMAD_iof_m
;
911 lp
->td_ring
[lp
->tx_next_done
].devcs
= ETHTX_fd_m
| ETHTX_ld_m
;
912 lp
->td_ring
[lp
->tx_next_done
].link
= 0;
913 lp
->td_ring
[lp
->tx_next_done
].ca
= 0;
916 /* go on to next transmission */
917 lp
->tx_next_done
= (lp
->tx_next_done
+ 1) & RC32434_TDS_MASK
;
918 td
= &lp
->td_ring
[lp
->tx_next_done
];
922 dmas
= __raw_readl(&lp
->tx_dma_regs
->dmas
);
923 __raw_writel( ~dmas
, &lp
->tx_dma_regs
->dmas
);
925 /* Enable F E bit in Tx DMA */
926 __raw_writel(__raw_readl(&lp
->tx_dma_regs
->dmasm
) & ~(DMASM_f_m
| DMASM_e_m
), &lp
->tx_dma_regs
->dmasm
);
927 spin_unlock_irqrestore(&lp
->lock
, flags
);
932 static struct net_device_stats
* rc32434_get_stats(struct net_device
*dev
)
934 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
940 * Set or clear the multicast filter for this adaptor.
942 static void rc32434_multicast_list(struct net_device
*dev
)
944 /* listen to broadcasts always and to treat */
945 /* IFF bits independantly */
946 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
948 u32 recognise
= ETHARC_ab_m
; /* always accept broadcasts */
950 if (dev
->flags
& IFF_PROMISC
) /* set promiscuous mode */
951 recognise
|= ETHARC_pro_m
;
953 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 15))
954 recognise
|= ETHARC_am_m
; /* all multicast & bcast */
955 else if (dev
->mc_count
> 0) {
956 DBG(2, __FUNCTION__
": mc_count %d\n", dev
->mc_count
);
957 recognise
|= ETHARC_am_m
; /* for the time being */
960 spin_lock_irqsave(&lp
->lock
, flags
);
961 __raw_writel(recognise
, &lp
->eth_regs
->etharc
);
962 spin_unlock_irqrestore(&lp
->lock
, flags
);
966 static void rc32434_tx_timeout(struct net_device
*dev
)
968 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
971 spin_lock_irqsave(&lp
->lock
, flags
);
972 rc32434_restart(dev
);
973 spin_unlock_irqrestore(&lp
->lock
, flags
);
979 * Initialize the RC32434 ethernet controller.
981 static int rc32434_init(struct net_device
*dev
)
983 struct rc32434_local
*lp
= (struct rc32434_local
*)dev
->priv
;
987 rc32434_abort_tx(dev
);
988 rc32434_abort_rx(dev
);
990 /* reset ethernet logic */
991 __raw_writel(0, &lp
->eth_regs
->ethintfc
);
992 while((__raw_readl(&lp
->eth_regs
->ethintfc
) & ETHINTFC_rip_m
))
993 dev
->trans_start
= jiffies
;
995 /* Enable Ethernet Interface */
996 __raw_writel(ETHINTFC_en_m
, &lp
->eth_regs
->ethintfc
);
998 #ifndef CONFIG_IDT_USE_NAPI
999 tasklet_disable(lp
->rx_tasklet
);
1001 tasklet_disable(lp
->tx_tasklet
);
1003 /* Initialize the transmit Descriptors */
1004 for (i
= 0; i
< RC32434_NUM_TDS
; i
++) {
1005 lp
->td_ring
[i
].control
= DMAD_iof_m
;
1006 lp
->td_ring
[i
].devcs
= ETHTX_fd_m
| ETHTX_ld_m
;
1007 lp
->td_ring
[i
].ca
= 0;
1008 lp
->td_ring
[i
].link
= 0;
1009 if (lp
->tx_skb
[i
] != NULL
) {
1010 dev_kfree_skb_any(lp
->tx_skb
[i
]);
1011 lp
->tx_skb
[i
] = NULL
;
1014 lp
->tx_next_done
= lp
->tx_chain_head
= lp
->tx_chain_tail
= lp
->tx_full
= lp
->tx_count
= 0;
1015 lp
-> tx_chain_status
= empty
;
1018 * Initialize the receive descriptors so that they
1019 * become a circular linked list, ie. let the last
1020 * descriptor point to the first again.
1022 for (i
=0; i
<RC32434_NUM_RDS
; i
++) {
1023 struct sk_buff
*skb
= lp
->rx_skb
[i
];
1025 if (lp
->rx_skb
[i
] == NULL
) {
1026 skb
= dev_alloc_skb(RC32434_RBSIZE
+ 2);
1028 ERR("No memory in the system\n");
1029 for (j
= 0; j
< RC32434_NUM_RDS
; j
++)
1030 if (lp
->rx_skb
[j
] != NULL
)
1031 dev_kfree_skb_any(lp
->rx_skb
[j
]);
1037 skb_reserve(skb
, 2);
1038 lp
->rx_skb
[i
] = skb
;
1039 lp
->rd_ring
[i
].ca
= CPHYSADDR(skb
->data
);
1043 lp
->rd_ring
[i
].control
= DMAD_iod_m
| DMA_COUNT(RC32434_RBSIZE
);
1044 lp
->rd_ring
[i
].devcs
= 0;
1045 lp
->rd_ring
[i
].ca
= CPHYSADDR(skb
->data
);
1046 lp
->rd_ring
[i
].link
= CPHYSADDR(&lp
->rd_ring
[i
+1]);
1050 lp
->rd_ring
[RC32434_NUM_RDS
-1].link
= CPHYSADDR(&lp
->rd_ring
[0]);
1051 lp
->rx_next_done
= 0;
1053 lp
->rd_ring
[RC32434_NUM_RDS
-1].control
|= DMAD_cod_m
;
1054 lp
->rx_chain_head
= 0;
1055 lp
->rx_chain_tail
= 0;
1056 lp
->rx_chain_status
= empty
;
1058 __raw_writel(0, &lp
->rx_dma_regs
->dmas
);
1060 rc32434_start_rx(lp
, &lp
->rd_ring
[0]);
1062 /* Enable F E bit in Tx DMA */
1063 __raw_writel(__raw_readl(&lp
->tx_dma_regs
->dmasm
) & ~(DMASM_f_m
| DMASM_e_m
), &lp
->tx_dma_regs
->dmasm
);
1064 /* Enable D H E bit in Rx DMA */
1065 __raw_writel(__raw_readl(&lp
->rx_dma_regs
->dmasm
) & ~(DMASM_d_m
| DMASM_h_m
| DMASM_e_m
), &lp
->rx_dma_regs
->dmasm
);
1067 /* Accept only packets destined for this Ethernet device address */
1068 __raw_writel(ETHARC_ab_m
, &lp
->eth_regs
->etharc
);
1070 /* Set all Ether station address registers to their initial values */
1071 __raw_writel(STATION_ADDRESS_LOW(dev
), &lp
->eth_regs
->ethsal0
);
1072 __raw_writel(STATION_ADDRESS_HIGH(dev
), &lp
->eth_regs
->ethsah0
);
1074 __raw_writel(STATION_ADDRESS_LOW(dev
), &lp
->eth_regs
->ethsal1
);
1075 __raw_writel(STATION_ADDRESS_HIGH(dev
), &lp
->eth_regs
->ethsah1
);
1077 __raw_writel(STATION_ADDRESS_LOW(dev
), &lp
->eth_regs
->ethsal2
);
1078 __raw_writel(STATION_ADDRESS_HIGH(dev
), &lp
->eth_regs
->ethsah2
);
1080 __raw_writel(STATION_ADDRESS_LOW(dev
), &lp
->eth_regs
->ethsal3
);
1081 __raw_writel(STATION_ADDRESS_HIGH(dev
), &lp
->eth_regs
->ethsah3
);
1084 /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
1085 __raw_writel(ETHMAC2_pe_m
| ETHMAC2_cen_m
| ETHMAC2_fd_m
, &lp
->eth_regs
->ethmac2
);
1086 //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
1088 /* Back to back inter-packet-gap */
1089 __raw_writel(0x15, &lp
->eth_regs
->ethipgt
);
1090 /* Non - Back to back inter-packet-gap */
1091 __raw_writel(0x12, &lp
->eth_regs
->ethipgr
);
1093 /* Management Clock Prescaler Divisor */
1094 /* Clock independent setting */
1095 __raw_writel(((idt_cpu_freq
)/MII_CLOCK
+1) & ~1,
1096 &lp
->eth_regs
->ethmcp
);
1098 /* don't transmit until fifo contains 48b */
1099 __raw_writel(48, &lp
->eth_regs
->ethfifott
);
1101 __raw_writel(ETHMAC1_re_m
, &lp
->eth_regs
->ethmac1
);
1103 napi_enable(&lp
->napi
);
1104 tasklet_enable(lp
->tx_tasklet
);
1106 netif_start_queue(dev
);
1111 static struct platform_driver korina_driver
= {
1112 .driver
.name
= "korina",
1113 .probe
= rc32434_probe
,
1114 .remove
= rc32434_remove
,
1117 static int __init
rc32434_init_module(void)
1119 return platform_driver_register(&korina_driver
);
1122 static void rc32434_cleanup_module(void)
1124 return platform_driver_unregister(&korina_driver
);
1127 module_init(rc32434_init_module
);
1128 module_exit(rc32434_cleanup_module
);