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add generic 2.6.26 patches/files
[openwrt.git] / target / linux / avr32 / patches / 100-git_sync.patch
1 --- /dev/null
2 +++ b/arch/avr32/boards/atngw100/Kconfig
3 @@ -0,0 +1,12 @@
4 +# NGW100 customization
5 +
6 +config BOARD_ATNGW100_I2C_GPIO
7 + bool "Use GPIO for i2c instead of built-in TWI module"
8 + help
9 + The driver for the built-in TWI module has been plagued by
10 + various problems, while the i2c-gpio driver is based on the
11 + trusty old i2c-algo-bit bitbanging engine, making it work
12 + on pretty much any setup.
13 +
14 + Choose 'Y' here if you're having i2c-related problems and
15 + want to rule out the i2c bus driver.
16 --- a/arch/avr32/boards/atngw100/setup.c
17 +++ b/arch/avr32/boards/atngw100/setup.c
18 @@ -20,7 +20,7 @@
19 #include <asm/io.h>
20 #include <asm/setup.h>
21
22 -#include <asm/arch/at32ap7000.h>
23 +#include <asm/arch/at32ap700x.h>
24 #include <asm/arch/board.h>
25 #include <asm/arch/init.h>
26 #include <asm/arch/portmux.h>
27 @@ -37,11 +37,16 @@
28 static struct spi_board_info spi0_board_info[] __initdata = {
29 {
30 .modalias = "mtd_dataflash",
31 - .max_speed_hz = 10000000,
32 + .max_speed_hz = 8000000,
33 .chip_select = 0,
34 },
35 };
36
37 +static struct mci_platform_data __initdata mci0_data = {
38 + .detect_pin = GPIO_PIN_PC(25),
39 + .wp_pin = GPIO_PIN_PE(0),
40 +};
41 +
42 /*
43 * The next two functions should go away as the boot loader is
44 * supposed to initialize the macb address registers with a valid
45 @@ -124,6 +129,7 @@
46 }
47 };
48
49 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
50 static struct i2c_gpio_platform_data i2c_gpio_data = {
51 .sda_pin = GPIO_PIN_PA(6),
52 .scl_pin = GPIO_PIN_PA(7),
53 @@ -139,6 +145,7 @@
54 .platform_data = &i2c_gpio_data,
55 },
56 };
57 +#endif
58
59 static int __init atngw100_init(void)
60 {
61 @@ -157,6 +164,7 @@
62 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
63
64 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
65 + at32_add_device_mci(0, &mci0_data);
66 at32_add_device_usba(0, NULL);
67
68 for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
69 @@ -165,11 +173,15 @@
70 }
71 platform_device_register(&ngw_gpio_leds);
72
73 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
74 at32_select_gpio(i2c_gpio_data.sda_pin,
75 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
76 at32_select_gpio(i2c_gpio_data.scl_pin,
77 AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
78 platform_device_register(&i2c_gpio_device);
79 +#else
80 + at32_add_device_twi(0, NULL, 0);
81 +#endif
82
83 return 0;
84 }
85 --- a/arch/avr32/boards/atstk1000/atstk1000.h
86 +++ b/arch/avr32/boards/atstk1000/atstk1000.h
87 @@ -12,4 +12,6 @@
88
89 extern struct atmel_lcdfb_info atstk1000_lcdc_data;
90
91 +void atstk1000_setup_j2_leds(void);
92 +
93 #endif /* __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H */
94 --- a/arch/avr32/boards/atstk1000/atstk1002.c
95 +++ b/arch/avr32/boards/atstk1000/atstk1002.c
96 @@ -11,7 +11,6 @@
97 #include <linux/etherdevice.h>
98 #include <linux/init.h>
99 #include <linux/kernel.h>
100 -#include <linux/leds.h>
101 #include <linux/platform_device.h>
102 #include <linux/string.h>
103 #include <linux/types.h>
104 @@ -22,7 +21,7 @@
105
106 #include <asm/io.h>
107 #include <asm/setup.h>
108 -#include <asm/arch/at32ap7000.h>
109 +#include <asm/arch/at32ap700x.h>
110 #include <asm/arch/board.h>
111 #include <asm/arch/init.h>
112 #include <asm/arch/portmux.h>
113 @@ -49,18 +48,16 @@
114 },
115 };
116
117 -#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
118 -#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
119 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
120 static struct at73c213_board_info at73c213_data = {
121 .ssc_id = 0,
122 .shortname = "AVR32 STK1000 external DAC",
123 };
124 #endif
125 -#endif
126
127 -#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
128 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
129 static struct spi_board_info spi0_board_info[] __initdata = {
130 -#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
131 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
132 {
133 /* AT73C213 */
134 .modalias = "at73c213",
135 @@ -80,12 +77,25 @@
136 };
137 #endif
138
139 -#ifdef CONFIG_BOARD_ATSTK1002_SPI1
140 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
141 static struct spi_board_info spi1_board_info[] __initdata = { {
142 /* patch in custom entries here */
143 } };
144 #endif
145
146 +static struct cf_platform_data __initdata cf0_data = {
147 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
148 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
149 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
150 +#else
151 + .detect_pin = GPIO_PIN_NONE,
152 + .reset_pin = GPIO_PIN_NONE,
153 +#endif
154 + .vcc_pin = GPIO_PIN_NONE,
155 + .ready_pin = GPIO_PIN_PB(27),
156 + .cs = 4,
157 +};
158 +
159 /*
160 * The next two functions should go away as the boot loader is
161 * supposed to initialize the macb address registers with a valid
162 @@ -141,68 +151,8 @@
163 clk_put(pclk);
164 }
165
166 -#ifdef CONFIG_BOARD_ATSTK1002_J2_LED
167 -
168 -static struct gpio_led stk_j2_led[] = {
169 -#ifdef CONFIG_BOARD_ATSTK1002_J2_LED8
170 -#define LEDSTRING "J2 jumpered to LED8"
171 - { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
172 - { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
173 - { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
174 - { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
175 - { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
176 - { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
177 - { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
178 - { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
179 - .default_trigger = "heartbeat", },
180 -#else /* RGB */
181 -#define LEDSTRING "J2 jumpered to RGB LEDs"
182 - { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
183 - { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
184 - { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
185 -
186 - { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
187 - .default_trigger = "heartbeat", },
188 - { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
189 - { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
190 - .default_trigger = "heartbeat", },
191 - /* PB16, PB30 unused */
192 -#endif
193 -};
194 -
195 -static struct gpio_led_platform_data stk_j2_led_data = {
196 - .num_leds = ARRAY_SIZE(stk_j2_led),
197 - .leds = stk_j2_led,
198 -};
199 -
200 -static struct platform_device stk_j2_led_dev = {
201 - .name = "leds-gpio",
202 - .id = 2, /* gpio block J2 */
203 - .dev = {
204 - .platform_data = &stk_j2_led_data,
205 - },
206 -};
207 -
208 -static void setup_j2_leds(void)
209 -{
210 - unsigned i;
211 -
212 - for (i = 0; i < ARRAY_SIZE(stk_j2_led); i++)
213 - at32_select_gpio(stk_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
214 -
215 - printk("STK1002: " LEDSTRING "\n");
216 - platform_device_register(&stk_j2_led_dev);
217 -}
218 -
219 -#else
220 -static void setup_j2_leds(void)
221 -{
222 -}
223 -#endif
224 -
225 -#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
226 -#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
227 -static void __init at73c213_set_clk(struct at73c213_board_info *info)
228 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
229 +static void __init atstk1002_setup_extdac(void)
230 {
231 struct clk *gclk;
232 struct clk *pll;
233 @@ -220,7 +170,7 @@
234 }
235
236 at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
237 - info->dac_clk = gclk;
238 + at73c213_data.dac_clk = gclk;
239
240 err_set_clk:
241 clk_put(pll);
242 @@ -229,12 +179,16 @@
243 err_gclk:
244 return;
245 }
246 -#endif
247 -#endif
248 +#else
249 +static void __init atstk1002_setup_extdac(void)
250 +{
251 +
252 +}
253 +#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
254
255 void __init setup_board(void)
256 {
257 -#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
258 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
259 at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
260 #else
261 at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
262 @@ -271,7 +225,7 @@
263
264 at32_add_system_devices();
265
266 -#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
267 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
268 at32_add_device_usart(1);
269 #else
270 at32_add_device_usart(0);
271 @@ -281,12 +235,16 @@
272 #ifndef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
273 set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
274 #endif
275 -#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
276 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
277 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
278 #endif
279 -#ifdef CONFIG_BOARD_ATSTK1002_SPI1
280 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
281 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
282 #endif
283 + at32_add_device_twi(0, NULL, 0);
284 +#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
285 + at32_add_device_mci(0, NULL);
286 +#endif
287 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
288 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
289 #else
290 @@ -294,18 +252,23 @@
291 fbmem_start, fbmem_size);
292 #endif
293 at32_add_device_usba(0, NULL);
294 -#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
295 - at32_add_device_ssc(0, ATMEL_SSC_TX);
296 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
297 + at32_add_device_ac97c(0);
298 +#else
299 + at32_add_device_abdac(0);
300 #endif
301 -
302 - setup_j2_leds();
303 -
304 -#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
305 -#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
306 - at73c213_set_clk(&at73c213_data);
307 +#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
308 + at32_add_device_ssc(0, ATMEL_SSC_TX);
309 #endif
310 + at32_add_device_cf(0, 2, &cf0_data);
311 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
312 + at32_add_device_psif(0);
313 + at32_add_device_psif(1);
314 #endif
315
316 + atstk1000_setup_j2_leds();
317 + atstk1002_setup_extdac();
318 +
319 return 0;
320 }
321 postcore_initcall(atstk1002_init);
322 --- /dev/null
323 +++ b/arch/avr32/boards/atstk1000/atstk1003.c
324 @@ -0,0 +1,185 @@
325 +/*
326 + * ATSTK1003 daughterboard-specific init code
327 + *
328 + * Copyright (C) 2007 Atmel Corporation
329 + *
330 + * This program is free software; you can redistribute it and/or modify
331 + * it under the terms of the GNU General Public License version 2 as
332 + * published by the Free Software Foundation.
333 + */
334 +#include <linux/clk.h>
335 +#include <linux/err.h>
336 +#include <linux/init.h>
337 +#include <linux/kernel.h>
338 +#include <linux/platform_device.h>
339 +#include <linux/string.h>
340 +#include <linux/types.h>
341 +
342 +#include <linux/spi/at73c213.h>
343 +#include <linux/spi/spi.h>
344 +
345 +#include <asm/setup.h>
346 +
347 +#include <asm/arch/at32ap700x.h>
348 +#include <asm/arch/board.h>
349 +#include <asm/arch/init.h>
350 +#include <asm/arch/portmux.h>
351 +
352 +#include "atstk1000.h"
353 +
354 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
355 +static struct at73c213_board_info at73c213_data = {
356 + .ssc_id = 0,
357 + .shortname = "AVR32 STK1000 external DAC",
358 +};
359 +#endif
360 +
361 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
362 +static struct spi_board_info spi0_board_info[] __initdata = {
363 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
364 + {
365 + /* AT73C213 */
366 + .modalias = "at73c213",
367 + .max_speed_hz = 200000,
368 + .chip_select = 0,
369 + .mode = SPI_MODE_1,
370 + .platform_data = &at73c213_data,
371 + },
372 +#endif
373 + /*
374 + * We can control the LTV350QV LCD panel, but it isn't much
375 + * point since we don't have an LCD controller...
376 + */
377 +};
378 +#endif
379 +
380 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
381 +static struct spi_board_info spi1_board_info[] __initdata = { {
382 + /* patch in custom entries here */
383 +} };
384 +#endif
385 +
386 +static struct cf_platform_data __initdata cf0_data = {
387 +#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
388 + .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
389 + .reset_pin = CONFIG_BOARD_ATSTK1000_CF_RESET_PIN,
390 +#else
391 + .detect_pin = GPIO_PIN_NONE,
392 + .reset_pin = GPIO_PIN_NONE,
393 +#endif
394 + .vcc_pin = GPIO_PIN_NONE,
395 + .ready_pin = GPIO_PIN_PB(27),
396 + .cs = 4,
397 +};
398 +
399 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
400 +static void __init atstk1003_setup_extdac(void)
401 +{
402 + struct clk *gclk;
403 + struct clk *pll;
404 +
405 + gclk = clk_get(NULL, "gclk0");
406 + if (IS_ERR(gclk))
407 + goto err_gclk;
408 + pll = clk_get(NULL, "pll0");
409 + if (IS_ERR(pll))
410 + goto err_pll;
411 +
412 + if (clk_set_parent(gclk, pll)) {
413 + pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
414 + goto err_set_clk;
415 + }
416 +
417 + at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
418 + at73c213_data.dac_clk = gclk;
419 +
420 +err_set_clk:
421 + clk_put(pll);
422 +err_pll:
423 + clk_put(gclk);
424 +err_gclk:
425 + return;
426 +}
427 +#else
428 +static void __init atstk1003_setup_extdac(void)
429 +{
430 +
431 +}
432 +#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
433 +
434 +void __init setup_board(void)
435 +{
436 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
437 + at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
438 +#else
439 + at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
440 +#endif
441 + /* USART 2/unused: expansion connector */
442 + at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
443 +
444 + at32_setup_serial_console(0);
445 +}
446 +
447 +static int __init atstk1003_init(void)
448 +{
449 + /*
450 + * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
451 + * SDRAM-specific pins so that nobody messes with them.
452 + */
453 + at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */
454 + at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */
455 + at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */
456 + at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */
457 + at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */
458 + at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */
459 + at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */
460 + at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */
461 + at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */
462 + at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */
463 + at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */
464 + at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */
465 + at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */
466 + at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */
467 + at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */
468 + at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */
469 + at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */
470 +
471 + at32_add_system_devices();
472 +
473 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
474 + at32_add_device_usart(1);
475 +#else
476 + at32_add_device_usart(0);
477 +#endif
478 + at32_add_device_usart(2);
479 +
480 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
481 + at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
482 +#endif
483 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
484 + at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
485 +#endif
486 +#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
487 + at32_add_device_mci(0, NULL);
488 +#endif
489 + at32_add_device_usba(0, NULL);
490 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
491 + at32_add_device_ac97c(0);
492 +#else
493 + at32_add_device_abdac(0);
494 +#endif
495 +#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
496 + at32_add_device_ssc(0, ATMEL_SSC_TX);
497 +#endif
498 + at32_add_device_cf(0, 2, &cf0_data);
499 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
500 + at32_add_device_psif(0);
501 + at32_add_device_psif(1);
502 +#endif
503 +
504 + atstk1000_setup_j2_leds();
505 + atstk1003_setup_extdac();
506 +
507 + return 0;
508 +}
509 +postcore_initcall(atstk1003_init);
510 --- /dev/null
511 +++ b/arch/avr32/boards/atstk1000/atstk1004.c
512 @@ -0,0 +1,156 @@
513 +/*
514 + * ATSTK1003 daughterboard-specific init code
515 + *
516 + * Copyright (C) 2007 Atmel Corporation
517 + *
518 + * This program is free software; you can redistribute it and/or modify
519 + * it under the terms of the GNU General Public License version 2 as
520 + * published by the Free Software Foundation.
521 + */
522 +#include <linux/clk.h>
523 +#include <linux/err.h>
524 +#include <linux/init.h>
525 +#include <linux/kernel.h>
526 +#include <linux/platform_device.h>
527 +#include <linux/string.h>
528 +#include <linux/types.h>
529 +
530 +#include <linux/spi/at73c213.h>
531 +#include <linux/spi/spi.h>
532 +
533 +#include <video/atmel_lcdc.h>
534 +
535 +#include <asm/setup.h>
536 +
537 +#include <asm/arch/at32ap700x.h>
538 +#include <asm/arch/board.h>
539 +#include <asm/arch/init.h>
540 +#include <asm/arch/portmux.h>
541 +
542 +#include "atstk1000.h"
543 +
544 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
545 +static struct at73c213_board_info at73c213_data = {
546 + .ssc_id = 0,
547 + .shortname = "AVR32 STK1000 external DAC",
548 +};
549 +#endif
550 +
551 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
552 +static struct spi_board_info spi0_board_info[] __initdata = {
553 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
554 + {
555 + /* AT73C213 */
556 + .modalias = "at73c213",
557 + .max_speed_hz = 200000,
558 + .chip_select = 0,
559 + .mode = SPI_MODE_1,
560 + .platform_data = &at73c213_data,
561 + },
562 +#endif
563 + {
564 + /* QVGA display */
565 + .modalias = "ltv350qv",
566 + .max_speed_hz = 16000000,
567 + .chip_select = 1,
568 + .mode = SPI_MODE_3,
569 + },
570 +};
571 +#endif
572 +
573 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
574 +static struct spi_board_info spi1_board_info[] __initdata = { {
575 + /* patch in custom entries here */
576 +} };
577 +#endif
578 +
579 +#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
580 +static void __init atstk1004_setup_extdac(void)
581 +{
582 + struct clk *gclk;
583 + struct clk *pll;
584 +
585 + gclk = clk_get(NULL, "gclk0");
586 + if (IS_ERR(gclk))
587 + goto err_gclk;
588 + pll = clk_get(NULL, "pll0");
589 + if (IS_ERR(pll))
590 + goto err_pll;
591 +
592 + if (clk_set_parent(gclk, pll)) {
593 + pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
594 + goto err_set_clk;
595 + }
596 +
597 + at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
598 + at73c213_data.dac_clk = gclk;
599 +
600 +err_set_clk:
601 + clk_put(pll);
602 +err_pll:
603 + clk_put(gclk);
604 +err_gclk:
605 + return;
606 +}
607 +#else
608 +static void __init atstk1004_setup_extdac(void)
609 +{
610 +
611 +}
612 +#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
613 +
614 +void __init setup_board(void)
615 +{
616 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
617 + at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
618 +#else
619 + at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
620 +#endif
621 + /* USART 2/unused: expansion connector */
622 + at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
623 +
624 + at32_setup_serial_console(0);
625 +}
626 +
627 +static int __init atstk1004_init(void)
628 +{
629 + at32_add_system_devices();
630 +
631 +#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
632 + at32_add_device_usart(1);
633 +#else
634 + at32_add_device_usart(0);
635 +#endif
636 + at32_add_device_usart(2);
637 +
638 +#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
639 + at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
640 +#endif
641 +#ifdef CONFIG_BOARD_ATSTK100X_SPI1
642 + at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
643 +#endif
644 +#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
645 + at32_add_device_mci(0, NULL);
646 +#endif
647 + at32_add_device_lcdc(0, &atstk1000_lcdc_data,
648 + fbmem_start, fbmem_size);
649 + at32_add_device_usba(0, NULL);
650 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
651 + at32_add_device_ac97c(0);
652 +#else
653 + at32_add_device_abdac(0);
654 +#endif
655 +#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
656 + at32_add_device_ssc(0, ATMEL_SSC_TX);
657 +#endif
658 +#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
659 + at32_add_device_psif(0);
660 + at32_add_device_psif(1);
661 +#endif
662 +
663 + atstk1000_setup_j2_leds();
664 + atstk1004_setup_extdac();
665 +
666 + return 0;
667 +}
668 +postcore_initcall(atstk1004_init);
669 --- a/arch/avr32/boards/atstk1000/Kconfig
670 +++ b/arch/avr32/boards/atstk1000/Kconfig
671 @@ -1,34 +1,53 @@
672 # STK1000 customization
673
674 -if BOARD_ATSTK1002
675 +if BOARD_ATSTK1000
676
677 -config BOARD_ATSTK1002_CUSTOM
678 - bool "Non-default STK-1002 jumper settings"
679 +choice
680 + prompt "ATSTK1000 CPU daughterboard type"
681 + default BOARD_ATSTK1002
682 +
683 +config BOARD_ATSTK1002
684 + bool "ATSTK1002"
685 + select CPU_AT32AP7000
686 +
687 +config BOARD_ATSTK1003
688 + bool "ATSTK1003"
689 + select CPU_AT32AP7001
690 +
691 +config BOARD_ATSTK1004
692 + bool "ATSTK1004"
693 + select CPU_AT32AP7002
694 +
695 +endchoice
696 +
697 +
698 +config BOARD_ATSTK100X_CUSTOM
699 + bool "Non-default STK1002/STK1003/STK1004 jumper settings"
700 help
701 You will normally leave the jumpers on the CPU card at their
702 default settings. If you need to use certain peripherals,
703 you will need to change some of those jumpers.
704
705 -if BOARD_ATSTK1002_CUSTOM
706 +if BOARD_ATSTK100X_CUSTOM
707
708 -config BOARD_ATSTK1002_SW1_CUSTOM
709 +config BOARD_ATSTK100X_SW1_CUSTOM
710 bool "SW1: use SSC1 (not SPI0)"
711 help
712 This also prevents using the external DAC as an audio interface,
713 and means you can't initialize the on-board QVGA display.
714
715 -config BOARD_ATSTK1002_SW2_CUSTOM
716 +config BOARD_ATSTK100X_SW2_CUSTOM
717 bool "SW2: use IRDA or TIMER0 (not UART-A, MMC/SD, and PS2-A)"
718 help
719 If you change this you'll want an updated boot loader putting
720 the console on UART-C not UART-A.
721
722 -config BOARD_ATSTK1002_SW3_CUSTOM
723 +config BOARD_ATSTK100X_SW3_CUSTOM
724 bool "SW3: use TIMER1 (not SSC0 and GCLK)"
725 help
726 This also prevents using the external DAC as an audio interface.
727
728 -config BOARD_ATSTK1002_SW4_CUSTOM
729 +config BOARD_ATSTK100X_SW4_CUSTOM
730 bool "SW4: use ISI/Camera (not GPIOs, SPI1, and PS2-B)"
731 help
732 To use the camera interface you'll need a custom card (on the
733 @@ -36,27 +55,29 @@
734
735 config BOARD_ATSTK1002_SW5_CUSTOM
736 bool "SW5: use MACB1 (not LCDC)"
737 + depends on BOARD_ATSTK1002
738
739 config BOARD_ATSTK1002_SW6_CUSTOM
740 bool "SW6: more GPIOs (not MACB0)"
741 + depends on BOARD_ATSTK1002
742
743 endif # custom
744
745 -config BOARD_ATSTK1002_SPI1
746 +config BOARD_ATSTK100X_SPI1
747 bool "Configure SPI1 controller"
748 - depends on !BOARD_ATSTK1002_SW4_CUSTOM
749 + depends on !BOARD_ATSTK100X_SW4_CUSTOM
750 help
751 All the signals for the second SPI controller are available on
752 GPIO lines and accessed through the J1 jumper block. Say "y"
753 here to configure that SPI controller.
754
755 -config BOARD_ATSTK1002_J2_LED
756 +config BOARD_ATSTK1000_J2_LED
757 bool
758 - default BOARD_ATSTK1002_J2_LED8 || BOARD_ATSTK1002_J2_RGB
759 + default BOARD_ATSTK1000_J2_LED8 || BOARD_ATSTK1000_J2_RGB
760
761 choice
762 prompt "LEDs connected to J2:"
763 - depends on LEDS_GPIO && !BOARD_ATSTK1002_SW4_CUSTOM
764 + depends on LEDS_GPIO && !BOARD_ATSTK100X_SW4_CUSTOM
765 optional
766 help
767 Select this if you have jumpered the J2 jumper block to the
768 @@ -64,16 +85,77 @@
769 IDC cable. A default "heartbeat" trigger is provided, but
770 you can of course override this.
771
772 -config BOARD_ATSTK1002_J2_LED8
773 +config BOARD_ATSTK1000_J2_LED8
774 bool "LED0..LED7"
775 help
776 Select this if J2 is jumpered to LED0..LED7 amber leds.
777
778 -config BOARD_ATSTK1002_J2_RGB
779 +config BOARD_ATSTK1000_J2_RGB
780 bool "RGB leds"
781 help
782 Select this if J2 is jumpered to the RGB leds.
783
784 endchoice
785
786 -endif # stk 1002
787 +config BOARD_ATSTK1000_EXTDAC
788 + bool
789 + depends on !BOARD_ATSTK100X_SW1_CUSTOM && !BOARD_ATSTK100X_SW3_CUSTOM
790 + default y
791 +
792 +config BOARD_ATSTK100X_ENABLE_AC97
793 + bool "Use AC97C instead of ABDAC"
794 + help
795 + Select this if you want to use the built-in AC97 controller
796 + instead of the built-in Audio Bitstream DAC. These share
797 + the same I/O pins on the AP7000, so both can't be enabled
798 + at the same time.
799 +
800 + Note that the STK1000 kit doesn't ship with an AC97 codec on
801 + board, so say N unless you've got an expansion board with an
802 + AC97 codec on it that you want to use.
803 +
804 +config BOARD_ATSTK1000_CF_HACKS
805 + bool "ATSTK1000 CompactFlash hacks"
806 + depends on !BOARD_ATSTK100X_SW4_CUSTOM
807 + help
808 + Select this if you have re-routed the CompactFlash RESET and
809 + CD signals to GPIOs on your STK1000. This is necessary for
810 + reset and card detection to work properly, although some CF
811 + cards may be able to cope without reset.
812 +
813 +config BOARD_ATSTK1000_CF_RESET_PIN
814 + hex "CompactFlash RESET pin"
815 + default 0x30
816 + depends on BOARD_ATSTK1000_CF_HACKS
817 + help
818 + Select which GPIO pin to use for the CompactFlash RESET
819 + signal. This is specified as a hexadecimal number and should
820 + be defined as 0x20 * gpio_port + pin.
821 +
822 + The default is 0x30, which is pin 16 on PIOB, aka GPIO14.
823 +
824 +config BOARD_ATSTK1000_CF_DETECT_PIN
825 + hex "CompactFlash DETECT pin"
826 + default 0x3e
827 + depends on BOARD_ATSTK1000_CF_HACKS
828 + help
829 + Select which GPIO pin to use for the CompactFlash CD
830 + signal. This is specified as a hexadecimal number and should
831 + be defined as 0x20 * gpio_port + pin.
832 +
833 + The default is 0x3e, which is pin 30 on PIOB, aka GPIO15.
834 +
835 +config BOARD_ATSTK100X_ENABLE_PSIF
836 + bool "Enable PSIF peripheral (PS/2 support)"
837 + default n
838 + help
839 + Select this if you want to use the PSIF peripheral to hook up PS/2
840 + devices to your STK1000. This will require a hardware modification to
841 + work correctly, since PS/2 devices require 5 volt power and signals,
842 + while the STK1000 only provides 3.3 volt.
843 +
844 + Say N if you have not modified the hardware to boost the voltage, say
845 + Y if you have level convertion hardware or a PS/2 device capable of
846 + operating on 3.3 volt.
847 +
848 +endif # stk 1000
849 --- a/arch/avr32/boards/atstk1000/Makefile
850 +++ b/arch/avr32/boards/atstk1000/Makefile
851 @@ -1,2 +1,4 @@
852 obj-y += setup.o flash.o
853 obj-$(CONFIG_BOARD_ATSTK1002) += atstk1002.o
854 +obj-$(CONFIG_BOARD_ATSTK1003) += atstk1003.o
855 +obj-$(CONFIG_BOARD_ATSTK1004) += atstk1004.o
856 --- a/arch/avr32/boards/atstk1000/setup.c
857 +++ b/arch/avr32/boards/atstk1000/setup.c
858 @@ -10,13 +10,17 @@
859 #include <linux/bootmem.h>
860 #include <linux/fb.h>
861 #include <linux/init.h>
862 +#include <linux/platform_device.h>
863 #include <linux/types.h>
864 #include <linux/linkage.h>
865
866 #include <video/atmel_lcdc.h>
867
868 #include <asm/setup.h>
869 +
870 +#include <asm/arch/at32ap700x.h>
871 #include <asm/arch/board.h>
872 +#include <asm/arch/portmux.h>
873
874 #include "atstk1000.h"
875
876 @@ -61,3 +65,63 @@
877 .default_monspecs = &atstk1000_default_monspecs,
878 .guard_time = 2,
879 };
880 +
881 +#ifdef CONFIG_BOARD_ATSTK1000_J2_LED
882 +#include <linux/leds.h>
883 +
884 +static struct gpio_led stk1000_j2_led[] = {
885 +#ifdef CONFIG_BOARD_ATSTK1000_J2_LED8
886 +#define LEDSTRING "J2 jumpered to LED8"
887 + { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
888 + { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
889 + { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
890 + { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
891 + { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
892 + { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
893 + { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
894 + { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
895 + .default_trigger = "heartbeat", },
896 +#else /* RGB */
897 +#define LEDSTRING "J2 jumpered to RGB LEDs"
898 + { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
899 + { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
900 + { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
901 +
902 + { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
903 + .default_trigger = "heartbeat", },
904 + { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
905 + { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
906 + .default_trigger = "heartbeat", },
907 + /* PB16, PB30 unused */
908 +#endif
909 +};
910 +
911 +static struct gpio_led_platform_data stk1000_j2_led_data = {
912 + .num_leds = ARRAY_SIZE(stk1000_j2_led),
913 + .leds = stk1000_j2_led,
914 +};
915 +
916 +static struct platform_device stk1000_j2_led_dev = {
917 + .name = "leds-gpio",
918 + .id = 2, /* gpio block J2 */
919 + .dev = {
920 + .platform_data = &stk1000_j2_led_data,
921 + },
922 +};
923 +
924 +void __init atstk1000_setup_j2_leds(void)
925 +{
926 + unsigned i;
927 +
928 + for (i = 0; i < ARRAY_SIZE(stk1000_j2_led); i++)
929 + at32_select_gpio(stk1000_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
930 +
931 + printk("STK1000: " LEDSTRING "\n");
932 + platform_device_register(&stk1000_j2_led_dev);
933 +}
934 +#else /* CONFIG_BOARD_ATSTK1000_J2_LED */
935 +void __init atstk1000_setup_j2_leds(void)
936 +{
937 +
938 +}
939 +#endif /* CONFIG_BOARD_ATSTK1000_J2_LED */
940 --- a/arch/avr32/configs/atngw100_defconfig
941 +++ b/arch/avr32/configs/atngw100_defconfig
942 @@ -1,46 +1,52 @@
943 #
944 # Automatically generated make config: don't edit
945 -# Linux kernel version: 2.6.22-rc5
946 -# Sat Jun 23 15:40:05 2007
947 +# Linux kernel version: 2.6.24
948 +# Thu Mar 6 12:49:54 2008
949 #
950 CONFIG_AVR32=y
951 CONFIG_GENERIC_GPIO=y
952 CONFIG_GENERIC_HARDIRQS=y
953 +CONFIG_STACKTRACE_SUPPORT=y
954 +CONFIG_LOCKDEP_SUPPORT=y
955 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
956 CONFIG_HARDIRQS_SW_RESEND=y
957 CONFIG_GENERIC_IRQ_PROBE=y
958 CONFIG_RWSEM_GENERIC_SPINLOCK=y
959 CONFIG_GENERIC_TIME=y
960 +CONFIG_GENERIC_CLOCKEVENTS=y
961 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
962 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
963 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
964 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
965 CONFIG_GENERIC_HWEIGHT=y
966 CONFIG_GENERIC_CALIBRATE_DELAY=y
967 CONFIG_GENERIC_BUG=y
968 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
969
970 #
971 -# Code maturity level options
972 +# General setup
973 #
974 CONFIG_EXPERIMENTAL=y
975 CONFIG_BROKEN_ON_SMP=y
976 CONFIG_INIT_ENV_ARG_LIMIT=32
977 -
978 -#
979 -# General setup
980 -#
981 CONFIG_LOCALVERSION=""
982 # CONFIG_LOCALVERSION_AUTO is not set
983 CONFIG_SWAP=y
984 CONFIG_SYSVIPC=y
985 -# CONFIG_IPC_NS is not set
986 CONFIG_SYSVIPC_SYSCTL=y
987 CONFIG_POSIX_MQUEUE=y
988 CONFIG_BSD_PROCESS_ACCT=y
989 CONFIG_BSD_PROCESS_ACCT_V3=y
990 # CONFIG_TASKSTATS is not set
991 -# CONFIG_UTS_NS is not set
992 +# CONFIG_USER_NS is not set
993 +# CONFIG_PID_NS is not set
994 # CONFIG_AUDIT is not set
995 # CONFIG_IKCONFIG is not set
996 CONFIG_LOG_BUF_SHIFT=14
997 +# CONFIG_CGROUPS is not set
998 +CONFIG_FAIR_GROUP_SCHED=y
999 +CONFIG_FAIR_USER_SCHED=y
1000 +# CONFIG_FAIR_CGROUP_SCHED is not set
1001 CONFIG_SYSFS_DEPRECATED=y
1002 # CONFIG_RELAY is not set
1003 CONFIG_BLK_DEV_INITRD=y
1004 @@ -61,35 +67,28 @@
1005 CONFIG_ANON_INODES=y
1006 CONFIG_EPOLL=y
1007 CONFIG_SIGNALFD=y
1008 -CONFIG_TIMERFD=y
1009 CONFIG_EVENTFD=y
1010 CONFIG_SHMEM=y
1011 CONFIG_VM_EVENT_COUNTERS=y
1012 -# CONFIG_SLUB_DEBUG is not set
1013 +CONFIG_SLUB_DEBUG=y
1014 # CONFIG_SLAB is not set
1015 CONFIG_SLUB=y
1016 # CONFIG_SLOB is not set
1017 +CONFIG_SLABINFO=y
1018 CONFIG_RT_MUTEXES=y
1019 # CONFIG_TINY_SHMEM is not set
1020 CONFIG_BASE_SMALL=1
1021 -
1022 -#
1023 -# Loadable module support
1024 -#
1025 CONFIG_MODULES=y
1026 CONFIG_MODULE_UNLOAD=y
1027 CONFIG_MODULE_FORCE_UNLOAD=y
1028 # CONFIG_MODVERSIONS is not set
1029 # CONFIG_MODULE_SRCVERSION_ALL is not set
1030 CONFIG_KMOD=y
1031 -
1032 -#
1033 -# Block layer
1034 -#
1035 CONFIG_BLOCK=y
1036 # CONFIG_LBD is not set
1037 # CONFIG_BLK_DEV_IO_TRACE is not set
1038 # CONFIG_LSF is not set
1039 +# CONFIG_BLK_DEV_BSG is not set
1040
1041 #
1042 # IO Schedulers
1043 @@ -107,21 +106,28 @@
1044 #
1045 # System Type and features
1046 #
1047 +CONFIG_TICK_ONESHOT=y
1048 +CONFIG_NO_HZ=y
1049 +CONFIG_HIGH_RES_TIMERS=y
1050 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1051 CONFIG_SUBARCH_AVR32B=y
1052 CONFIG_MMU=y
1053 CONFIG_PERFORMANCE_COUNTERS=y
1054 CONFIG_PLATFORM_AT32AP=y
1055 +CONFIG_CPU_AT32AP700X=y
1056 CONFIG_CPU_AT32AP7000=y
1057 # CONFIG_BOARD_ATSTK1000 is not set
1058 CONFIG_BOARD_ATNGW100=y
1059 +CONFIG_BOARD_ATNGW100_I2C_GPIO=y
1060 CONFIG_LOADER_U_BOOT=y
1061
1062 #
1063 # Atmel AVR32 AP options
1064 #
1065 -# CONFIG_AP7000_32_BIT_SMC is not set
1066 -CONFIG_AP7000_16_BIT_SMC=y
1067 -# CONFIG_AP7000_8_BIT_SMC is not set
1068 +# CONFIG_AP700X_32_BIT_SMC is not set
1069 +CONFIG_AP700X_16_BIT_SMC=y
1070 +# CONFIG_AP700X_8_BIT_SMC is not set
1071 +CONFIG_GPIO_DEV=y
1072 CONFIG_LOAD_ADDRESS=0x10000000
1073 CONFIG_ENTRY_ADDRESS=0x90000000
1074 CONFIG_PHYS_OFFSET=0x10000000
1075 @@ -141,10 +147,14 @@
1076 CONFIG_FLATMEM=y
1077 CONFIG_FLAT_NODE_MEM_MAP=y
1078 # CONFIG_SPARSEMEM_STATIC is not set
1079 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
1080 CONFIG_SPLIT_PTLOCK_CPUS=4
1081 # CONFIG_RESOURCES_64BIT is not set
1082 CONFIG_ZONE_DMA_FLAG=0
1083 +CONFIG_VIRT_TO_BUS=y
1084 # CONFIG_OWNERSHIP_TRACE is not set
1085 +# CONFIG_NMI_DEBUGGING is not set
1086 +CONFIG_DW_DMAC=y
1087 # CONFIG_HZ_100 is not set
1088 CONFIG_HZ_250=y
1089 # CONFIG_HZ_300 is not set
1090 @@ -153,13 +163,31 @@
1091 CONFIG_CMDLINE=""
1092
1093 #
1094 -# Bus options
1095 +# Power management options
1096 #
1097 -# CONFIG_ARCH_SUPPORTS_MSI is not set
1098
1099 #
1100 -# PCCARD (PCMCIA/CardBus) support
1101 +# CPU Frequency scaling
1102 +#
1103 +CONFIG_CPU_FREQ=y
1104 +CONFIG_CPU_FREQ_TABLE=y
1105 +# CONFIG_CPU_FREQ_DEBUG is not set
1106 +# CONFIG_CPU_FREQ_STAT is not set
1107 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
1108 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
1109 +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
1110 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
1111 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1112 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
1113 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
1114 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
1115 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
1116 +CONFIG_CPU_FREQ_AT32AP=y
1117 +
1118 +#
1119 +# Bus options
1120 #
1121 +# CONFIG_ARCH_SUPPORTS_MSI is not set
1122 # CONFIG_PCCARD is not set
1123
1124 #
1125 @@ -213,6 +241,7 @@
1126 CONFIG_INET_XFRM_MODE_TRANSPORT=y
1127 CONFIG_INET_XFRM_MODE_TUNNEL=y
1128 CONFIG_INET_XFRM_MODE_BEET=y
1129 +# CONFIG_INET_LRO is not set
1130 CONFIG_INET_DIAG=y
1131 CONFIG_INET_TCP_DIAG=y
1132 # CONFIG_TCP_CONG_ADVANCED is not set
1133 @@ -240,6 +269,7 @@
1134 # CONFIG_NETWORK_SECMARK is not set
1135 CONFIG_NETFILTER=y
1136 # CONFIG_NETFILTER_DEBUG is not set
1137 +CONFIG_BRIDGE_NETFILTER=y
1138
1139 #
1140 # Core Netfilter Configuration
1141 @@ -252,6 +282,7 @@
1142 # CONFIG_NF_CONNTRACK_EVENTS is not set
1143 CONFIG_NF_CT_PROTO_GRE=m
1144 # CONFIG_NF_CT_PROTO_SCTP is not set
1145 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
1146 CONFIG_NF_CONNTRACK_AMANDA=m
1147 CONFIG_NF_CONNTRACK_FTP=m
1148 CONFIG_NF_CONNTRACK_H323=m
1149 @@ -269,9 +300,11 @@
1150 CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
1151 CONFIG_NETFILTER_XT_TARGET_NFLOG=m
1152 # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
1153 +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
1154 CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
1155 CONFIG_NETFILTER_XT_MATCH_COMMENT=m
1156 CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
1157 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
1158 CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
1159 CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
1160 # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
1161 @@ -284,6 +317,7 @@
1162 CONFIG_NETFILTER_XT_MATCH_MARK=m
1163 CONFIG_NETFILTER_XT_MATCH_POLICY=m
1164 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
1165 +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
1166 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
1167 CONFIG_NETFILTER_XT_MATCH_QUOTA=m
1168 CONFIG_NETFILTER_XT_MATCH_REALM=m
1169 @@ -292,6 +326,8 @@
1170 CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
1171 CONFIG_NETFILTER_XT_MATCH_STRING=m
1172 CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
1173 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
1174 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
1175 CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
1176
1177 #
1178 @@ -359,13 +395,19 @@
1179 CONFIG_IP6_NF_MANGLE=m
1180 CONFIG_IP6_NF_TARGET_HL=m
1181 CONFIG_IP6_NF_RAW=m
1182 +
1183 +#
1184 +# Bridge: Netfilter Configuration
1185 +#
1186 +# CONFIG_BRIDGE_NF_EBTABLES is not set
1187 # CONFIG_IP_DCCP is not set
1188 # CONFIG_IP_SCTP is not set
1189 # CONFIG_TIPC is not set
1190 # CONFIG_ATM is not set
1191 -# CONFIG_BRIDGE is not set
1192 +CONFIG_BRIDGE=m
1193 CONFIG_VLAN_8021Q=m
1194 # CONFIG_DECNET is not set
1195 +CONFIG_LLC=m
1196 # CONFIG_LLC2 is not set
1197 # CONFIG_IPX is not set
1198 # CONFIG_ATALK is not set
1199 @@ -373,10 +415,6 @@
1200 # CONFIG_LAPB is not set
1201 # CONFIG_ECONET is not set
1202 # CONFIG_WAN_ROUTER is not set
1203 -
1204 -#
1205 -# QoS and/or fair queueing
1206 -#
1207 # CONFIG_NET_SCHED is not set
1208 CONFIG_NET_CLS_ROUTE=y
1209
1210 @@ -384,6 +422,7 @@
1211 # Network testing
1212 #
1213 # CONFIG_NET_PKTGEN is not set
1214 +# CONFIG_NET_TCPPROBE is not set
1215 # CONFIG_HAMRADIO is not set
1216 # CONFIG_IRDA is not set
1217 # CONFIG_BT is not set
1218 @@ -397,6 +436,7 @@
1219 # CONFIG_MAC80211 is not set
1220 # CONFIG_IEEE80211 is not set
1221 # CONFIG_RFKILL is not set
1222 +# CONFIG_NET_9P is not set
1223
1224 #
1225 # Device Drivers
1226 @@ -405,16 +445,13 @@
1227 #
1228 # Generic Driver Options
1229 #
1230 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1231 CONFIG_STANDALONE=y
1232 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
1233 # CONFIG_FW_LOADER is not set
1234 # CONFIG_DEBUG_DRIVER is not set
1235 # CONFIG_DEBUG_DEVRES is not set
1236 # CONFIG_SYS_HYPERVISOR is not set
1237 -
1238 -#
1239 -# Connector - unified userspace <-> kernelspace linker
1240 -#
1241 # CONFIG_CONNECTOR is not set
1242 CONFIG_MTD=y
1243 # CONFIG_MTD_DEBUG is not set
1244 @@ -434,6 +471,7 @@
1245 # CONFIG_INFTL is not set
1246 # CONFIG_RFD_FTL is not set
1247 # CONFIG_SSFDC is not set
1248 +# CONFIG_MTD_OOPS is not set
1249
1250 #
1251 # RAM/ROM/Flash chip drivers
1252 @@ -493,20 +531,8 @@
1253 # UBI - Unsorted block images
1254 #
1255 # CONFIG_MTD_UBI is not set
1256 -
1257 -#
1258 -# Parallel port support
1259 -#
1260 # CONFIG_PARPORT is not set
1261 -
1262 -#
1263 -# Plug and Play support
1264 -#
1265 -# CONFIG_PNPACPI is not set
1266 -
1267 -#
1268 -# Block devices
1269 -#
1270 +CONFIG_BLK_DEV=y
1271 # CONFIG_BLK_DEV_COW_COMMON is not set
1272 CONFIG_BLK_DEV_LOOP=m
1273 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
1274 @@ -517,11 +543,13 @@
1275 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1276 # CONFIG_CDROM_PKTCDVD is not set
1277 # CONFIG_ATA_OVER_ETH is not set
1278 -
1279 -#
1280 -# Misc devices
1281 -#
1282 -# CONFIG_BLINK is not set
1283 +CONFIG_MISC_DEVICES=y
1284 +# CONFIG_ATMEL_PWM is not set
1285 +CONFIG_ATMEL_TCLIB=y
1286 +CONFIG_ATMEL_TCB_CLKSRC=y
1287 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
1288 +# CONFIG_EEPROM_93CX6 is not set
1289 +# CONFIG_ATMEL_SSC is not set
1290 # CONFIG_IDE is not set
1291
1292 #
1293 @@ -529,30 +557,42 @@
1294 #
1295 # CONFIG_RAID_ATTRS is not set
1296 # CONFIG_SCSI is not set
1297 +# CONFIG_SCSI_DMA is not set
1298 # CONFIG_SCSI_NETLINK is not set
1299 # CONFIG_ATA is not set
1300 -
1301 -#
1302 -# Multi-device support (RAID and LVM)
1303 -#
1304 # CONFIG_MD is not set
1305 -
1306 -#
1307 -# Network device support
1308 -#
1309 CONFIG_NETDEVICES=y
1310 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
1311 # CONFIG_DUMMY is not set
1312 # CONFIG_BONDING is not set
1313 +# CONFIG_MACVLAN is not set
1314 # CONFIG_EQUALIZER is not set
1315 CONFIG_TUN=m
1316 -# CONFIG_PHYLIB is not set
1317 +# CONFIG_VETH is not set
1318 +CONFIG_PHYLIB=y
1319
1320 #
1321 -# Ethernet (10 or 100Mbit)
1322 +# MII PHY device drivers
1323 #
1324 +# CONFIG_MARVELL_PHY is not set
1325 +# CONFIG_DAVICOM_PHY is not set
1326 +# CONFIG_QSEMI_PHY is not set
1327 +# CONFIG_LXT_PHY is not set
1328 +# CONFIG_CICADA_PHY is not set
1329 +# CONFIG_VITESSE_PHY is not set
1330 +# CONFIG_SMSC_PHY is not set
1331 +# CONFIG_BROADCOM_PHY is not set
1332 +# CONFIG_ICPLUS_PHY is not set
1333 +# CONFIG_FIXED_PHY is not set
1334 +# CONFIG_MDIO_BITBANG is not set
1335 CONFIG_NET_ETHERNET=y
1336 -CONFIG_MII=y
1337 +# CONFIG_MII is not set
1338 CONFIG_MACB=y
1339 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
1340 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
1341 +# CONFIG_IBM_NEW_EMAC_TAH is not set
1342 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1343 +# CONFIG_B44 is not set
1344 # CONFIG_NETDEV_1000 is not set
1345 # CONFIG_NETDEV_10000 is not set
1346
1347 @@ -571,21 +611,14 @@
1348 CONFIG_PPP_BSDCOMP=m
1349 CONFIG_PPP_MPPE=m
1350 CONFIG_PPPOE=m
1351 +# CONFIG_PPPOL2TP is not set
1352 # CONFIG_SLIP is not set
1353 CONFIG_SLHC=m
1354 # CONFIG_SHAPER is not set
1355 # CONFIG_NETCONSOLE is not set
1356 # CONFIG_NETPOLL is not set
1357 # CONFIG_NET_POLL_CONTROLLER is not set
1358 -
1359 -#
1360 -# ISDN subsystem
1361 -#
1362 # CONFIG_ISDN is not set
1363 -
1364 -#
1365 -# Telephony Support
1366 -#
1367 # CONFIG_PHONE is not set
1368
1369 #
1370 @@ -615,28 +648,57 @@
1371 #
1372 CONFIG_SERIAL_ATMEL=y
1373 CONFIG_SERIAL_ATMEL_CONSOLE=y
1374 +CONFIG_SERIAL_ATMEL_PDC=y
1375 # CONFIG_SERIAL_ATMEL_TTYAT is not set
1376 CONFIG_SERIAL_CORE=y
1377 CONFIG_SERIAL_CORE_CONSOLE=y
1378 CONFIG_UNIX98_PTYS=y
1379 # CONFIG_LEGACY_PTYS is not set
1380 -
1381 -#
1382 -# IPMI
1383 -#
1384 # CONFIG_IPMI_HANDLER is not set
1385 -# CONFIG_WATCHDOG is not set
1386 # CONFIG_HW_RANDOM is not set
1387 # CONFIG_RTC is not set
1388 # CONFIG_GEN_RTC is not set
1389 # CONFIG_R3964 is not set
1390 # CONFIG_RAW_DRIVER is not set
1391 -
1392 -#
1393 -# TPM devices
1394 -#
1395 # CONFIG_TCG_TPM is not set
1396 -# CONFIG_I2C is not set
1397 +CONFIG_I2C=m
1398 +CONFIG_I2C_BOARDINFO=y
1399 +CONFIG_I2C_CHARDEV=m
1400 +
1401 +#
1402 +# I2C Algorithms
1403 +#
1404 +CONFIG_I2C_ALGOBIT=m
1405 +# CONFIG_I2C_ALGOPCF is not set
1406 +# CONFIG_I2C_ALGOPCA is not set
1407 +
1408 +#
1409 +# I2C Hardware Bus support
1410 +#
1411 +CONFIG_I2C_ATMELTWI=m
1412 +CONFIG_I2C_GPIO=m
1413 +# CONFIG_I2C_OCORES is not set
1414 +# CONFIG_I2C_PARPORT_LIGHT is not set
1415 +# CONFIG_I2C_SIMTEC is not set
1416 +# CONFIG_I2C_TAOS_EVM is not set
1417 +# CONFIG_I2C_STUB is not set
1418 +
1419 +#
1420 +# Miscellaneous I2C Chip support
1421 +#
1422 +# CONFIG_SENSORS_DS1337 is not set
1423 +# CONFIG_SENSORS_DS1374 is not set
1424 +# CONFIG_DS1682 is not set
1425 +# CONFIG_SENSORS_EEPROM is not set
1426 +# CONFIG_SENSORS_PCF8574 is not set
1427 +# CONFIG_SENSORS_PCA9539 is not set
1428 +# CONFIG_SENSORS_PCF8591 is not set
1429 +# CONFIG_SENSORS_MAX6875 is not set
1430 +# CONFIG_SENSORS_TSL2550 is not set
1431 +# CONFIG_I2C_DEBUG_CORE is not set
1432 +# CONFIG_I2C_DEBUG_ALGO is not set
1433 +# CONFIG_I2C_DEBUG_BUS is not set
1434 +# CONFIG_I2C_DEBUG_CHIP is not set
1435
1436 #
1437 # SPI support
1438 @@ -655,13 +717,25 @@
1439 # SPI Protocol Masters
1440 #
1441 # CONFIG_SPI_AT25 is not set
1442 -# CONFIG_SPI_SPIDEV is not set
1443 +CONFIG_SPI_SPIDEV=m
1444 +# CONFIG_SPI_TLE62X0 is not set
1445 +# CONFIG_W1 is not set
1446 +# CONFIG_POWER_SUPPLY is not set
1447 +# CONFIG_HWMON is not set
1448 +CONFIG_WATCHDOG=y
1449 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1450
1451 #
1452 -# Dallas's 1-wire bus
1453 +# Watchdog Device Drivers
1454 #
1455 -# CONFIG_W1 is not set
1456 -# CONFIG_HWMON is not set
1457 +# CONFIG_SOFT_WATCHDOG is not set
1458 +CONFIG_AT32AP700X_WDT=y
1459 +
1460 +#
1461 +# Sonics Silicon Backplane
1462 +#
1463 +CONFIG_SSB_POSSIBLE=y
1464 +# CONFIG_SSB is not set
1465
1466 #
1467 # Multifunction device drivers
1468 @@ -678,23 +752,21 @@
1469 #
1470 # Graphics support
1471 #
1472 +# CONFIG_VGASTATE is not set
1473 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1474 +# CONFIG_FB is not set
1475 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1476
1477 #
1478 # Display device support
1479 #
1480 # CONFIG_DISPLAY_SUPPORT is not set
1481 -# CONFIG_VGASTATE is not set
1482 -# CONFIG_FB is not set
1483
1484 #
1485 # Sound
1486 #
1487 # CONFIG_SOUND is not set
1488 -
1489 -#
1490 -# USB support
1491 -#
1492 +CONFIG_USB_SUPPORT=y
1493 # CONFIG_USB_ARCH_HAS_HCD is not set
1494 # CONFIG_USB_ARCH_HAS_OHCI is not set
1495 # CONFIG_USB_ARCH_HAS_EHCI is not set
1496 @@ -706,12 +778,48 @@
1497 #
1498 # USB Gadget Support
1499 #
1500 -# CONFIG_USB_GADGET is not set
1501 -# CONFIG_MMC is not set
1502 +CONFIG_USB_GADGET=y
1503 +# CONFIG_USB_GADGET_DEBUG is not set
1504 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1505 +CONFIG_USB_GADGET_SELECTED=y
1506 +# CONFIG_USB_GADGET_AMD5536UDC is not set
1507 +CONFIG_USB_GADGET_ATMEL_USBA=y
1508 +CONFIG_USB_ATMEL_USBA=y
1509 +# CONFIG_USB_GADGET_FSL_USB2 is not set
1510 +# CONFIG_USB_GADGET_NET2280 is not set
1511 +# CONFIG_USB_GADGET_PXA2XX is not set
1512 +# CONFIG_USB_GADGET_M66592 is not set
1513 +# CONFIG_USB_GADGET_GOKU is not set
1514 +# CONFIG_USB_GADGET_LH7A40X is not set
1515 +# CONFIG_USB_GADGET_OMAP is not set
1516 +# CONFIG_USB_GADGET_S3C2410 is not set
1517 +# CONFIG_USB_GADGET_AT91 is not set
1518 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1519 +CONFIG_USB_GADGET_DUALSPEED=y
1520 +CONFIG_USB_ZERO=m
1521 +CONFIG_USB_ETH=m
1522 +CONFIG_USB_ETH_RNDIS=y
1523 +CONFIG_USB_GADGETFS=m
1524 +CONFIG_USB_FILE_STORAGE=m
1525 +# CONFIG_USB_FILE_STORAGE_TEST is not set
1526 +CONFIG_USB_G_SERIAL=m
1527 +# CONFIG_USB_MIDI_GADGET is not set
1528 +CONFIG_MMC=y
1529 +# CONFIG_MMC_DEBUG is not set
1530 +# CONFIG_MMC_UNSAFE_RESUME is not set
1531 +
1532 +#
1533 +# MMC/SD Card Drivers
1534 +#
1535 +CONFIG_MMC_BLOCK=y
1536 +# CONFIG_MMC_BLOCK_BOUNCE is not set
1537 +# CONFIG_SDIO_UART is not set
1538
1539 #
1540 -# LED devices
1541 +# MMC/SD Host Controller Drivers
1542 #
1543 +CONFIG_MMC_ATMELMCI=y
1544 +CONFIG_MMC_SPI=m
1545 CONFIG_NEW_LEDS=y
1546 CONFIG_LEDS_CLASS=y
1547
1548 @@ -726,53 +834,71 @@
1549 CONFIG_LEDS_TRIGGERS=y
1550 CONFIG_LEDS_TRIGGER_TIMER=y
1551 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1552 -
1553 +CONFIG_RTC_LIB=y
1554 +CONFIG_RTC_CLASS=y
1555 +CONFIG_RTC_HCTOSYS=y
1556 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1557 +# CONFIG_RTC_DEBUG is not set
1558
1559 #
1560 -# LED drivers
1561 -#
1562 -
1563 -#
1564 -# LED Triggers
1565 -#
1566 -
1567 -#
1568 -# InfiniBand support
1569 +# RTC interfaces
1570 #
1571 +CONFIG_RTC_INTF_SYSFS=y
1572 +CONFIG_RTC_INTF_PROC=y
1573 +CONFIG_RTC_INTF_DEV=y
1574 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1575 +# CONFIG_RTC_DRV_TEST is not set
1576
1577 #
1578 -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1579 +# I2C RTC drivers
1580 #
1581 +# CONFIG_RTC_DRV_DS1307 is not set
1582 +# CONFIG_RTC_DRV_DS1374 is not set
1583 +# CONFIG_RTC_DRV_DS1672 is not set
1584 +# CONFIG_RTC_DRV_MAX6900 is not set
1585 +# CONFIG_RTC_DRV_RS5C372 is not set
1586 +# CONFIG_RTC_DRV_ISL1208 is not set
1587 +# CONFIG_RTC_DRV_X1205 is not set
1588 +# CONFIG_RTC_DRV_PCF8563 is not set
1589 +# CONFIG_RTC_DRV_PCF8583 is not set
1590 +# CONFIG_RTC_DRV_M41T80 is not set
1591
1592 #
1593 -# Real Time Clock
1594 +# SPI RTC drivers
1595 #
1596 -# CONFIG_RTC_CLASS is not set
1597 +# CONFIG_RTC_DRV_RS5C348 is not set
1598 +# CONFIG_RTC_DRV_MAX6902 is not set
1599
1600 #
1601 -# DMA Engine support
1602 +# Platform RTC drivers
1603 #
1604 -# CONFIG_DMA_ENGINE is not set
1605 +# CONFIG_RTC_DRV_DS1553 is not set
1606 +# CONFIG_RTC_DRV_STK17TA8 is not set
1607 +# CONFIG_RTC_DRV_DS1742 is not set
1608 +# CONFIG_RTC_DRV_M48T86 is not set
1609 +# CONFIG_RTC_DRV_M48T59 is not set
1610 +# CONFIG_RTC_DRV_V3020 is not set
1611
1612 #
1613 -# DMA Clients
1614 +# on-CPU RTC drivers
1615 #
1616 +CONFIG_RTC_DRV_AT32AP700X=y
1617
1618 #
1619 -# DMA Devices
1620 +# Userspace I/O
1621 #
1622 +# CONFIG_UIO is not set
1623
1624 #
1625 # File systems
1626 #
1627 -CONFIG_EXT2_FS=y
1628 +CONFIG_EXT2_FS=m
1629 # CONFIG_EXT2_FS_XATTR is not set
1630 # CONFIG_EXT2_FS_XIP is not set
1631 -CONFIG_EXT3_FS=y
1632 +CONFIG_EXT3_FS=m
1633 # CONFIG_EXT3_FS_XATTR is not set
1634 # CONFIG_EXT4DEV_FS is not set
1635 -CONFIG_JBD=y
1636 -# CONFIG_JBD_DEBUG is not set
1637 +CONFIG_JBD=m
1638 # CONFIG_REISERFS_FS is not set
1639 # CONFIG_JFS_FS is not set
1640 # CONFIG_FS_POSIX_ACL is not set
1641 @@ -781,7 +907,8 @@
1642 # CONFIG_OCFS2_FS is not set
1643 # CONFIG_MINIX_FS is not set
1644 # CONFIG_ROMFS_FS is not set
1645 -# CONFIG_INOTIFY is not set
1646 +CONFIG_INOTIFY=y
1647 +CONFIG_INOTIFY_USER=y
1648 # CONFIG_QUOTA is not set
1649 # CONFIG_DNOTIFY is not set
1650 # CONFIG_AUTOFS_FS is not set
1651 @@ -814,7 +941,6 @@
1652 CONFIG_TMPFS=y
1653 # CONFIG_TMPFS_POSIX_ACL is not set
1654 # CONFIG_HUGETLB_PAGE is not set
1655 -CONFIG_RAMFS=y
1656 CONFIG_CONFIGFS_FS=y
1657
1658 #
1659 @@ -830,10 +956,12 @@
1660 CONFIG_JFFS2_FS=y
1661 CONFIG_JFFS2_FS_DEBUG=0
1662 CONFIG_JFFS2_FS_WRITEBUFFER=y
1663 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1664 # CONFIG_JFFS2_SUMMARY is not set
1665 # CONFIG_JFFS2_FS_XATTR is not set
1666 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1667 CONFIG_JFFS2_ZLIB=y
1668 +# CONFIG_JFFS2_LZO is not set
1669 CONFIG_JFFS2_RTIME=y
1670 # CONFIG_JFFS2_RUBIN is not set
1671 # CONFIG_CRAMFS is not set
1672 @@ -842,19 +970,21 @@
1673 # CONFIG_QNX4FS_FS is not set
1674 # CONFIG_SYSV_FS is not set
1675 # CONFIG_UFS_FS is not set
1676 -
1677 -#
1678 -# Network File Systems
1679 -#
1680 +CONFIG_NETWORK_FILESYSTEMS=y
1681 CONFIG_NFS_FS=y
1682 CONFIG_NFS_V3=y
1683 # CONFIG_NFS_V3_ACL is not set
1684 # CONFIG_NFS_V4 is not set
1685 # CONFIG_NFS_DIRECTIO is not set
1686 -# CONFIG_NFSD is not set
1687 +CONFIG_NFSD=m
1688 +CONFIG_NFSD_V3=y
1689 +# CONFIG_NFSD_V3_ACL is not set
1690 +# CONFIG_NFSD_V4 is not set
1691 +CONFIG_NFSD_TCP=y
1692 CONFIG_ROOT_NFS=y
1693 CONFIG_LOCKD=y
1694 CONFIG_LOCKD_V4=y
1695 +CONFIG_EXPORTFS=m
1696 CONFIG_NFS_COMMON=y
1697 CONFIG_SUNRPC=y
1698 # CONFIG_SUNRPC_BIND34 is not set
1699 @@ -871,23 +1001,18 @@
1700 # CONFIG_NCP_FS is not set
1701 # CONFIG_CODA_FS is not set
1702 # CONFIG_AFS_FS is not set
1703 -# CONFIG_9P_FS is not set
1704
1705 #
1706 # Partition Types
1707 #
1708 # CONFIG_PARTITION_ADVANCED is not set
1709 CONFIG_MSDOS_PARTITION=y
1710 -
1711 -#
1712 -# Native Language Support
1713 -#
1714 -CONFIG_NLS=y
1715 +CONFIG_NLS=m
1716 CONFIG_NLS_DEFAULT="iso8859-1"
1717 -# CONFIG_NLS_CODEPAGE_437 is not set
1718 +CONFIG_NLS_CODEPAGE_437=m
1719 # CONFIG_NLS_CODEPAGE_737 is not set
1720 # CONFIG_NLS_CODEPAGE_775 is not set
1721 -CONFIG_NLS_CODEPAGE_850=y
1722 +CONFIG_NLS_CODEPAGE_850=m
1723 # CONFIG_NLS_CODEPAGE_852 is not set
1724 # CONFIG_NLS_CODEPAGE_855 is not set
1725 # CONFIG_NLS_CODEPAGE_857 is not set
1726 @@ -908,7 +1033,7 @@
1727 # CONFIG_NLS_CODEPAGE_1250 is not set
1728 # CONFIG_NLS_CODEPAGE_1251 is not set
1729 # CONFIG_NLS_ASCII is not set
1730 -CONFIG_NLS_ISO8859_1=y
1731 +CONFIG_NLS_ISO8859_1=m
1732 # CONFIG_NLS_ISO8859_2 is not set
1733 # CONFIG_NLS_ISO8859_3 is not set
1734 # CONFIG_NLS_ISO8859_4 is not set
1735 @@ -921,18 +1046,19 @@
1736 # CONFIG_NLS_ISO8859_15 is not set
1737 # CONFIG_NLS_KOI8_R is not set
1738 # CONFIG_NLS_KOI8_U is not set
1739 -CONFIG_NLS_UTF8=y
1740 -
1741 -#
1742 -# Distributed Lock Manager
1743 -#
1744 +CONFIG_NLS_UTF8=m
1745 # CONFIG_DLM is not set
1746 +CONFIG_INSTRUMENTATION=y
1747 +CONFIG_PROFILING=y
1748 +CONFIG_OPROFILE=m
1749 +CONFIG_KPROBES=y
1750 +# CONFIG_MARKERS is not set
1751
1752 #
1753 # Kernel hacking
1754 #
1755 -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1756 # CONFIG_PRINTK_TIME is not set
1757 +CONFIG_ENABLE_WARN_DEPRECATED=y
1758 CONFIG_ENABLE_MUST_CHECK=y
1759 CONFIG_MAGIC_SYSRQ=y
1760 # CONFIG_UNUSED_SYMBOLS is not set
1761 @@ -941,12 +1067,17 @@
1762 CONFIG_DEBUG_KERNEL=y
1763 # CONFIG_DEBUG_SHIRQ is not set
1764 CONFIG_DETECT_SOFTLOCKUP=y
1765 +CONFIG_SCHED_DEBUG=y
1766 # CONFIG_SCHEDSTATS is not set
1767 # CONFIG_TIMER_STATS is not set
1768 +# CONFIG_SLUB_DEBUG_ON is not set
1769 # CONFIG_DEBUG_RT_MUTEXES is not set
1770 # CONFIG_RT_MUTEX_TESTER is not set
1771 # CONFIG_DEBUG_SPINLOCK is not set
1772 # CONFIG_DEBUG_MUTEXES is not set
1773 +# CONFIG_DEBUG_LOCK_ALLOC is not set
1774 +# CONFIG_PROVE_LOCKING is not set
1775 +# CONFIG_LOCK_STAT is not set
1776 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1777 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1778 # CONFIG_DEBUG_KOBJECT is not set
1779 @@ -954,21 +1085,21 @@
1780 # CONFIG_DEBUG_INFO is not set
1781 # CONFIG_DEBUG_VM is not set
1782 # CONFIG_DEBUG_LIST is not set
1783 +# CONFIG_DEBUG_SG is not set
1784 CONFIG_FRAME_POINTER=y
1785 # CONFIG_FORCED_INLINING is not set
1786 +# CONFIG_BOOT_PRINTK_DELAY is not set
1787 # CONFIG_RCU_TORTURE_TEST is not set
1788 +# CONFIG_LKDTM is not set
1789 # CONFIG_FAULT_INJECTION is not set
1790 -# CONFIG_KPROBES is not set
1791 +# CONFIG_SAMPLES is not set
1792
1793 #
1794 # Security options
1795 #
1796 # CONFIG_KEYS is not set
1797 # CONFIG_SECURITY is not set
1798 -
1799 -#
1800 -# Cryptographic options
1801 -#
1802 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1803 CONFIG_CRYPTO=y
1804 CONFIG_CRYPTO_ALGAPI=y
1805 CONFIG_CRYPTO_BLKCIPHER=y
1806 @@ -989,6 +1120,7 @@
1807 CONFIG_CRYPTO_CBC=y
1808 CONFIG_CRYPTO_PCBC=m
1809 # CONFIG_CRYPTO_LRW is not set
1810 +# CONFIG_CRYPTO_XTS is not set
1811 # CONFIG_CRYPTO_CRYPTD is not set
1812 CONFIG_CRYPTO_DES=y
1813 # CONFIG_CRYPTO_FCRYPT is not set
1814 @@ -1002,15 +1134,14 @@
1815 CONFIG_CRYPTO_ARC4=m
1816 # CONFIG_CRYPTO_KHAZAD is not set
1817 # CONFIG_CRYPTO_ANUBIS is not set
1818 +# CONFIG_CRYPTO_SEED is not set
1819 CONFIG_CRYPTO_DEFLATE=y
1820 # CONFIG_CRYPTO_MICHAEL_MIC is not set
1821 # CONFIG_CRYPTO_CRC32C is not set
1822 # CONFIG_CRYPTO_CAMELLIA is not set
1823 # CONFIG_CRYPTO_TEST is not set
1824 -
1825 -#
1826 -# Hardware crypto devices
1827 -#
1828 +# CONFIG_CRYPTO_AUTHENC is not set
1829 +CONFIG_CRYPTO_HW=y
1830
1831 #
1832 # Library routines
1833 @@ -1018,8 +1149,9 @@
1834 CONFIG_BITREVERSE=y
1835 CONFIG_CRC_CCITT=m
1836 # CONFIG_CRC16 is not set
1837 -# CONFIG_CRC_ITU_T is not set
1838 +CONFIG_CRC_ITU_T=m
1839 CONFIG_CRC32=y
1840 +CONFIG_CRC7=m
1841 # CONFIG_LIBCRC32C is not set
1842 CONFIG_ZLIB_INFLATE=y
1843 CONFIG_ZLIB_DEFLATE=y
1844 --- a/arch/avr32/configs/atstk1002_defconfig
1845 +++ b/arch/avr32/configs/atstk1002_defconfig
1846 @@ -1,48 +1,49 @@
1847 #
1848 # Automatically generated make config: don't edit
1849 -# Linux kernel version: 2.6.22-rc5
1850 -# Sat Jun 23 15:32:08 2007
1851 +# Linux kernel version: 2.6.24
1852 +# Thu Mar 6 12:49:17 2008
1853 #
1854 CONFIG_AVR32=y
1855 CONFIG_GENERIC_GPIO=y
1856 CONFIG_GENERIC_HARDIRQS=y
1857 +CONFIG_STACKTRACE_SUPPORT=y
1858 +CONFIG_LOCKDEP_SUPPORT=y
1859 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1860 CONFIG_HARDIRQS_SW_RESEND=y
1861 CONFIG_GENERIC_IRQ_PROBE=y
1862 CONFIG_RWSEM_GENERIC_SPINLOCK=y
1863 CONFIG_GENERIC_TIME=y
1864 +CONFIG_GENERIC_CLOCKEVENTS=y
1865 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
1866 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
1867 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
1868 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
1869 CONFIG_GENERIC_HWEIGHT=y
1870 CONFIG_GENERIC_CALIBRATE_DELAY=y
1871 CONFIG_GENERIC_BUG=y
1872 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1873
1874 #
1875 -# Code maturity level options
1876 +# General setup
1877 #
1878 CONFIG_EXPERIMENTAL=y
1879 CONFIG_BROKEN_ON_SMP=y
1880 CONFIG_INIT_ENV_ARG_LIMIT=32
1881 -
1882 -#
1883 -# General setup
1884 -#
1885 CONFIG_LOCALVERSION=""
1886 # CONFIG_LOCALVERSION_AUTO is not set
1887 CONFIG_SWAP=y
1888 CONFIG_SYSVIPC=y
1889 -# CONFIG_IPC_NS is not set
1890 CONFIG_SYSVIPC_SYSCTL=y
1891 CONFIG_POSIX_MQUEUE=y
1892 -CONFIG_BSD_PROCESS_ACCT=y
1893 -CONFIG_BSD_PROCESS_ACCT_V3=y
1894 -CONFIG_TASKSTATS=y
1895 -CONFIG_TASK_DELAY_ACCT=y
1896 -# CONFIG_TASK_XACCT is not set
1897 -# CONFIG_UTS_NS is not set
1898 -CONFIG_AUDIT=y
1899 +# CONFIG_BSD_PROCESS_ACCT is not set
1900 +# CONFIG_TASKSTATS is not set
1901 +# CONFIG_USER_NS is not set
1902 +# CONFIG_PID_NS is not set
1903 +# CONFIG_AUDIT is not set
1904 # CONFIG_IKCONFIG is not set
1905 CONFIG_LOG_BUF_SHIFT=14
1906 +# CONFIG_CGROUPS is not set
1907 +# CONFIG_FAIR_GROUP_SCHED is not set
1908 CONFIG_SYSFS_DEPRECATED=y
1909 CONFIG_RELAY=y
1910 CONFIG_BLK_DEV_INITRD=y
1911 @@ -63,35 +64,28 @@
1912 CONFIG_ANON_INODES=y
1913 CONFIG_EPOLL=y
1914 CONFIG_SIGNALFD=y
1915 -CONFIG_TIMERFD=y
1916 CONFIG_EVENTFD=y
1917 CONFIG_SHMEM=y
1918 CONFIG_VM_EVENT_COUNTERS=y
1919 -# CONFIG_SLUB_DEBUG is not set
1920 +CONFIG_SLUB_DEBUG=y
1921 # CONFIG_SLAB is not set
1922 CONFIG_SLUB=y
1923 # CONFIG_SLOB is not set
1924 +CONFIG_SLABINFO=y
1925 CONFIG_RT_MUTEXES=y
1926 # CONFIG_TINY_SHMEM is not set
1927 CONFIG_BASE_SMALL=1
1928 -
1929 -#
1930 -# Loadable module support
1931 -#
1932 CONFIG_MODULES=y
1933 CONFIG_MODULE_UNLOAD=y
1934 # CONFIG_MODULE_FORCE_UNLOAD is not set
1935 # CONFIG_MODVERSIONS is not set
1936 # CONFIG_MODULE_SRCVERSION_ALL is not set
1937 # CONFIG_KMOD is not set
1938 -
1939 -#
1940 -# Block layer
1941 -#
1942 CONFIG_BLOCK=y
1943 # CONFIG_LBD is not set
1944 # CONFIG_BLK_DEV_IO_TRACE is not set
1945 # CONFIG_LSF is not set
1946 +# CONFIG_BLK_DEV_BSG is not set
1947
1948 #
1949 # IO Schedulers
1950 @@ -99,32 +93,49 @@
1951 CONFIG_IOSCHED_NOOP=y
1952 # CONFIG_IOSCHED_AS is not set
1953 # CONFIG_IOSCHED_DEADLINE is not set
1954 -# CONFIG_IOSCHED_CFQ is not set
1955 +CONFIG_IOSCHED_CFQ=y
1956 # CONFIG_DEFAULT_AS is not set
1957 # CONFIG_DEFAULT_DEADLINE is not set
1958 -# CONFIG_DEFAULT_CFQ is not set
1959 -CONFIG_DEFAULT_NOOP=y
1960 -CONFIG_DEFAULT_IOSCHED="noop"
1961 +CONFIG_DEFAULT_CFQ=y
1962 +# CONFIG_DEFAULT_NOOP is not set
1963 +CONFIG_DEFAULT_IOSCHED="cfq"
1964
1965 #
1966 # System Type and features
1967 #
1968 +CONFIG_TICK_ONESHOT=y
1969 +CONFIG_NO_HZ=y
1970 +CONFIG_HIGH_RES_TIMERS=y
1971 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
1972 CONFIG_SUBARCH_AVR32B=y
1973 CONFIG_MMU=y
1974 CONFIG_PERFORMANCE_COUNTERS=y
1975 CONFIG_PLATFORM_AT32AP=y
1976 +CONFIG_CPU_AT32AP700X=y
1977 CONFIG_CPU_AT32AP7000=y
1978 -CONFIG_BOARD_ATSTK1002=y
1979 CONFIG_BOARD_ATSTK1000=y
1980 # CONFIG_BOARD_ATNGW100 is not set
1981 +CONFIG_BOARD_ATSTK1002=y
1982 +# CONFIG_BOARD_ATSTK1003 is not set
1983 +# CONFIG_BOARD_ATSTK1004 is not set
1984 +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
1985 +# CONFIG_BOARD_ATSTK100X_SPI1 is not set
1986 +# CONFIG_BOARD_ATSTK1000_J2_LED is not set
1987 +# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
1988 +# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
1989 +CONFIG_BOARD_ATSTK1000_EXTDAC=y
1990 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
1991 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
1992 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
1993 CONFIG_LOADER_U_BOOT=y
1994
1995 #
1996 # Atmel AVR32 AP options
1997 #
1998 -# CONFIG_AP7000_32_BIT_SMC is not set
1999 -CONFIG_AP7000_16_BIT_SMC=y
2000 -# CONFIG_AP7000_8_BIT_SMC is not set
2001 +# CONFIG_AP700X_32_BIT_SMC is not set
2002 +CONFIG_AP700X_16_BIT_SMC=y
2003 +# CONFIG_AP700X_8_BIT_SMC is not set
2004 +CONFIG_GPIO_DEV=y
2005 CONFIG_LOAD_ADDRESS=0x10000000
2006 CONFIG_ENTRY_ADDRESS=0x90000000
2007 CONFIG_PHYS_OFFSET=0x10000000
2008 @@ -144,10 +155,14 @@
2009 CONFIG_FLATMEM=y
2010 CONFIG_FLAT_NODE_MEM_MAP=y
2011 # CONFIG_SPARSEMEM_STATIC is not set
2012 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
2013 CONFIG_SPLIT_PTLOCK_CPUS=4
2014 # CONFIG_RESOURCES_64BIT is not set
2015 CONFIG_ZONE_DMA_FLAG=0
2016 +CONFIG_VIRT_TO_BUS=y
2017 # CONFIG_OWNERSHIP_TRACE is not set
2018 +CONFIG_NMI_DEBUGGING=y
2019 +CONFIG_DW_DMAC=y
2020 # CONFIG_HZ_100 is not set
2021 CONFIG_HZ_250=y
2022 # CONFIG_HZ_300 is not set
2023 @@ -156,13 +171,31 @@
2024 CONFIG_CMDLINE=""
2025
2026 #
2027 -# Bus options
2028 +# Power management options
2029 #
2030 -# CONFIG_ARCH_SUPPORTS_MSI is not set
2031
2032 #
2033 -# PCCARD (PCMCIA/CardBus) support
2034 +# CPU Frequency scaling
2035 +#
2036 +CONFIG_CPU_FREQ=y
2037 +CONFIG_CPU_FREQ_TABLE=y
2038 +# CONFIG_CPU_FREQ_DEBUG is not set
2039 +# CONFIG_CPU_FREQ_STAT is not set
2040 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
2041 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
2042 +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
2043 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
2044 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2045 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
2046 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
2047 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2048 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
2049 +CONFIG_CPU_FREQ_AT32AP=y
2050 +
2051 +#
2052 +# Bus options
2053 #
2054 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2055 # CONFIG_PCCARD is not set
2056
2057 #
2058 @@ -182,7 +215,12 @@
2059 CONFIG_PACKET=y
2060 CONFIG_PACKET_MMAP=y
2061 CONFIG_UNIX=y
2062 -# CONFIG_NET_KEY is not set
2063 +CONFIG_XFRM=y
2064 +CONFIG_XFRM_USER=m
2065 +# CONFIG_XFRM_SUB_POLICY is not set
2066 +# CONFIG_XFRM_MIGRATE is not set
2067 +CONFIG_NET_KEY=m
2068 +# CONFIG_NET_KEY_MIGRATE is not set
2069 CONFIG_INET=y
2070 # CONFIG_IP_MULTICAST is not set
2071 # CONFIG_IP_ADVANCED_ROUTER is not set
2072 @@ -191,36 +229,52 @@
2073 CONFIG_IP_PNP_DHCP=y
2074 # CONFIG_IP_PNP_BOOTP is not set
2075 # CONFIG_IP_PNP_RARP is not set
2076 -# CONFIG_NET_IPIP is not set
2077 -# CONFIG_NET_IPGRE is not set
2078 +CONFIG_NET_IPIP=m
2079 +CONFIG_NET_IPGRE=m
2080 # CONFIG_ARPD is not set
2081 # CONFIG_SYN_COOKIES is not set
2082 -# CONFIG_INET_AH is not set
2083 -# CONFIG_INET_ESP is not set
2084 +CONFIG_INET_AH=m
2085 +CONFIG_INET_ESP=m
2086 # CONFIG_INET_IPCOMP is not set
2087 # CONFIG_INET_XFRM_TUNNEL is not set
2088 -# CONFIG_INET_TUNNEL is not set
2089 -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
2090 -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
2091 -# CONFIG_INET_XFRM_MODE_BEET is not set
2092 +CONFIG_INET_TUNNEL=m
2093 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
2094 +CONFIG_INET_XFRM_MODE_TUNNEL=m
2095 +CONFIG_INET_XFRM_MODE_BEET=m
2096 +# CONFIG_INET_LRO is not set
2097 CONFIG_INET_DIAG=y
2098 CONFIG_INET_TCP_DIAG=y
2099 # CONFIG_TCP_CONG_ADVANCED is not set
2100 CONFIG_TCP_CONG_CUBIC=y
2101 CONFIG_DEFAULT_TCP_CONG="cubic"
2102 # CONFIG_TCP_MD5SIG is not set
2103 -# CONFIG_IPV6 is not set
2104 -# CONFIG_INET6_XFRM_TUNNEL is not set
2105 -# CONFIG_INET6_TUNNEL is not set
2106 +CONFIG_IPV6=m
2107 +# CONFIG_IPV6_PRIVACY is not set
2108 +# CONFIG_IPV6_ROUTER_PREF is not set
2109 +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
2110 +CONFIG_INET6_AH=m
2111 +CONFIG_INET6_ESP=m
2112 +CONFIG_INET6_IPCOMP=m
2113 +# CONFIG_IPV6_MIP6 is not set
2114 +CONFIG_INET6_XFRM_TUNNEL=m
2115 +CONFIG_INET6_TUNNEL=m
2116 +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
2117 +CONFIG_INET6_XFRM_MODE_TUNNEL=m
2118 +CONFIG_INET6_XFRM_MODE_BEET=m
2119 +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
2120 +CONFIG_IPV6_SIT=m
2121 +CONFIG_IPV6_TUNNEL=m
2122 +# CONFIG_IPV6_MULTIPLE_TABLES is not set
2123 # CONFIG_NETWORK_SECMARK is not set
2124 # CONFIG_NETFILTER is not set
2125 # CONFIG_IP_DCCP is not set
2126 # CONFIG_IP_SCTP is not set
2127 # CONFIG_TIPC is not set
2128 # CONFIG_ATM is not set
2129 -# CONFIG_BRIDGE is not set
2130 +CONFIG_BRIDGE=m
2131 # CONFIG_VLAN_8021Q is not set
2132 # CONFIG_DECNET is not set
2133 +CONFIG_LLC=m
2134 # CONFIG_LLC2 is not set
2135 # CONFIG_IPX is not set
2136 # CONFIG_ATALK is not set
2137 @@ -228,16 +282,13 @@
2138 # CONFIG_LAPB is not set
2139 # CONFIG_ECONET is not set
2140 # CONFIG_WAN_ROUTER is not set
2141 -
2142 -#
2143 -# QoS and/or fair queueing
2144 -#
2145 # CONFIG_NET_SCHED is not set
2146
2147 #
2148 # Network testing
2149 #
2150 # CONFIG_NET_PKTGEN is not set
2151 +# CONFIG_NET_TCPPROBE is not set
2152 # CONFIG_HAMRADIO is not set
2153 # CONFIG_IRDA is not set
2154 # CONFIG_BT is not set
2155 @@ -251,6 +302,7 @@
2156 # CONFIG_MAC80211 is not set
2157 # CONFIG_IEEE80211 is not set
2158 # CONFIG_RFKILL is not set
2159 +# CONFIG_NET_9P is not set
2160
2161 #
2162 # Device Drivers
2163 @@ -259,16 +311,13 @@
2164 #
2165 # Generic Driver Options
2166 #
2167 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2168 CONFIG_STANDALONE=y
2169 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
2170 # CONFIG_FW_LOADER is not set
2171 # CONFIG_DEBUG_DRIVER is not set
2172 # CONFIG_DEBUG_DEVRES is not set
2173 # CONFIG_SYS_HYPERVISOR is not set
2174 -
2175 -#
2176 -# Connector - unified userspace <-> kernelspace linker
2177 -#
2178 # CONFIG_CONNECTOR is not set
2179 CONFIG_MTD=y
2180 # CONFIG_MTD_DEBUG is not set
2181 @@ -288,6 +337,7 @@
2182 # CONFIG_INFTL is not set
2183 # CONFIG_RFD_FTL is not set
2184 # CONFIG_SSFDC is not set
2185 +# CONFIG_MTD_OOPS is not set
2186
2187 #
2188 # RAM/ROM/Flash chip drivers
2189 @@ -327,6 +377,8 @@
2190 #
2191 # Self-contained MTD device drivers
2192 #
2193 +CONFIG_MTD_DATAFLASH=m
2194 +CONFIG_MTD_M25P80=m
2195 # CONFIG_MTD_SLRAM is not set
2196 # CONFIG_MTD_PHRAM is not set
2197 # CONFIG_MTD_MTDRAM is not set
2198 @@ -345,20 +397,8 @@
2199 # UBI - Unsorted block images
2200 #
2201 # CONFIG_MTD_UBI is not set
2202 -
2203 -#
2204 -# Parallel port support
2205 -#
2206 # CONFIG_PARPORT is not set
2207 -
2208 -#
2209 -# Plug and Play support
2210 -#
2211 -# CONFIG_PNPACPI is not set
2212 -
2213 -#
2214 -# Block devices
2215 -#
2216 +CONFIG_BLK_DEV=y
2217 # CONFIG_BLK_DEV_COW_COMMON is not set
2218 CONFIG_BLK_DEV_LOOP=m
2219 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
2220 @@ -369,42 +409,91 @@
2221 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
2222 # CONFIG_CDROM_PKTCDVD is not set
2223 # CONFIG_ATA_OVER_ETH is not set
2224 -
2225 -#
2226 -# Misc devices
2227 -#
2228 -# CONFIG_BLINK is not set
2229 +CONFIG_MISC_DEVICES=y
2230 +CONFIG_ATMEL_PWM=m
2231 +CONFIG_ATMEL_TCLIB=y
2232 +CONFIG_ATMEL_TCB_CLKSRC=y
2233 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
2234 +# CONFIG_EEPROM_93CX6 is not set
2235 +CONFIG_ATMEL_SSC=m
2236 # CONFIG_IDE is not set
2237
2238 #
2239 # SCSI device support
2240 #
2241 # CONFIG_RAID_ATTRS is not set
2242 -# CONFIG_SCSI is not set
2243 +CONFIG_SCSI=m
2244 +CONFIG_SCSI_DMA=y
2245 +# CONFIG_SCSI_TGT is not set
2246 # CONFIG_SCSI_NETLINK is not set
2247 -# CONFIG_ATA is not set
2248 +# CONFIG_SCSI_PROC_FS is not set
2249
2250 #
2251 -# Multi-device support (RAID and LVM)
2252 +# SCSI support type (disk, tape, CD-ROM)
2253 #
2254 -# CONFIG_MD is not set
2255 +CONFIG_BLK_DEV_SD=m
2256 +# CONFIG_CHR_DEV_ST is not set
2257 +# CONFIG_CHR_DEV_OSST is not set
2258 +CONFIG_BLK_DEV_SR=m
2259 +# CONFIG_BLK_DEV_SR_VENDOR is not set
2260 +# CONFIG_CHR_DEV_SG is not set
2261 +# CONFIG_CHR_DEV_SCH is not set
2262 +
2263 +#
2264 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
2265 +#
2266 +# CONFIG_SCSI_MULTI_LUN is not set
2267 +# CONFIG_SCSI_CONSTANTS is not set
2268 +# CONFIG_SCSI_LOGGING is not set
2269 +# CONFIG_SCSI_SCAN_ASYNC is not set
2270 +CONFIG_SCSI_WAIT_SCAN=m
2271
2272 #
2273 -# Network device support
2274 +# SCSI Transports
2275 #
2276 +# CONFIG_SCSI_SPI_ATTRS is not set
2277 +# CONFIG_SCSI_FC_ATTRS is not set
2278 +# CONFIG_SCSI_ISCSI_ATTRS is not set
2279 +# CONFIG_SCSI_SAS_LIBSAS is not set
2280 +# CONFIG_SCSI_SRP_ATTRS is not set
2281 +# CONFIG_SCSI_LOWLEVEL is not set
2282 +CONFIG_ATA=m
2283 +# CONFIG_ATA_NONSTANDARD is not set
2284 +CONFIG_PATA_AT32=m
2285 +# CONFIG_PATA_PLATFORM is not set
2286 +# CONFIG_MD is not set
2287 CONFIG_NETDEVICES=y
2288 -CONFIG_DUMMY=y
2289 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
2290 +# CONFIG_DUMMY is not set
2291 # CONFIG_BONDING is not set
2292 +# CONFIG_MACVLAN is not set
2293 # CONFIG_EQUALIZER is not set
2294 CONFIG_TUN=m
2295 -# CONFIG_PHYLIB is not set
2296 +# CONFIG_VETH is not set
2297 +CONFIG_PHYLIB=y
2298
2299 #
2300 -# Ethernet (10 or 100Mbit)
2301 +# MII PHY device drivers
2302 #
2303 +# CONFIG_MARVELL_PHY is not set
2304 +# CONFIG_DAVICOM_PHY is not set
2305 +# CONFIG_QSEMI_PHY is not set
2306 +# CONFIG_LXT_PHY is not set
2307 +# CONFIG_CICADA_PHY is not set
2308 +# CONFIG_VITESSE_PHY is not set
2309 +# CONFIG_SMSC_PHY is not set
2310 +# CONFIG_BROADCOM_PHY is not set
2311 +# CONFIG_ICPLUS_PHY is not set
2312 +# CONFIG_FIXED_PHY is not set
2313 +# CONFIG_MDIO_BITBANG is not set
2314 CONFIG_NET_ETHERNET=y
2315 -CONFIG_MII=y
2316 +# CONFIG_MII is not set
2317 CONFIG_MACB=y
2318 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
2319 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
2320 +# CONFIG_IBM_NEW_EMAC_TAH is not set
2321 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
2322 +# CONFIG_B44 is not set
2323 # CONFIG_NETDEV_1000 is not set
2324 # CONFIG_NETDEV_10000 is not set
2325
2326 @@ -423,27 +512,54 @@
2327 CONFIG_PPP_BSDCOMP=m
2328 # CONFIG_PPP_MPPE is not set
2329 # CONFIG_PPPOE is not set
2330 +# CONFIG_PPPOL2TP is not set
2331 # CONFIG_SLIP is not set
2332 CONFIG_SLHC=m
2333 # CONFIG_SHAPER is not set
2334 # CONFIG_NETCONSOLE is not set
2335 # CONFIG_NETPOLL is not set
2336 # CONFIG_NET_POLL_CONTROLLER is not set
2337 -
2338 -#
2339 -# ISDN subsystem
2340 -#
2341 # CONFIG_ISDN is not set
2342 -
2343 -#
2344 -# Telephony Support
2345 -#
2346 # CONFIG_PHONE is not set
2347
2348 #
2349 # Input device support
2350 #
2351 -# CONFIG_INPUT is not set
2352 +CONFIG_INPUT=m
2353 +# CONFIG_INPUT_FF_MEMLESS is not set
2354 +CONFIG_INPUT_POLLDEV=m
2355 +
2356 +#
2357 +# Userland interfaces
2358 +#
2359 +CONFIG_INPUT_MOUSEDEV=m
2360 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
2361 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2362 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2363 +# CONFIG_INPUT_JOYDEV is not set
2364 +CONFIG_INPUT_EVDEV=m
2365 +# CONFIG_INPUT_EVBUG is not set
2366 +
2367 +#
2368 +# Input Device Drivers
2369 +#
2370 +CONFIG_INPUT_KEYBOARD=y
2371 +# CONFIG_KEYBOARD_ATKBD is not set
2372 +# CONFIG_KEYBOARD_SUNKBD is not set
2373 +# CONFIG_KEYBOARD_LKKBD is not set
2374 +# CONFIG_KEYBOARD_XTKBD is not set
2375 +# CONFIG_KEYBOARD_NEWTON is not set
2376 +# CONFIG_KEYBOARD_STOWAWAY is not set
2377 +CONFIG_KEYBOARD_GPIO=m
2378 +CONFIG_INPUT_MOUSE=y
2379 +# CONFIG_MOUSE_PS2 is not set
2380 +# CONFIG_MOUSE_SERIAL is not set
2381 +# CONFIG_MOUSE_VSXXXAA is not set
2382 +CONFIG_MOUSE_GPIO=m
2383 +# CONFIG_INPUT_JOYSTICK is not set
2384 +# CONFIG_INPUT_TABLET is not set
2385 +# CONFIG_INPUT_TOUCHSCREEN is not set
2386 +# CONFIG_INPUT_MISC is not set
2387
2388 #
2389 # Hardware I/O ports
2390 @@ -467,40 +583,94 @@
2391 #
2392 CONFIG_SERIAL_ATMEL=y
2393 CONFIG_SERIAL_ATMEL_CONSOLE=y
2394 +CONFIG_SERIAL_ATMEL_PDC=y
2395 # CONFIG_SERIAL_ATMEL_TTYAT is not set
2396 CONFIG_SERIAL_CORE=y
2397 CONFIG_SERIAL_CORE_CONSOLE=y
2398 CONFIG_UNIX98_PTYS=y
2399 # CONFIG_LEGACY_PTYS is not set
2400 -
2401 -#
2402 -# IPMI
2403 -#
2404 # CONFIG_IPMI_HANDLER is not set
2405 -# CONFIG_WATCHDOG is not set
2406 # CONFIG_HW_RANDOM is not set
2407 # CONFIG_RTC is not set
2408 # CONFIG_GEN_RTC is not set
2409 # CONFIG_R3964 is not set
2410 # CONFIG_RAW_DRIVER is not set
2411 +# CONFIG_TCG_TPM is not set
2412 +CONFIG_I2C=m
2413 +CONFIG_I2C_BOARDINFO=y
2414 +CONFIG_I2C_CHARDEV=m
2415 +
2416 +#
2417 +# I2C Algorithms
2418 +#
2419 +CONFIG_I2C_ALGOBIT=m
2420 +# CONFIG_I2C_ALGOPCF is not set
2421 +# CONFIG_I2C_ALGOPCA is not set
2422 +
2423 +#
2424 +# I2C Hardware Bus support
2425 +#
2426 +CONFIG_I2C_ATMELTWI=m
2427 +CONFIG_I2C_GPIO=m
2428 +# CONFIG_I2C_OCORES is not set
2429 +# CONFIG_I2C_PARPORT_LIGHT is not set
2430 +# CONFIG_I2C_SIMTEC is not set
2431 +# CONFIG_I2C_TAOS_EVM is not set
2432 +# CONFIG_I2C_STUB is not set
2433 +
2434 +#
2435 +# Miscellaneous I2C Chip support
2436 +#
2437 +# CONFIG_SENSORS_DS1337 is not set
2438 +# CONFIG_SENSORS_DS1374 is not set
2439 +# CONFIG_DS1682 is not set
2440 +# CONFIG_SENSORS_EEPROM is not set
2441 +# CONFIG_SENSORS_PCF8574 is not set
2442 +# CONFIG_SENSORS_PCA9539 is not set
2443 +# CONFIG_SENSORS_PCF8591 is not set
2444 +# CONFIG_SENSORS_MAX6875 is not set
2445 +# CONFIG_SENSORS_TSL2550 is not set
2446 +# CONFIG_I2C_DEBUG_CORE is not set
2447 +# CONFIG_I2C_DEBUG_ALGO is not set
2448 +# CONFIG_I2C_DEBUG_BUS is not set
2449 +# CONFIG_I2C_DEBUG_CHIP is not set
2450
2451 #
2452 -# TPM devices
2453 +# SPI support
2454 #
2455 -# CONFIG_TCG_TPM is not set
2456 -# CONFIG_I2C is not set
2457 +CONFIG_SPI=y
2458 +# CONFIG_SPI_DEBUG is not set
2459 +CONFIG_SPI_MASTER=y
2460
2461 #
2462 -# SPI support
2463 +# SPI Master Controller Drivers
2464 #
2465 -# CONFIG_SPI is not set
2466 -# CONFIG_SPI_MASTER is not set
2467 +CONFIG_SPI_ATMEL=y
2468 +# CONFIG_SPI_BITBANG is not set
2469
2470 #
2471 -# Dallas's 1-wire bus
2472 +# SPI Protocol Masters
2473 #
2474 +# CONFIG_SPI_AT25 is not set
2475 +CONFIG_SPI_SPIDEV=m
2476 +# CONFIG_SPI_TLE62X0 is not set
2477 # CONFIG_W1 is not set
2478 +# CONFIG_POWER_SUPPLY is not set
2479 # CONFIG_HWMON is not set
2480 +CONFIG_WATCHDOG=y
2481 +# CONFIG_WATCHDOG_NOWAYOUT is not set
2482 +
2483 +#
2484 +# Watchdog Device Drivers
2485 +#
2486 +# CONFIG_SOFT_WATCHDOG is not set
2487 +CONFIG_AT32AP700X_WDT=y
2488 +
2489 +#
2490 +# Sonics Silicon Backplane
2491 +#
2492 +CONFIG_SSB_POSSIBLE=y
2493 +# CONFIG_SSB is not set
2494
2495 #
2496 # Multifunction device drivers
2497 @@ -517,23 +687,104 @@
2498 #
2499 # Graphics support
2500 #
2501 -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
2502 +# CONFIG_VGASTATE is not set
2503 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
2504 +CONFIG_FB=y
2505 +# CONFIG_FIRMWARE_EDID is not set
2506 +# CONFIG_FB_DDC is not set
2507 +CONFIG_FB_CFB_FILLRECT=y
2508 +CONFIG_FB_CFB_COPYAREA=y
2509 +CONFIG_FB_CFB_IMAGEBLIT=y
2510 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
2511 +# CONFIG_FB_SYS_FILLRECT is not set
2512 +# CONFIG_FB_SYS_COPYAREA is not set
2513 +# CONFIG_FB_SYS_IMAGEBLIT is not set
2514 +# CONFIG_FB_SYS_FOPS is not set
2515 +CONFIG_FB_DEFERRED_IO=y
2516 +# CONFIG_FB_SVGALIB is not set
2517 +# CONFIG_FB_MACMODES is not set
2518 +# CONFIG_FB_BACKLIGHT is not set
2519 +# CONFIG_FB_MODE_HELPERS is not set
2520 +# CONFIG_FB_TILEBLITTING is not set
2521 +
2522 +#
2523 +# Frame buffer hardware drivers
2524 +#
2525 +# CONFIG_FB_S1D13XXX is not set
2526 +CONFIG_FB_ATMEL=y
2527 +# CONFIG_FB_VIRTUAL is not set
2528 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
2529 +CONFIG_LCD_CLASS_DEVICE=y
2530 +CONFIG_LCD_LTV350QV=y
2531 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
2532
2533 #
2534 # Display device support
2535 #
2536 # CONFIG_DISPLAY_SUPPORT is not set
2537 -# CONFIG_VGASTATE is not set
2538 -# CONFIG_FB is not set
2539 +# CONFIG_LOGO is not set
2540
2541 #
2542 # Sound
2543 #
2544 -# CONFIG_SOUND is not set
2545 +CONFIG_SOUND=m
2546 +
2547 +#
2548 +# Advanced Linux Sound Architecture
2549 +#
2550 +CONFIG_SND=m
2551 +CONFIG_SND_TIMER=m
2552 +CONFIG_SND_PCM=m
2553 +# CONFIG_SND_SEQUENCER is not set
2554 +CONFIG_SND_OSSEMUL=y
2555 +CONFIG_SND_MIXER_OSS=m
2556 +CONFIG_SND_PCM_OSS=m
2557 +CONFIG_SND_PCM_OSS_PLUGINS=y
2558 +# CONFIG_SND_DYNAMIC_MINORS is not set
2559 +# CONFIG_SND_SUPPORT_OLD_API is not set
2560 +# CONFIG_SND_VERBOSE_PROCFS is not set
2561 +# CONFIG_SND_VERBOSE_PRINTK is not set
2562 +# CONFIG_SND_DEBUG is not set
2563 +
2564 +#
2565 +# Generic devices
2566 +#
2567 +CONFIG_SND_AC97_CODEC=m
2568 +# CONFIG_SND_DUMMY is not set
2569 +# CONFIG_SND_MTPAV is not set
2570 +# CONFIG_SND_SERIAL_U16550 is not set
2571 +# CONFIG_SND_MPU401 is not set
2572 +
2573 +#
2574 +# AVR32 devices
2575 +#
2576 +CONFIG_SND_ATMEL_AC97=m
2577
2578 #
2579 -# USB support
2580 +# SPI devices
2581 #
2582 +CONFIG_SND_AT73C213=m
2583 +CONFIG_SND_AT73C213_TARGET_BITRATE=48000
2584 +
2585 +#
2586 +# System on Chip audio support
2587 +#
2588 +# CONFIG_SND_SOC is not set
2589 +
2590 +#
2591 +# SoC Audio support for SuperH
2592 +#
2593 +
2594 +#
2595 +# Open Sound System
2596 +#
2597 +CONFIG_SOUND_PRIME=m
2598 +# CONFIG_SOUND_MSNDCLAS is not set
2599 +# CONFIG_SOUND_MSNDPIN is not set
2600 +CONFIG_SOUND_AT32_ABDAC=m
2601 +CONFIG_AC97_BUS=m
2602 +# CONFIG_HID_SUPPORT is not set
2603 +CONFIG_USB_SUPPORT=y
2604 # CONFIG_USB_ARCH_HAS_HCD is not set
2605 # CONFIG_USB_ARCH_HAS_OHCI is not set
2606 # CONFIG_USB_ARCH_HAS_EHCI is not set
2607 @@ -545,63 +796,137 @@
2608 #
2609 # USB Gadget Support
2610 #
2611 -# CONFIG_USB_GADGET is not set
2612 -# CONFIG_MMC is not set
2613 -
2614 -#
2615 -# LED devices
2616 -#
2617 -# CONFIG_NEW_LEDS is not set
2618 +CONFIG_USB_GADGET=y
2619 +# CONFIG_USB_GADGET_DEBUG is not set
2620 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
2621 +# CONFIG_USB_GADGET_DEBUG_FS is not set
2622 +CONFIG_USB_GADGET_SELECTED=y
2623 +# CONFIG_USB_GADGET_AMD5536UDC is not set
2624 +CONFIG_USB_GADGET_ATMEL_USBA=y
2625 +CONFIG_USB_ATMEL_USBA=y
2626 +# CONFIG_USB_GADGET_FSL_USB2 is not set
2627 +# CONFIG_USB_GADGET_NET2280 is not set
2628 +# CONFIG_USB_GADGET_PXA2XX is not set
2629 +# CONFIG_USB_GADGET_M66592 is not set
2630 +# CONFIG_USB_GADGET_GOKU is not set
2631 +# CONFIG_USB_GADGET_LH7A40X is not set
2632 +# CONFIG_USB_GADGET_OMAP is not set
2633 +# CONFIG_USB_GADGET_S3C2410 is not set
2634 +# CONFIG_USB_GADGET_AT91 is not set
2635 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
2636 +CONFIG_USB_GADGET_DUALSPEED=y
2637 +CONFIG_USB_ZERO=m
2638 +CONFIG_USB_ETH=m
2639 +CONFIG_USB_ETH_RNDIS=y
2640 +CONFIG_USB_GADGETFS=m
2641 +CONFIG_USB_FILE_STORAGE=m
2642 +# CONFIG_USB_FILE_STORAGE_TEST is not set
2643 +CONFIG_USB_G_SERIAL=m
2644 +# CONFIG_USB_MIDI_GADGET is not set
2645 +CONFIG_MMC=y
2646 +# CONFIG_MMC_DEBUG is not set
2647 +# CONFIG_MMC_UNSAFE_RESUME is not set
2648 +
2649 +#
2650 +# MMC/SD Card Drivers
2651 +#
2652 +CONFIG_MMC_BLOCK=y
2653 +# CONFIG_MMC_BLOCK_BOUNCE is not set
2654 +# CONFIG_SDIO_UART is not set
2655 +
2656 +#
2657 +# MMC/SD Host Controller Drivers
2658 +#
2659 +CONFIG_MMC_ATMELMCI=y
2660 +CONFIG_MMC_SPI=m
2661 +CONFIG_NEW_LEDS=y
2662 +CONFIG_LEDS_CLASS=m
2663
2664 #
2665 # LED drivers
2666 #
2667 +CONFIG_LEDS_ATMEL_PWM=m
2668 +CONFIG_LEDS_GPIO=m
2669
2670 #
2671 # LED Triggers
2672 #
2673 +CONFIG_LEDS_TRIGGERS=y
2674 +CONFIG_LEDS_TRIGGER_TIMER=m
2675 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
2676 +CONFIG_RTC_LIB=y
2677 +CONFIG_RTC_CLASS=y
2678 +CONFIG_RTC_HCTOSYS=y
2679 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2680 +# CONFIG_RTC_DEBUG is not set
2681
2682 #
2683 -# InfiniBand support
2684 +# RTC interfaces
2685 #
2686 +CONFIG_RTC_INTF_SYSFS=y
2687 +CONFIG_RTC_INTF_PROC=y
2688 +CONFIG_RTC_INTF_DEV=y
2689 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
2690 +# CONFIG_RTC_DRV_TEST is not set
2691
2692 #
2693 -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
2694 +# I2C RTC drivers
2695 #
2696 +# CONFIG_RTC_DRV_DS1307 is not set
2697 +# CONFIG_RTC_DRV_DS1374 is not set
2698 +# CONFIG_RTC_DRV_DS1672 is not set
2699 +# CONFIG_RTC_DRV_MAX6900 is not set
2700 +# CONFIG_RTC_DRV_RS5C372 is not set
2701 +# CONFIG_RTC_DRV_ISL1208 is not set
2702 +# CONFIG_RTC_DRV_X1205 is not set
2703 +# CONFIG_RTC_DRV_PCF8563 is not set
2704 +# CONFIG_RTC_DRV_PCF8583 is not set
2705 +# CONFIG_RTC_DRV_M41T80 is not set
2706
2707 #
2708 -# Real Time Clock
2709 +# SPI RTC drivers
2710 #
2711 -# CONFIG_RTC_CLASS is not set
2712 +# CONFIG_RTC_DRV_RS5C348 is not set
2713 +# CONFIG_RTC_DRV_MAX6902 is not set
2714
2715 #
2716 -# DMA Engine support
2717 +# Platform RTC drivers
2718 #
2719 -# CONFIG_DMA_ENGINE is not set
2720 +# CONFIG_RTC_DRV_DS1553 is not set
2721 +# CONFIG_RTC_DRV_STK17TA8 is not set
2722 +# CONFIG_RTC_DRV_DS1742 is not set
2723 +# CONFIG_RTC_DRV_M48T86 is not set
2724 +# CONFIG_RTC_DRV_M48T59 is not set
2725 +# CONFIG_RTC_DRV_V3020 is not set
2726
2727 #
2728 -# DMA Clients
2729 +# on-CPU RTC drivers
2730 #
2731 +CONFIG_RTC_DRV_AT32AP700X=y
2732
2733 #
2734 -# DMA Devices
2735 +# Userspace I/O
2736 #
2737 +# CONFIG_UIO is not set
2738
2739 #
2740 # File systems
2741 #
2742 -CONFIG_EXT2_FS=m
2743 +CONFIG_EXT2_FS=y
2744 # CONFIG_EXT2_FS_XATTR is not set
2745 # CONFIG_EXT2_FS_XIP is not set
2746 -# CONFIG_EXT3_FS is not set
2747 +CONFIG_EXT3_FS=y
2748 +# CONFIG_EXT3_FS_XATTR is not set
2749 # CONFIG_EXT4DEV_FS is not set
2750 +CONFIG_JBD=y
2751 +# CONFIG_JBD_DEBUG is not set
2752 # CONFIG_REISERFS_FS is not set
2753 # CONFIG_JFS_FS is not set
2754 # CONFIG_FS_POSIX_ACL is not set
2755 # CONFIG_XFS_FS is not set
2756 # CONFIG_GFS2_FS is not set
2757 # CONFIG_OCFS2_FS is not set
2758 -CONFIG_MINIX_FS=m
2759 +# CONFIG_MINIX_FS is not set
2760 # CONFIG_ROMFS_FS is not set
2761 CONFIG_INOTIFY=y
2762 CONFIG_INOTIFY_USER=y
2763 @@ -609,7 +934,7 @@
2764 # CONFIG_DNOTIFY is not set
2765 # CONFIG_AUTOFS_FS is not set
2766 # CONFIG_AUTOFS4_FS is not set
2767 -# CONFIG_FUSE_FS is not set
2768 +CONFIG_FUSE_FS=m
2769
2770 #
2771 # CD-ROM/DVD Filesystems
2772 @@ -637,8 +962,7 @@
2773 CONFIG_TMPFS=y
2774 # CONFIG_TMPFS_POSIX_ACL is not set
2775 # CONFIG_HUGETLB_PAGE is not set
2776 -CONFIG_RAMFS=y
2777 -CONFIG_CONFIGFS_FS=m
2778 +CONFIG_CONFIGFS_FS=y
2779
2780 #
2781 # Miscellaneous filesystems
2782 @@ -652,11 +976,12 @@
2783 # CONFIG_EFS_FS is not set
2784 CONFIG_JFFS2_FS=y
2785 CONFIG_JFFS2_FS_DEBUG=0
2786 -CONFIG_JFFS2_FS_WRITEBUFFER=y
2787 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set
2788 # CONFIG_JFFS2_SUMMARY is not set
2789 # CONFIG_JFFS2_FS_XATTR is not set
2790 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2791 CONFIG_JFFS2_ZLIB=y
2792 +# CONFIG_JFFS2_LZO is not set
2793 CONFIG_JFFS2_RTIME=y
2794 # CONFIG_JFFS2_RUBIN is not set
2795 # CONFIG_CRAMFS is not set
2796 @@ -665,10 +990,7 @@
2797 # CONFIG_QNX4FS_FS is not set
2798 # CONFIG_SYSV_FS is not set
2799 # CONFIG_UFS_FS is not set
2800 -
2801 -#
2802 -# Network File Systems
2803 -#
2804 +CONFIG_NETWORK_FILESYSTEMS=y
2805 CONFIG_NFS_FS=y
2806 CONFIG_NFS_V3=y
2807 # CONFIG_NFS_V3_ACL is not set
2808 @@ -688,17 +1010,12 @@
2809 # CONFIG_NCP_FS is not set
2810 # CONFIG_CODA_FS is not set
2811 # CONFIG_AFS_FS is not set
2812 -# CONFIG_9P_FS is not set
2813
2814 #
2815 # Partition Types
2816 #
2817 # CONFIG_PARTITION_ADVANCED is not set
2818 CONFIG_MSDOS_PARTITION=y
2819 -
2820 -#
2821 -# Native Language Support
2822 -#
2823 CONFIG_NLS=m
2824 CONFIG_NLS_DEFAULT="iso8859-1"
2825 CONFIG_NLS_CODEPAGE_437=m
2826 @@ -739,17 +1056,18 @@
2827 # CONFIG_NLS_KOI8_R is not set
2828 # CONFIG_NLS_KOI8_U is not set
2829 CONFIG_NLS_UTF8=m
2830 -
2831 -#
2832 -# Distributed Lock Manager
2833 -#
2834 # CONFIG_DLM is not set
2835 +CONFIG_INSTRUMENTATION=y
2836 +CONFIG_PROFILING=y
2837 +CONFIG_OPROFILE=m
2838 +CONFIG_KPROBES=y
2839 +# CONFIG_MARKERS is not set
2840
2841 #
2842 # Kernel hacking
2843 #
2844 -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2845 # CONFIG_PRINTK_TIME is not set
2846 +CONFIG_ENABLE_WARN_DEPRECATED=y
2847 CONFIG_ENABLE_MUST_CHECK=y
2848 CONFIG_MAGIC_SYSRQ=y
2849 # CONFIG_UNUSED_SYMBOLS is not set
2850 @@ -758,12 +1076,17 @@
2851 CONFIG_DEBUG_KERNEL=y
2852 # CONFIG_DEBUG_SHIRQ is not set
2853 CONFIG_DETECT_SOFTLOCKUP=y
2854 +CONFIG_SCHED_DEBUG=y
2855 # CONFIG_SCHEDSTATS is not set
2856 # CONFIG_TIMER_STATS is not set
2857 +# CONFIG_SLUB_DEBUG_ON is not set
2858 # CONFIG_DEBUG_RT_MUTEXES is not set
2859 # CONFIG_RT_MUTEX_TESTER is not set
2860 # CONFIG_DEBUG_SPINLOCK is not set
2861 # CONFIG_DEBUG_MUTEXES is not set
2862 +# CONFIG_DEBUG_LOCK_ALLOC is not set
2863 +# CONFIG_PROVE_LOCKING is not set
2864 +# CONFIG_LOCK_STAT is not set
2865 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
2866 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
2867 # CONFIG_DEBUG_KOBJECT is not set
2868 @@ -771,22 +1094,63 @@
2869 # CONFIG_DEBUG_INFO is not set
2870 # CONFIG_DEBUG_VM is not set
2871 # CONFIG_DEBUG_LIST is not set
2872 +# CONFIG_DEBUG_SG is not set
2873 CONFIG_FRAME_POINTER=y
2874 CONFIG_FORCED_INLINING=y
2875 +# CONFIG_BOOT_PRINTK_DELAY is not set
2876 # CONFIG_RCU_TORTURE_TEST is not set
2877 +# CONFIG_LKDTM is not set
2878 # CONFIG_FAULT_INJECTION is not set
2879 -# CONFIG_KPROBES is not set
2880 +# CONFIG_SAMPLES is not set
2881
2882 #
2883 # Security options
2884 #
2885 # CONFIG_KEYS is not set
2886 # CONFIG_SECURITY is not set
2887 -
2888 -#
2889 -# Cryptographic options
2890 -#
2891 -# CONFIG_CRYPTO is not set
2892 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2893 +CONFIG_CRYPTO=y
2894 +CONFIG_CRYPTO_ALGAPI=m
2895 +CONFIG_CRYPTO_BLKCIPHER=m
2896 +CONFIG_CRYPTO_HASH=m
2897 +CONFIG_CRYPTO_MANAGER=m
2898 +CONFIG_CRYPTO_HMAC=m
2899 +# CONFIG_CRYPTO_XCBC is not set
2900 +# CONFIG_CRYPTO_NULL is not set
2901 +# CONFIG_CRYPTO_MD4 is not set
2902 +CONFIG_CRYPTO_MD5=m
2903 +CONFIG_CRYPTO_SHA1=m
2904 +# CONFIG_CRYPTO_SHA256 is not set
2905 +# CONFIG_CRYPTO_SHA512 is not set
2906 +# CONFIG_CRYPTO_WP512 is not set
2907 +# CONFIG_CRYPTO_TGR192 is not set
2908 +# CONFIG_CRYPTO_GF128MUL is not set
2909 +# CONFIG_CRYPTO_ECB is not set
2910 +CONFIG_CRYPTO_CBC=m
2911 +# CONFIG_CRYPTO_PCBC is not set
2912 +# CONFIG_CRYPTO_LRW is not set
2913 +# CONFIG_CRYPTO_XTS is not set
2914 +# CONFIG_CRYPTO_CRYPTD is not set
2915 +CONFIG_CRYPTO_DES=m
2916 +# CONFIG_CRYPTO_FCRYPT is not set
2917 +# CONFIG_CRYPTO_BLOWFISH is not set
2918 +# CONFIG_CRYPTO_TWOFISH is not set
2919 +# CONFIG_CRYPTO_SERPENT is not set
2920 +# CONFIG_CRYPTO_AES is not set
2921 +# CONFIG_CRYPTO_CAST5 is not set
2922 +# CONFIG_CRYPTO_CAST6 is not set
2923 +# CONFIG_CRYPTO_TEA is not set
2924 +# CONFIG_CRYPTO_ARC4 is not set
2925 +# CONFIG_CRYPTO_KHAZAD is not set
2926 +# CONFIG_CRYPTO_ANUBIS is not set
2927 +# CONFIG_CRYPTO_SEED is not set
2928 +CONFIG_CRYPTO_DEFLATE=m
2929 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
2930 +# CONFIG_CRYPTO_CRC32C is not set
2931 +# CONFIG_CRYPTO_CAMELLIA is not set
2932 +# CONFIG_CRYPTO_TEST is not set
2933 +# CONFIG_CRYPTO_AUTHENC is not set
2934 +# CONFIG_CRYPTO_HW is not set
2935
2936 #
2937 # Library routines
2938 @@ -794,10 +1158,10 @@
2939 CONFIG_BITREVERSE=y
2940 CONFIG_CRC_CCITT=m
2941 # CONFIG_CRC16 is not set
2942 -# CONFIG_CRC_ITU_T is not set
2943 +CONFIG_CRC_ITU_T=m
2944 CONFIG_CRC32=y
2945 +CONFIG_CRC7=m
2946 # CONFIG_LIBCRC32C is not set
2947 -CONFIG_AUDIT_GENERIC=y
2948 CONFIG_ZLIB_INFLATE=y
2949 CONFIG_ZLIB_DEFLATE=y
2950 CONFIG_PLIST=y
2951 --- /dev/null
2952 +++ b/arch/avr32/configs/atstk1003_defconfig
2953 @@ -0,0 +1,1041 @@
2954 +#
2955 +# Automatically generated make config: don't edit
2956 +# Linux kernel version: 2.6.24
2957 +# Thu Mar 6 12:50:27 2008
2958 +#
2959 +CONFIG_AVR32=y
2960 +CONFIG_GENERIC_GPIO=y
2961 +CONFIG_GENERIC_HARDIRQS=y
2962 +CONFIG_STACKTRACE_SUPPORT=y
2963 +CONFIG_LOCKDEP_SUPPORT=y
2964 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
2965 +CONFIG_HARDIRQS_SW_RESEND=y
2966 +CONFIG_GENERIC_IRQ_PROBE=y
2967 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2968 +CONFIG_GENERIC_TIME=y
2969 +CONFIG_GENERIC_CLOCKEVENTS=y
2970 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
2971 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2972 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2973 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
2974 +CONFIG_GENERIC_HWEIGHT=y
2975 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2976 +CONFIG_GENERIC_BUG=y
2977 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2978 +
2979 +#
2980 +# General setup
2981 +#
2982 +CONFIG_EXPERIMENTAL=y
2983 +CONFIG_BROKEN_ON_SMP=y
2984 +CONFIG_INIT_ENV_ARG_LIMIT=32
2985 +CONFIG_LOCALVERSION=""
2986 +# CONFIG_LOCALVERSION_AUTO is not set
2987 +CONFIG_SWAP=y
2988 +CONFIG_SYSVIPC=y
2989 +CONFIG_SYSVIPC_SYSCTL=y
2990 +CONFIG_POSIX_MQUEUE=y
2991 +CONFIG_BSD_PROCESS_ACCT=y
2992 +CONFIG_BSD_PROCESS_ACCT_V3=y
2993 +CONFIG_TASKSTATS=y
2994 +CONFIG_TASK_DELAY_ACCT=y
2995 +# CONFIG_TASK_XACCT is not set
2996 +# CONFIG_USER_NS is not set
2997 +# CONFIG_PID_NS is not set
2998 +CONFIG_AUDIT=y
2999 +# CONFIG_IKCONFIG is not set
3000 +CONFIG_LOG_BUF_SHIFT=14
3001 +# CONFIG_CGROUPS is not set
3002 +CONFIG_FAIR_GROUP_SCHED=y
3003 +CONFIG_FAIR_USER_SCHED=y
3004 +# CONFIG_FAIR_CGROUP_SCHED is not set
3005 +CONFIG_SYSFS_DEPRECATED=y
3006 +CONFIG_RELAY=y
3007 +CONFIG_BLK_DEV_INITRD=y
3008 +CONFIG_INITRAMFS_SOURCE=""
3009 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
3010 +CONFIG_SYSCTL=y
3011 +CONFIG_EMBEDDED=y
3012 +# CONFIG_SYSCTL_SYSCALL is not set
3013 +CONFIG_KALLSYMS=y
3014 +# CONFIG_KALLSYMS_ALL is not set
3015 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
3016 +CONFIG_HOTPLUG=y
3017 +CONFIG_PRINTK=y
3018 +CONFIG_BUG=y
3019 +CONFIG_ELF_CORE=y
3020 +# CONFIG_BASE_FULL is not set
3021 +CONFIG_FUTEX=y
3022 +CONFIG_ANON_INODES=y
3023 +CONFIG_EPOLL=y
3024 +CONFIG_SIGNALFD=y
3025 +CONFIG_EVENTFD=y
3026 +CONFIG_SHMEM=y
3027 +CONFIG_VM_EVENT_COUNTERS=y
3028 +# CONFIG_SLUB_DEBUG is not set
3029 +# CONFIG_SLAB is not set
3030 +CONFIG_SLUB=y
3031 +# CONFIG_SLOB is not set
3032 +CONFIG_SLABINFO=y
3033 +CONFIG_RT_MUTEXES=y
3034 +# CONFIG_TINY_SHMEM is not set
3035 +CONFIG_BASE_SMALL=1
3036 +CONFIG_MODULES=y
3037 +CONFIG_MODULE_UNLOAD=y
3038 +# CONFIG_MODULE_FORCE_UNLOAD is not set
3039 +# CONFIG_MODVERSIONS is not set
3040 +# CONFIG_MODULE_SRCVERSION_ALL is not set
3041 +# CONFIG_KMOD is not set
3042 +CONFIG_BLOCK=y
3043 +# CONFIG_LBD is not set
3044 +# CONFIG_BLK_DEV_IO_TRACE is not set
3045 +# CONFIG_LSF is not set
3046 +# CONFIG_BLK_DEV_BSG is not set
3047 +
3048 +#
3049 +# IO Schedulers
3050 +#
3051 +CONFIG_IOSCHED_NOOP=y
3052 +# CONFIG_IOSCHED_AS is not set
3053 +# CONFIG_IOSCHED_DEADLINE is not set
3054 +CONFIG_IOSCHED_CFQ=y
3055 +# CONFIG_DEFAULT_AS is not set
3056 +# CONFIG_DEFAULT_DEADLINE is not set
3057 +CONFIG_DEFAULT_CFQ=y
3058 +# CONFIG_DEFAULT_NOOP is not set
3059 +CONFIG_DEFAULT_IOSCHED="cfq"
3060 +
3061 +#
3062 +# System Type and features
3063 +#
3064 +CONFIG_TICK_ONESHOT=y
3065 +CONFIG_NO_HZ=y
3066 +CONFIG_HIGH_RES_TIMERS=y
3067 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
3068 +CONFIG_SUBARCH_AVR32B=y
3069 +CONFIG_MMU=y
3070 +CONFIG_PERFORMANCE_COUNTERS=y
3071 +CONFIG_PLATFORM_AT32AP=y
3072 +CONFIG_CPU_AT32AP700X=y
3073 +CONFIG_CPU_AT32AP7001=y
3074 +CONFIG_BOARD_ATSTK1000=y
3075 +# CONFIG_BOARD_ATNGW100 is not set
3076 +# CONFIG_BOARD_ATSTK1002 is not set
3077 +CONFIG_BOARD_ATSTK1003=y
3078 +# CONFIG_BOARD_ATSTK1004 is not set
3079 +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
3080 +# CONFIG_BOARD_ATSTK100X_SPI1 is not set
3081 +# CONFIG_BOARD_ATSTK1000_J2_LED is not set
3082 +# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
3083 +# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
3084 +CONFIG_BOARD_ATSTK1000_EXTDAC=y
3085 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
3086 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
3087 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
3088 +CONFIG_LOADER_U_BOOT=y
3089 +
3090 +#
3091 +# Atmel AVR32 AP options
3092 +#
3093 +# CONFIG_AP700X_32_BIT_SMC is not set
3094 +CONFIG_AP700X_16_BIT_SMC=y
3095 +# CONFIG_AP700X_8_BIT_SMC is not set
3096 +CONFIG_GPIO_DEV=y
3097 +CONFIG_LOAD_ADDRESS=0x10000000
3098 +CONFIG_ENTRY_ADDRESS=0x90000000
3099 +CONFIG_PHYS_OFFSET=0x10000000
3100 +CONFIG_PREEMPT_NONE=y
3101 +# CONFIG_PREEMPT_VOLUNTARY is not set
3102 +# CONFIG_PREEMPT is not set
3103 +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
3104 +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
3105 +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
3106 +CONFIG_ARCH_FLATMEM_ENABLE=y
3107 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
3108 +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
3109 +CONFIG_SELECT_MEMORY_MODEL=y
3110 +CONFIG_FLATMEM_MANUAL=y
3111 +# CONFIG_DISCONTIGMEM_MANUAL is not set
3112 +# CONFIG_SPARSEMEM_MANUAL is not set
3113 +CONFIG_FLATMEM=y
3114 +CONFIG_FLAT_NODE_MEM_MAP=y
3115 +# CONFIG_SPARSEMEM_STATIC is not set
3116 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
3117 +CONFIG_SPLIT_PTLOCK_CPUS=4
3118 +# CONFIG_RESOURCES_64BIT is not set
3119 +CONFIG_ZONE_DMA_FLAG=0
3120 +CONFIG_VIRT_TO_BUS=y
3121 +# CONFIG_OWNERSHIP_TRACE is not set
3122 +CONFIG_NMI_DEBUGGING=y
3123 +CONFIG_DW_DMAC=y
3124 +# CONFIG_HZ_100 is not set
3125 +CONFIG_HZ_250=y
3126 +# CONFIG_HZ_300 is not set
3127 +# CONFIG_HZ_1000 is not set
3128 +CONFIG_HZ=250
3129 +CONFIG_CMDLINE=""
3130 +
3131 +#
3132 +# Power management options
3133 +#
3134 +
3135 +#
3136 +# CPU Frequency scaling
3137 +#
3138 +CONFIG_CPU_FREQ=y
3139 +CONFIG_CPU_FREQ_TABLE=y
3140 +# CONFIG_CPU_FREQ_DEBUG is not set
3141 +# CONFIG_CPU_FREQ_STAT is not set
3142 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
3143 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
3144 +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
3145 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
3146 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
3147 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
3148 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
3149 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
3150 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
3151 +CONFIG_CPU_FREQ_AT32AP=y
3152 +
3153 +#
3154 +# Bus options
3155 +#
3156 +# CONFIG_ARCH_SUPPORTS_MSI is not set
3157 +# CONFIG_PCCARD is not set
3158 +
3159 +#
3160 +# Executable file formats
3161 +#
3162 +CONFIG_BINFMT_ELF=y
3163 +# CONFIG_BINFMT_MISC is not set
3164 +
3165 +#
3166 +# Networking
3167 +#
3168 +CONFIG_NET=y
3169 +
3170 +#
3171 +# Networking options
3172 +#
3173 +CONFIG_PACKET=y
3174 +CONFIG_PACKET_MMAP=y
3175 +CONFIG_UNIX=y
3176 +# CONFIG_NET_KEY is not set
3177 +CONFIG_INET=y
3178 +# CONFIG_IP_MULTICAST is not set
3179 +# CONFIG_IP_ADVANCED_ROUTER is not set
3180 +CONFIG_IP_FIB_HASH=y
3181 +# CONFIG_IP_PNP is not set
3182 +# CONFIG_NET_IPIP is not set
3183 +# CONFIG_NET_IPGRE is not set
3184 +# CONFIG_ARPD is not set
3185 +# CONFIG_SYN_COOKIES is not set
3186 +# CONFIG_INET_AH is not set
3187 +# CONFIG_INET_ESP is not set
3188 +# CONFIG_INET_IPCOMP is not set
3189 +# CONFIG_INET_XFRM_TUNNEL is not set
3190 +# CONFIG_INET_TUNNEL is not set
3191 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
3192 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
3193 +# CONFIG_INET_XFRM_MODE_BEET is not set
3194 +# CONFIG_INET_LRO is not set
3195 +# CONFIG_INET_DIAG is not set
3196 +# CONFIG_TCP_CONG_ADVANCED is not set
3197 +CONFIG_TCP_CONG_CUBIC=y
3198 +CONFIG_DEFAULT_TCP_CONG="cubic"
3199 +# CONFIG_TCP_MD5SIG is not set
3200 +# CONFIG_IPV6 is not set
3201 +# CONFIG_INET6_XFRM_TUNNEL is not set
3202 +# CONFIG_INET6_TUNNEL is not set
3203 +# CONFIG_NETWORK_SECMARK is not set
3204 +# CONFIG_NETFILTER is not set
3205 +# CONFIG_IP_DCCP is not set
3206 +# CONFIG_IP_SCTP is not set
3207 +# CONFIG_TIPC is not set
3208 +# CONFIG_ATM is not set
3209 +# CONFIG_BRIDGE is not set
3210 +# CONFIG_VLAN_8021Q is not set
3211 +# CONFIG_DECNET is not set
3212 +# CONFIG_LLC2 is not set
3213 +# CONFIG_IPX is not set
3214 +# CONFIG_ATALK is not set
3215 +# CONFIG_X25 is not set
3216 +# CONFIG_LAPB is not set
3217 +# CONFIG_ECONET is not set
3218 +# CONFIG_WAN_ROUTER is not set
3219 +# CONFIG_NET_SCHED is not set
3220 +
3221 +#
3222 +# Network testing
3223 +#
3224 +# CONFIG_NET_PKTGEN is not set
3225 +# CONFIG_NET_TCPPROBE is not set
3226 +# CONFIG_HAMRADIO is not set
3227 +# CONFIG_IRDA is not set
3228 +# CONFIG_BT is not set
3229 +# CONFIG_AF_RXRPC is not set
3230 +
3231 +#
3232 +# Wireless
3233 +#
3234 +# CONFIG_CFG80211 is not set
3235 +# CONFIG_WIRELESS_EXT is not set
3236 +# CONFIG_MAC80211 is not set
3237 +# CONFIG_IEEE80211 is not set
3238 +# CONFIG_RFKILL is not set
3239 +# CONFIG_NET_9P is not set
3240 +
3241 +#
3242 +# Device Drivers
3243 +#
3244 +
3245 +#
3246 +# Generic Driver Options
3247 +#
3248 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
3249 +CONFIG_STANDALONE=y
3250 +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
3251 +# CONFIG_FW_LOADER is not set
3252 +# CONFIG_DEBUG_DRIVER is not set
3253 +# CONFIG_DEBUG_DEVRES is not set
3254 +# CONFIG_SYS_HYPERVISOR is not set
3255 +# CONFIG_CONNECTOR is not set
3256 +CONFIG_MTD=y
3257 +# CONFIG_MTD_DEBUG is not set
3258 +# CONFIG_MTD_CONCAT is not set
3259 +CONFIG_MTD_PARTITIONS=y
3260 +# CONFIG_MTD_REDBOOT_PARTS is not set
3261 +CONFIG_MTD_CMDLINE_PARTS=y
3262 +
3263 +#
3264 +# User Modules And Translation Layers
3265 +#
3266 +CONFIG_MTD_CHAR=y
3267 +CONFIG_MTD_BLKDEVS=y
3268 +CONFIG_MTD_BLOCK=y
3269 +# CONFIG_FTL is not set
3270 +# CONFIG_NFTL is not set
3271 +# CONFIG_INFTL is not set
3272 +# CONFIG_RFD_FTL is not set
3273 +# CONFIG_SSFDC is not set
3274 +# CONFIG_MTD_OOPS is not set
3275 +
3276 +#
3277 +# RAM/ROM/Flash chip drivers
3278 +#
3279 +CONFIG_MTD_CFI=y
3280 +# CONFIG_MTD_JEDECPROBE is not set
3281 +CONFIG_MTD_GEN_PROBE=y
3282 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
3283 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
3284 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
3285 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
3286 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
3287 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
3288 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
3289 +CONFIG_MTD_CFI_I1=y
3290 +CONFIG_MTD_CFI_I2=y
3291 +# CONFIG_MTD_CFI_I4 is not set
3292 +# CONFIG_MTD_CFI_I8 is not set
3293 +# CONFIG_MTD_CFI_INTELEXT is not set
3294 +CONFIG_MTD_CFI_AMDSTD=y
3295 +# CONFIG_MTD_CFI_STAA is not set
3296 +CONFIG_MTD_CFI_UTIL=y
3297 +# CONFIG_MTD_RAM is not set
3298 +# CONFIG_MTD_ROM is not set
3299 +# CONFIG_MTD_ABSENT is not set
3300 +
3301 +#
3302 +# Mapping drivers for chip access
3303 +#
3304 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
3305 +CONFIG_MTD_PHYSMAP=y
3306 +CONFIG_MTD_PHYSMAP_START=0x8000000
3307 +CONFIG_MTD_PHYSMAP_LEN=0x0
3308 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
3309 +# CONFIG_MTD_PLATRAM is not set
3310 +
3311 +#
3312 +# Self-contained MTD device drivers
3313 +#
3314 +CONFIG_MTD_DATAFLASH=m
3315 +CONFIG_MTD_M25P80=m
3316 +# CONFIG_MTD_SLRAM is not set
3317 +# CONFIG_MTD_PHRAM is not set
3318 +# CONFIG_MTD_MTDRAM is not set
3319 +# CONFIG_MTD_BLOCK2MTD is not set
3320 +
3321 +#
3322 +# Disk-On-Chip Device Drivers
3323 +#
3324 +# CONFIG_MTD_DOC2000 is not set
3325 +# CONFIG_MTD_DOC2001 is not set
3326 +# CONFIG_MTD_DOC2001PLUS is not set
3327 +# CONFIG_MTD_NAND is not set
3328 +# CONFIG_MTD_ONENAND is not set
3329 +
3330 +#
3331 +# UBI - Unsorted block images
3332 +#
3333 +# CONFIG_MTD_UBI is not set
3334 +# CONFIG_PARPORT is not set
3335 +CONFIG_BLK_DEV=y
3336 +# CONFIG_BLK_DEV_COW_COMMON is not set
3337 +CONFIG_BLK_DEV_LOOP=m
3338 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
3339 +CONFIG_BLK_DEV_NBD=m
3340 +CONFIG_BLK_DEV_RAM=m
3341 +CONFIG_BLK_DEV_RAM_COUNT=16
3342 +CONFIG_BLK_DEV_RAM_SIZE=4096
3343 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
3344 +# CONFIG_CDROM_PKTCDVD is not set
3345 +# CONFIG_ATA_OVER_ETH is not set
3346 +CONFIG_MISC_DEVICES=y
3347 +CONFIG_ATMEL_PWM=m
3348 +CONFIG_ATMEL_TCLIB=y
3349 +CONFIG_ATMEL_TCB_CLKSRC=y
3350 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
3351 +# CONFIG_EEPROM_93CX6 is not set
3352 +CONFIG_ATMEL_SSC=m
3353 +# CONFIG_IDE is not set
3354 +
3355 +#
3356 +# SCSI device support
3357 +#
3358 +# CONFIG_RAID_ATTRS is not set
3359 +CONFIG_SCSI=m
3360 +CONFIG_SCSI_DMA=y
3361 +# CONFIG_SCSI_TGT is not set
3362 +# CONFIG_SCSI_NETLINK is not set
3363 +# CONFIG_SCSI_PROC_FS is not set
3364 +
3365 +#
3366 +# SCSI support type (disk, tape, CD-ROM)
3367 +#
3368 +CONFIG_BLK_DEV_SD=m
3369 +# CONFIG_CHR_DEV_ST is not set
3370 +# CONFIG_CHR_DEV_OSST is not set
3371 +CONFIG_BLK_DEV_SR=m
3372 +# CONFIG_BLK_DEV_SR_VENDOR is not set
3373 +# CONFIG_CHR_DEV_SG is not set
3374 +# CONFIG_CHR_DEV_SCH is not set
3375 +
3376 +#
3377 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
3378 +#
3379 +# CONFIG_SCSI_MULTI_LUN is not set
3380 +# CONFIG_SCSI_CONSTANTS is not set
3381 +# CONFIG_SCSI_LOGGING is not set
3382 +# CONFIG_SCSI_SCAN_ASYNC is not set
3383 +CONFIG_SCSI_WAIT_SCAN=m
3384 +
3385 +#
3386 +# SCSI Transports
3387 +#
3388 +# CONFIG_SCSI_SPI_ATTRS is not set
3389 +# CONFIG_SCSI_FC_ATTRS is not set
3390 +# CONFIG_SCSI_ISCSI_ATTRS is not set
3391 +# CONFIG_SCSI_SAS_LIBSAS is not set
3392 +# CONFIG_SCSI_SRP_ATTRS is not set
3393 +CONFIG_SCSI_LOWLEVEL=y
3394 +# CONFIG_ISCSI_TCP is not set
3395 +# CONFIG_SCSI_DEBUG is not set
3396 +CONFIG_ATA=m
3397 +# CONFIG_ATA_NONSTANDARD is not set
3398 +CONFIG_PATA_AT32=m
3399 +# CONFIG_PATA_PLATFORM is not set
3400 +# CONFIG_MD is not set
3401 +CONFIG_NETDEVICES=y
3402 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
3403 +# CONFIG_DUMMY is not set
3404 +# CONFIG_BONDING is not set
3405 +# CONFIG_MACVLAN is not set
3406 +# CONFIG_EQUALIZER is not set
3407 +# CONFIG_TUN is not set
3408 +# CONFIG_VETH is not set
3409 +# CONFIG_NET_ETHERNET is not set
3410 +# CONFIG_NETDEV_1000 is not set
3411 +# CONFIG_NETDEV_10000 is not set
3412 +
3413 +#
3414 +# Wireless LAN
3415 +#
3416 +# CONFIG_WLAN_PRE80211 is not set
3417 +# CONFIG_WLAN_80211 is not set
3418 +# CONFIG_WAN is not set
3419 +CONFIG_PPP=m
3420 +# CONFIG_PPP_MULTILINK is not set
3421 +# CONFIG_PPP_FILTER is not set
3422 +CONFIG_PPP_ASYNC=m
3423 +# CONFIG_PPP_SYNC_TTY is not set
3424 +CONFIG_PPP_DEFLATE=m
3425 +CONFIG_PPP_BSDCOMP=m
3426 +# CONFIG_PPP_MPPE is not set
3427 +# CONFIG_PPPOE is not set
3428 +# CONFIG_PPPOL2TP is not set
3429 +# CONFIG_SLIP is not set
3430 +CONFIG_SLHC=m
3431 +# CONFIG_SHAPER is not set
3432 +# CONFIG_NETCONSOLE is not set
3433 +# CONFIG_NETPOLL is not set
3434 +# CONFIG_NET_POLL_CONTROLLER is not set
3435 +# CONFIG_ISDN is not set
3436 +# CONFIG_PHONE is not set
3437 +
3438 +#
3439 +# Input device support
3440 +#
3441 +CONFIG_INPUT=m
3442 +# CONFIG_INPUT_FF_MEMLESS is not set
3443 +CONFIG_INPUT_POLLDEV=m
3444 +
3445 +#
3446 +# Userland interfaces
3447 +#
3448 +CONFIG_INPUT_MOUSEDEV=m
3449 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
3450 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
3451 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
3452 +# CONFIG_INPUT_JOYDEV is not set
3453 +# CONFIG_INPUT_EVDEV is not set
3454 +# CONFIG_INPUT_EVBUG is not set
3455 +
3456 +#
3457 +# Input Device Drivers
3458 +#
3459 +CONFIG_INPUT_KEYBOARD=y
3460 +# CONFIG_KEYBOARD_ATKBD is not set
3461 +# CONFIG_KEYBOARD_SUNKBD is not set
3462 +# CONFIG_KEYBOARD_LKKBD is not set
3463 +# CONFIG_KEYBOARD_XTKBD is not set
3464 +# CONFIG_KEYBOARD_NEWTON is not set
3465 +# CONFIG_KEYBOARD_STOWAWAY is not set
3466 +CONFIG_KEYBOARD_GPIO=m
3467 +CONFIG_INPUT_MOUSE=y
3468 +# CONFIG_MOUSE_PS2 is not set
3469 +# CONFIG_MOUSE_SERIAL is not set
3470 +# CONFIG_MOUSE_VSXXXAA is not set
3471 +CONFIG_MOUSE_GPIO=m
3472 +# CONFIG_INPUT_JOYSTICK is not set
3473 +# CONFIG_INPUT_TABLET is not set
3474 +# CONFIG_INPUT_TOUCHSCREEN is not set
3475 +# CONFIG_INPUT_MISC is not set
3476 +
3477 +#
3478 +# Hardware I/O ports
3479 +#
3480 +# CONFIG_SERIO is not set
3481 +# CONFIG_GAMEPORT is not set
3482 +
3483 +#
3484 +# Character devices
3485 +#
3486 +# CONFIG_VT is not set
3487 +# CONFIG_SERIAL_NONSTANDARD is not set
3488 +
3489 +#
3490 +# Serial drivers
3491 +#
3492 +# CONFIG_SERIAL_8250 is not set
3493 +
3494 +#
3495 +# Non-8250 serial port support
3496 +#
3497 +CONFIG_SERIAL_ATMEL=y
3498 +CONFIG_SERIAL_ATMEL_CONSOLE=y
3499 +CONFIG_SERIAL_ATMEL_PDC=y
3500 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
3501 +CONFIG_SERIAL_CORE=y
3502 +CONFIG_SERIAL_CORE_CONSOLE=y
3503 +CONFIG_UNIX98_PTYS=y
3504 +# CONFIG_LEGACY_PTYS is not set
3505 +# CONFIG_IPMI_HANDLER is not set
3506 +# CONFIG_HW_RANDOM is not set
3507 +# CONFIG_RTC is not set
3508 +# CONFIG_GEN_RTC is not set
3509 +# CONFIG_R3964 is not set
3510 +# CONFIG_RAW_DRIVER is not set
3511 +# CONFIG_TCG_TPM is not set
3512 +CONFIG_I2C=m
3513 +CONFIG_I2C_BOARDINFO=y
3514 +CONFIG_I2C_CHARDEV=m
3515 +
3516 +#
3517 +# I2C Algorithms
3518 +#
3519 +CONFIG_I2C_ALGOBIT=m
3520 +# CONFIG_I2C_ALGOPCF is not set
3521 +# CONFIG_I2C_ALGOPCA is not set
3522 +
3523 +#
3524 +# I2C Hardware Bus support
3525 +#
3526 +CONFIG_I2C_ATMELTWI=m
3527 +CONFIG_I2C_GPIO=m
3528 +# CONFIG_I2C_OCORES is not set
3529 +# CONFIG_I2C_PARPORT_LIGHT is not set
3530 +# CONFIG_I2C_SIMTEC is not set
3531 +# CONFIG_I2C_TAOS_EVM is not set
3532 +# CONFIG_I2C_STUB is not set
3533 +
3534 +#
3535 +# Miscellaneous I2C Chip support
3536 +#
3537 +# CONFIG_SENSORS_DS1337 is not set
3538 +# CONFIG_SENSORS_DS1374 is not set
3539 +# CONFIG_DS1682 is not set
3540 +# CONFIG_SENSORS_EEPROM is not set
3541 +# CONFIG_SENSORS_PCF8574 is not set
3542 +# CONFIG_SENSORS_PCA9539 is not set
3543 +# CONFIG_SENSORS_PCF8591 is not set
3544 +# CONFIG_SENSORS_MAX6875 is not set
3545 +# CONFIG_SENSORS_TSL2550 is not set
3546 +# CONFIG_I2C_DEBUG_CORE is not set
3547 +# CONFIG_I2C_DEBUG_ALGO is not set
3548 +# CONFIG_I2C_DEBUG_BUS is not set
3549 +# CONFIG_I2C_DEBUG_CHIP is not set
3550 +
3551 +#
3552 +# SPI support
3553 +#
3554 +CONFIG_SPI=y
3555 +# CONFIG_SPI_DEBUG is not set
3556 +CONFIG_SPI_MASTER=y
3557 +
3558 +#
3559 +# SPI Master Controller Drivers
3560 +#
3561 +CONFIG_SPI_ATMEL=y
3562 +# CONFIG_SPI_BITBANG is not set
3563 +
3564 +#
3565 +# SPI Protocol Masters
3566 +#
3567 +# CONFIG_SPI_AT25 is not set
3568 +CONFIG_SPI_SPIDEV=m
3569 +# CONFIG_SPI_TLE62X0 is not set
3570 +# CONFIG_W1 is not set
3571 +# CONFIG_POWER_SUPPLY is not set
3572 +# CONFIG_HWMON is not set
3573 +CONFIG_WATCHDOG=y
3574 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3575 +
3576 +#
3577 +# Watchdog Device Drivers
3578 +#
3579 +# CONFIG_SOFT_WATCHDOG is not set
3580 +CONFIG_AT32AP700X_WDT=y
3581 +
3582 +#
3583 +# Sonics Silicon Backplane
3584 +#
3585 +CONFIG_SSB_POSSIBLE=y
3586 +# CONFIG_SSB is not set
3587 +
3588 +#
3589 +# Multifunction device drivers
3590 +#
3591 +# CONFIG_MFD_SM501 is not set
3592 +
3593 +#
3594 +# Multimedia devices
3595 +#
3596 +# CONFIG_VIDEO_DEV is not set
3597 +# CONFIG_DVB_CORE is not set
3598 +# CONFIG_DAB is not set
3599 +
3600 +#
3601 +# Graphics support
3602 +#
3603 +# CONFIG_VGASTATE is not set
3604 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
3605 +# CONFIG_FB is not set
3606 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
3607 +
3608 +#
3609 +# Display device support
3610 +#
3611 +# CONFIG_DISPLAY_SUPPORT is not set
3612 +
3613 +#
3614 +# Sound
3615 +#
3616 +CONFIG_SOUND=m
3617 +
3618 +#
3619 +# Advanced Linux Sound Architecture
3620 +#
3621 +CONFIG_SND=m
3622 +CONFIG_SND_TIMER=m
3623 +CONFIG_SND_PCM=m
3624 +# CONFIG_SND_SEQUENCER is not set
3625 +CONFIG_SND_OSSEMUL=y
3626 +CONFIG_SND_MIXER_OSS=m
3627 +CONFIG_SND_PCM_OSS=m
3628 +CONFIG_SND_PCM_OSS_PLUGINS=y
3629 +# CONFIG_SND_DYNAMIC_MINORS is not set
3630 +CONFIG_SND_SUPPORT_OLD_API=y
3631 +CONFIG_SND_VERBOSE_PROCFS=y
3632 +# CONFIG_SND_VERBOSE_PRINTK is not set
3633 +# CONFIG_SND_DEBUG is not set
3634 +
3635 +#
3636 +# Generic devices
3637 +#
3638 +CONFIG_SND_AC97_CODEC=m
3639 +# CONFIG_SND_DUMMY is not set
3640 +# CONFIG_SND_MTPAV is not set
3641 +# CONFIG_SND_SERIAL_U16550 is not set
3642 +# CONFIG_SND_MPU401 is not set
3643 +
3644 +#
3645 +# AVR32 devices
3646 +#
3647 +CONFIG_SND_ATMEL_AC97=m
3648 +
3649 +#
3650 +# SPI devices
3651 +#
3652 +CONFIG_SND_AT73C213=m
3653 +CONFIG_SND_AT73C213_TARGET_BITRATE=48000
3654 +
3655 +#
3656 +# System on Chip audio support
3657 +#
3658 +# CONFIG_SND_SOC is not set
3659 +
3660 +#
3661 +# SoC Audio support for SuperH
3662 +#
3663 +
3664 +#
3665 +# Open Sound System
3666 +#
3667 +# CONFIG_SOUND_PRIME is not set
3668 +CONFIG_AC97_BUS=m
3669 +# CONFIG_HID_SUPPORT is not set
3670 +CONFIG_USB_SUPPORT=y
3671 +# CONFIG_USB_ARCH_HAS_HCD is not set
3672 +# CONFIG_USB_ARCH_HAS_OHCI is not set
3673 +# CONFIG_USB_ARCH_HAS_EHCI is not set
3674 +
3675 +#
3676 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
3677 +#
3678 +
3679 +#
3680 +# USB Gadget Support
3681 +#
3682 +CONFIG_USB_GADGET=y
3683 +# CONFIG_USB_GADGET_DEBUG is not set
3684 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3685 +CONFIG_USB_GADGET_DEBUG_FS=y
3686 +CONFIG_USB_GADGET_SELECTED=y
3687 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3688 +CONFIG_USB_GADGET_ATMEL_USBA=y
3689 +CONFIG_USB_ATMEL_USBA=y
3690 +# CONFIG_USB_GADGET_FSL_USB2 is not set
3691 +# CONFIG_USB_GADGET_NET2280 is not set
3692 +# CONFIG_USB_GADGET_PXA2XX is not set
3693 +# CONFIG_USB_GADGET_M66592 is not set
3694 +# CONFIG_USB_GADGET_GOKU is not set
3695 +# CONFIG_USB_GADGET_LH7A40X is not set
3696 +# CONFIG_USB_GADGET_OMAP is not set
3697 +# CONFIG_USB_GADGET_S3C2410 is not set
3698 +# CONFIG_USB_GADGET_AT91 is not set
3699 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3700 +CONFIG_USB_GADGET_DUALSPEED=y
3701 +CONFIG_USB_ZERO=m
3702 +CONFIG_USB_ETH=m
3703 +CONFIG_USB_ETH_RNDIS=y
3704 +CONFIG_USB_GADGETFS=m
3705 +CONFIG_USB_FILE_STORAGE=m
3706 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3707 +CONFIG_USB_G_SERIAL=m
3708 +# CONFIG_USB_MIDI_GADGET is not set
3709 +CONFIG_MMC=y
3710 +# CONFIG_MMC_DEBUG is not set
3711 +# CONFIG_MMC_UNSAFE_RESUME is not set
3712 +
3713 +#
3714 +# MMC/SD Card Drivers
3715 +#
3716 +CONFIG_MMC_BLOCK=y
3717 +# CONFIG_MMC_BLOCK_BOUNCE is not set
3718 +# CONFIG_SDIO_UART is not set
3719 +
3720 +#
3721 +# MMC/SD Host Controller Drivers
3722 +#
3723 +CONFIG_MMC_ATMELMCI=y
3724 +CONFIG_MMC_SPI=m
3725 +CONFIG_NEW_LEDS=y
3726 +CONFIG_LEDS_CLASS=y
3727 +
3728 +#
3729 +# LED drivers
3730 +#
3731 +CONFIG_LEDS_ATMEL_PWM=m
3732 +CONFIG_LEDS_GPIO=y
3733 +
3734 +#
3735 +# LED Triggers
3736 +#
3737 +CONFIG_LEDS_TRIGGERS=y
3738 +CONFIG_LEDS_TRIGGER_TIMER=y
3739 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
3740 +CONFIG_RTC_LIB=y
3741 +CONFIG_RTC_CLASS=y
3742 +CONFIG_RTC_HCTOSYS=y
3743 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
3744 +# CONFIG_RTC_DEBUG is not set
3745 +
3746 +#
3747 +# RTC interfaces
3748 +#
3749 +CONFIG_RTC_INTF_SYSFS=y
3750 +CONFIG_RTC_INTF_PROC=y
3751 +CONFIG_RTC_INTF_DEV=y
3752 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
3753 +# CONFIG_RTC_DRV_TEST is not set
3754 +
3755 +#
3756 +# I2C RTC drivers
3757 +#
3758 +# CONFIG_RTC_DRV_DS1307 is not set
3759 +# CONFIG_RTC_DRV_DS1374 is not set
3760 +# CONFIG_RTC_DRV_DS1672 is not set
3761 +# CONFIG_RTC_DRV_MAX6900 is not set
3762 +# CONFIG_RTC_DRV_RS5C372 is not set
3763 +# CONFIG_RTC_DRV_ISL1208 is not set
3764 +# CONFIG_RTC_DRV_X1205 is not set
3765 +# CONFIG_RTC_DRV_PCF8563 is not set
3766 +# CONFIG_RTC_DRV_PCF8583 is not set
3767 +# CONFIG_RTC_DRV_M41T80 is not set
3768 +
3769 +#
3770 +# SPI RTC drivers
3771 +#
3772 +# CONFIG_RTC_DRV_RS5C348 is not set
3773 +# CONFIG_RTC_DRV_MAX6902 is not set
3774 +
3775 +#
3776 +# Platform RTC drivers
3777 +#
3778 +# CONFIG_RTC_DRV_DS1553 is not set
3779 +# CONFIG_RTC_DRV_STK17TA8 is not set
3780 +# CONFIG_RTC_DRV_DS1742 is not set
3781 +# CONFIG_RTC_DRV_M48T86 is not set
3782 +# CONFIG_RTC_DRV_M48T59 is not set
3783 +# CONFIG_RTC_DRV_V3020 is not set
3784 +
3785 +#
3786 +# on-CPU RTC drivers
3787 +#
3788 +CONFIG_RTC_DRV_AT32AP700X=y
3789 +
3790 +#
3791 +# Userspace I/O
3792 +#
3793 +CONFIG_UIO=m
3794 +
3795 +#
3796 +# File systems
3797 +#
3798 +CONFIG_EXT2_FS=m
3799 +# CONFIG_EXT2_FS_XATTR is not set
3800 +# CONFIG_EXT2_FS_XIP is not set
3801 +CONFIG_EXT3_FS=m
3802 +# CONFIG_EXT3_FS_XATTR is not set
3803 +# CONFIG_EXT4DEV_FS is not set
3804 +CONFIG_JBD=m
3805 +# CONFIG_JBD_DEBUG is not set
3806 +# CONFIG_REISERFS_FS is not set
3807 +# CONFIG_JFS_FS is not set
3808 +# CONFIG_FS_POSIX_ACL is not set
3809 +# CONFIG_XFS_FS is not set
3810 +# CONFIG_GFS2_FS is not set
3811 +# CONFIG_OCFS2_FS is not set
3812 +# CONFIG_MINIX_FS is not set
3813 +# CONFIG_ROMFS_FS is not set
3814 +CONFIG_INOTIFY=y
3815 +CONFIG_INOTIFY_USER=y
3816 +# CONFIG_QUOTA is not set
3817 +# CONFIG_DNOTIFY is not set
3818 +# CONFIG_AUTOFS_FS is not set
3819 +# CONFIG_AUTOFS4_FS is not set
3820 +CONFIG_FUSE_FS=m
3821 +
3822 +#
3823 +# CD-ROM/DVD Filesystems
3824 +#
3825 +# CONFIG_ISO9660_FS is not set
3826 +# CONFIG_UDF_FS is not set
3827 +
3828 +#
3829 +# DOS/FAT/NT Filesystems
3830 +#
3831 +CONFIG_FAT_FS=m
3832 +CONFIG_MSDOS_FS=m
3833 +CONFIG_VFAT_FS=m
3834 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3835 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3836 +# CONFIG_NTFS_FS is not set
3837 +
3838 +#
3839 +# Pseudo filesystems
3840 +#
3841 +CONFIG_PROC_FS=y
3842 +CONFIG_PROC_KCORE=y
3843 +CONFIG_PROC_SYSCTL=y
3844 +CONFIG_SYSFS=y
3845 +CONFIG_TMPFS=y
3846 +# CONFIG_TMPFS_POSIX_ACL is not set
3847 +# CONFIG_HUGETLB_PAGE is not set
3848 +CONFIG_CONFIGFS_FS=y
3849 +
3850 +#
3851 +# Miscellaneous filesystems
3852 +#
3853 +# CONFIG_ADFS_FS is not set
3854 +# CONFIG_AFFS_FS is not set
3855 +# CONFIG_HFS_FS is not set
3856 +# CONFIG_HFSPLUS_FS is not set
3857 +# CONFIG_BEFS_FS is not set
3858 +# CONFIG_BFS_FS is not set
3859 +# CONFIG_EFS_FS is not set
3860 +CONFIG_JFFS2_FS=y
3861 +CONFIG_JFFS2_FS_DEBUG=0
3862 +CONFIG_JFFS2_FS_WRITEBUFFER=y
3863 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3864 +# CONFIG_JFFS2_SUMMARY is not set
3865 +# CONFIG_JFFS2_FS_XATTR is not set
3866 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3867 +CONFIG_JFFS2_ZLIB=y
3868 +# CONFIG_JFFS2_LZO is not set
3869 +CONFIG_JFFS2_RTIME=y
3870 +# CONFIG_JFFS2_RUBIN is not set
3871 +# CONFIG_CRAMFS is not set
3872 +# CONFIG_VXFS_FS is not set
3873 +# CONFIG_HPFS_FS is not set
3874 +# CONFIG_QNX4FS_FS is not set
3875 +# CONFIG_SYSV_FS is not set
3876 +# CONFIG_UFS_FS is not set
3877 +# CONFIG_NETWORK_FILESYSTEMS is not set
3878 +
3879 +#
3880 +# Partition Types
3881 +#
3882 +# CONFIG_PARTITION_ADVANCED is not set
3883 +CONFIG_MSDOS_PARTITION=y
3884 +CONFIG_NLS=m
3885 +CONFIG_NLS_DEFAULT="iso8859-1"
3886 +CONFIG_NLS_CODEPAGE_437=m
3887 +# CONFIG_NLS_CODEPAGE_737 is not set
3888 +# CONFIG_NLS_CODEPAGE_775 is not set
3889 +# CONFIG_NLS_CODEPAGE_850 is not set
3890 +# CONFIG_NLS_CODEPAGE_852 is not set
3891 +# CONFIG_NLS_CODEPAGE_855 is not set
3892 +# CONFIG_NLS_CODEPAGE_857 is not set
3893 +# CONFIG_NLS_CODEPAGE_860 is not set
3894 +# CONFIG_NLS_CODEPAGE_861 is not set
3895 +# CONFIG_NLS_CODEPAGE_862 is not set
3896 +# CONFIG_NLS_CODEPAGE_863 is not set
3897 +# CONFIG_NLS_CODEPAGE_864 is not set
3898 +# CONFIG_NLS_CODEPAGE_865 is not set
3899 +# CONFIG_NLS_CODEPAGE_866 is not set
3900 +# CONFIG_NLS_CODEPAGE_869 is not set
3901 +# CONFIG_NLS_CODEPAGE_936 is not set
3902 +# CONFIG_NLS_CODEPAGE_950 is not set
3903 +# CONFIG_NLS_CODEPAGE_932 is not set
3904 +# CONFIG_NLS_CODEPAGE_949 is not set
3905 +# CONFIG_NLS_CODEPAGE_874 is not set
3906 +# CONFIG_NLS_ISO8859_8 is not set
3907 +# CONFIG_NLS_CODEPAGE_1250 is not set
3908 +# CONFIG_NLS_CODEPAGE_1251 is not set
3909 +# CONFIG_NLS_ASCII is not set
3910 +CONFIG_NLS_ISO8859_1=m
3911 +# CONFIG_NLS_ISO8859_2 is not set
3912 +# CONFIG_NLS_ISO8859_3 is not set
3913 +# CONFIG_NLS_ISO8859_4 is not set
3914 +# CONFIG_NLS_ISO8859_5 is not set
3915 +# CONFIG_NLS_ISO8859_6 is not set
3916 +# CONFIG_NLS_ISO8859_7 is not set
3917 +# CONFIG_NLS_ISO8859_9 is not set
3918 +# CONFIG_NLS_ISO8859_13 is not set
3919 +# CONFIG_NLS_ISO8859_14 is not set
3920 +# CONFIG_NLS_ISO8859_15 is not set
3921 +# CONFIG_NLS_KOI8_R is not set
3922 +# CONFIG_NLS_KOI8_U is not set
3923 +CONFIG_NLS_UTF8=m
3924 +# CONFIG_DLM is not set
3925 +CONFIG_INSTRUMENTATION=y
3926 +CONFIG_PROFILING=y
3927 +CONFIG_OPROFILE=m
3928 +CONFIG_KPROBES=y
3929 +# CONFIG_MARKERS is not set
3930 +
3931 +#
3932 +# Kernel hacking
3933 +#
3934 +# CONFIG_PRINTK_TIME is not set
3935 +CONFIG_ENABLE_WARN_DEPRECATED=y
3936 +CONFIG_ENABLE_MUST_CHECK=y
3937 +CONFIG_MAGIC_SYSRQ=y
3938 +# CONFIG_UNUSED_SYMBOLS is not set
3939 +CONFIG_DEBUG_FS=y
3940 +# CONFIG_HEADERS_CHECK is not set
3941 +CONFIG_DEBUG_KERNEL=y
3942 +# CONFIG_DEBUG_SHIRQ is not set
3943 +CONFIG_DETECT_SOFTLOCKUP=y
3944 +CONFIG_SCHED_DEBUG=y
3945 +# CONFIG_SCHEDSTATS is not set
3946 +# CONFIG_TIMER_STATS is not set
3947 +# CONFIG_DEBUG_RT_MUTEXES is not set
3948 +# CONFIG_RT_MUTEX_TESTER is not set
3949 +# CONFIG_DEBUG_SPINLOCK is not set
3950 +# CONFIG_DEBUG_MUTEXES is not set
3951 +# CONFIG_DEBUG_LOCK_ALLOC is not set
3952 +# CONFIG_PROVE_LOCKING is not set
3953 +# CONFIG_LOCK_STAT is not set
3954 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
3955 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
3956 +# CONFIG_DEBUG_KOBJECT is not set
3957 +CONFIG_DEBUG_BUGVERBOSE=y
3958 +# CONFIG_DEBUG_INFO is not set
3959 +# CONFIG_DEBUG_VM is not set
3960 +# CONFIG_DEBUG_LIST is not set
3961 +# CONFIG_DEBUG_SG is not set
3962 +CONFIG_FRAME_POINTER=y
3963 +CONFIG_FORCED_INLINING=y
3964 +# CONFIG_BOOT_PRINTK_DELAY is not set
3965 +# CONFIG_RCU_TORTURE_TEST is not set
3966 +# CONFIG_LKDTM is not set
3967 +# CONFIG_FAULT_INJECTION is not set
3968 +# CONFIG_SAMPLES is not set
3969 +
3970 +#
3971 +# Security options
3972 +#
3973 +# CONFIG_KEYS is not set
3974 +# CONFIG_SECURITY is not set
3975 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
3976 +# CONFIG_CRYPTO is not set
3977 +
3978 +#
3979 +# Library routines
3980 +#
3981 +CONFIG_BITREVERSE=y
3982 +CONFIG_CRC_CCITT=m
3983 +# CONFIG_CRC16 is not set
3984 +CONFIG_CRC_ITU_T=m
3985 +CONFIG_CRC32=y
3986 +CONFIG_CRC7=m
3987 +# CONFIG_LIBCRC32C is not set
3988 +CONFIG_AUDIT_GENERIC=y
3989 +CONFIG_ZLIB_INFLATE=y
3990 +CONFIG_ZLIB_DEFLATE=y
3991 +CONFIG_PLIST=y
3992 +CONFIG_HAS_IOMEM=y
3993 +CONFIG_HAS_IOPORT=y
3994 +CONFIG_HAS_DMA=y
3995 --- /dev/null
3996 +++ b/arch/avr32/configs/atstk1004_defconfig
3997 @@ -0,0 +1,639 @@
3998 +#
3999 +# Automatically generated make config: don't edit
4000 +# Linux kernel version: 2.6.24
4001 +# Thu Mar 6 12:51:05 2008
4002 +#
4003 +CONFIG_AVR32=y
4004 +CONFIG_GENERIC_GPIO=y
4005 +CONFIG_GENERIC_HARDIRQS=y
4006 +CONFIG_STACKTRACE_SUPPORT=y
4007 +CONFIG_LOCKDEP_SUPPORT=y
4008 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
4009 +CONFIG_HARDIRQS_SW_RESEND=y
4010 +CONFIG_GENERIC_IRQ_PROBE=y
4011 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
4012 +CONFIG_GENERIC_TIME=y
4013 +CONFIG_GENERIC_CLOCKEVENTS=y
4014 +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
4015 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
4016 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
4017 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
4018 +CONFIG_GENERIC_HWEIGHT=y
4019 +CONFIG_GENERIC_CALIBRATE_DELAY=y
4020 +CONFIG_GENERIC_BUG=y
4021 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
4022 +
4023 +#
4024 +# General setup
4025 +#
4026 +CONFIG_EXPERIMENTAL=y
4027 +CONFIG_BROKEN_ON_SMP=y
4028 +CONFIG_INIT_ENV_ARG_LIMIT=32
4029 +CONFIG_LOCALVERSION=""
4030 +# CONFIG_LOCALVERSION_AUTO is not set
4031 +# CONFIG_SYSVIPC is not set
4032 +# CONFIG_POSIX_MQUEUE is not set
4033 +# CONFIG_BSD_PROCESS_ACCT is not set
4034 +# CONFIG_TASKSTATS is not set
4035 +# CONFIG_USER_NS is not set
4036 +# CONFIG_PID_NS is not set
4037 +# CONFIG_AUDIT is not set
4038 +# CONFIG_IKCONFIG is not set
4039 +CONFIG_LOG_BUF_SHIFT=14
4040 +# CONFIG_CGROUPS is not set
4041 +# CONFIG_FAIR_GROUP_SCHED is not set
4042 +CONFIG_SYSFS_DEPRECATED=y
4043 +# CONFIG_RELAY is not set
4044 +# CONFIG_BLK_DEV_INITRD is not set
4045 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
4046 +CONFIG_SYSCTL=y
4047 +CONFIG_EMBEDDED=y
4048 +# CONFIG_SYSCTL_SYSCALL is not set
4049 +CONFIG_KALLSYMS=y
4050 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
4051 +CONFIG_HOTPLUG=y
4052 +CONFIG_PRINTK=y
4053 +CONFIG_BUG=y
4054 +CONFIG_ELF_CORE=y
4055 +# CONFIG_BASE_FULL is not set
4056 +# CONFIG_FUTEX is not set
4057 +# CONFIG_EPOLL is not set
4058 +# CONFIG_SIGNALFD is not set
4059 +# CONFIG_EVENTFD is not set
4060 +CONFIG_SHMEM=y
4061 +CONFIG_VM_EVENT_COUNTERS=y
4062 +# CONFIG_SLAB is not set
4063 +# CONFIG_SLUB is not set
4064 +CONFIG_SLOB=y
4065 +# CONFIG_TINY_SHMEM is not set
4066 +CONFIG_BASE_SMALL=1
4067 +# CONFIG_MODULES is not set
4068 +# CONFIG_BLOCK is not set
4069 +
4070 +#
4071 +# System Type and features
4072 +#
4073 +CONFIG_TICK_ONESHOT=y
4074 +CONFIG_NO_HZ=y
4075 +CONFIG_HIGH_RES_TIMERS=y
4076 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
4077 +CONFIG_SUBARCH_AVR32B=y
4078 +CONFIG_MMU=y
4079 +CONFIG_PERFORMANCE_COUNTERS=y
4080 +CONFIG_PLATFORM_AT32AP=y
4081 +CONFIG_CPU_AT32AP700X=y
4082 +CONFIG_CPU_AT32AP7002=y
4083 +CONFIG_BOARD_ATSTK1000=y
4084 +# CONFIG_BOARD_ATNGW100 is not set
4085 +# CONFIG_BOARD_ATSTK1002 is not set
4086 +# CONFIG_BOARD_ATSTK1003 is not set
4087 +CONFIG_BOARD_ATSTK1004=y
4088 +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
4089 +# CONFIG_BOARD_ATSTK100X_SPI1 is not set
4090 +# CONFIG_BOARD_ATSTK1000_J2_LED is not set
4091 +CONFIG_BOARD_ATSTK1000_EXTDAC=y
4092 +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
4093 +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
4094 +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
4095 +CONFIG_LOADER_U_BOOT=y
4096 +
4097 +#
4098 +# Atmel AVR32 AP options
4099 +#
4100 +# CONFIG_AP700X_32_BIT_SMC is not set
4101 +CONFIG_AP700X_16_BIT_SMC=y
4102 +# CONFIG_AP700X_8_BIT_SMC is not set
4103 +# CONFIG_GPIO_DEV is not set
4104 +CONFIG_LOAD_ADDRESS=0x10000000
4105 +CONFIG_ENTRY_ADDRESS=0x90000000
4106 +CONFIG_PHYS_OFFSET=0x10000000
4107 +CONFIG_PREEMPT_NONE=y
4108 +# CONFIG_PREEMPT_VOLUNTARY is not set
4109 +# CONFIG_PREEMPT is not set
4110 +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
4111 +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
4112 +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
4113 +CONFIG_ARCH_FLATMEM_ENABLE=y
4114 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
4115 +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
4116 +CONFIG_SELECT_MEMORY_MODEL=y
4117 +CONFIG_FLATMEM_MANUAL=y
4118 +# CONFIG_DISCONTIGMEM_MANUAL is not set
4119 +# CONFIG_SPARSEMEM_MANUAL is not set
4120 +CONFIG_FLATMEM=y
4121 +CONFIG_FLAT_NODE_MEM_MAP=y
4122 +# CONFIG_SPARSEMEM_STATIC is not set
4123 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
4124 +CONFIG_SPLIT_PTLOCK_CPUS=4
4125 +# CONFIG_RESOURCES_64BIT is not set
4126 +CONFIG_ZONE_DMA_FLAG=0
4127 +CONFIG_VIRT_TO_BUS=y
4128 +# CONFIG_OWNERSHIP_TRACE is not set
4129 +# CONFIG_NMI_DEBUGGING is not set
4130 +# CONFIG_DW_DMAC is not set
4131 +# CONFIG_HZ_100 is not set
4132 +CONFIG_HZ_250=y
4133 +# CONFIG_HZ_300 is not set
4134 +# CONFIG_HZ_1000 is not set
4135 +CONFIG_HZ=250
4136 +CONFIG_CMDLINE=""
4137 +
4138 +#
4139 +# Power management options
4140 +#
4141 +
4142 +#
4143 +# CPU Frequency scaling
4144 +#
4145 +CONFIG_CPU_FREQ=y
4146 +CONFIG_CPU_FREQ_TABLE=y
4147 +# CONFIG_CPU_FREQ_DEBUG is not set
4148 +# CONFIG_CPU_FREQ_STAT is not set
4149 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
4150 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
4151 +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
4152 +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
4153 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
4154 +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
4155 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
4156 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
4157 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
4158 +CONFIG_CPU_FREQ_AT32AP=y
4159 +
4160 +#
4161 +# Bus options
4162 +#
4163 +# CONFIG_ARCH_SUPPORTS_MSI is not set
4164 +# CONFIG_PCCARD is not set
4165 +
4166 +#
4167 +# Executable file formats
4168 +#
4169 +CONFIG_BINFMT_ELF=y
4170 +# CONFIG_BINFMT_MISC is not set
4171 +
4172 +#
4173 +# Networking
4174 +#
4175 +CONFIG_NET=y
4176 +
4177 +#
4178 +# Networking options
4179 +#
4180 +CONFIG_PACKET=y
4181 +CONFIG_PACKET_MMAP=y
4182 +CONFIG_UNIX=y
4183 +# CONFIG_NET_KEY is not set
4184 +CONFIG_INET=y
4185 +# CONFIG_IP_MULTICAST is not set
4186 +# CONFIG_IP_ADVANCED_ROUTER is not set
4187 +CONFIG_IP_FIB_HASH=y
4188 +# CONFIG_IP_PNP is not set
4189 +# CONFIG_NET_IPIP is not set
4190 +# CONFIG_NET_IPGRE is not set
4191 +# CONFIG_ARPD is not set
4192 +# CONFIG_SYN_COOKIES is not set
4193 +# CONFIG_INET_AH is not set
4194 +# CONFIG_INET_ESP is not set
4195 +# CONFIG_INET_IPCOMP is not set
4196 +# CONFIG_INET_XFRM_TUNNEL is not set
4197 +# CONFIG_INET_TUNNEL is not set
4198 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
4199 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
4200 +# CONFIG_INET_XFRM_MODE_BEET is not set
4201 +# CONFIG_INET_LRO is not set
4202 +# CONFIG_INET_DIAG is not set
4203 +# CONFIG_TCP_CONG_ADVANCED is not set
4204 +CONFIG_TCP_CONG_CUBIC=y
4205 +CONFIG_DEFAULT_TCP_CONG="cubic"
4206 +# CONFIG_TCP_MD5SIG is not set
4207 +# CONFIG_IPV6 is not set
4208 +# CONFIG_INET6_XFRM_TUNNEL is not set
4209 +# CONFIG_INET6_TUNNEL is not set
4210 +# CONFIG_NETWORK_SECMARK is not set
4211 +# CONFIG_NETFILTER is not set
4212 +# CONFIG_IP_DCCP is not set
4213 +# CONFIG_IP_SCTP is not set
4214 +# CONFIG_TIPC is not set
4215 +# CONFIG_ATM is not set
4216 +# CONFIG_BRIDGE is not set
4217 +# CONFIG_VLAN_8021Q is not set
4218 +# CONFIG_DECNET is not set
4219 +# CONFIG_LLC2 is not set
4220 +# CONFIG_IPX is not set
4221 +# CONFIG_ATALK is not set
4222 +# CONFIG_X25 is not set
4223 +# CONFIG_LAPB is not set
4224 +# CONFIG_ECONET is not set
4225 +# CONFIG_WAN_ROUTER is not set
4226 +# CONFIG_NET_SCHED is not set
4227 +
4228 +#
4229 +# Network testing
4230 +#
4231 +# CONFIG_NET_PKTGEN is not set
4232 +# CONFIG_HAMRADIO is not set
4233 +# CONFIG_IRDA is not set
4234 +# CONFIG_BT is not set
4235 +# CONFIG_AF_RXRPC is not set
4236 +
4237 +#
4238 +# Wireless
4239 +#
4240 +# CONFIG_CFG80211 is not set
4241 +# CONFIG_WIRELESS_EXT is not set
4242 +# CONFIG_MAC80211 is not set
4243 +# CONFIG_IEEE80211 is not set
4244 +# CONFIG_RFKILL is not set
4245 +# CONFIG_NET_9P is not set
4246 +
4247 +#
4248 +# Device Drivers
4249 +#
4250 +
4251 +#
4252 +# Generic Driver Options
4253 +#
4254 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
4255 +CONFIG_STANDALONE=y
4256 +# CONFIG_PREVENT_FIRMWARE_BUILD is not set
4257 +# CONFIG_FW_LOADER is not set
4258 +# CONFIG_SYS_HYPERVISOR is not set
4259 +# CONFIG_CONNECTOR is not set
4260 +CONFIG_MTD=y
4261 +# CONFIG_MTD_DEBUG is not set
4262 +# CONFIG_MTD_CONCAT is not set
4263 +CONFIG_MTD_PARTITIONS=y
4264 +# CONFIG_MTD_REDBOOT_PARTS is not set
4265 +CONFIG_MTD_CMDLINE_PARTS=y
4266 +
4267 +#
4268 +# User Modules And Translation Layers
4269 +#
4270 +CONFIG_MTD_CHAR=y
4271 +# CONFIG_MTD_OOPS is not set
4272 +
4273 +#
4274 +# RAM/ROM/Flash chip drivers
4275 +#
4276 +CONFIG_MTD_CFI=y
4277 +# CONFIG_MTD_JEDECPROBE is not set
4278 +CONFIG_MTD_GEN_PROBE=y
4279 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
4280 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
4281 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
4282 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
4283 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
4284 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
4285 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
4286 +CONFIG_MTD_CFI_I1=y
4287 +CONFIG_MTD_CFI_I2=y
4288 +# CONFIG_MTD_CFI_I4 is not set
4289 +# CONFIG_MTD_CFI_I8 is not set
4290 +# CONFIG_MTD_CFI_INTELEXT is not set
4291 +CONFIG_MTD_CFI_AMDSTD=y
4292 +# CONFIG_MTD_CFI_STAA is not set
4293 +CONFIG_MTD_CFI_UTIL=y
4294 +# CONFIG_MTD_RAM is not set
4295 +# CONFIG_MTD_ROM is not set
4296 +# CONFIG_MTD_ABSENT is not set
4297 +
4298 +#
4299 +# Mapping drivers for chip access
4300 +#
4301 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
4302 +CONFIG_MTD_PHYSMAP=y
4303 +CONFIG_MTD_PHYSMAP_START=0x8000000
4304 +CONFIG_MTD_PHYSMAP_LEN=0x0
4305 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
4306 +# CONFIG_MTD_PLATRAM is not set
4307 +
4308 +#
4309 +# Self-contained MTD device drivers
4310 +#
4311 +# CONFIG_MTD_DATAFLASH is not set
4312 +# CONFIG_MTD_M25P80 is not set
4313 +# CONFIG_MTD_SLRAM is not set
4314 +# CONFIG_MTD_PHRAM is not set
4315 +# CONFIG_MTD_MTDRAM is not set
4316 +
4317 +#
4318 +# Disk-On-Chip Device Drivers
4319 +#
4320 +# CONFIG_MTD_DOC2000 is not set
4321 +# CONFIG_MTD_DOC2001 is not set
4322 +# CONFIG_MTD_DOC2001PLUS is not set
4323 +# CONFIG_MTD_NAND is not set
4324 +# CONFIG_MTD_ONENAND is not set
4325 +
4326 +#
4327 +# UBI - Unsorted block images
4328 +#
4329 +# CONFIG_MTD_UBI is not set
4330 +# CONFIG_PARPORT is not set
4331 +CONFIG_MISC_DEVICES=y
4332 +# CONFIG_ATMEL_PWM is not set
4333 +CONFIG_ATMEL_TCLIB=y
4334 +CONFIG_ATMEL_TCB_CLKSRC=y
4335 +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
4336 +# CONFIG_EEPROM_93CX6 is not set
4337 +# CONFIG_ATMEL_SSC is not set
4338 +
4339 +#
4340 +# SCSI device support
4341 +#
4342 +# CONFIG_SCSI_DMA is not set
4343 +# CONFIG_SCSI_NETLINK is not set
4344 +# CONFIG_NETDEVICES is not set
4345 +# CONFIG_ISDN is not set
4346 +# CONFIG_PHONE is not set
4347 +
4348 +#
4349 +# Input device support
4350 +#
4351 +# CONFIG_INPUT is not set
4352 +
4353 +#
4354 +# Hardware I/O ports
4355 +#
4356 +# CONFIG_SERIO is not set
4357 +# CONFIG_GAMEPORT is not set
4358 +
4359 +#
4360 +# Character devices
4361 +#
4362 +# CONFIG_VT is not set
4363 +# CONFIG_SERIAL_NONSTANDARD is not set
4364 +
4365 +#
4366 +# Serial drivers
4367 +#
4368 +# CONFIG_SERIAL_8250 is not set
4369 +
4370 +#
4371 +# Non-8250 serial port support
4372 +#
4373 +CONFIG_SERIAL_ATMEL=y
4374 +CONFIG_SERIAL_ATMEL_CONSOLE=y
4375 +# CONFIG_SERIAL_ATMEL_PDC is not set
4376 +# CONFIG_SERIAL_ATMEL_TTYAT is not set
4377 +CONFIG_SERIAL_CORE=y
4378 +CONFIG_SERIAL_CORE_CONSOLE=y
4379 +CONFIG_UNIX98_PTYS=y
4380 +# CONFIG_LEGACY_PTYS is not set
4381 +# CONFIG_IPMI_HANDLER is not set
4382 +# CONFIG_HW_RANDOM is not set
4383 +# CONFIG_RTC is not set
4384 +# CONFIG_GEN_RTC is not set
4385 +# CONFIG_R3964 is not set
4386 +# CONFIG_TCG_TPM is not set
4387 +# CONFIG_I2C is not set
4388 +
4389 +#
4390 +# SPI support
4391 +#
4392 +CONFIG_SPI=y
4393 +CONFIG_SPI_MASTER=y
4394 +
4395 +#
4396 +# SPI Master Controller Drivers
4397 +#
4398 +CONFIG_SPI_ATMEL=y
4399 +# CONFIG_SPI_BITBANG is not set
4400 +
4401 +#
4402 +# SPI Protocol Masters
4403 +#
4404 +# CONFIG_SPI_AT25 is not set
4405 +# CONFIG_SPI_SPIDEV is not set
4406 +# CONFIG_SPI_TLE62X0 is not set
4407 +# CONFIG_W1 is not set
4408 +# CONFIG_POWER_SUPPLY is not set
4409 +# CONFIG_HWMON is not set
4410 +CONFIG_WATCHDOG=y
4411 +# CONFIG_WATCHDOG_NOWAYOUT is not set
4412 +
4413 +#
4414 +# Watchdog Device Drivers
4415 +#
4416 +# CONFIG_SOFT_WATCHDOG is not set
4417 +CONFIG_AT32AP700X_WDT=y
4418 +
4419 +#
4420 +# Sonics Silicon Backplane
4421 +#
4422 +CONFIG_SSB_POSSIBLE=y
4423 +# CONFIG_SSB is not set
4424 +
4425 +#
4426 +# Multifunction device drivers
4427 +#
4428 +# CONFIG_MFD_SM501 is not set
4429 +
4430 +#
4431 +# Multimedia devices
4432 +#
4433 +# CONFIG_VIDEO_DEV is not set
4434 +# CONFIG_DVB_CORE is not set
4435 +# CONFIG_DAB is not set
4436 +
4437 +#
4438 +# Graphics support
4439 +#
4440 +# CONFIG_VGASTATE is not set
4441 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
4442 +CONFIG_FB=y
4443 +# CONFIG_FIRMWARE_EDID is not set
4444 +# CONFIG_FB_DDC is not set
4445 +CONFIG_FB_CFB_FILLRECT=y
4446 +CONFIG_FB_CFB_COPYAREA=y
4447 +CONFIG_FB_CFB_IMAGEBLIT=y
4448 +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
4449 +# CONFIG_FB_SYS_FILLRECT is not set
4450 +# CONFIG_FB_SYS_COPYAREA is not set
4451 +# CONFIG_FB_SYS_IMAGEBLIT is not set
4452 +# CONFIG_FB_SYS_FOPS is not set
4453 +CONFIG_FB_DEFERRED_IO=y
4454 +# CONFIG_FB_SVGALIB is not set
4455 +# CONFIG_FB_MACMODES is not set
4456 +# CONFIG_FB_BACKLIGHT is not set
4457 +# CONFIG_FB_MODE_HELPERS is not set
4458 +# CONFIG_FB_TILEBLITTING is not set
4459 +
4460 +#
4461 +# Frame buffer hardware drivers
4462 +#
4463 +# CONFIG_FB_S1D13XXX is not set
4464 +CONFIG_FB_ATMEL=y
4465 +# CONFIG_FB_VIRTUAL is not set
4466 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
4467 +CONFIG_LCD_CLASS_DEVICE=y
4468 +CONFIG_LCD_LTV350QV=y
4469 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
4470 +
4471 +#
4472 +# Display device support
4473 +#
4474 +# CONFIG_DISPLAY_SUPPORT is not set
4475 +# CONFIG_LOGO is not set
4476 +
4477 +#
4478 +# Sound
4479 +#
4480 +# CONFIG_SOUND is not set
4481 +CONFIG_USB_SUPPORT=y
4482 +# CONFIG_USB_ARCH_HAS_HCD is not set
4483 +# CONFIG_USB_ARCH_HAS_OHCI is not set
4484 +# CONFIG_USB_ARCH_HAS_EHCI is not set
4485 +
4486 +#
4487 +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
4488 +#
4489 +
4490 +#
4491 +# USB Gadget Support
4492 +#
4493 +CONFIG_USB_GADGET=y
4494 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
4495 +CONFIG_USB_GADGET_SELECTED=y
4496 +# CONFIG_USB_GADGET_AMD5536UDC is not set
4497 +CONFIG_USB_GADGET_ATMEL_USBA=y
4498 +CONFIG_USB_ATMEL_USBA=y
4499 +# CONFIG_USB_GADGET_FSL_USB2 is not set
4500 +# CONFIG_USB_GADGET_NET2280 is not set
4501 +# CONFIG_USB_GADGET_PXA2XX is not set
4502 +# CONFIG_USB_GADGET_M66592 is not set
4503 +# CONFIG_USB_GADGET_GOKU is not set
4504 +# CONFIG_USB_GADGET_LH7A40X is not set
4505 +# CONFIG_USB_GADGET_OMAP is not set
4506 +# CONFIG_USB_GADGET_S3C2410 is not set
4507 +# CONFIG_USB_GADGET_AT91 is not set
4508 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
4509 +CONFIG_USB_GADGET_DUALSPEED=y
4510 +# CONFIG_USB_ZERO is not set
4511 +CONFIG_USB_ETH=y
4512 +# CONFIG_USB_ETH_RNDIS is not set
4513 +# CONFIG_USB_GADGETFS is not set
4514 +# CONFIG_USB_FILE_STORAGE is not set
4515 +# CONFIG_USB_G_SERIAL is not set
4516 +# CONFIG_USB_MIDI_GADGET is not set
4517 +# CONFIG_MMC is not set
4518 +# CONFIG_NEW_LEDS is not set
4519 +CONFIG_RTC_LIB=y
4520 +CONFIG_RTC_CLASS=y
4521 +CONFIG_RTC_HCTOSYS=y
4522 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
4523 +# CONFIG_RTC_DEBUG is not set
4524 +
4525 +#
4526 +# RTC interfaces
4527 +#
4528 +CONFIG_RTC_INTF_SYSFS=y
4529 +# CONFIG_RTC_INTF_PROC is not set
4530 +CONFIG_RTC_INTF_DEV=y
4531 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
4532 +# CONFIG_RTC_DRV_TEST is not set
4533 +
4534 +#
4535 +# SPI RTC drivers
4536 +#
4537 +# CONFIG_RTC_DRV_RS5C348 is not set
4538 +# CONFIG_RTC_DRV_MAX6902 is not set
4539 +
4540 +#
4541 +# Platform RTC drivers
4542 +#
4543 +# CONFIG_RTC_DRV_DS1553 is not set
4544 +# CONFIG_RTC_DRV_STK17TA8 is not set
4545 +# CONFIG_RTC_DRV_DS1742 is not set
4546 +# CONFIG_RTC_DRV_M48T86 is not set
4547 +# CONFIG_RTC_DRV_M48T59 is not set
4548 +# CONFIG_RTC_DRV_V3020 is not set
4549 +
4550 +#
4551 +# on-CPU RTC drivers
4552 +#
4553 +CONFIG_RTC_DRV_AT32AP700X=y
4554 +
4555 +#
4556 +# Userspace I/O
4557 +#
4558 +# CONFIG_UIO is not set
4559 +
4560 +#
4561 +# File systems
4562 +#
4563 +# CONFIG_INOTIFY is not set
4564 +# CONFIG_QUOTA is not set
4565 +# CONFIG_DNOTIFY is not set
4566 +# CONFIG_AUTOFS_FS is not set
4567 +# CONFIG_AUTOFS4_FS is not set
4568 +# CONFIG_FUSE_FS is not set
4569 +
4570 +#
4571 +# Pseudo filesystems
4572 +#
4573 +CONFIG_PROC_FS=y
4574 +CONFIG_PROC_KCORE=y
4575 +CONFIG_PROC_SYSCTL=y
4576 +CONFIG_SYSFS=y
4577 +CONFIG_TMPFS=y
4578 +# CONFIG_TMPFS_POSIX_ACL is not set
4579 +# CONFIG_HUGETLB_PAGE is not set
4580 +# CONFIG_CONFIGFS_FS is not set
4581 +
4582 +#
4583 +# Miscellaneous filesystems
4584 +#
4585 +CONFIG_JFFS2_FS=y
4586 +CONFIG_JFFS2_FS_DEBUG=0
4587 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set
4588 +# CONFIG_JFFS2_SUMMARY is not set
4589 +# CONFIG_JFFS2_FS_XATTR is not set
4590 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
4591 +CONFIG_JFFS2_ZLIB=y
4592 +# CONFIG_JFFS2_LZO is not set
4593 +CONFIG_JFFS2_RTIME=y
4594 +# CONFIG_JFFS2_RUBIN is not set
4595 +# CONFIG_NETWORK_FILESYSTEMS is not set
4596 +# CONFIG_NLS is not set
4597 +# CONFIG_DLM is not set
4598 +# CONFIG_INSTRUMENTATION is not set
4599 +
4600 +#
4601 +# Kernel hacking
4602 +#
4603 +# CONFIG_PRINTK_TIME is not set
4604 +CONFIG_ENABLE_WARN_DEPRECATED=y
4605 +CONFIG_ENABLE_MUST_CHECK=y
4606 +CONFIG_MAGIC_SYSRQ=y
4607 +# CONFIG_UNUSED_SYMBOLS is not set
4608 +# CONFIG_DEBUG_FS is not set
4609 +# CONFIG_HEADERS_CHECK is not set
4610 +# CONFIG_DEBUG_KERNEL is not set
4611 +# CONFIG_DEBUG_BUGVERBOSE is not set
4612 +# CONFIG_SAMPLES is not set
4613 +
4614 +#
4615 +# Security options
4616 +#
4617 +# CONFIG_KEYS is not set
4618 +# CONFIG_SECURITY is not set
4619 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4620 +# CONFIG_CRYPTO is not set
4621 +
4622 +#
4623 +# Library routines
4624 +#
4625 +CONFIG_BITREVERSE=y
4626 +# CONFIG_CRC_CCITT is not set
4627 +# CONFIG_CRC16 is not set
4628 +# CONFIG_CRC_ITU_T is not set
4629 +CONFIG_CRC32=y
4630 +# CONFIG_CRC7 is not set
4631 +# CONFIG_LIBCRC32C is not set
4632 +CONFIG_ZLIB_INFLATE=y
4633 +CONFIG_ZLIB_DEFLATE=y
4634 +CONFIG_HAS_IOMEM=y
4635 +CONFIG_HAS_IOPORT=y
4636 +CONFIG_HAS_DMA=y
4637 --- /dev/null
4638 +++ b/arch/avr32/drivers/dw-dmac.c
4639 @@ -0,0 +1,761 @@
4640 +/*
4641 + * Driver for the Synopsys DesignWare DMA Controller
4642 + *
4643 + * Copyright (C) 2005-2006 Atmel Corporation
4644 + *
4645 + * This program is free software; you can redistribute it and/or modify
4646 + * it under the terms of the GNU General Public License version 2 as
4647 + * published by the Free Software Foundation.
4648 + */
4649 +#include <linux/clk.h>
4650 +#include <linux/device.h>
4651 +#include <linux/dma-mapping.h>
4652 +#include <linux/dmapool.h>
4653 +#include <linux/init.h>
4654 +#include <linux/interrupt.h>
4655 +#include <linux/module.h>
4656 +#include <linux/platform_device.h>
4657 +
4658 +#include <asm/dma-controller.h>
4659 +#include <asm/io.h>
4660 +
4661 +#include "dw-dmac.h"
4662 +
4663 +#define DMAC_NR_CHANNELS 3
4664 +#define DMAC_MAX_BLOCKSIZE 4095
4665 +
4666 +enum {
4667 + CH_STATE_FREE = 0,
4668 + CH_STATE_ALLOCATED,
4669 + CH_STATE_BUSY,
4670 +};
4671 +
4672 +struct dw_dma_lli {
4673 + dma_addr_t sar;
4674 + dma_addr_t dar;
4675 + dma_addr_t llp;
4676 + u32 ctllo;
4677 + u32 ctlhi;
4678 + u32 sstat;
4679 + u32 dstat;
4680 +};
4681 +
4682 +struct dw_dma_block {
4683 + struct dw_dma_lli *lli_vaddr;
4684 + dma_addr_t lli_dma_addr;
4685 +};
4686 +
4687 +struct dw_dma_channel {
4688 + unsigned int state;
4689 + int is_cyclic;
4690 + struct dma_request_sg *req_sg;
4691 + struct dma_request_cyclic *req_cyclic;
4692 + unsigned int nr_blocks;
4693 + int direction;
4694 + struct dw_dma_block *block;
4695 +};
4696 +
4697 +struct dw_dma_controller {
4698 + spinlock_t lock;
4699 + void * __iomem regs;
4700 + struct dma_pool *lli_pool;
4701 + struct clk *hclk;
4702 + struct dma_controller dma;
4703 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
4704 +};
4705 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
4706 +
4707 +#define dmac_writel_hi(dmac, reg, value) \
4708 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
4709 +#define dmac_readl_hi(dmac, reg) \
4710 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
4711 +#define dmac_writel_lo(dmac, reg, value) \
4712 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
4713 +#define dmac_readl_lo(dmac, reg) \
4714 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
4715 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
4716 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
4717 + + DW_DMAC_CHAN_##reg + 4))
4718 +#define dmac_chan_readl_hi(dmac, chan, reg) \
4719 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
4720 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
4721 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
4722 +#define dmac_chan_readl_lo(dmac, chan, reg) \
4723 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
4724 +#define set_channel_bit(dmac, reg, chan) \
4725 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
4726 +#define clear_channel_bit(dmac, reg, chan) \
4727 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
4728 +
4729 +static int dmac_alloc_channel(struct dma_controller *_dmac)
4730 +{
4731 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4732 + struct dw_dma_channel *chan;
4733 + unsigned long flags;
4734 + int i;
4735 +
4736 + spin_lock_irqsave(&dmac->lock, flags);
4737 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
4738 + if (dmac->channel[i].state == CH_STATE_FREE)
4739 + break;
4740 +
4741 + if (i < DMAC_NR_CHANNELS) {
4742 + chan = &dmac->channel[i];
4743 + chan->state = CH_STATE_ALLOCATED;
4744 + } else {
4745 + i = -EBUSY;
4746 + }
4747 +
4748 + spin_unlock_irqrestore(&dmac->lock, flags);
4749 +
4750 + return i;
4751 +}
4752 +
4753 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
4754 +{
4755 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4756 +
4757 + BUG_ON(channel >= DMAC_NR_CHANNELS
4758 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
4759 +
4760 + dmac->channel[channel].state = CH_STATE_FREE;
4761 +}
4762 +
4763 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
4764 + unsigned int nr_blocks)
4765 +{
4766 + struct dw_dma_block *block;
4767 + void *p;
4768 + unsigned int i;
4769 +
4770 + block = kmalloc(nr_blocks * sizeof(*block),
4771 + GFP_KERNEL);
4772 + if (unlikely(!block))
4773 + return NULL;
4774 +
4775 + for (i = 0; i < nr_blocks; i++) {
4776 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
4777 + &block[i].lli_dma_addr);
4778 + block[i].lli_vaddr = p;
4779 + if (unlikely(!p))
4780 + goto fail;
4781 + }
4782 +
4783 + return block;
4784 +
4785 +fail:
4786 + for (i = 0; i < nr_blocks; i++) {
4787 + if (!block[i].lli_vaddr)
4788 + break;
4789 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
4790 + block[i].lli_dma_addr);
4791 + }
4792 + kfree(block);
4793 + return NULL;
4794 +}
4795 +
4796 +static void cleanup_channel(struct dw_dma_controller *dmac,
4797 + struct dw_dma_channel *chan)
4798 +{
4799 + unsigned int i;
4800 +
4801 + if (chan->nr_blocks > 1) {
4802 + for (i = 0; i < chan->nr_blocks; i++)
4803 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
4804 + chan->block[i].lli_dma_addr);
4805 + kfree(chan->block);
4806 + }
4807 +
4808 + chan->state = CH_STATE_ALLOCATED;
4809 +}
4810 +
4811 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
4812 + struct dma_request_sg *req)
4813 +{
4814 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4815 + struct dw_dma_channel *chan;
4816 + unsigned long ctlhi, ctllo, cfghi, cfglo;
4817 + unsigned long block_size;
4818 + unsigned int nr_blocks;
4819 + int ret, i, direction;
4820 + unsigned long flags;
4821 +
4822 + spin_lock_irqsave(&dmac->lock, flags);
4823 +
4824 + ret = -EINVAL;
4825 + if (req->req.channel >= DMAC_NR_CHANNELS
4826 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
4827 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
4828 + spin_unlock_irqrestore(&dmac->lock, flags);
4829 + return -EINVAL;
4830 + }
4831 +
4832 + chan = &dmac->channel[req->req.channel];
4833 + chan->state = CH_STATE_BUSY;
4834 + chan->req_sg = req;
4835 + chan->is_cyclic = 0;
4836 +
4837 + /*
4838 + * We have marked the channel as busy, so no need to keep the
4839 + * lock as long as we only touch the channel-specific
4840 + * registers
4841 + */
4842 + spin_unlock_irqrestore(&dmac->lock, flags);
4843 +
4844 + /*
4845 + * There may be limitations in the driver and/or the DMA
4846 + * controller that prevents us from sending a whole
4847 + * scatterlist item in one go. Taking this into account,
4848 + * calculate the number of block transfers we need to set up.
4849 + *
4850 + * FIXME: Let the peripheral driver know about the maximum
4851 + * block size we support. We really don't want to use a
4852 + * different block size than what was suggested by the
4853 + * peripheral.
4854 + *
4855 + * Each block will get its own Linked List Item (LLI) below.
4856 + */
4857 + block_size = req->block_size;
4858 + nr_blocks = req->nr_blocks;
4859 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
4860 + block_size, nr_blocks, req->nr_sg);
4861 +
4862 + BUG_ON(nr_blocks == 0);
4863 + chan->nr_blocks = nr_blocks;
4864 +
4865 + ret = -EINVAL;
4866 + cfglo = cfghi = 0;
4867 + switch (req->direction) {
4868 + case DMA_DIR_MEM_TO_PERIPH:
4869 + direction = DMA_TO_DEVICE;
4870 + cfghi = req->periph_id << (43 - 32);
4871 + break;
4872 +
4873 + case DMA_DIR_PERIPH_TO_MEM:
4874 + direction = DMA_FROM_DEVICE;
4875 + cfghi = req->periph_id << (39 - 32);
4876 + break;
4877 + default:
4878 + goto out_unclaim_channel;
4879 + }
4880 +
4881 + chan->direction = direction;
4882 +
4883 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
4884 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
4885 +
4886 + ctlhi = block_size >> req->width;
4887 + ctllo = ((req->direction << 20)
4888 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
4889 + | (req->width << 4) | (req->width << 1)
4890 + | (1 << 0)); // interrupt enable
4891 +
4892 + if (nr_blocks == 1) {
4893 + /* Only one block: No need to use block chaining */
4894 + if (direction == DMA_TO_DEVICE) {
4895 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
4896 + req->sg->dma_address);
4897 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
4898 + req->data_reg);
4899 + ctllo |= 2 << 7; // no dst increment
4900 + } else {
4901 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
4902 + req->data_reg);
4903 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
4904 + req->sg->dma_address);
4905 + ctllo |= 2 << 9; // no src increment
4906 + }
4907 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
4908 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
4909 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
4910 + } else {
4911 + struct dw_dma_lli *lli, *lli_prev = NULL;
4912 + int j = 0, offset = 0;
4913 +
4914 + ret = -ENOMEM;
4915 + chan->block = allocate_blocks(dmac, nr_blocks);
4916 + if (!chan->block)
4917 + goto out_unclaim_channel;
4918 +
4919 + if (direction == DMA_TO_DEVICE)
4920 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
4921 + else
4922 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
4923 +
4924 + /*
4925 + * Map scatterlist items to blocks. One scatterlist
4926 + * item may need more than one block for the reasons
4927 + * mentioned above.
4928 + */
4929 + for (i = 0; i < nr_blocks; i++) {
4930 + lli = chan->block[i].lli_vaddr;
4931 + if (lli_prev) {
4932 + lli_prev->llp = chan->block[i].lli_dma_addr;
4933 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
4934 + i - 1, chan->block[i - 1].lli_vaddr,
4935 + chan->block[i - 1].lli_dma_addr,
4936 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
4937 + lli_prev->ctllo, lli_prev->ctlhi);
4938 + }
4939 + lli->llp = 0;
4940 + lli->ctllo = ctllo;
4941 + lli->ctlhi = ctlhi;
4942 + if (direction == DMA_TO_DEVICE) {
4943 + lli->sar = req->sg[j].dma_address + offset;
4944 + lli->dar = req->data_reg;
4945 + } else {
4946 + lli->sar = req->data_reg;
4947 + lli->dar = req->sg[j].dma_address + offset;
4948 + }
4949 + lli_prev = lli;
4950 +
4951 + offset += block_size;
4952 + if (offset > req->sg[j].length) {
4953 + j++;
4954 + offset = 0;
4955 + }
4956 + }
4957 +
4958 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
4959 + i - 1, chan->block[i - 1].lli_vaddr,
4960 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
4961 + lli_prev->dar, lli_prev->llp,
4962 + lli_prev->ctllo, lli_prev->ctlhi);
4963 +
4964 + /*
4965 + * SAR, DAR and CTL are initialized from the LLI. We
4966 + * only have to enable the LLI bits in CTL.
4967 + */
4968 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
4969 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
4970 + chan->block[0].lli_dma_addr);
4971 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
4972 + }
4973 +
4974 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
4975 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
4976 + if (req->req.block_complete)
4977 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4978 + else
4979 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
4980 +
4981 + return 0;
4982 +
4983 +out_unclaim_channel:
4984 + chan->state = CH_STATE_ALLOCATED;
4985 + return ret;
4986 +}
4987 +
4988 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
4989 + struct dma_request_cyclic *req)
4990 +{
4991 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
4992 + struct dw_dma_channel *chan;
4993 + unsigned long ctlhi, ctllo, cfghi, cfglo;
4994 + unsigned long block_size;
4995 + int ret, i, direction;
4996 + unsigned long flags;
4997 +
4998 + spin_lock_irqsave(&dmac->lock, flags);
4999 +
5000 + block_size = (req->buffer_size/req->periods) >> req->width;
5001 +
5002 + ret = -EINVAL;
5003 + if (req->req.channel >= DMAC_NR_CHANNELS
5004 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
5005 + || (req->periods == 0)
5006 + || block_size > DMAC_MAX_BLOCKSIZE) {
5007 + spin_unlock_irqrestore(&dmac->lock, flags);
5008 + return -EINVAL;
5009 + }
5010 +
5011 + chan = &dmac->channel[req->req.channel];
5012 + chan->state = CH_STATE_BUSY;
5013 + chan->is_cyclic = 1;
5014 + chan->req_cyclic = req;
5015 +
5016 + /*
5017 + * We have marked the channel as busy, so no need to keep the
5018 + * lock as long as we only touch the channel-specific
5019 + * registers
5020 + */
5021 + spin_unlock_irqrestore(&dmac->lock, flags);
5022 +
5023 + /*
5024 + Setup
5025 + */
5026 + BUG_ON(req->buffer_size % req->periods);
5027 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
5028 +
5029 + chan->nr_blocks = req->periods;
5030 +
5031 + ret = -EINVAL;
5032 + cfglo = cfghi = 0;
5033 + switch (req->direction) {
5034 + case DMA_DIR_MEM_TO_PERIPH:
5035 + direction = DMA_TO_DEVICE;
5036 + cfghi = req->periph_id << (43 - 32);
5037 + break;
5038 +
5039 + case DMA_DIR_PERIPH_TO_MEM:
5040 + direction = DMA_FROM_DEVICE;
5041 + cfghi = req->periph_id << (39 - 32);
5042 + break;
5043 + default:
5044 + goto out_unclaim_channel;
5045 + }
5046 +
5047 + chan->direction = direction;
5048 +
5049 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
5050 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
5051 +
5052 + ctlhi = block_size;
5053 + ctllo = ((req->direction << 20)
5054 + | (req->width << 4) | (req->width << 1)
5055 + | (1 << 0)); // interrupt enable
5056 +
5057 + {
5058 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
5059 +
5060 + ret = -ENOMEM;
5061 + chan->block = allocate_blocks(dmac, req->periods);
5062 + if (!chan->block)
5063 + goto out_unclaim_channel;
5064 +
5065 + if (direction == DMA_TO_DEVICE)
5066 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
5067 + else
5068 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
5069 +
5070 + /*
5071 + * Set up a linked list items where each period gets
5072 + * an item. The linked list item for the last period
5073 + * points back to the star of the buffer making a
5074 + * cyclic buffer.
5075 + */
5076 + for (i = 0; i < req->periods; i++) {
5077 + lli = chan->block[i].lli_vaddr;
5078 + if (lli_prev) {
5079 + lli_prev->llp = chan->block[i].lli_dma_addr;
5080 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
5081 + i - 1, chan->block[i - 1].lli_vaddr,
5082 + chan->block[i - 1].lli_dma_addr,
5083 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
5084 + lli_prev->ctllo, lli_prev->ctlhi);*/
5085 + }
5086 + lli->llp = 0;
5087 + lli->ctllo = ctllo;
5088 + lli->ctlhi = ctlhi;
5089 + if (direction == DMA_TO_DEVICE) {
5090 + lli->sar = req->buffer_start + i*(block_size << req->width);
5091 + lli->dar = req->data_reg;
5092 + } else {
5093 + lli->sar = req->data_reg;
5094 + lli->dar = req->buffer_start + i*(block_size << req->width);
5095 + }
5096 + lli_prev = lli;
5097 + }
5098 + lli->llp = chan->block[0].lli_dma_addr;
5099 +
5100 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
5101 + i - 1, chan->block[i - 1].lli_vaddr,
5102 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
5103 + lli_prev->dar, lli_prev->llp,
5104 + lli_prev->ctllo, lli_prev->ctlhi); */
5105 +
5106 + /*
5107 + * SAR, DAR and CTL are initialized from the LLI. We
5108 + * only have to enable the LLI bits in CTL.
5109 + */
5110 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
5111 + chan->block[0].lli_dma_addr);
5112 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
5113 + }
5114 +
5115 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
5116 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
5117 + if (req->req.block_complete)
5118 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
5119 + else
5120 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
5121 +
5122 + return 0;
5123 +
5124 +out_unclaim_channel:
5125 + chan->state = CH_STATE_ALLOCATED;
5126 + return ret;
5127 +}
5128 +
5129 +static int dmac_start_request(struct dma_controller *_dmac,
5130 + unsigned int channel)
5131 +{
5132 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
5133 +
5134 + BUG_ON(channel >= DMAC_NR_CHANNELS);
5135 +
5136 + set_channel_bit(dmac, CH_EN, channel);
5137 +
5138 + return 0;
5139 +}
5140 +
5141 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
5142 + unsigned int channel)
5143 +{
5144 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
5145 + struct dw_dma_channel *chan;
5146 + dma_addr_t current_pos;
5147 +
5148 + BUG_ON(channel >= DMAC_NR_CHANNELS);
5149 +
5150 + chan = &dmac->channel[channel];
5151 +
5152 + switch (chan->direction) {
5153 + case DMA_TO_DEVICE:
5154 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
5155 + break;
5156 + case DMA_FROM_DEVICE:
5157 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
5158 + break;
5159 + default:
5160 + return 0;
5161 + }
5162 +
5163 +
5164 + if (!current_pos) {
5165 + if (chan->is_cyclic) {
5166 + current_pos = chan->req_cyclic->buffer_start;
5167 + } else {
5168 + current_pos = chan->req_sg->sg->dma_address;
5169 + }
5170 + }
5171 +
5172 + return current_pos;
5173 +}
5174 +
5175 +
5176 +static int dmac_stop_request(struct dma_controller *_dmac,
5177 + unsigned int channel)
5178 +{
5179 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
5180 + struct dw_dma_channel *chan;
5181 +
5182 + BUG_ON(channel >= DMAC_NR_CHANNELS);
5183 +
5184 + chan = &dmac->channel[channel];
5185 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
5186 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
5187 + dmac_chan_readl_lo(dmac, channel, DAR),
5188 + dmac_chan_readl_lo(dmac, channel, LLP),
5189 + dmac_chan_readl_hi(dmac, channel, CTL),
5190 + dmac_chan_readl_lo(dmac, channel, CTL));
5191 +
5192 + if (chan->state == CH_STATE_BUSY) {
5193 + clear_channel_bit(dmac, CH_EN, channel);
5194 + cleanup_channel(dmac, &dmac->channel[channel]);
5195 + }
5196 +
5197 + return 0;
5198 +}
5199 +
5200 +
5201 +static void dmac_block_complete(struct dw_dma_controller *dmac)
5202 +{
5203 + struct dw_dma_channel *chan;
5204 + unsigned long status, chanid;
5205 +
5206 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
5207 +
5208 + while (status) {
5209 + struct dma_request *req;
5210 + chanid = __ffs(status);
5211 + chan = &dmac->channel[chanid];
5212 +
5213 + if (chan->is_cyclic) {
5214 + BUG_ON(!chan->req_cyclic
5215 + || !chan->req_cyclic->req.block_complete);
5216 + req = &chan->req_cyclic->req;
5217 + } else {
5218 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
5219 + req = &chan->req_sg->req;
5220 + }
5221 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
5222 + req->block_complete(req);
5223 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
5224 + }
5225 +}
5226 +
5227 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
5228 +{
5229 + struct dw_dma_channel *chan;
5230 + struct dma_request *req;
5231 + unsigned long status, chanid;
5232 +
5233 + status = dmac_readl_lo(dmac, STATUS_XFER);
5234 +
5235 + while (status) {
5236 + chanid = __ffs(status);
5237 + chan = &dmac->channel[chanid];
5238 +
5239 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
5240 +
5241 + req = &chan->req_sg->req;
5242 + BUG_ON(!req);
5243 + cleanup_channel(dmac, chan);
5244 + if (req->xfer_complete)
5245 + req->xfer_complete(req);
5246 +
5247 + status = dmac_readl_lo(dmac, STATUS_XFER);
5248 + }
5249 +}
5250 +
5251 +static void dmac_error(struct dw_dma_controller *dmac)
5252 +{
5253 + struct dw_dma_channel *chan;
5254 + unsigned long status, chanid;
5255 +
5256 + status = dmac_readl_lo(dmac, STATUS_ERROR);
5257 +
5258 + while (status) {
5259 + struct dma_request *req;
5260 +
5261 + chanid = __ffs(status);
5262 + chan = &dmac->channel[chanid];
5263 +
5264 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
5265 + clear_channel_bit(dmac, CH_EN, chanid);
5266 +
5267 + if (chan->is_cyclic) {
5268 + BUG_ON(!chan->req_cyclic);
5269 + req = &chan->req_cyclic->req;
5270 + } else {
5271 + BUG_ON(!chan->req_sg);
5272 + req = &chan->req_sg->req;
5273 + }
5274 +
5275 + cleanup_channel(dmac, chan);
5276 + if (req->error)
5277 + req->error(req);
5278 +
5279 + status = dmac_readl_lo(dmac, STATUS_XFER);
5280 + }
5281 +}
5282 +
5283 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
5284 +{
5285 + struct dw_dma_controller *dmac = dev_id;
5286 + unsigned long status;
5287 + int ret = IRQ_NONE;
5288 +
5289 + spin_lock(&dmac->lock);
5290 +
5291 + status = dmac_readl_lo(dmac, STATUS_INT);
5292 +
5293 + while (status) {
5294 + ret = IRQ_HANDLED;
5295 + if (status & 0x10)
5296 + dmac_error(dmac);
5297 + if (status & 0x02)
5298 + dmac_block_complete(dmac);
5299 + if (status & 0x01)
5300 + dmac_xfer_complete(dmac);
5301 +
5302 + status = dmac_readl_lo(dmac, STATUS_INT);
5303 + }
5304 +
5305 + spin_unlock(&dmac->lock);
5306 + return ret;
5307 +}
5308 +
5309 +static int __devinit dmac_probe(struct platform_device *pdev)
5310 +{
5311 + struct dw_dma_controller *dmac;
5312 + struct resource *regs;
5313 + int ret;
5314 +
5315 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5316 + if (!regs)
5317 + return -ENXIO;
5318 +
5319 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
5320 + if (!dmac)
5321 + return -ENOMEM;
5322 + memset(dmac, 0, sizeof(*dmac));
5323 +
5324 + dmac->hclk = clk_get(&pdev->dev, "hclk");
5325 + if (IS_ERR(dmac->hclk)) {
5326 + ret = PTR_ERR(dmac->hclk);
5327 + goto out_free_dmac;
5328 + }
5329 + clk_enable(dmac->hclk);
5330 +
5331 + ret = -ENOMEM;
5332 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
5333 + sizeof(struct dw_dma_lli), 4, 0);
5334 + if (!dmac->lli_pool)
5335 + goto out_disable_clk;
5336 +
5337 + spin_lock_init(&dmac->lock);
5338 + dmac->dma.dev = &pdev->dev;
5339 + dmac->dma.alloc_channel = dmac_alloc_channel;
5340 + dmac->dma.release_channel = dmac_release_channel;
5341 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
5342 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
5343 + dmac->dma.start_request = dmac_start_request;
5344 + dmac->dma.stop_request = dmac_stop_request;
5345 + dmac->dma.get_current_pos = dmac_get_current_pos;
5346 +
5347 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
5348 + if (!dmac->regs)
5349 + goto out_free_pool;
5350 +
5351 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
5352 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
5353 + if (ret)
5354 + goto out_unmap_regs;
5355 +
5356 + /* Enable the DMA controller */
5357 + dmac_writel_lo(dmac, CFG, 1);
5358 +
5359 + register_dma_controller(&dmac->dma);
5360 +
5361 + printk(KERN_INFO
5362 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
5363 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
5364 +
5365 + return 0;
5366 +
5367 +out_unmap_regs:
5368 + iounmap(dmac->regs);
5369 +out_free_pool:
5370 + dma_pool_destroy(dmac->lli_pool);
5371 +out_disable_clk:
5372 + clk_disable(dmac->hclk);
5373 + clk_put(dmac->hclk);
5374 +out_free_dmac:
5375 + kfree(dmac);
5376 + return ret;
5377 +}
5378 +
5379 +static struct platform_driver dmac_driver = {
5380 + .probe = dmac_probe,
5381 + .driver = {
5382 + .name = "dmaca",
5383 + },
5384 +};
5385 +
5386 +static int __init dmac_init(void)
5387 +{
5388 + return platform_driver_register(&dmac_driver);
5389 +}
5390 +subsys_initcall(dmac_init);
5391 +
5392 +static void __exit dmac_exit(void)
5393 +{
5394 + platform_driver_unregister(&dmac_driver);
5395 +}
5396 +module_exit(dmac_exit);
5397 +
5398 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
5399 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
5400 +MODULE_LICENSE("GPL");
5401 --- /dev/null
5402 +++ b/arch/avr32/drivers/dw-dmac.h
5403 @@ -0,0 +1,42 @@
5404 +/*
5405 + * Driver for the Synopsys DesignWare DMA Controller
5406 + *
5407 + * Copyright (C) 2005-2006 Atmel Corporation
5408 + *
5409 + * This program is free software; you can redistribute it and/or modify
5410 + * it under the terms of the GNU General Public License version 2 as
5411 + * published by the Free Software Foundation.
5412 + */
5413 +#ifndef __AVR32_DW_DMAC_H__
5414 +#define __AVR32_DW_DMAC_H__
5415 +
5416 +#define DW_DMAC_CFG 0x398
5417 +#define DW_DMAC_CH_EN 0x3a0
5418 +
5419 +#define DW_DMAC_STATUS_XFER 0x2e8
5420 +#define DW_DMAC_STATUS_BLOCK 0x2f0
5421 +#define DW_DMAC_STATUS_ERROR 0x308
5422 +
5423 +#define DW_DMAC_MASK_XFER 0x310
5424 +#define DW_DMAC_MASK_BLOCK 0x318
5425 +#define DW_DMAC_MASK_ERROR 0x330
5426 +
5427 +#define DW_DMAC_CLEAR_XFER 0x338
5428 +#define DW_DMAC_CLEAR_BLOCK 0x340
5429 +#define DW_DMAC_CLEAR_ERROR 0x358
5430 +
5431 +#define DW_DMAC_STATUS_INT 0x360
5432 +
5433 +#define DW_DMAC_CHAN_SAR 0x000
5434 +#define DW_DMAC_CHAN_DAR 0x008
5435 +#define DW_DMAC_CHAN_LLP 0x010
5436 +#define DW_DMAC_CHAN_CTL 0x018
5437 +#define DW_DMAC_CHAN_SSTAT 0x020
5438 +#define DW_DMAC_CHAN_DSTAT 0x028
5439 +#define DW_DMAC_CHAN_SSTATAR 0x030
5440 +#define DW_DMAC_CHAN_DSTATAR 0x038
5441 +#define DW_DMAC_CHAN_CFG 0x040
5442 +#define DW_DMAC_CHAN_SGR 0x048
5443 +#define DW_DMAC_CHAN_DSR 0x050
5444 +
5445 +#endif /* __AVR32_DW_DMAC_H__ */
5446 --- /dev/null
5447 +++ b/arch/avr32/drivers/Makefile
5448 @@ -0,0 +1 @@
5449 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
5450 --- a/arch/avr32/Kconfig
5451 +++ b/arch/avr32/Kconfig
5452 @@ -45,6 +45,9 @@
5453 config GENERIC_TIME
5454 def_bool y
5455
5456 +config GENERIC_CLOCKEVENTS
5457 + def_bool y
5458 +
5459 config RWSEM_XCHGADD_ALGORITHM
5460 def_bool n
5461
5462 @@ -54,6 +57,9 @@
5463 config ARCH_HAS_ILOG2_U64
5464 def_bool n
5465
5466 +config ARCH_SUPPORTS_OPROFILE
5467 + def_bool y
5468 +
5469 config GENERIC_HWEIGHT
5470 def_bool y
5471
5472 @@ -68,6 +74,8 @@
5473
5474 menu "System Type and features"
5475
5476 +source "kernel/time/Kconfig"
5477 +
5478 config SUBARCH_AVR32B
5479 bool
5480 config MMU
5481 @@ -81,19 +89,23 @@
5482 select MMU
5483 select PERFORMANCE_COUNTERS
5484
5485 -choice
5486 - prompt "AVR32 CPU type"
5487 - default CPU_AT32AP7000
5488 +#
5489 +# CPU types
5490 +#
5491
5492 -config CPU_AT32AP7000
5493 - bool "AT32AP7000"
5494 +# AP7000 derivatives
5495 +config CPU_AT32AP700X
5496 + bool
5497 select PLATFORM_AT32AP
5498 -endchoice
5499 -
5500 -#
5501 -# CPU Daughterboards for ATSTK1000
5502 -config BOARD_ATSTK1002
5503 +config CPU_AT32AP7000
5504 + bool
5505 + select CPU_AT32AP700X
5506 +config CPU_AT32AP7001
5507 + bool
5508 + select CPU_AT32AP700X
5509 +config CPU_AT32AP7002
5510 bool
5511 + select CPU_AT32AP700X
5512
5513 choice
5514 prompt "AVR32 board type"
5515 @@ -101,15 +113,18 @@
5516
5517 config BOARD_ATSTK1000
5518 bool "ATSTK1000 evaluation board"
5519 - select BOARD_ATSTK1002 if CPU_AT32AP7000
5520
5521 config BOARD_ATNGW100
5522 bool "ATNGW100 Network Gateway"
5523 + select CPU_AT32AP7000
5524 endchoice
5525
5526 if BOARD_ATSTK1000
5527 source "arch/avr32/boards/atstk1000/Kconfig"
5528 endif
5529 +if BOARD_ATNGW100
5530 +source "arch/avr32/boards/atngw100/Kconfig"
5531 +endif
5532
5533 choice
5534 prompt "Boot loader type"
5535 @@ -123,15 +138,15 @@
5536
5537 config LOAD_ADDRESS
5538 hex
5539 - default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP7000=y
5540 + default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
5541
5542 config ENTRY_ADDRESS
5543 hex
5544 - default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP7000=y
5545 + default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
5546
5547 config PHYS_OFFSET
5548 hex
5549 - default 0x10000000 if CPU_AT32AP7000=y
5550 + default 0x10000000 if CPU_AT32AP700X=y
5551
5552 source "kernel/Kconfig.preempt"
5553
5554 @@ -163,6 +178,20 @@
5555 enabling Nexus-compliant debuggers to keep track of the PID of the
5556 currently executing task.
5557
5558 +config NMI_DEBUGGING
5559 + bool "NMI Debugging"
5560 + default n
5561 + help
5562 + Say Y here and pass the nmi_debug command-line parameter to
5563 + the kernel to turn on NMI debugging. Depending on the value
5564 + of the nmi_debug option, various pieces of information will
5565 + be dumped to the console when a Non-Maskable Interrupt
5566 + happens.
5567 +
5568 +config DW_DMAC
5569 + tristate "Synopsys DesignWare DMA Controller support"
5570 + default y if CPU_AT32AP7000
5571 +
5572 # FPU emulation goes here
5573
5574 source "kernel/Kconfig.hz"
5575 @@ -219,6 +248,8 @@
5576
5577 source "fs/Kconfig"
5578
5579 +source "kernel/Kconfig.instrumentation"
5580 +
5581 source "arch/avr32/Kconfig.debug"
5582
5583 source "security/Kconfig"
5584 --- a/arch/avr32/Kconfig.debug
5585 +++ b/arch/avr32/Kconfig.debug
5586 @@ -6,14 +6,4 @@
5587
5588 source "lib/Kconfig.debug"
5589
5590 -config KPROBES
5591 - bool "Kprobes"
5592 - depends on DEBUG_KERNEL
5593 - help
5594 - Kprobes allows you to trap at almost any kernel address and
5595 - execute a callback function. register_kprobe() establishes
5596 - a probepoint and specifies the callback. Kprobes is useful
5597 - for kernel debugging, non-intrusive instrumentation and testing.
5598 - If in doubt, say "N".
5599 -
5600 endmenu
5601 --- a/arch/avr32/kernel/cpu.c
5602 +++ b/arch/avr32/kernel/cpu.c
5603 @@ -13,6 +13,7 @@
5604 #include <linux/percpu.h>
5605 #include <linux/param.h>
5606 #include <linux/errno.h>
5607 +#include <linux/clk.h>
5608
5609 #include <asm/setup.h>
5610 #include <asm/sysreg.h>
5611 @@ -187,9 +188,20 @@
5612
5613 subsys_initcall(topology_init);
5614
5615 +struct chip_id_map {
5616 + u16 mid;
5617 + u16 pn;
5618 + const char *name;
5619 +};
5620 +
5621 +static const struct chip_id_map chip_names[] = {
5622 + { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
5623 +};
5624 +#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
5625 +
5626 static const char *cpu_names[] = {
5627 "Morgan",
5628 - "AP7000",
5629 + "AP7",
5630 };
5631 #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
5632
5633 @@ -206,12 +218,32 @@
5634 "MPU"
5635 };
5636
5637 +static const char *cpu_feature_flags[] = {
5638 + "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
5639 +};
5640 +
5641 +static const char *get_chip_name(struct avr32_cpuinfo *cpu)
5642 +{
5643 + unsigned int i;
5644 + unsigned int mid = avr32_get_manufacturer_id(cpu);
5645 + unsigned int pn = avr32_get_product_number(cpu);
5646 +
5647 + for (i = 0; i < NR_CHIP_NAMES; i++) {
5648 + if (chip_names[i].mid == mid && chip_names[i].pn == pn)
5649 + return chip_names[i].name;
5650 + }
5651 +
5652 + return "(unknown)";
5653 +}
5654 +
5655 void __init setup_processor(void)
5656 {
5657 unsigned long config0, config1;
5658 unsigned long features;
5659 unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
5660 + unsigned device_id;
5661 unsigned tmp;
5662 + unsigned i;
5663
5664 config0 = sysreg_read(CONFIG0);
5665 config1 = sysreg_read(CONFIG1);
5666 @@ -221,11 +253,14 @@
5667 arch_rev = SYSREG_BFEXT(AR, config0);
5668 mmu_type = SYSREG_BFEXT(MMUT, config0);
5669
5670 + device_id = ocd_read(DID);
5671 +
5672 boot_cpu_data.arch_type = arch_id;
5673 boot_cpu_data.cpu_type = cpu_id;
5674 boot_cpu_data.arch_revision = arch_rev;
5675 boot_cpu_data.cpu_revision = cpu_rev;
5676 boot_cpu_data.tlb_config = mmu_type;
5677 + boot_cpu_data.device_id = device_id;
5678
5679 tmp = SYSREG_BFEXT(ILSZ, config1);
5680 if (tmp) {
5681 @@ -247,41 +282,34 @@
5682 return;
5683 }
5684
5685 - printk ("CPU: %s [%02x] revision %d (%s revision %d)\n",
5686 + printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
5687 + avr32_get_chip_revision(&boot_cpu_data) + 'A');
5688 + printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
5689 cpu_names[cpu_id], cpu_id, cpu_rev,
5690 arch_names[arch_id], arch_rev);
5691 printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
5692
5693 printk ("CPU: features:");
5694 features = 0;
5695 - if (config0 & SYSREG_BIT(CONFIG0_R)) {
5696 + if (config0 & SYSREG_BIT(CONFIG0_R))
5697 features |= AVR32_FEATURE_RMW;
5698 - printk(" rmw");
5699 - }
5700 - if (config0 & SYSREG_BIT(CONFIG0_D)) {
5701 + if (config0 & SYSREG_BIT(CONFIG0_D))
5702 features |= AVR32_FEATURE_DSP;
5703 - printk(" dsp");
5704 - }
5705 - if (config0 & SYSREG_BIT(CONFIG0_S)) {
5706 + if (config0 & SYSREG_BIT(CONFIG0_S))
5707 features |= AVR32_FEATURE_SIMD;
5708 - printk(" simd");
5709 - }
5710 - if (config0 & SYSREG_BIT(CONFIG0_O)) {
5711 + if (config0 & SYSREG_BIT(CONFIG0_O))
5712 features |= AVR32_FEATURE_OCD;
5713 - printk(" ocd");
5714 - }
5715 - if (config0 & SYSREG_BIT(CONFIG0_P)) {
5716 + if (config0 & SYSREG_BIT(CONFIG0_P))
5717 features |= AVR32_FEATURE_PCTR;
5718 - printk(" perfctr");
5719 - }
5720 - if (config0 & SYSREG_BIT(CONFIG0_J)) {
5721 + if (config0 & SYSREG_BIT(CONFIG0_J))
5722 features |= AVR32_FEATURE_JAVA;
5723 - printk(" java");
5724 - }
5725 - if (config0 & SYSREG_BIT(CONFIG0_F)) {
5726 + if (config0 & SYSREG_BIT(CONFIG0_F))
5727 features |= AVR32_FEATURE_FPU;
5728 - printk(" fpu");
5729 - }
5730 +
5731 + for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
5732 + if (features & (1 << i))
5733 + printk(" %s", cpu_feature_flags[i]);
5734 +
5735 printk("\n");
5736 boot_cpu_data.features = features;
5737 }
5738 @@ -291,6 +319,8 @@
5739 {
5740 unsigned int icache_size, dcache_size;
5741 unsigned int cpu = smp_processor_id();
5742 + unsigned int freq;
5743 + unsigned int i;
5744
5745 icache_size = boot_cpu_data.icache.ways *
5746 boot_cpu_data.icache.sets *
5747 @@ -301,15 +331,21 @@
5748
5749 seq_printf(m, "processor\t: %d\n", cpu);
5750
5751 + seq_printf(m, "chip type\t: %s revision %c\n",
5752 + get_chip_name(&boot_cpu_data),
5753 + avr32_get_chip_revision(&boot_cpu_data) + 'A');
5754 if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
5755 - seq_printf(m, "cpu family\t: %s revision %d\n",
5756 + seq_printf(m, "cpu arch\t: %s revision %d\n",
5757 arch_names[boot_cpu_data.arch_type],
5758 boot_cpu_data.arch_revision);
5759 if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
5760 - seq_printf(m, "cpu type\t: %s revision %d\n",
5761 + seq_printf(m, "cpu core\t: %s revision %d\n",
5762 cpu_names[boot_cpu_data.cpu_type],
5763 boot_cpu_data.cpu_revision);
5764
5765 + freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
5766 + seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
5767 +
5768 seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
5769 icache_size >> 10,
5770 boot_cpu_data.icache.ways,
5771 @@ -320,7 +356,13 @@
5772 boot_cpu_data.dcache.ways,
5773 boot_cpu_data.dcache.sets,
5774 boot_cpu_data.dcache.linesz);
5775 - seq_printf(m, "bogomips\t: %lu.%02lu\n",
5776 +
5777 + seq_printf(m, "features\t:");
5778 + for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
5779 + if (boot_cpu_data.features & (1 << i))
5780 + seq_printf(m, " %s", cpu_feature_flags[i]);
5781 +
5782 + seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
5783 boot_cpu_data.loops_per_jiffy / (500000/HZ),
5784 (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
5785
5786 @@ -343,7 +385,7 @@
5787
5788 }
5789
5790 -struct seq_operations cpuinfo_op = {
5791 +const struct seq_operations cpuinfo_op = {
5792 .start = c_start,
5793 .next = c_next,
5794 .stop = c_stop,
5795 --- /dev/null
5796 +++ b/arch/avr32/kernel/dma-controller.c
5797 @@ -0,0 +1,34 @@
5798 +/*
5799 + * Preliminary DMA controller framework for AVR32
5800 + *
5801 + * Copyright (C) 2005-2006 Atmel Corporation
5802 + *
5803 + * This program is free software; you can redistribute it and/or modify
5804 + * it under the terms of the GNU General Public License version 2 as
5805 + * published by the Free Software Foundation.
5806 + */
5807 +#include <asm/dma-controller.h>
5808 +
5809 +static LIST_HEAD(controllers);
5810 +
5811 +int register_dma_controller(struct dma_controller *dmac)
5812 +{
5813 + static int next_id;
5814 +
5815 + dmac->id = next_id++;
5816 + list_add_tail(&dmac->list, &controllers);
5817 +
5818 + return 0;
5819 +}
5820 +EXPORT_SYMBOL(register_dma_controller);
5821 +
5822 +struct dma_controller *find_dma_controller(int id)
5823 +{
5824 + struct dma_controller *dmac;
5825 +
5826 + list_for_each_entry(dmac, &controllers, list)
5827 + if (dmac->id == id)
5828 + return dmac;
5829 + return NULL;
5830 +}
5831 +EXPORT_SYMBOL(find_dma_controller);
5832 --- a/arch/avr32/kernel/entry-avr32b.S
5833 +++ b/arch/avr32/kernel/entry-avr32b.S
5834 @@ -741,26 +741,6 @@
5835
5836 .section .irq.text,"ax",@progbits
5837
5838 -.global cpu_idle_sleep
5839 -cpu_idle_sleep:
5840 - mask_interrupts
5841 - get_thread_info r8
5842 - ld.w r9, r8[TI_flags]
5843 - bld r9, TIF_NEED_RESCHED
5844 - brcs cpu_idle_enable_int_and_exit
5845 - sbr r9, TIF_CPU_GOING_TO_SLEEP
5846 - st.w r8[TI_flags], r9
5847 - unmask_interrupts
5848 - sleep 0
5849 -cpu_idle_skip_sleep:
5850 - mask_interrupts
5851 - ld.w r9, r8[TI_flags]
5852 - cbr r9, TIF_CPU_GOING_TO_SLEEP
5853 - st.w r8[TI_flags], r9
5854 -cpu_idle_enable_int_and_exit:
5855 - unmask_interrupts
5856 - retal r12
5857 -
5858 .global irq_level0
5859 .global irq_level1
5860 .global irq_level2
5861 --- a/arch/avr32/kernel/irq.c
5862 +++ b/arch/avr32/kernel/irq.c
5863 @@ -25,6 +25,17 @@
5864 printk("unexpected IRQ %u\n", irq);
5865 }
5866
5867 +/* May be overridden by platform code */
5868 +int __weak nmi_enable(void)
5869 +{
5870 + return -ENOSYS;
5871 +}
5872 +
5873 +void __weak nmi_disable(void)
5874 +{
5875 +
5876 +}
5877 +
5878 #ifdef CONFIG_PROC_FS
5879 int show_interrupts(struct seq_file *p, void *v)
5880 {
5881 --- a/arch/avr32/kernel/kprobes.c
5882 +++ b/arch/avr32/kernel/kprobes.c
5883 @@ -48,6 +48,7 @@
5884 void __kprobes arch_arm_kprobe(struct kprobe *p)
5885 {
5886 pr_debug("arming kprobe at %p\n", p->addr);
5887 + ocd_enable(NULL);
5888 *p->addr = BREAKPOINT_INSTRUCTION;
5889 flush_icache_range((unsigned long)p->addr,
5890 (unsigned long)p->addr + sizeof(kprobe_opcode_t));
5891 @@ -56,6 +57,7 @@
5892 void __kprobes arch_disarm_kprobe(struct kprobe *p)
5893 {
5894 pr_debug("disarming kprobe at %p\n", p->addr);
5895 + ocd_disable(NULL);
5896 *p->addr = p->opcode;
5897 flush_icache_range((unsigned long)p->addr,
5898 (unsigned long)p->addr + sizeof(kprobe_opcode_t));
5899 @@ -260,9 +262,6 @@
5900
5901 int __init arch_init_kprobes(void)
5902 {
5903 - printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
5904 - ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
5905 -
5906 /* TODO: Register kretprobe trampoline */
5907 return 0;
5908 }
5909 --- a/arch/avr32/kernel/Makefile
5910 +++ b/arch/avr32/kernel/Makefile
5911 @@ -6,9 +6,11 @@
5912
5913 obj-$(CONFIG_SUBARCH_AVR32B) += entry-avr32b.o
5914 obj-y += syscall_table.o syscall-stubs.o irq.o
5915 -obj-y += setup.o traps.o semaphore.o ptrace.o
5916 +obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
5917 obj-y += signal.o sys_avr32.o process.o time.o
5918 obj-y += init_task.o switch_to.o cpu.o
5919 +obj-y += dma-controller.o
5920 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
5921 obj-$(CONFIG_KPROBES) += kprobes.o
5922 obj-$(CONFIG_STACKTRACE) += stacktrace.o
5923 +obj-$(CONFIG_NMI_DEBUGGING) += nmi_debug.o
5924 --- /dev/null
5925 +++ b/arch/avr32/kernel/nmi_debug.c
5926 @@ -0,0 +1,82 @@
5927 +/*
5928 + * Copyright (C) 2007 Atmel Corporation
5929 + *
5930 + * This program is free software; you can redistribute it and/or modify
5931 + * it under the terms of the GNU General Public License version 2 as
5932 + * published by the Free Software Foundation.
5933 + */
5934 +#include <linux/delay.h>
5935 +#include <linux/kdebug.h>
5936 +#include <linux/notifier.h>
5937 +#include <linux/sched.h>
5938 +
5939 +#include <asm/irq.h>
5940 +
5941 +enum nmi_action {
5942 + NMI_SHOW_STATE = 1 << 0,
5943 + NMI_SHOW_REGS = 1 << 1,
5944 + NMI_DIE = 1 << 2,
5945 + NMI_DEBOUNCE = 1 << 3,
5946 +};
5947 +
5948 +static unsigned long nmi_actions;
5949 +
5950 +static int nmi_debug_notify(struct notifier_block *self,
5951 + unsigned long val, void *data)
5952 +{
5953 + struct die_args *args = data;
5954 +
5955 + if (likely(val != DIE_NMI))
5956 + return NOTIFY_DONE;
5957 +
5958 + if (nmi_actions & NMI_SHOW_STATE)
5959 + show_state();
5960 + if (nmi_actions & NMI_SHOW_REGS)
5961 + show_regs(args->regs);
5962 + if (nmi_actions & NMI_DEBOUNCE)
5963 + mdelay(10);
5964 + if (nmi_actions & NMI_DIE)
5965 + return NOTIFY_BAD;
5966 +
5967 + return NOTIFY_OK;
5968 +}
5969 +
5970 +static struct notifier_block nmi_debug_nb = {
5971 + .notifier_call = nmi_debug_notify,
5972 +};
5973 +
5974 +static int __init nmi_debug_setup(char *str)
5975 +{
5976 + char *p, *sep;
5977 +
5978 + register_die_notifier(&nmi_debug_nb);
5979 + if (nmi_enable()) {
5980 + printk(KERN_WARNING "Unable to enable NMI.\n");
5981 + return 0;
5982 + }
5983 +
5984 + if (*str != '=')
5985 + return 0;
5986 +
5987 + for (p = str + 1; *p; p = sep + 1) {
5988 + sep = strchr(p, ',');
5989 + if (sep)
5990 + *sep = 0;
5991 + if (strcmp(p, "state") == 0)
5992 + nmi_actions |= NMI_SHOW_STATE;
5993 + else if (strcmp(p, "regs") == 0)
5994 + nmi_actions |= NMI_SHOW_REGS;
5995 + else if (strcmp(p, "debounce") == 0)
5996 + nmi_actions |= NMI_DEBOUNCE;
5997 + else if (strcmp(p, "die") == 0)
5998 + nmi_actions |= NMI_DIE;
5999 + else
6000 + printk(KERN_WARNING "NMI: Unrecognized action `%s'\n",
6001 + p);
6002 + if (!sep)
6003 + break;
6004 + }
6005 +
6006 + return 0;
6007 +}
6008 +__setup("nmi_debug", nmi_debug_setup);
6009 --- /dev/null
6010 +++ b/arch/avr32/kernel/ocd.c
6011 @@ -0,0 +1,163 @@
6012 +/*
6013 + * Copyright (C) 2007 Atmel Corporation
6014 + *
6015 + * This program is free software; you can redistribute it and/or modify
6016 + * it under the terms of the GNU General Public License version 2 as
6017 + * published by the Free Software Foundation.
6018 + */
6019 +#include <linux/init.h>
6020 +#include <linux/sched.h>
6021 +#include <linux/spinlock.h>
6022 +
6023 +#include <asm/ocd.h>
6024 +
6025 +static long ocd_count;
6026 +static spinlock_t ocd_lock;
6027 +
6028 +/**
6029 + * ocd_enable - enable on-chip debugging
6030 + * @child: task to be debugged
6031 + *
6032 + * If @child is non-NULL, ocd_enable() first checks if debugging has
6033 + * already been enabled for @child, and if it has, does nothing.
6034 + *
6035 + * If @child is NULL (e.g. when debugging the kernel), or debugging
6036 + * has not already been enabled for it, ocd_enable() increments the
6037 + * reference count and enables the debugging hardware.
6038 + */
6039 +void ocd_enable(struct task_struct *child)
6040 +{
6041 + u32 dc;
6042 +
6043 + if (child)
6044 + pr_debug("ocd_enable: child=%s [%u]\n",
6045 + child->comm, child->pid);
6046 + else
6047 + pr_debug("ocd_enable (no child)\n");
6048 +
6049 + if (!child || !test_and_set_tsk_thread_flag(child, TIF_DEBUG)) {
6050 + spin_lock(&ocd_lock);
6051 + ocd_count++;
6052 + dc = ocd_read(DC);
6053 + dc |= (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT);
6054 + ocd_write(DC, dc);
6055 + spin_unlock(&ocd_lock);
6056 + }
6057 +}
6058 +
6059 +/**
6060 + * ocd_disable - disable on-chip debugging
6061 + * @child: task that was being debugged, but isn't anymore
6062 + *
6063 + * If @child is non-NULL, ocd_disable() checks if debugging is enabled
6064 + * for @child, and if it isn't, does nothing.
6065 + *
6066 + * If @child is NULL (e.g. when debugging the kernel), or debugging is
6067 + * enabled, ocd_disable() decrements the reference count, and if it
6068 + * reaches zero, disables the debugging hardware.
6069 + */
6070 +void ocd_disable(struct task_struct *child)
6071 +{
6072 + u32 dc;
6073 +
6074 + if (!child)
6075 + pr_debug("ocd_disable (no child)\n");
6076 + else if (test_tsk_thread_flag(child, TIF_DEBUG))
6077 + pr_debug("ocd_disable: child=%s [%u]\n",
6078 + child->comm, child->pid);
6079 +
6080 + if (!child || test_and_clear_tsk_thread_flag(child, TIF_DEBUG)) {
6081 + spin_lock(&ocd_lock);
6082 + ocd_count--;
6083 +
6084 + WARN_ON(ocd_count < 0);
6085 +
6086 + if (ocd_count <= 0) {
6087 + dc = ocd_read(DC);
6088 + dc &= ~((1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
6089 + ocd_write(DC, dc);
6090 + }
6091 + spin_unlock(&ocd_lock);
6092 + }
6093 +}
6094 +
6095 +#ifdef CONFIG_DEBUG_FS
6096 +#include <linux/debugfs.h>
6097 +#include <linux/module.h>
6098 +
6099 +static struct dentry *ocd_debugfs_root;
6100 +static struct dentry *ocd_debugfs_DC;
6101 +static struct dentry *ocd_debugfs_DS;
6102 +static struct dentry *ocd_debugfs_count;
6103 +
6104 +static u64 ocd_DC_get(void *data)
6105 +{
6106 + return ocd_read(DC);
6107 +}
6108 +static void ocd_DC_set(void *data, u64 val)
6109 +{
6110 + ocd_write(DC, val);
6111 +}
6112 +DEFINE_SIMPLE_ATTRIBUTE(fops_DC, ocd_DC_get, ocd_DC_set, "0x%08llx\n");
6113 +
6114 +static u64 ocd_DS_get(void *data)
6115 +{
6116 + return ocd_read(DS);
6117 +}
6118 +DEFINE_SIMPLE_ATTRIBUTE(fops_DS, ocd_DS_get, NULL, "0x%08llx\n");
6119 +
6120 +static u64 ocd_count_get(void *data)
6121 +{
6122 + return ocd_count;
6123 +}
6124 +DEFINE_SIMPLE_ATTRIBUTE(fops_count, ocd_count_get, NULL, "%lld\n");
6125 +
6126 +static void ocd_debugfs_init(void)
6127 +{
6128 + struct dentry *root;
6129 +
6130 + root = debugfs_create_dir("ocd", NULL);
6131 + if (IS_ERR(root) || !root)
6132 + goto err_root;
6133 + ocd_debugfs_root = root;
6134 +
6135 + ocd_debugfs_DC = debugfs_create_file("DC", S_IRUSR | S_IWUSR,
6136 + root, NULL, &fops_DC);
6137 + if (!ocd_debugfs_DC)
6138 + goto err_DC;
6139 +
6140 + ocd_debugfs_DS = debugfs_create_file("DS", S_IRUSR, root,
6141 + NULL, &fops_DS);
6142 + if (!ocd_debugfs_DS)
6143 + goto err_DS;
6144 +
6145 + ocd_debugfs_count = debugfs_create_file("count", S_IRUSR, root,
6146 + NULL, &fops_count);
6147 + if (!ocd_debugfs_count)
6148 + goto err_count;
6149 +
6150 + return;
6151 +
6152 +err_count:
6153 + debugfs_remove(ocd_debugfs_DS);
6154 +err_DS:
6155 + debugfs_remove(ocd_debugfs_DC);
6156 +err_DC:
6157 + debugfs_remove(ocd_debugfs_root);
6158 +err_root:
6159 + printk(KERN_WARNING "OCD: Failed to create debugfs entries\n");
6160 +}
6161 +#else
6162 +static inline void ocd_debugfs_init(void)
6163 +{
6164 +
6165 +}
6166 +#endif
6167 +
6168 +static int __init ocd_init(void)
6169 +{
6170 + spin_lock_init(&ocd_lock);
6171 + ocd_debugfs_init();
6172 + return 0;
6173 +}
6174 +arch_initcall(ocd_init);
6175 --- a/arch/avr32/kernel/process.c
6176 +++ b/arch/avr32/kernel/process.c
6177 @@ -11,17 +11,18 @@
6178 #include <linux/fs.h>
6179 #include <linux/ptrace.h>
6180 #include <linux/reboot.h>
6181 +#include <linux/tick.h>
6182 #include <linux/uaccess.h>
6183 #include <linux/unistd.h>
6184
6185 #include <asm/sysreg.h>
6186 #include <asm/ocd.h>
6187
6188 +#include <asm/arch/pm.h>
6189 +
6190 void (*pm_power_off)(void) = NULL;
6191 EXPORT_SYMBOL(pm_power_off);
6192
6193 -extern void cpu_idle_sleep(void);
6194 -
6195 /*
6196 * This file handles the architecture-dependent parts of process handling..
6197 */
6198 @@ -30,8 +31,10 @@
6199 {
6200 /* endless idle loop with no priority at all */
6201 while (1) {
6202 + tick_nohz_stop_sched_tick();
6203 while (!need_resched())
6204 cpu_idle_sleep();
6205 + tick_nohz_restart_sched_tick();
6206 preempt_enable_no_resched();
6207 schedule();
6208 preempt_disable();
6209 @@ -103,7 +106,7 @@
6210 */
6211 void exit_thread(void)
6212 {
6213 - /* nothing to do */
6214 + ocd_disable(current);
6215 }
6216
6217 void flush_thread(void)
6218 @@ -345,6 +348,10 @@
6219 p->thread.cpu_context.ksp = (unsigned long)childregs;
6220 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
6221
6222 + clear_tsk_thread_flag(p, TIF_DEBUG);
6223 + if ((clone_flags & CLONE_PTRACE) && test_thread_flag(TIF_DEBUG))
6224 + ocd_enable(p);
6225 +
6226 return 0;
6227 }
6228
6229 --- a/arch/avr32/kernel/ptrace.c
6230 +++ b/arch/avr32/kernel/ptrace.c
6231 @@ -58,6 +58,7 @@
6232 {
6233 clear_tsk_thread_flag(child, TIF_SINGLE_STEP);
6234 clear_tsk_thread_flag(child, TIF_BREAKPOINT);
6235 + ocd_disable(child);
6236 }
6237
6238 /*
6239 @@ -144,10 +145,6 @@
6240 {
6241 int ret;
6242
6243 - pr_debug("ptrace: Enabling monitor mode...\n");
6244 - ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
6245 - | (1 << OCD_DC_DBE_BIT));
6246 -
6247 switch (request) {
6248 /* Read the word at location addr in the child process */
6249 case PTRACE_PEEKTEXT:
6250 --- a/arch/avr32/kernel/setup.c
6251 +++ b/arch/avr32/kernel/setup.c
6252 @@ -273,6 +273,8 @@
6253 printk(KERN_WARNING
6254 "Failed to allocate framebuffer memory\n");
6255 fbmem_size = 0;
6256 + } else {
6257 + memset(__va(fbmem_start), 0, fbmem_size);
6258 }
6259 }
6260
6261 --- a/arch/avr32/kernel/signal.c
6262 +++ b/arch/avr32/kernel/signal.c
6263 @@ -270,19 +270,12 @@
6264 if (!user_mode(regs))
6265 return 0;
6266
6267 - if (try_to_freeze()) {
6268 - signr = 0;
6269 - if (!signal_pending(current))
6270 - goto no_signal;
6271 - }
6272 -
6273 if (test_thread_flag(TIF_RESTORE_SIGMASK))
6274 oldset = &current->saved_sigmask;
6275 else if (!oldset)
6276 oldset = &current->blocked;
6277
6278 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
6279 -no_signal:
6280 if (syscall) {
6281 switch (regs->r12) {
6282 case -ERESTART_RESTARTBLOCK:
6283 --- a/arch/avr32/kernel/time.c
6284 +++ b/arch/avr32/kernel/time.c
6285 @@ -1,16 +1,12 @@
6286 /*
6287 * Copyright (C) 2004-2007 Atmel Corporation
6288 *
6289 - * Based on MIPS implementation arch/mips/kernel/time.c
6290 - * Copyright 2001 MontaVista Software Inc.
6291 - *
6292 * This program is free software; you can redistribute it and/or modify
6293 * it under the terms of the GNU General Public License version 2 as
6294 * published by the Free Software Foundation.
6295 */
6296 -
6297 #include <linux/clk.h>
6298 -#include <linux/clocksource.h>
6299 +#include <linux/clockchips.h>
6300 #include <linux/time.h>
6301 #include <linux/module.h>
6302 #include <linux/interrupt.h>
6303 @@ -27,207 +23,133 @@
6304 #include <asm/io.h>
6305 #include <asm/sections.h>
6306
6307 -/* how many counter cycles in a jiffy? */
6308 -static u32 cycles_per_jiffy;
6309 +#include <asm/arch/pm.h>
6310
6311 -/* the count value for the next timer interrupt */
6312 -static u32 expirelo;
6313
6314 -cycle_t __weak read_cycle_count(void)
6315 +static cycle_t read_cycle_count(void)
6316 {
6317 return (cycle_t)sysreg_read(COUNT);
6318 }
6319
6320 -struct clocksource __weak clocksource_avr32 = {
6321 - .name = "avr32",
6322 - .rating = 350,
6323 +/*
6324 + * The architectural cycle count registers are a fine clocksource unless
6325 + * the system idle loop use sleep states like "idle": the CPU cycles
6326 + * measured by COUNT (and COMPARE) don't happen during sleep states.
6327 + * Their duration also changes if cpufreq changes the CPU clock rate.
6328 + * So we rate the clocksource using COUNT as very low quality.
6329 + */
6330 +static struct clocksource counter = {
6331 + .name = "avr32_counter",
6332 + .rating = 50,
6333 .read = read_cycle_count,
6334 .mask = CLOCKSOURCE_MASK(32),
6335 .shift = 16,
6336 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
6337 };
6338
6339 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
6340 -
6341 -struct irqaction timer_irqaction = {
6342 - .handler = timer_interrupt,
6343 - .flags = IRQF_DISABLED,
6344 - .name = "timer",
6345 -};
6346 -
6347 -/*
6348 - * By default we provide the null RTC ops
6349 - */
6350 -static unsigned long null_rtc_get_time(void)
6351 +static irqreturn_t timer_interrupt(int irq, void *dev_id)
6352 {
6353 - return mktime(2007, 1, 1, 0, 0, 0);
6354 -}
6355 -
6356 -static int null_rtc_set_time(unsigned long sec)
6357 -{
6358 - return 0;
6359 -}
6360 + struct clock_event_device *evdev = dev_id;
6361
6362 -static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
6363 -static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
6364 -
6365 -static void avr32_timer_ack(void)
6366 -{
6367 - u32 count;
6368 -
6369 - /* Ack this timer interrupt and set the next one */
6370 - expirelo += cycles_per_jiffy;
6371 - /* setting COMPARE to 0 stops the COUNT-COMPARE */
6372 - if (expirelo == 0) {
6373 - sysreg_write(COMPARE, expirelo + 1);
6374 - } else {
6375 - sysreg_write(COMPARE, expirelo);
6376 - }
6377 + /*
6378 + * Disable the interrupt until the clockevent subsystem
6379 + * reprograms it.
6380 + */
6381 + sysreg_write(COMPARE, 0);
6382
6383 - /* Check to see if we have missed any timer interrupts */
6384 - count = sysreg_read(COUNT);
6385 - if ((count - expirelo) < 0x7fffffff) {
6386 - expirelo = count + cycles_per_jiffy;
6387 - sysreg_write(COMPARE, expirelo);
6388 - }
6389 + evdev->event_handler(evdev);
6390 + return IRQ_HANDLED;
6391 }
6392
6393 -int __weak avr32_hpt_init(void)
6394 -{
6395 - int ret;
6396 - unsigned long mult, shift, count_hz;
6397 -
6398 - count_hz = clk_get_rate(boot_cpu_data.clk);
6399 - shift = clocksource_avr32.shift;
6400 - mult = clocksource_hz2mult(count_hz, shift);
6401 - clocksource_avr32.mult = mult;
6402 -
6403 - {
6404 - u64 tmp;
6405 -
6406 - tmp = TICK_NSEC;
6407 - tmp <<= shift;
6408 - tmp += mult / 2;
6409 - do_div(tmp, mult);
6410 -
6411 - cycles_per_jiffy = tmp;
6412 - }
6413 +static struct irqaction timer_irqaction = {
6414 + .handler = timer_interrupt,
6415 + .flags = IRQF_TIMER | IRQF_DISABLED,
6416 + .name = "avr32_comparator",
6417 +};
6418
6419 - ret = setup_irq(0, &timer_irqaction);
6420 - if (ret) {
6421 - pr_debug("timer: could not request IRQ 0: %d\n", ret);
6422 - return -ENODEV;
6423 - }
6424 +static int comparator_next_event(unsigned long delta,
6425 + struct clock_event_device *evdev)
6426 +{
6427 + unsigned long flags;
6428
6429 - printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
6430 - "%lu.%03lu MHz\n",
6431 - ((count_hz + 500) / 1000) / 1000,
6432 - ((count_hz + 500) / 1000) % 1000);
6433 + raw_local_irq_save(flags);
6434
6435 - return 0;
6436 -}
6437 + /* The time to read COUNT then update COMPARE must be less
6438 + * than the min_delta_ns value for this clockevent source.
6439 + */
6440 + sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
6441
6442 -/*
6443 - * Taken from MIPS c0_hpt_timer_init().
6444 - *
6445 - * The reason COUNT is written twice is probably to make sure we don't get any
6446 - * timer interrupts while we are messing with the counter.
6447 - */
6448 -int __weak avr32_hpt_start(void)
6449 -{
6450 - u32 count = sysreg_read(COUNT);
6451 - expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
6452 - sysreg_write(COUNT, expirelo - cycles_per_jiffy);
6453 - sysreg_write(COMPARE, expirelo);
6454 - sysreg_write(COUNT, count);
6455 + raw_local_irq_restore(flags);
6456
6457 return 0;
6458 }
6459
6460 -/*
6461 - * local_timer_interrupt() does profiling and process accounting on a
6462 - * per-CPU basis.
6463 - *
6464 - * In UP mode, it is invoked from the (global) timer_interrupt.
6465 - */
6466 -void local_timer_interrupt(int irq, void *dev_id)
6467 +static void comparator_mode(enum clock_event_mode mode,
6468 + struct clock_event_device *evdev)
6469 {
6470 - if (current->pid)
6471 - profile_tick(CPU_PROFILING);
6472 - update_process_times(user_mode(get_irq_regs()));
6473 + switch (mode) {
6474 + case CLOCK_EVT_MODE_ONESHOT:
6475 + pr_debug("%s: start\n", evdev->name);
6476 + /* FALLTHROUGH */
6477 + case CLOCK_EVT_MODE_RESUME:
6478 + cpu_disable_idle_sleep();
6479 + break;
6480 + case CLOCK_EVT_MODE_UNUSED:
6481 + case CLOCK_EVT_MODE_SHUTDOWN:
6482 + sysreg_write(COMPARE, 0);
6483 + pr_debug("%s: stop\n", evdev->name);
6484 + cpu_enable_idle_sleep();
6485 + break;
6486 + default:
6487 + BUG();
6488 + }
6489 }
6490
6491 -irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
6492 -{
6493 - /* ack timer interrupt and try to set next interrupt */
6494 - avr32_timer_ack();
6495 -
6496 - /*
6497 - * Call the generic timer interrupt handler
6498 - */
6499 - write_seqlock(&xtime_lock);
6500 - do_timer(1);
6501 - write_sequnlock(&xtime_lock);
6502 -
6503 - /*
6504 - * In UP mode, we call local_timer_interrupt() to do profiling
6505 - * and process accounting.
6506 - *
6507 - * SMP is not supported yet.
6508 - */
6509 - local_timer_interrupt(irq, dev_id);
6510 -
6511 - return IRQ_HANDLED;
6512 -}
6513 +static struct clock_event_device comparator = {
6514 + .name = "avr32_comparator",
6515 + .features = CLOCK_EVT_FEAT_ONESHOT,
6516 + .shift = 16,
6517 + .rating = 50,
6518 + .cpumask = CPU_MASK_CPU0,
6519 + .set_next_event = comparator_next_event,
6520 + .set_mode = comparator_mode,
6521 +};
6522
6523 void __init time_init(void)
6524 {
6525 + unsigned long counter_hz;
6526 int ret;
6527
6528 - /*
6529 - * Make sure we don't get any COMPARE interrupts before we can
6530 - * handle them.
6531 - */
6532 - sysreg_write(COMPARE, 0);
6533 -
6534 - xtime.tv_sec = rtc_get_time();
6535 + xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
6536 xtime.tv_nsec = 0;
6537
6538 set_normalized_timespec(&wall_to_monotonic,
6539 -xtime.tv_sec, -xtime.tv_nsec);
6540
6541 - ret = avr32_hpt_init();
6542 - if (ret) {
6543 - pr_debug("timer: failed setup: %d\n", ret);
6544 - return;
6545 - }
6546 + /* figure rate for counter */
6547 + counter_hz = clk_get_rate(boot_cpu_data.clk);
6548 + counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
6549
6550 - ret = clocksource_register(&clocksource_avr32);
6551 + ret = clocksource_register(&counter);
6552 if (ret)
6553 pr_debug("timer: could not register clocksource: %d\n", ret);
6554
6555 - ret = avr32_hpt_start();
6556 - if (ret) {
6557 - pr_debug("timer: failed starting: %d\n", ret);
6558 - return;
6559 - }
6560 -}
6561 + /* setup COMPARE clockevent */
6562 + comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
6563 + comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
6564 + comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
6565
6566 -static struct sysdev_class timer_class = {
6567 - set_kset_name("timer"),
6568 -};
6569 + sysreg_write(COMPARE, 0);
6570 + timer_irqaction.dev_id = &comparator;
6571
6572 -static struct sys_device timer_device = {
6573 - .id = 0,
6574 - .cls = &timer_class,
6575 -};
6576 + ret = setup_irq(0, &timer_irqaction);
6577 + if (ret)
6578 + pr_debug("timer: could not request IRQ 0: %d\n", ret);
6579 + else {
6580 + clockevents_register_device(&comparator);
6581
6582 -static int __init init_timer_sysfs(void)
6583 -{
6584 - int err = sysdev_class_register(&timer_class);
6585 - if (!err)
6586 - err = sysdev_register(&timer_device);
6587 - return err;
6588 + pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
6589 + ((counter_hz + 500) / 1000) / 1000,
6590 + ((counter_hz + 500) / 1000) % 1000);
6591 + }
6592 }
6593 -
6594 -device_initcall(init_timer_sysfs);
6595 --- a/arch/avr32/kernel/traps.c
6596 +++ b/arch/avr32/kernel/traps.c
6597 @@ -9,6 +9,7 @@
6598 #include <linux/bug.h>
6599 #include <linux/init.h>
6600 #include <linux/kallsyms.h>
6601 +#include <linux/kdebug.h>
6602 #include <linux/module.h>
6603 #include <linux/notifier.h>
6604 #include <linux/sched.h>
6605 @@ -107,9 +108,23 @@
6606
6607 asmlinkage void do_nmi(unsigned long ecr, struct pt_regs *regs)
6608 {
6609 - printk(KERN_ALERT "Got Non-Maskable Interrupt, dumping regs\n");
6610 - show_regs_log_lvl(regs, KERN_ALERT);
6611 - show_stack_log_lvl(current, regs->sp, regs, KERN_ALERT);
6612 + int ret;
6613 +
6614 + nmi_enter();
6615 +
6616 + ret = notify_die(DIE_NMI, "NMI", regs, 0, ecr, SIGINT);
6617 + switch (ret) {
6618 + case NOTIFY_OK:
6619 + case NOTIFY_STOP:
6620 + return;
6621 + case NOTIFY_BAD:
6622 + die("Fatal Non-Maskable Interrupt", regs, SIGINT);
6623 + default:
6624 + break;
6625 + }
6626 +
6627 + printk(KERN_ALERT "Got NMI, but nobody cared. Disabling...\n");
6628 + nmi_disable();
6629 }
6630
6631 asmlinkage void do_critical_exception(unsigned long ecr, struct pt_regs *regs)
6632 --- a/arch/avr32/mach-at32ap/at32ap7000.c
6633 +++ /dev/null
6634 @@ -1,1730 +0,0 @@
6635 -/*
6636 - * Copyright (C) 2005-2006 Atmel Corporation
6637 - *
6638 - * This program is free software; you can redistribute it and/or modify
6639 - * it under the terms of the GNU General Public License version 2 as
6640 - * published by the Free Software Foundation.
6641 - */
6642 -#include <linux/clk.h>
6643 -#include <linux/fb.h>
6644 -#include <linux/init.h>
6645 -#include <linux/platform_device.h>
6646 -#include <linux/dma-mapping.h>
6647 -#include <linux/spi/spi.h>
6648 -
6649 -#include <asm/io.h>
6650 -
6651 -#include <asm/arch/at32ap7000.h>
6652 -#include <asm/arch/board.h>
6653 -#include <asm/arch/portmux.h>
6654 -
6655 -#include <video/atmel_lcdc.h>
6656 -
6657 -#include "clock.h"
6658 -#include "hmatrix.h"
6659 -#include "pio.h"
6660 -#include "pm.h"
6661 -
6662 -
6663 -#define PBMEM(base) \
6664 - { \
6665 - .start = base, \
6666 - .end = base + 0x3ff, \
6667 - .flags = IORESOURCE_MEM, \
6668 - }
6669 -#define IRQ(num) \
6670 - { \
6671 - .start = num, \
6672 - .end = num, \
6673 - .flags = IORESOURCE_IRQ, \
6674 - }
6675 -#define NAMED_IRQ(num, _name) \
6676 - { \
6677 - .start = num, \
6678 - .end = num, \
6679 - .name = _name, \
6680 - .flags = IORESOURCE_IRQ, \
6681 - }
6682 -
6683 -/* REVISIT these assume *every* device supports DMA, but several
6684 - * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
6685 - */
6686 -#define DEFINE_DEV(_name, _id) \
6687 -static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
6688 -static struct platform_device _name##_id##_device = { \
6689 - .name = #_name, \
6690 - .id = _id, \
6691 - .dev = { \
6692 - .dma_mask = &_name##_id##_dma_mask, \
6693 - .coherent_dma_mask = DMA_32BIT_MASK, \
6694 - }, \
6695 - .resource = _name##_id##_resource, \
6696 - .num_resources = ARRAY_SIZE(_name##_id##_resource), \
6697 -}
6698 -#define DEFINE_DEV_DATA(_name, _id) \
6699 -static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
6700 -static struct platform_device _name##_id##_device = { \
6701 - .name = #_name, \
6702 - .id = _id, \
6703 - .dev = { \
6704 - .dma_mask = &_name##_id##_dma_mask, \
6705 - .platform_data = &_name##_id##_data, \
6706 - .coherent_dma_mask = DMA_32BIT_MASK, \
6707 - }, \
6708 - .resource = _name##_id##_resource, \
6709 - .num_resources = ARRAY_SIZE(_name##_id##_resource), \
6710 -}
6711 -
6712 -#define select_peripheral(pin, periph, flags) \
6713 - at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
6714 -
6715 -#define DEV_CLK(_name, devname, bus, _index) \
6716 -static struct clk devname##_##_name = { \
6717 - .name = #_name, \
6718 - .dev = &devname##_device.dev, \
6719 - .parent = &bus##_clk, \
6720 - .mode = bus##_clk_mode, \
6721 - .get_rate = bus##_clk_get_rate, \
6722 - .index = _index, \
6723 -}
6724 -
6725 -static DEFINE_SPINLOCK(pm_lock);
6726 -
6727 -unsigned long at32ap7000_osc_rates[3] = {
6728 - [0] = 32768,
6729 - /* FIXME: these are ATSTK1002-specific */
6730 - [1] = 20000000,
6731 - [2] = 12000000,
6732 -};
6733 -
6734 -static unsigned long osc_get_rate(struct clk *clk)
6735 -{
6736 - return at32ap7000_osc_rates[clk->index];
6737 -}
6738 -
6739 -static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
6740 -{
6741 - unsigned long div, mul, rate;
6742 -
6743 - if (!(control & PM_BIT(PLLEN)))
6744 - return 0;
6745 -
6746 - div = PM_BFEXT(PLLDIV, control) + 1;
6747 - mul = PM_BFEXT(PLLMUL, control) + 1;
6748 -
6749 - rate = clk->parent->get_rate(clk->parent);
6750 - rate = (rate + div / 2) / div;
6751 - rate *= mul;
6752 -
6753 - return rate;
6754 -}
6755 -
6756 -static unsigned long pll0_get_rate(struct clk *clk)
6757 -{
6758 - u32 control;
6759 -
6760 - control = pm_readl(PLL0);
6761 -
6762 - return pll_get_rate(clk, control);
6763 -}
6764 -
6765 -static unsigned long pll1_get_rate(struct clk *clk)
6766 -{
6767 - u32 control;
6768 -
6769 - control = pm_readl(PLL1);
6770 -
6771 - return pll_get_rate(clk, control);
6772 -}
6773 -
6774 -/*
6775 - * The AT32AP7000 has five primary clock sources: One 32kHz
6776 - * oscillator, two crystal oscillators and two PLLs.
6777 - */
6778 -static struct clk osc32k = {
6779 - .name = "osc32k",
6780 - .get_rate = osc_get_rate,
6781 - .users = 1,
6782 - .index = 0,
6783 -};
6784 -static struct clk osc0 = {
6785 - .name = "osc0",
6786 - .get_rate = osc_get_rate,
6787 - .users = 1,
6788 - .index = 1,
6789 -};
6790 -static struct clk osc1 = {
6791 - .name = "osc1",
6792 - .get_rate = osc_get_rate,
6793 - .index = 2,
6794 -};
6795 -static struct clk pll0 = {
6796 - .name = "pll0",
6797 - .get_rate = pll0_get_rate,
6798 - .parent = &osc0,
6799 -};
6800 -static struct clk pll1 = {
6801 - .name = "pll1",
6802 - .get_rate = pll1_get_rate,
6803 - .parent = &osc0,
6804 -};
6805 -
6806 -/*
6807 - * The main clock can be either osc0 or pll0. The boot loader may
6808 - * have chosen one for us, so we don't really know which one until we
6809 - * have a look at the SM.
6810 - */
6811 -static struct clk *main_clock;
6812 -
6813 -/*
6814 - * Synchronous clocks are generated from the main clock. The clocks
6815 - * must satisfy the constraint
6816 - * fCPU >= fHSB >= fPB
6817 - * i.e. each clock must not be faster than its parent.
6818 - */
6819 -static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
6820 -{
6821 - return main_clock->get_rate(main_clock) >> shift;
6822 -};
6823 -
6824 -static void cpu_clk_mode(struct clk *clk, int enabled)
6825 -{
6826 - unsigned long flags;
6827 - u32 mask;
6828 -
6829 - spin_lock_irqsave(&pm_lock, flags);
6830 - mask = pm_readl(CPU_MASK);
6831 - if (enabled)
6832 - mask |= 1 << clk->index;
6833 - else
6834 - mask &= ~(1 << clk->index);
6835 - pm_writel(CPU_MASK, mask);
6836 - spin_unlock_irqrestore(&pm_lock, flags);
6837 -}
6838 -
6839 -static unsigned long cpu_clk_get_rate(struct clk *clk)
6840 -{
6841 - unsigned long cksel, shift = 0;
6842 -
6843 - cksel = pm_readl(CKSEL);
6844 - if (cksel & PM_BIT(CPUDIV))
6845 - shift = PM_BFEXT(CPUSEL, cksel) + 1;
6846 -
6847 - return bus_clk_get_rate(clk, shift);
6848 -}
6849 -
6850 -static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
6851 -{
6852 - u32 control;
6853 - unsigned long parent_rate, child_div, actual_rate, div;
6854 -
6855 - parent_rate = clk->parent->get_rate(clk->parent);
6856 - control = pm_readl(CKSEL);
6857 -
6858 - if (control & PM_BIT(HSBDIV))
6859 - child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
6860 - else
6861 - child_div = 1;
6862 -
6863 - if (rate > 3 * (parent_rate / 4) || child_div == 1) {
6864 - actual_rate = parent_rate;
6865 - control &= ~PM_BIT(CPUDIV);
6866 - } else {
6867 - unsigned int cpusel;
6868 - div = (parent_rate + rate / 2) / rate;
6869 - if (div > child_div)
6870 - div = child_div;
6871 - cpusel = (div > 1) ? (fls(div) - 2) : 0;
6872 - control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
6873 - actual_rate = parent_rate / (1 << (cpusel + 1));
6874 - }
6875 -
6876 - pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
6877 - clk->name, rate, actual_rate);
6878 -
6879 - if (apply)
6880 - pm_writel(CKSEL, control);
6881 -
6882 - return actual_rate;
6883 -}
6884 -
6885 -static void hsb_clk_mode(struct clk *clk, int enabled)
6886 -{
6887 - unsigned long flags;
6888 - u32 mask;
6889 -
6890 - spin_lock_irqsave(&pm_lock, flags);
6891 - mask = pm_readl(HSB_MASK);
6892 - if (enabled)
6893 - mask |= 1 << clk->index;
6894 - else
6895 - mask &= ~(1 << clk->index);
6896 - pm_writel(HSB_MASK, mask);
6897 - spin_unlock_irqrestore(&pm_lock, flags);
6898 -}
6899 -
6900 -static unsigned long hsb_clk_get_rate(struct clk *clk)
6901 -{
6902 - unsigned long cksel, shift = 0;
6903 -
6904 - cksel = pm_readl(CKSEL);
6905 - if (cksel & PM_BIT(HSBDIV))
6906 - shift = PM_BFEXT(HSBSEL, cksel) + 1;
6907 -
6908 - return bus_clk_get_rate(clk, shift);
6909 -}
6910 -
6911 -static void pba_clk_mode(struct clk *clk, int enabled)
6912 -{
6913 - unsigned long flags;
6914 - u32 mask;
6915 -
6916 - spin_lock_irqsave(&pm_lock, flags);
6917 - mask = pm_readl(PBA_MASK);
6918 - if (enabled)
6919 - mask |= 1 << clk->index;
6920 - else
6921 - mask &= ~(1 << clk->index);
6922 - pm_writel(PBA_MASK, mask);
6923 - spin_unlock_irqrestore(&pm_lock, flags);
6924 -}
6925 -
6926 -static unsigned long pba_clk_get_rate(struct clk *clk)
6927 -{
6928 - unsigned long cksel, shift = 0;
6929 -
6930 - cksel = pm_readl(CKSEL);
6931 - if (cksel & PM_BIT(PBADIV))
6932 - shift = PM_BFEXT(PBASEL, cksel) + 1;
6933 -
6934 - return bus_clk_get_rate(clk, shift);
6935 -}
6936 -
6937 -static void pbb_clk_mode(struct clk *clk, int enabled)
6938 -{
6939 - unsigned long flags;
6940 - u32 mask;
6941 -
6942 - spin_lock_irqsave(&pm_lock, flags);
6943 - mask = pm_readl(PBB_MASK);
6944 - if (enabled)
6945 - mask |= 1 << clk->index;
6946 - else
6947 - mask &= ~(1 << clk->index);
6948 - pm_writel(PBB_MASK, mask);
6949 - spin_unlock_irqrestore(&pm_lock, flags);
6950 -}
6951 -
6952 -static unsigned long pbb_clk_get_rate(struct clk *clk)
6953 -{
6954 - unsigned long cksel, shift = 0;
6955 -
6956 - cksel = pm_readl(CKSEL);
6957 - if (cksel & PM_BIT(PBBDIV))
6958 - shift = PM_BFEXT(PBBSEL, cksel) + 1;
6959 -
6960 - return bus_clk_get_rate(clk, shift);
6961 -}
6962 -
6963 -static struct clk cpu_clk = {
6964 - .name = "cpu",
6965 - .get_rate = cpu_clk_get_rate,
6966 - .set_rate = cpu_clk_set_rate,
6967 - .users = 1,
6968 -};
6969 -static struct clk hsb_clk = {
6970 - .name = "hsb",
6971 - .parent = &cpu_clk,
6972 - .get_rate = hsb_clk_get_rate,
6973 -};
6974 -static struct clk pba_clk = {
6975 - .name = "pba",
6976 - .parent = &hsb_clk,
6977 - .mode = hsb_clk_mode,
6978 - .get_rate = pba_clk_get_rate,
6979 - .index = 1,
6980 -};
6981 -static struct clk pbb_clk = {
6982 - .name = "pbb",
6983 - .parent = &hsb_clk,
6984 - .mode = hsb_clk_mode,
6985 - .get_rate = pbb_clk_get_rate,
6986 - .users = 1,
6987 - .index = 2,
6988 -};
6989 -
6990 -/* --------------------------------------------------------------------
6991 - * Generic Clock operations
6992 - * -------------------------------------------------------------------- */
6993 -
6994 -static void genclk_mode(struct clk *clk, int enabled)
6995 -{
6996 - u32 control;
6997 -
6998 - control = pm_readl(GCCTRL(clk->index));
6999 - if (enabled)
7000 - control |= PM_BIT(CEN);
7001 - else
7002 - control &= ~PM_BIT(CEN);
7003 - pm_writel(GCCTRL(clk->index), control);
7004 -}
7005 -
7006 -static unsigned long genclk_get_rate(struct clk *clk)
7007 -{
7008 - u32 control;
7009 - unsigned long div = 1;
7010 -
7011 - control = pm_readl(GCCTRL(clk->index));
7012 - if (control & PM_BIT(DIVEN))
7013 - div = 2 * (PM_BFEXT(DIV, control) + 1);
7014 -
7015 - return clk->parent->get_rate(clk->parent) / div;
7016 -}
7017 -
7018 -static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
7019 -{
7020 - u32 control;
7021 - unsigned long parent_rate, actual_rate, div;
7022 -
7023 - parent_rate = clk->parent->get_rate(clk->parent);
7024 - control = pm_readl(GCCTRL(clk->index));
7025 -
7026 - if (rate > 3 * parent_rate / 4) {
7027 - actual_rate = parent_rate;
7028 - control &= ~PM_BIT(DIVEN);
7029 - } else {
7030 - div = (parent_rate + rate) / (2 * rate) - 1;
7031 - control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
7032 - actual_rate = parent_rate / (2 * (div + 1));
7033 - }
7034 -
7035 - dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
7036 - clk->name, rate, actual_rate);
7037 -
7038 - if (apply)
7039 - pm_writel(GCCTRL(clk->index), control);
7040 -
7041 - return actual_rate;
7042 -}
7043 -
7044 -int genclk_set_parent(struct clk *clk, struct clk *parent)
7045 -{
7046 - u32 control;
7047 -
7048 - dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
7049 - clk->name, parent->name, clk->parent->name);
7050 -
7051 - control = pm_readl(GCCTRL(clk->index));
7052 -
7053 - if (parent == &osc1 || parent == &pll1)
7054 - control |= PM_BIT(OSCSEL);
7055 - else if (parent == &osc0 || parent == &pll0)
7056 - control &= ~PM_BIT(OSCSEL);
7057 - else
7058 - return -EINVAL;
7059 -
7060 - if (parent == &pll0 || parent == &pll1)
7061 - control |= PM_BIT(PLLSEL);
7062 - else
7063 - control &= ~PM_BIT(PLLSEL);
7064 -
7065 - pm_writel(GCCTRL(clk->index), control);
7066 - clk->parent = parent;
7067 -
7068 - return 0;
7069 -}
7070 -
7071 -static void __init genclk_init_parent(struct clk *clk)
7072 -{
7073 - u32 control;
7074 - struct clk *parent;
7075 -
7076 - BUG_ON(clk->index > 7);
7077 -
7078 - control = pm_readl(GCCTRL(clk->index));
7079 - if (control & PM_BIT(OSCSEL))
7080 - parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
7081 - else
7082 - parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
7083 -
7084 - clk->parent = parent;
7085 -}
7086 -
7087 -/* --------------------------------------------------------------------
7088 - * System peripherals
7089 - * -------------------------------------------------------------------- */
7090 -static struct resource at32_pm0_resource[] = {
7091 - {
7092 - .start = 0xfff00000,
7093 - .end = 0xfff0007f,
7094 - .flags = IORESOURCE_MEM,
7095 - },
7096 - IRQ(20),
7097 -};
7098 -
7099 -static struct resource at32ap700x_rtc0_resource[] = {
7100 - {
7101 - .start = 0xfff00080,
7102 - .end = 0xfff000af,
7103 - .flags = IORESOURCE_MEM,
7104 - },
7105 - IRQ(21),
7106 -};
7107 -
7108 -static struct resource at32_wdt0_resource[] = {
7109 - {
7110 - .start = 0xfff000b0,
7111 - .end = 0xfff000cf,
7112 - .flags = IORESOURCE_MEM,
7113 - },
7114 -};
7115 -
7116 -static struct resource at32_eic0_resource[] = {
7117 - {
7118 - .start = 0xfff00100,
7119 - .end = 0xfff0013f,
7120 - .flags = IORESOURCE_MEM,
7121 - },
7122 - IRQ(19),
7123 -};
7124 -
7125 -DEFINE_DEV(at32_pm, 0);
7126 -DEFINE_DEV(at32ap700x_rtc, 0);
7127 -DEFINE_DEV(at32_wdt, 0);
7128 -DEFINE_DEV(at32_eic, 0);
7129 -
7130 -/*
7131 - * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
7132 - * is always running.
7133 - */
7134 -static struct clk at32_pm_pclk = {
7135 - .name = "pclk",
7136 - .dev = &at32_pm0_device.dev,
7137 - .parent = &pbb_clk,
7138 - .mode = pbb_clk_mode,
7139 - .get_rate = pbb_clk_get_rate,
7140 - .users = 1,
7141 - .index = 0,
7142 -};
7143 -
7144 -static struct resource intc0_resource[] = {
7145 - PBMEM(0xfff00400),
7146 -};
7147 -struct platform_device at32_intc0_device = {
7148 - .name = "intc",
7149 - .id = 0,
7150 - .resource = intc0_resource,
7151 - .num_resources = ARRAY_SIZE(intc0_resource),
7152 -};
7153 -DEV_CLK(pclk, at32_intc0, pbb, 1);
7154 -
7155 -static struct clk ebi_clk = {
7156 - .name = "ebi",
7157 - .parent = &hsb_clk,
7158 - .mode = hsb_clk_mode,
7159 - .get_rate = hsb_clk_get_rate,
7160 - .users = 1,
7161 -};
7162 -static struct clk hramc_clk = {
7163 - .name = "hramc",
7164 - .parent = &hsb_clk,
7165 - .mode = hsb_clk_mode,
7166 - .get_rate = hsb_clk_get_rate,
7167 - .users = 1,
7168 - .index = 3,
7169 -};
7170 -
7171 -static struct resource smc0_resource[] = {
7172 - PBMEM(0xfff03400),
7173 -};
7174 -DEFINE_DEV(smc, 0);
7175 -DEV_CLK(pclk, smc0, pbb, 13);
7176 -DEV_CLK(mck, smc0, hsb, 0);
7177 -
7178 -static struct platform_device pdc_device = {
7179 - .name = "pdc",
7180 - .id = 0,
7181 -};
7182 -DEV_CLK(hclk, pdc, hsb, 4);
7183 -DEV_CLK(pclk, pdc, pba, 16);
7184 -
7185 -static struct clk pico_clk = {
7186 - .name = "pico",
7187 - .parent = &cpu_clk,
7188 - .mode = cpu_clk_mode,
7189 - .get_rate = cpu_clk_get_rate,
7190 - .users = 1,
7191 -};
7192 -
7193 -static struct resource dmaca0_resource[] = {
7194 - {
7195 - .start = 0xff200000,
7196 - .end = 0xff20ffff,
7197 - .flags = IORESOURCE_MEM,
7198 - },
7199 - IRQ(2),
7200 -};
7201 -DEFINE_DEV(dmaca, 0);
7202 -DEV_CLK(hclk, dmaca0, hsb, 10);
7203 -
7204 -/* --------------------------------------------------------------------
7205 - * HMATRIX
7206 - * -------------------------------------------------------------------- */
7207 -
7208 -static struct clk hmatrix_clk = {
7209 - .name = "hmatrix_clk",
7210 - .parent = &pbb_clk,
7211 - .mode = pbb_clk_mode,
7212 - .get_rate = pbb_clk_get_rate,
7213 - .index = 2,
7214 - .users = 1,
7215 -};
7216 -#define HMATRIX_BASE ((void __iomem *)0xfff00800)
7217 -
7218 -#define hmatrix_readl(reg) \
7219 - __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
7220 -#define hmatrix_writel(reg,value) \
7221 - __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
7222 -
7223 -/*
7224 - * Set bits in the HMATRIX Special Function Register (SFR) used by the
7225 - * External Bus Interface (EBI). This can be used to enable special
7226 - * features like CompactFlash support, NAND Flash support, etc. on
7227 - * certain chipselects.
7228 - */
7229 -static inline void set_ebi_sfr_bits(u32 mask)
7230 -{
7231 - u32 sfr;
7232 -
7233 - clk_enable(&hmatrix_clk);
7234 - sfr = hmatrix_readl(SFR4);
7235 - sfr |= mask;
7236 - hmatrix_writel(SFR4, sfr);
7237 - clk_disable(&hmatrix_clk);
7238 -}
7239 -
7240 -/* --------------------------------------------------------------------
7241 - * System Timer/Counter (TC)
7242 - * -------------------------------------------------------------------- */
7243 -static struct resource at32_systc0_resource[] = {
7244 - PBMEM(0xfff00c00),
7245 - IRQ(22),
7246 -};
7247 -struct platform_device at32_systc0_device = {
7248 - .name = "systc",
7249 - .id = 0,
7250 - .resource = at32_systc0_resource,
7251 - .num_resources = ARRAY_SIZE(at32_systc0_resource),
7252 -};
7253 -DEV_CLK(pclk, at32_systc0, pbb, 3);
7254 -
7255 -/* --------------------------------------------------------------------
7256 - * PIO
7257 - * -------------------------------------------------------------------- */
7258 -
7259 -static struct resource pio0_resource[] = {
7260 - PBMEM(0xffe02800),
7261 - IRQ(13),
7262 -};
7263 -DEFINE_DEV(pio, 0);
7264 -DEV_CLK(mck, pio0, pba, 10);
7265 -
7266 -static struct resource pio1_resource[] = {
7267 - PBMEM(0xffe02c00),
7268 - IRQ(14),
7269 -};
7270 -DEFINE_DEV(pio, 1);
7271 -DEV_CLK(mck, pio1, pba, 11);
7272 -
7273 -static struct resource pio2_resource[] = {
7274 - PBMEM(0xffe03000),
7275 - IRQ(15),
7276 -};
7277 -DEFINE_DEV(pio, 2);
7278 -DEV_CLK(mck, pio2, pba, 12);
7279 -
7280 -static struct resource pio3_resource[] = {
7281 - PBMEM(0xffe03400),
7282 - IRQ(16),
7283 -};
7284 -DEFINE_DEV(pio, 3);
7285 -DEV_CLK(mck, pio3, pba, 13);
7286 -
7287 -static struct resource pio4_resource[] = {
7288 - PBMEM(0xffe03800),
7289 - IRQ(17),
7290 -};
7291 -DEFINE_DEV(pio, 4);
7292 -DEV_CLK(mck, pio4, pba, 14);
7293 -
7294 -void __init at32_add_system_devices(void)
7295 -{
7296 - platform_device_register(&at32_pm0_device);
7297 - platform_device_register(&at32_intc0_device);
7298 - platform_device_register(&at32ap700x_rtc0_device);
7299 - platform_device_register(&at32_wdt0_device);
7300 - platform_device_register(&at32_eic0_device);
7301 - platform_device_register(&smc0_device);
7302 - platform_device_register(&pdc_device);
7303 - platform_device_register(&dmaca0_device);
7304 -
7305 - platform_device_register(&at32_systc0_device);
7306 -
7307 - platform_device_register(&pio0_device);
7308 - platform_device_register(&pio1_device);
7309 - platform_device_register(&pio2_device);
7310 - platform_device_register(&pio3_device);
7311 - platform_device_register(&pio4_device);
7312 -}
7313 -
7314 -/* --------------------------------------------------------------------
7315 - * USART
7316 - * -------------------------------------------------------------------- */
7317 -
7318 -static struct atmel_uart_data atmel_usart0_data = {
7319 - .use_dma_tx = 1,
7320 - .use_dma_rx = 1,
7321 -};
7322 -static struct resource atmel_usart0_resource[] = {
7323 - PBMEM(0xffe00c00),
7324 - IRQ(6),
7325 -};
7326 -DEFINE_DEV_DATA(atmel_usart, 0);
7327 -DEV_CLK(usart, atmel_usart0, pba, 3);
7328 -
7329 -static struct atmel_uart_data atmel_usart1_data = {
7330 - .use_dma_tx = 1,
7331 - .use_dma_rx = 1,
7332 -};
7333 -static struct resource atmel_usart1_resource[] = {
7334 - PBMEM(0xffe01000),
7335 - IRQ(7),
7336 -};
7337 -DEFINE_DEV_DATA(atmel_usart, 1);
7338 -DEV_CLK(usart, atmel_usart1, pba, 4);
7339 -
7340 -static struct atmel_uart_data atmel_usart2_data = {
7341 - .use_dma_tx = 1,
7342 - .use_dma_rx = 1,
7343 -};
7344 -static struct resource atmel_usart2_resource[] = {
7345 - PBMEM(0xffe01400),
7346 - IRQ(8),
7347 -};
7348 -DEFINE_DEV_DATA(atmel_usart, 2);
7349 -DEV_CLK(usart, atmel_usart2, pba, 5);
7350 -
7351 -static struct atmel_uart_data atmel_usart3_data = {
7352 - .use_dma_tx = 1,
7353 - .use_dma_rx = 1,
7354 -};
7355 -static struct resource atmel_usart3_resource[] = {
7356 - PBMEM(0xffe01800),
7357 - IRQ(9),
7358 -};
7359 -DEFINE_DEV_DATA(atmel_usart, 3);
7360 -DEV_CLK(usart, atmel_usart3, pba, 6);
7361 -
7362 -static inline void configure_usart0_pins(void)
7363 -{
7364 - select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
7365 - select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
7366 -}
7367 -
7368 -static inline void configure_usart1_pins(void)
7369 -{
7370 - select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
7371 - select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
7372 -}
7373 -
7374 -static inline void configure_usart2_pins(void)
7375 -{
7376 - select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
7377 - select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
7378 -}
7379 -
7380 -static inline void configure_usart3_pins(void)
7381 -{
7382 - select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
7383 - select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
7384 -}
7385 -
7386 -static struct platform_device *__initdata at32_usarts[4];
7387 -
7388 -void __init at32_map_usart(unsigned int hw_id, unsigned int line)
7389 -{
7390 - struct platform_device *pdev;
7391 -
7392 - switch (hw_id) {
7393 - case 0:
7394 - pdev = &atmel_usart0_device;
7395 - configure_usart0_pins();
7396 - break;
7397 - case 1:
7398 - pdev = &atmel_usart1_device;
7399 - configure_usart1_pins();
7400 - break;
7401 - case 2:
7402 - pdev = &atmel_usart2_device;
7403 - configure_usart2_pins();
7404 - break;
7405 - case 3:
7406 - pdev = &atmel_usart3_device;
7407 - configure_usart3_pins();
7408 - break;
7409 - default:
7410 - return;
7411 - }
7412 -
7413 - if (PXSEG(pdev->resource[0].start) == P4SEG) {
7414 - /* Addresses in the P4 segment are permanently mapped 1:1 */
7415 - struct atmel_uart_data *data = pdev->dev.platform_data;
7416 - data->regs = (void __iomem *)pdev->resource[0].start;
7417 - }
7418 -
7419 - pdev->id = line;
7420 - at32_usarts[line] = pdev;
7421 -}
7422 -
7423 -struct platform_device *__init at32_add_device_usart(unsigned int id)
7424 -{
7425 - platform_device_register(at32_usarts[id]);
7426 - return at32_usarts[id];
7427 -}
7428 -
7429 -struct platform_device *atmel_default_console_device;
7430 -
7431 -void __init at32_setup_serial_console(unsigned int usart_id)
7432 -{
7433 - atmel_default_console_device = at32_usarts[usart_id];
7434 -}
7435 -
7436 -/* --------------------------------------------------------------------
7437 - * Ethernet
7438 - * -------------------------------------------------------------------- */
7439 -
7440 -static struct eth_platform_data macb0_data;
7441 -static struct resource macb0_resource[] = {
7442 - PBMEM(0xfff01800),
7443 - IRQ(25),
7444 -};
7445 -DEFINE_DEV_DATA(macb, 0);
7446 -DEV_CLK(hclk, macb0, hsb, 8);
7447 -DEV_CLK(pclk, macb0, pbb, 6);
7448 -
7449 -static struct eth_platform_data macb1_data;
7450 -static struct resource macb1_resource[] = {
7451 - PBMEM(0xfff01c00),
7452 - IRQ(26),
7453 -};
7454 -DEFINE_DEV_DATA(macb, 1);
7455 -DEV_CLK(hclk, macb1, hsb, 9);
7456 -DEV_CLK(pclk, macb1, pbb, 7);
7457 -
7458 -struct platform_device *__init
7459 -at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
7460 -{
7461 - struct platform_device *pdev;
7462 -
7463 - switch (id) {
7464 - case 0:
7465 - pdev = &macb0_device;
7466 -
7467 - select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
7468 - select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
7469 - select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
7470 - select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
7471 - select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
7472 - select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
7473 - select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
7474 - select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
7475 - select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
7476 - select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
7477 -
7478 - if (!data->is_rmii) {
7479 - select_peripheral(PC(0), PERIPH_A, 0); /* COL */
7480 - select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
7481 - select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
7482 - select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
7483 - select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
7484 - select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
7485 - select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
7486 - select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
7487 - select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
7488 - }
7489 - break;
7490 -
7491 - case 1:
7492 - pdev = &macb1_device;
7493 -
7494 - select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
7495 - select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
7496 - select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
7497 - select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
7498 - select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
7499 - select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
7500 - select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
7501 - select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
7502 - select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
7503 - select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
7504 -
7505 - if (!data->is_rmii) {
7506 - select_peripheral(PC(19), PERIPH_B, 0); /* COL */
7507 - select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
7508 - select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
7509 - select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
7510 - select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
7511 - select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
7512 - select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
7513 - select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
7514 - select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
7515 - }
7516 - break;
7517 -
7518 - default:
7519 - return NULL;
7520 - }
7521 -
7522 - memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
7523 - platform_device_register(pdev);
7524 -
7525 - return pdev;
7526 -}
7527 -
7528 -/* --------------------------------------------------------------------
7529 - * SPI
7530 - * -------------------------------------------------------------------- */
7531 -static struct resource atmel_spi0_resource[] = {
7532 - PBMEM(0xffe00000),
7533 - IRQ(3),
7534 -};
7535 -DEFINE_DEV(atmel_spi, 0);
7536 -DEV_CLK(spi_clk, atmel_spi0, pba, 0);
7537 -
7538 -static struct resource atmel_spi1_resource[] = {
7539 - PBMEM(0xffe00400),
7540 - IRQ(4),
7541 -};
7542 -DEFINE_DEV(atmel_spi, 1);
7543 -DEV_CLK(spi_clk, atmel_spi1, pba, 1);
7544 -
7545 -static void __init
7546 -at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
7547 - unsigned int n, const u8 *pins)
7548 -{
7549 - unsigned int pin, mode;
7550 -
7551 - for (; n; n--, b++) {
7552 - b->bus_num = bus_num;
7553 - if (b->chip_select >= 4)
7554 - continue;
7555 - pin = (unsigned)b->controller_data;
7556 - if (!pin) {
7557 - pin = pins[b->chip_select];
7558 - b->controller_data = (void *)pin;
7559 - }
7560 - mode = AT32_GPIOF_OUTPUT;
7561 - if (!(b->mode & SPI_CS_HIGH))
7562 - mode |= AT32_GPIOF_HIGH;
7563 - at32_select_gpio(pin, mode);
7564 - }
7565 -}
7566 -
7567 -struct platform_device *__init
7568 -at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
7569 -{
7570 - /*
7571 - * Manage the chipselects as GPIOs, normally using the same pins
7572 - * the SPI controller expects; but boards can use other pins.
7573 - */
7574 - static u8 __initdata spi0_pins[] =
7575 - { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
7576 - GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
7577 - static u8 __initdata spi1_pins[] =
7578 - { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
7579 - GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
7580 - struct platform_device *pdev;
7581 -
7582 - switch (id) {
7583 - case 0:
7584 - pdev = &atmel_spi0_device;
7585 - select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
7586 - select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
7587 - select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
7588 - at32_spi_setup_slaves(0, b, n, spi0_pins);
7589 - break;
7590 -
7591 - case 1:
7592 - pdev = &atmel_spi1_device;
7593 - select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
7594 - select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
7595 - select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
7596 - at32_spi_setup_slaves(1, b, n, spi1_pins);
7597 - break;
7598 -
7599 - default:
7600 - return NULL;
7601 - }
7602 -
7603 - spi_register_board_info(b, n);
7604 - platform_device_register(pdev);
7605 - return pdev;
7606 -}
7607 -
7608 -/* --------------------------------------------------------------------
7609 - * TWI
7610 - * -------------------------------------------------------------------- */
7611 -static struct resource atmel_twi0_resource[] __initdata = {
7612 - PBMEM(0xffe00800),
7613 - IRQ(5),
7614 -};
7615 -static struct clk atmel_twi0_pclk = {
7616 - .name = "twi_pclk",
7617 - .parent = &pba_clk,
7618 - .mode = pba_clk_mode,
7619 - .get_rate = pba_clk_get_rate,
7620 - .index = 2,
7621 -};
7622 -
7623 -struct platform_device *__init at32_add_device_twi(unsigned int id)
7624 -{
7625 - struct platform_device *pdev;
7626 -
7627 - if (id != 0)
7628 - return NULL;
7629 -
7630 - pdev = platform_device_alloc("atmel_twi", id);
7631 - if (!pdev)
7632 - return NULL;
7633 -
7634 - if (platform_device_add_resources(pdev, atmel_twi0_resource,
7635 - ARRAY_SIZE(atmel_twi0_resource)))
7636 - goto err_add_resources;
7637 -
7638 - select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
7639 - select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
7640 -
7641 - atmel_twi0_pclk.dev = &pdev->dev;
7642 -
7643 - platform_device_add(pdev);
7644 - return pdev;
7645 -
7646 -err_add_resources:
7647 - platform_device_put(pdev);
7648 - return NULL;
7649 -}
7650 -
7651 -/* --------------------------------------------------------------------
7652 - * MMC
7653 - * -------------------------------------------------------------------- */
7654 -static struct resource atmel_mci0_resource[] __initdata = {
7655 - PBMEM(0xfff02400),
7656 - IRQ(28),
7657 -};
7658 -static struct clk atmel_mci0_pclk = {
7659 - .name = "mci_clk",
7660 - .parent = &pbb_clk,
7661 - .mode = pbb_clk_mode,
7662 - .get_rate = pbb_clk_get_rate,
7663 - .index = 9,
7664 -};
7665 -
7666 -struct platform_device *__init at32_add_device_mci(unsigned int id)
7667 -{
7668 - struct platform_device *pdev;
7669 -
7670 - if (id != 0)
7671 - return NULL;
7672 -
7673 - pdev = platform_device_alloc("atmel_mci", id);
7674 - if (!pdev)
7675 - return NULL;
7676 -
7677 - if (platform_device_add_resources(pdev, atmel_mci0_resource,
7678 - ARRAY_SIZE(atmel_mci0_resource)))
7679 - goto err_add_resources;
7680 -
7681 - select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
7682 - select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
7683 - select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
7684 - select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
7685 - select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
7686 - select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
7687 -
7688 - atmel_mci0_pclk.dev = &pdev->dev;
7689 -
7690 - platform_device_add(pdev);
7691 - return pdev;
7692 -
7693 -err_add_resources:
7694 - platform_device_put(pdev);
7695 - return NULL;
7696 -}
7697 -
7698 -/* --------------------------------------------------------------------
7699 - * LCDC
7700 - * -------------------------------------------------------------------- */
7701 -static struct atmel_lcdfb_info atmel_lcdfb0_data;
7702 -static struct resource atmel_lcdfb0_resource[] = {
7703 - {
7704 - .start = 0xff000000,
7705 - .end = 0xff000fff,
7706 - .flags = IORESOURCE_MEM,
7707 - },
7708 - IRQ(1),
7709 - {
7710 - /* Placeholder for pre-allocated fb memory */
7711 - .start = 0x00000000,
7712 - .end = 0x00000000,
7713 - .flags = 0,
7714 - },
7715 -};
7716 -DEFINE_DEV_DATA(atmel_lcdfb, 0);
7717 -DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
7718 -static struct clk atmel_lcdfb0_pixclk = {
7719 - .name = "lcdc_clk",
7720 - .dev = &atmel_lcdfb0_device.dev,
7721 - .mode = genclk_mode,
7722 - .get_rate = genclk_get_rate,
7723 - .set_rate = genclk_set_rate,
7724 - .set_parent = genclk_set_parent,
7725 - .index = 7,
7726 -};
7727 -
7728 -struct platform_device *__init
7729 -at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
7730 - unsigned long fbmem_start, unsigned long fbmem_len)
7731 -{
7732 - struct platform_device *pdev;
7733 - struct atmel_lcdfb_info *info;
7734 - struct fb_monspecs *monspecs;
7735 - struct fb_videomode *modedb;
7736 - unsigned int modedb_size;
7737 -
7738 - /*
7739 - * Do a deep copy of the fb data, monspecs and modedb. Make
7740 - * sure all allocations are done before setting up the
7741 - * portmux.
7742 - */
7743 - monspecs = kmemdup(data->default_monspecs,
7744 - sizeof(struct fb_monspecs), GFP_KERNEL);
7745 - if (!monspecs)
7746 - return NULL;
7747 -
7748 - modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
7749 - modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
7750 - if (!modedb)
7751 - goto err_dup_modedb;
7752 - monspecs->modedb = modedb;
7753 -
7754 - switch (id) {
7755 - case 0:
7756 - pdev = &atmel_lcdfb0_device;
7757 - select_peripheral(PC(19), PERIPH_A, 0); /* CC */
7758 - select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
7759 - select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
7760 - select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
7761 - select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
7762 - select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
7763 - select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
7764 - select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
7765 - select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
7766 - select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
7767 - select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
7768 - select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
7769 - select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
7770 - select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
7771 - select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
7772 - select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
7773 - select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
7774 - select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
7775 - select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
7776 - select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
7777 - select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
7778 - select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
7779 - select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
7780 - select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
7781 - select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
7782 - select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
7783 - select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
7784 - select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
7785 - select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
7786 - select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
7787 - select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
7788 -
7789 - clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
7790 - clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
7791 - break;
7792 -
7793 - default:
7794 - goto err_invalid_id;
7795 - }
7796 -
7797 - if (fbmem_len) {
7798 - pdev->resource[2].start = fbmem_start;
7799 - pdev->resource[2].end = fbmem_start + fbmem_len - 1;
7800 - pdev->resource[2].flags = IORESOURCE_MEM;
7801 - }
7802 -
7803 - info = pdev->dev.platform_data;
7804 - memcpy(info, data, sizeof(struct atmel_lcdfb_info));
7805 - info->default_monspecs = monspecs;
7806 -
7807 - platform_device_register(pdev);
7808 - return pdev;
7809 -
7810 -err_invalid_id:
7811 - kfree(modedb);
7812 -err_dup_modedb:
7813 - kfree(monspecs);
7814 - return NULL;
7815 -}
7816 -
7817 -/* --------------------------------------------------------------------
7818 - * SSC
7819 - * -------------------------------------------------------------------- */
7820 -static struct resource ssc0_resource[] = {
7821 - PBMEM(0xffe01c00),
7822 - IRQ(10),
7823 -};
7824 -DEFINE_DEV(ssc, 0);
7825 -DEV_CLK(pclk, ssc0, pba, 7);
7826 -
7827 -static struct resource ssc1_resource[] = {
7828 - PBMEM(0xffe02000),
7829 - IRQ(11),
7830 -};
7831 -DEFINE_DEV(ssc, 1);
7832 -DEV_CLK(pclk, ssc1, pba, 8);
7833 -
7834 -static struct resource ssc2_resource[] = {
7835 - PBMEM(0xffe02400),
7836 - IRQ(12),
7837 -};
7838 -DEFINE_DEV(ssc, 2);
7839 -DEV_CLK(pclk, ssc2, pba, 9);
7840 -
7841 -struct platform_device *__init
7842 -at32_add_device_ssc(unsigned int id, unsigned int flags)
7843 -{
7844 - struct platform_device *pdev;
7845 -
7846 - switch (id) {
7847 - case 0:
7848 - pdev = &ssc0_device;
7849 - if (flags & ATMEL_SSC_RF)
7850 - select_peripheral(PA(21), PERIPH_A, 0); /* RF */
7851 - if (flags & ATMEL_SSC_RK)
7852 - select_peripheral(PA(22), PERIPH_A, 0); /* RK */
7853 - if (flags & ATMEL_SSC_TK)
7854 - select_peripheral(PA(23), PERIPH_A, 0); /* TK */
7855 - if (flags & ATMEL_SSC_TF)
7856 - select_peripheral(PA(24), PERIPH_A, 0); /* TF */
7857 - if (flags & ATMEL_SSC_TD)
7858 - select_peripheral(PA(25), PERIPH_A, 0); /* TD */
7859 - if (flags & ATMEL_SSC_RD)
7860 - select_peripheral(PA(26), PERIPH_A, 0); /* RD */
7861 - break;
7862 - case 1:
7863 - pdev = &ssc1_device;
7864 - if (flags & ATMEL_SSC_RF)
7865 - select_peripheral(PA(0), PERIPH_B, 0); /* RF */
7866 - if (flags & ATMEL_SSC_RK)
7867 - select_peripheral(PA(1), PERIPH_B, 0); /* RK */
7868 - if (flags & ATMEL_SSC_TK)
7869 - select_peripheral(PA(2), PERIPH_B, 0); /* TK */
7870 - if (flags & ATMEL_SSC_TF)
7871 - select_peripheral(PA(3), PERIPH_B, 0); /* TF */
7872 - if (flags & ATMEL_SSC_TD)
7873 - select_peripheral(PA(4), PERIPH_B, 0); /* TD */
7874 - if (flags & ATMEL_SSC_RD)
7875 - select_peripheral(PA(5), PERIPH_B, 0); /* RD */
7876 - break;
7877 - case 2:
7878 - pdev = &ssc2_device;
7879 - if (flags & ATMEL_SSC_TD)
7880 - select_peripheral(PB(13), PERIPH_A, 0); /* TD */
7881 - if (flags & ATMEL_SSC_RD)
7882 - select_peripheral(PB(14), PERIPH_A, 0); /* RD */
7883 - if (flags & ATMEL_SSC_TK)
7884 - select_peripheral(PB(15), PERIPH_A, 0); /* TK */
7885 - if (flags & ATMEL_SSC_TF)
7886 - select_peripheral(PB(16), PERIPH_A, 0); /* TF */
7887 - if (flags & ATMEL_SSC_RF)
7888 - select_peripheral(PB(17), PERIPH_A, 0); /* RF */
7889 - if (flags & ATMEL_SSC_RK)
7890 - select_peripheral(PB(18), PERIPH_A, 0); /* RK */
7891 - break;
7892 - default:
7893 - return NULL;
7894 - }
7895 -
7896 - platform_device_register(pdev);
7897 - return pdev;
7898 -}
7899 -
7900 -/* --------------------------------------------------------------------
7901 - * USB Device Controller
7902 - * -------------------------------------------------------------------- */
7903 -static struct resource usba0_resource[] __initdata = {
7904 - {
7905 - .start = 0xff300000,
7906 - .end = 0xff3fffff,
7907 - .flags = IORESOURCE_MEM,
7908 - }, {
7909 - .start = 0xfff03000,
7910 - .end = 0xfff033ff,
7911 - .flags = IORESOURCE_MEM,
7912 - },
7913 - IRQ(31),
7914 -};
7915 -static struct clk usba0_pclk = {
7916 - .name = "pclk",
7917 - .parent = &pbb_clk,
7918 - .mode = pbb_clk_mode,
7919 - .get_rate = pbb_clk_get_rate,
7920 - .index = 12,
7921 -};
7922 -static struct clk usba0_hclk = {
7923 - .name = "hclk",
7924 - .parent = &hsb_clk,
7925 - .mode = hsb_clk_mode,
7926 - .get_rate = hsb_clk_get_rate,
7927 - .index = 6,
7928 -};
7929 -
7930 -struct platform_device *__init
7931 -at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
7932 -{
7933 - struct platform_device *pdev;
7934 -
7935 - if (id != 0)
7936 - return NULL;
7937 -
7938 - pdev = platform_device_alloc("atmel_usba_udc", 0);
7939 - if (!pdev)
7940 - return NULL;
7941 -
7942 - if (platform_device_add_resources(pdev, usba0_resource,
7943 - ARRAY_SIZE(usba0_resource)))
7944 - goto out_free_pdev;
7945 -
7946 - if (data) {
7947 - if (platform_device_add_data(pdev, data, sizeof(*data)))
7948 - goto out_free_pdev;
7949 -
7950 - if (data->vbus_pin != GPIO_PIN_NONE)
7951 - at32_select_gpio(data->vbus_pin, 0);
7952 - }
7953 -
7954 - usba0_pclk.dev = &pdev->dev;
7955 - usba0_hclk.dev = &pdev->dev;
7956 -
7957 - platform_device_add(pdev);
7958 -
7959 - return pdev;
7960 -
7961 -out_free_pdev:
7962 - platform_device_put(pdev);
7963 - return NULL;
7964 -}
7965 -
7966 -/* --------------------------------------------------------------------
7967 - * IDE / CompactFlash
7968 - * -------------------------------------------------------------------- */
7969 -static struct resource at32_smc_cs4_resource[] __initdata = {
7970 - {
7971 - .start = 0x04000000,
7972 - .end = 0x07ffffff,
7973 - .flags = IORESOURCE_MEM,
7974 - },
7975 - IRQ(~0UL), /* Magic IRQ will be overridden */
7976 -};
7977 -static struct resource at32_smc_cs5_resource[] __initdata = {
7978 - {
7979 - .start = 0x20000000,
7980 - .end = 0x23ffffff,
7981 - .flags = IORESOURCE_MEM,
7982 - },
7983 - IRQ(~0UL), /* Magic IRQ will be overridden */
7984 -};
7985 -
7986 -static int __init at32_init_ide_or_cf(struct platform_device *pdev,
7987 - unsigned int cs, unsigned int extint)
7988 -{
7989 - static unsigned int extint_pin_map[4] __initdata = {
7990 - GPIO_PIN_PB(25),
7991 - GPIO_PIN_PB(26),
7992 - GPIO_PIN_PB(27),
7993 - GPIO_PIN_PB(28),
7994 - };
7995 - static bool common_pins_initialized __initdata = false;
7996 - unsigned int extint_pin;
7997 - int ret;
7998 -
7999 - if (extint >= ARRAY_SIZE(extint_pin_map))
8000 - return -EINVAL;
8001 - extint_pin = extint_pin_map[extint];
8002 -
8003 - switch (cs) {
8004 - case 4:
8005 - ret = platform_device_add_resources(pdev,
8006 - at32_smc_cs4_resource,
8007 - ARRAY_SIZE(at32_smc_cs4_resource));
8008 - if (ret)
8009 - return ret;
8010 -
8011 - select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
8012 - set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
8013 - break;
8014 - case 5:
8015 - ret = platform_device_add_resources(pdev,
8016 - at32_smc_cs5_resource,
8017 - ARRAY_SIZE(at32_smc_cs5_resource));
8018 - if (ret)
8019 - return ret;
8020 -
8021 - select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
8022 - set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
8023 - break;
8024 - default:
8025 - return -EINVAL;
8026 - }
8027 -
8028 - if (!common_pins_initialized) {
8029 - select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
8030 - select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
8031 - select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
8032 - select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
8033 - common_pins_initialized = true;
8034 - }
8035 -
8036 - at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
8037 -
8038 - pdev->resource[1].start = EIM_IRQ_BASE + extint;
8039 - pdev->resource[1].end = pdev->resource[1].start;
8040 -
8041 - return 0;
8042 -}
8043 -
8044 -struct platform_device *__init
8045 -at32_add_device_ide(unsigned int id, unsigned int extint,
8046 - struct ide_platform_data *data)
8047 -{
8048 - struct platform_device *pdev;
8049 -
8050 - pdev = platform_device_alloc("at32_ide", id);
8051 - if (!pdev)
8052 - goto fail;
8053 -
8054 - if (platform_device_add_data(pdev, data,
8055 - sizeof(struct ide_platform_data)))
8056 - goto fail;
8057 -
8058 - if (at32_init_ide_or_cf(pdev, data->cs, extint))
8059 - goto fail;
8060 -
8061 - platform_device_add(pdev);
8062 - return pdev;
8063 -
8064 -fail:
8065 - platform_device_put(pdev);
8066 - return NULL;
8067 -}
8068 -
8069 -struct platform_device *__init
8070 -at32_add_device_cf(unsigned int id, unsigned int extint,
8071 - struct cf_platform_data *data)
8072 -{
8073 - struct platform_device *pdev;
8074 -
8075 - pdev = platform_device_alloc("at32_cf", id);
8076 - if (!pdev)
8077 - goto fail;
8078 -
8079 - if (platform_device_add_data(pdev, data,
8080 - sizeof(struct cf_platform_data)))
8081 - goto fail;
8082 -
8083 - if (at32_init_ide_or_cf(pdev, data->cs, extint))
8084 - goto fail;
8085 -
8086 - if (data->detect_pin != GPIO_PIN_NONE)
8087 - at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
8088 - if (data->reset_pin != GPIO_PIN_NONE)
8089 - at32_select_gpio(data->reset_pin, 0);
8090 - if (data->vcc_pin != GPIO_PIN_NONE)
8091 - at32_select_gpio(data->vcc_pin, 0);
8092 - /* READY is used as extint, so we can't select it as gpio */
8093 -
8094 - platform_device_add(pdev);
8095 - return pdev;
8096 -
8097 -fail:
8098 - platform_device_put(pdev);
8099 - return NULL;
8100 -}
8101 -
8102 -/* --------------------------------------------------------------------
8103 - * AC97C
8104 - * -------------------------------------------------------------------- */
8105 -static struct resource atmel_ac97c0_resource[] __initdata = {
8106 - PBMEM(0xfff02800),
8107 - IRQ(29),
8108 -};
8109 -static struct clk atmel_ac97c0_pclk = {
8110 - .name = "pclk",
8111 - .parent = &pbb_clk,
8112 - .mode = pbb_clk_mode,
8113 - .get_rate = pbb_clk_get_rate,
8114 - .index = 10,
8115 -};
8116 -
8117 -struct platform_device *__init at32_add_device_ac97c(unsigned int id)
8118 -{
8119 - struct platform_device *pdev;
8120 -
8121 - if (id != 0)
8122 - return NULL;
8123 -
8124 - pdev = platform_device_alloc("atmel_ac97c", id);
8125 - if (!pdev)
8126 - return NULL;
8127 -
8128 - if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
8129 - ARRAY_SIZE(atmel_ac97c0_resource)))
8130 - goto err_add_resources;
8131 -
8132 - select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
8133 - select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
8134 - select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
8135 - select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
8136 -
8137 - atmel_ac97c0_pclk.dev = &pdev->dev;
8138 -
8139 - platform_device_add(pdev);
8140 - return pdev;
8141 -
8142 -err_add_resources:
8143 - platform_device_put(pdev);
8144 - return NULL;
8145 -}
8146 -
8147 -/* --------------------------------------------------------------------
8148 - * ABDAC
8149 - * -------------------------------------------------------------------- */
8150 -static struct resource abdac0_resource[] __initdata = {
8151 - PBMEM(0xfff02000),
8152 - IRQ(27),
8153 -};
8154 -static struct clk abdac0_pclk = {
8155 - .name = "pclk",
8156 - .parent = &pbb_clk,
8157 - .mode = pbb_clk_mode,
8158 - .get_rate = pbb_clk_get_rate,
8159 - .index = 8,
8160 -};
8161 -static struct clk abdac0_sample_clk = {
8162 - .name = "sample_clk",
8163 - .mode = genclk_mode,
8164 - .get_rate = genclk_get_rate,
8165 - .set_rate = genclk_set_rate,
8166 - .set_parent = genclk_set_parent,
8167 - .index = 6,
8168 -};
8169 -
8170 -struct platform_device *__init at32_add_device_abdac(unsigned int id)
8171 -{
8172 - struct platform_device *pdev;
8173 -
8174 - if (id != 0)
8175 - return NULL;
8176 -
8177 - pdev = platform_device_alloc("abdac", id);
8178 - if (!pdev)
8179 - return NULL;
8180 -
8181 - if (platform_device_add_resources(pdev, abdac0_resource,
8182 - ARRAY_SIZE(abdac0_resource)))
8183 - goto err_add_resources;
8184 -
8185 - select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
8186 - select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
8187 - select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
8188 - select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
8189 -
8190 - abdac0_pclk.dev = &pdev->dev;
8191 - abdac0_sample_clk.dev = &pdev->dev;
8192 -
8193 - platform_device_add(pdev);
8194 - return pdev;
8195 -
8196 -err_add_resources:
8197 - platform_device_put(pdev);
8198 - return NULL;
8199 -}
8200 -
8201 -/* --------------------------------------------------------------------
8202 - * GCLK
8203 - * -------------------------------------------------------------------- */
8204 -static struct clk gclk0 = {
8205 - .name = "gclk0",
8206 - .mode = genclk_mode,
8207 - .get_rate = genclk_get_rate,
8208 - .set_rate = genclk_set_rate,
8209 - .set_parent = genclk_set_parent,
8210 - .index = 0,
8211 -};
8212 -static struct clk gclk1 = {
8213 - .name = "gclk1",
8214 - .mode = genclk_mode,
8215 - .get_rate = genclk_get_rate,
8216 - .set_rate = genclk_set_rate,
8217 - .set_parent = genclk_set_parent,
8218 - .index = 1,
8219 -};
8220 -static struct clk gclk2 = {
8221 - .name = "gclk2",
8222 - .mode = genclk_mode,
8223 - .get_rate = genclk_get_rate,
8224 - .set_rate = genclk_set_rate,
8225 - .set_parent = genclk_set_parent,
8226 - .index = 2,
8227 -};
8228 -static struct clk gclk3 = {
8229 - .name = "gclk3",
8230 - .mode = genclk_mode,
8231 - .get_rate = genclk_get_rate,
8232 - .set_rate = genclk_set_rate,
8233 - .set_parent = genclk_set_parent,
8234 - .index = 3,
8235 -};
8236 -static struct clk gclk4 = {
8237 - .name = "gclk4",
8238 - .mode = genclk_mode,
8239 - .get_rate = genclk_get_rate,
8240 - .set_rate = genclk_set_rate,
8241 - .set_parent = genclk_set_parent,
8242 - .index = 4,
8243 -};
8244 -
8245 -struct clk *at32_clock_list[] = {
8246 - &osc32k,
8247 - &osc0,
8248 - &osc1,
8249 - &pll0,
8250 - &pll1,
8251 - &cpu_clk,
8252 - &hsb_clk,
8253 - &pba_clk,
8254 - &pbb_clk,
8255 - &at32_pm_pclk,
8256 - &at32_intc0_pclk,
8257 - &hmatrix_clk,
8258 - &ebi_clk,
8259 - &hramc_clk,
8260 - &smc0_pclk,
8261 - &smc0_mck,
8262 - &pdc_hclk,
8263 - &pdc_pclk,
8264 - &dmaca0_hclk,
8265 - &pico_clk,
8266 - &pio0_mck,
8267 - &pio1_mck,
8268 - &pio2_mck,
8269 - &pio3_mck,
8270 - &pio4_mck,
8271 - &at32_systc0_pclk,
8272 - &atmel_usart0_usart,
8273 - &atmel_usart1_usart,
8274 - &atmel_usart2_usart,
8275 - &atmel_usart3_usart,
8276 - &macb0_hclk,
8277 - &macb0_pclk,
8278 - &macb1_hclk,
8279 - &macb1_pclk,
8280 - &atmel_spi0_spi_clk,
8281 - &atmel_spi1_spi_clk,
8282 - &atmel_twi0_pclk,
8283 - &atmel_mci0_pclk,
8284 - &atmel_lcdfb0_hck1,
8285 - &atmel_lcdfb0_pixclk,
8286 - &ssc0_pclk,
8287 - &ssc1_pclk,
8288 - &ssc2_pclk,
8289 - &usba0_hclk,
8290 - &usba0_pclk,
8291 - &atmel_ac97c0_pclk,
8292 - &abdac0_pclk,
8293 - &abdac0_sample_clk,
8294 - &gclk0,
8295 - &gclk1,
8296 - &gclk2,
8297 - &gclk3,
8298 - &gclk4,
8299 -};
8300 -unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
8301 -
8302 -void __init at32_portmux_init(void)
8303 -{
8304 - at32_init_pio(&pio0_device);
8305 - at32_init_pio(&pio1_device);
8306 - at32_init_pio(&pio2_device);
8307 - at32_init_pio(&pio3_device);
8308 - at32_init_pio(&pio4_device);
8309 -}
8310 -
8311 -void __init at32_clock_init(void)
8312 -{
8313 - u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
8314 - int i;
8315 -
8316 - if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
8317 - main_clock = &pll0;
8318 - cpu_clk.parent = &pll0;
8319 - } else {
8320 - main_clock = &osc0;
8321 - cpu_clk.parent = &osc0;
8322 - }
8323 -
8324 - if (pm_readl(PLL0) & PM_BIT(PLLOSC))
8325 - pll0.parent = &osc1;
8326 - if (pm_readl(PLL1) & PM_BIT(PLLOSC))
8327 - pll1.parent = &osc1;
8328 -
8329 - genclk_init_parent(&gclk0);
8330 - genclk_init_parent(&gclk1);
8331 - genclk_init_parent(&gclk2);
8332 - genclk_init_parent(&gclk3);
8333 - genclk_init_parent(&gclk4);
8334 - genclk_init_parent(&atmel_lcdfb0_pixclk);
8335 - genclk_init_parent(&abdac0_sample_clk);
8336 -
8337 - /*
8338 - * Turn on all clocks that have at least one user already, and
8339 - * turn off everything else. We only do this for module
8340 - * clocks, and even though it isn't particularly pretty to
8341 - * check the address of the mode function, it should do the
8342 - * trick...
8343 - */
8344 - for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
8345 - struct clk *clk = at32_clock_list[i];
8346 -
8347 - if (clk->users == 0)
8348 - continue;
8349 -
8350 - if (clk->mode == &cpu_clk_mode)
8351 - cpu_mask |= 1 << clk->index;
8352 - else if (clk->mode == &hsb_clk_mode)
8353 - hsb_mask |= 1 << clk->index;
8354 - else if (clk->mode == &pba_clk_mode)
8355 - pba_mask |= 1 << clk->index;
8356 - else if (clk->mode == &pbb_clk_mode)
8357 - pbb_mask |= 1 << clk->index;
8358 - }
8359 -
8360 - pm_writel(CPU_MASK, cpu_mask);
8361 - pm_writel(HSB_MASK, hsb_mask);
8362 - pm_writel(PBA_MASK, pba_mask);
8363 - pm_writel(PBB_MASK, pbb_mask);
8364 -}
8365 --- /dev/null
8366 +++ b/arch/avr32/mach-at32ap/at32ap700x.c
8367 @@ -0,0 +1,1944 @@
8368 +/*
8369 + * Copyright (C) 2005-2006 Atmel Corporation
8370 + *
8371 + * This program is free software; you can redistribute it and/or modify
8372 + * it under the terms of the GNU General Public License version 2 as
8373 + * published by the Free Software Foundation.
8374 + */
8375 +#include <linux/clk.h>
8376 +#include <linux/fb.h>
8377 +#include <linux/init.h>
8378 +#include <linux/platform_device.h>
8379 +#include <linux/dma-mapping.h>
8380 +#include <linux/spi/spi.h>
8381 +#include <linux/usb/atmel_usba_udc.h>
8382 +
8383 +#include <asm/io.h>
8384 +#include <asm/irq.h>
8385 +
8386 +#include <asm/arch/at32ap700x.h>
8387 +#include <asm/arch/board.h>
8388 +#include <asm/arch/portmux.h>
8389 +
8390 +#include <video/atmel_lcdc.h>
8391 +
8392 +#include "clock.h"
8393 +#include "hmatrix.h"
8394 +#include "pio.h"
8395 +#include "pm.h"
8396 +
8397 +
8398 +#define PBMEM(base) \
8399 + { \
8400 + .start = base, \
8401 + .end = base + 0x3ff, \
8402 + .flags = IORESOURCE_MEM, \
8403 + }
8404 +#define IRQ(num) \
8405 + { \
8406 + .start = num, \
8407 + .end = num, \
8408 + .flags = IORESOURCE_IRQ, \
8409 + }
8410 +#define NAMED_IRQ(num, _name) \
8411 + { \
8412 + .start = num, \
8413 + .end = num, \
8414 + .name = _name, \
8415 + .flags = IORESOURCE_IRQ, \
8416 + }
8417 +
8418 +/* REVISIT these assume *every* device supports DMA, but several
8419 + * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
8420 + */
8421 +#define DEFINE_DEV(_name, _id) \
8422 +static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
8423 +static struct platform_device _name##_id##_device = { \
8424 + .name = #_name, \
8425 + .id = _id, \
8426 + .dev = { \
8427 + .dma_mask = &_name##_id##_dma_mask, \
8428 + .coherent_dma_mask = DMA_32BIT_MASK, \
8429 + }, \
8430 + .resource = _name##_id##_resource, \
8431 + .num_resources = ARRAY_SIZE(_name##_id##_resource), \
8432 +}
8433 +#define DEFINE_DEV_DATA(_name, _id) \
8434 +static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
8435 +static struct platform_device _name##_id##_device = { \
8436 + .name = #_name, \
8437 + .id = _id, \
8438 + .dev = { \
8439 + .dma_mask = &_name##_id##_dma_mask, \
8440 + .platform_data = &_name##_id##_data, \
8441 + .coherent_dma_mask = DMA_32BIT_MASK, \
8442 + }, \
8443 + .resource = _name##_id##_resource, \
8444 + .num_resources = ARRAY_SIZE(_name##_id##_resource), \
8445 +}
8446 +
8447 +#define select_peripheral(pin, periph, flags) \
8448 + at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
8449 +
8450 +#define DEV_CLK(_name, devname, bus, _index) \
8451 +static struct clk devname##_##_name = { \
8452 + .name = #_name, \
8453 + .dev = &devname##_device.dev, \
8454 + .parent = &bus##_clk, \
8455 + .mode = bus##_clk_mode, \
8456 + .get_rate = bus##_clk_get_rate, \
8457 + .index = _index, \
8458 +}
8459 +
8460 +static DEFINE_SPINLOCK(pm_lock);
8461 +
8462 +unsigned long at32ap7000_osc_rates[3] = {
8463 + [0] = 32768,
8464 + /* FIXME: these are ATSTK1002-specific */
8465 + [1] = 20000000,
8466 + [2] = 12000000,
8467 +};
8468 +
8469 +static unsigned long osc_get_rate(struct clk *clk)
8470 +{
8471 + return at32ap7000_osc_rates[clk->index];
8472 +}
8473 +
8474 +static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
8475 +{
8476 + unsigned long div, mul, rate;
8477 +
8478 + if (!(control & PM_BIT(PLLEN)))
8479 + return 0;
8480 +
8481 + div = PM_BFEXT(PLLDIV, control) + 1;
8482 + mul = PM_BFEXT(PLLMUL, control) + 1;
8483 +
8484 + rate = clk->parent->get_rate(clk->parent);
8485 + rate = (rate + div / 2) / div;
8486 + rate *= mul;
8487 +
8488 + return rate;
8489 +}
8490 +
8491 +static unsigned long pll0_get_rate(struct clk *clk)
8492 +{
8493 + u32 control;
8494 +
8495 + control = pm_readl(PLL0);
8496 +
8497 + return pll_get_rate(clk, control);
8498 +}
8499 +
8500 +static unsigned long pll1_get_rate(struct clk *clk)
8501 +{
8502 + u32 control;
8503 +
8504 + control = pm_readl(PLL1);
8505 +
8506 + return pll_get_rate(clk, control);
8507 +}
8508 +
8509 +/*
8510 + * The AT32AP7000 has five primary clock sources: One 32kHz
8511 + * oscillator, two crystal oscillators and two PLLs.
8512 + */
8513 +static struct clk osc32k = {
8514 + .name = "osc32k",
8515 + .get_rate = osc_get_rate,
8516 + .users = 1,
8517 + .index = 0,
8518 +};
8519 +static struct clk osc0 = {
8520 + .name = "osc0",
8521 + .get_rate = osc_get_rate,
8522 + .users = 1,
8523 + .index = 1,
8524 +};
8525 +static struct clk osc1 = {
8526 + .name = "osc1",
8527 + .get_rate = osc_get_rate,
8528 + .index = 2,
8529 +};
8530 +static struct clk pll0 = {
8531 + .name = "pll0",
8532 + .get_rate = pll0_get_rate,
8533 + .parent = &osc0,
8534 +};
8535 +static struct clk pll1 = {
8536 + .name = "pll1",
8537 + .get_rate = pll1_get_rate,
8538 + .parent = &osc0,
8539 +};
8540 +
8541 +/*
8542 + * The main clock can be either osc0 or pll0. The boot loader may
8543 + * have chosen one for us, so we don't really know which one until we
8544 + * have a look at the SM.
8545 + */
8546 +static struct clk *main_clock;
8547 +
8548 +/*
8549 + * Synchronous clocks are generated from the main clock. The clocks
8550 + * must satisfy the constraint
8551 + * fCPU >= fHSB >= fPB
8552 + * i.e. each clock must not be faster than its parent.
8553 + */
8554 +static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
8555 +{
8556 + return main_clock->get_rate(main_clock) >> shift;
8557 +};
8558 +
8559 +static void cpu_clk_mode(struct clk *clk, int enabled)
8560 +{
8561 + unsigned long flags;
8562 + u32 mask;
8563 +
8564 + spin_lock_irqsave(&pm_lock, flags);
8565 + mask = pm_readl(CPU_MASK);
8566 + if (enabled)
8567 + mask |= 1 << clk->index;
8568 + else
8569 + mask &= ~(1 << clk->index);
8570 + pm_writel(CPU_MASK, mask);
8571 + spin_unlock_irqrestore(&pm_lock, flags);
8572 +}
8573 +
8574 +static unsigned long cpu_clk_get_rate(struct clk *clk)
8575 +{
8576 + unsigned long cksel, shift = 0;
8577 +
8578 + cksel = pm_readl(CKSEL);
8579 + if (cksel & PM_BIT(CPUDIV))
8580 + shift = PM_BFEXT(CPUSEL, cksel) + 1;
8581 +
8582 + return bus_clk_get_rate(clk, shift);
8583 +}
8584 +
8585 +static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
8586 +{
8587 + u32 control;
8588 + unsigned long parent_rate, child_div, actual_rate, div;
8589 +
8590 + parent_rate = clk->parent->get_rate(clk->parent);
8591 + control = pm_readl(CKSEL);
8592 +
8593 + if (control & PM_BIT(HSBDIV))
8594 + child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
8595 + else
8596 + child_div = 1;
8597 +
8598 + if (rate > 3 * (parent_rate / 4) || child_div == 1) {
8599 + actual_rate = parent_rate;
8600 + control &= ~PM_BIT(CPUDIV);
8601 + } else {
8602 + unsigned int cpusel;
8603 + div = (parent_rate + rate / 2) / rate;
8604 + if (div > child_div)
8605 + div = child_div;
8606 + cpusel = (div > 1) ? (fls(div) - 2) : 0;
8607 + control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
8608 + actual_rate = parent_rate / (1 << (cpusel + 1));
8609 + }
8610 +
8611 + pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
8612 + clk->name, rate, actual_rate);
8613 +
8614 + if (apply)
8615 + pm_writel(CKSEL, control);
8616 +
8617 + return actual_rate;
8618 +}
8619 +
8620 +static void hsb_clk_mode(struct clk *clk, int enabled)
8621 +{
8622 + unsigned long flags;
8623 + u32 mask;
8624 +
8625 + spin_lock_irqsave(&pm_lock, flags);
8626 + mask = pm_readl(HSB_MASK);
8627 + if (enabled)
8628 + mask |= 1 << clk->index;
8629 + else
8630 + mask &= ~(1 << clk->index);
8631 + pm_writel(HSB_MASK, mask);
8632 + spin_unlock_irqrestore(&pm_lock, flags);
8633 +}
8634 +
8635 +static unsigned long hsb_clk_get_rate(struct clk *clk)
8636 +{
8637 + unsigned long cksel, shift = 0;
8638 +
8639 + cksel = pm_readl(CKSEL);
8640 + if (cksel & PM_BIT(HSBDIV))
8641 + shift = PM_BFEXT(HSBSEL, cksel) + 1;
8642 +
8643 + return bus_clk_get_rate(clk, shift);
8644 +}
8645 +
8646 +static void pba_clk_mode(struct clk *clk, int enabled)
8647 +{
8648 + unsigned long flags;
8649 + u32 mask;
8650 +
8651 + spin_lock_irqsave(&pm_lock, flags);
8652 + mask = pm_readl(PBA_MASK);
8653 + if (enabled)
8654 + mask |= 1 << clk->index;
8655 + else
8656 + mask &= ~(1 << clk->index);
8657 + pm_writel(PBA_MASK, mask);
8658 + spin_unlock_irqrestore(&pm_lock, flags);
8659 +}
8660 +
8661 +static unsigned long pba_clk_get_rate(struct clk *clk)
8662 +{
8663 + unsigned long cksel, shift = 0;
8664 +
8665 + cksel = pm_readl(CKSEL);
8666 + if (cksel & PM_BIT(PBADIV))
8667 + shift = PM_BFEXT(PBASEL, cksel) + 1;
8668 +
8669 + return bus_clk_get_rate(clk, shift);
8670 +}
8671 +
8672 +static void pbb_clk_mode(struct clk *clk, int enabled)
8673 +{
8674 + unsigned long flags;
8675 + u32 mask;
8676 +
8677 + spin_lock_irqsave(&pm_lock, flags);
8678 + mask = pm_readl(PBB_MASK);
8679 + if (enabled)
8680 + mask |= 1 << clk->index;
8681 + else
8682 + mask &= ~(1 << clk->index);
8683 + pm_writel(PBB_MASK, mask);
8684 + spin_unlock_irqrestore(&pm_lock, flags);
8685 +}
8686 +
8687 +static unsigned long pbb_clk_get_rate(struct clk *clk)
8688 +{
8689 + unsigned long cksel, shift = 0;
8690 +
8691 + cksel = pm_readl(CKSEL);
8692 + if (cksel & PM_BIT(PBBDIV))
8693 + shift = PM_BFEXT(PBBSEL, cksel) + 1;
8694 +
8695 + return bus_clk_get_rate(clk, shift);
8696 +}
8697 +
8698 +static struct clk cpu_clk = {
8699 + .name = "cpu",
8700 + .get_rate = cpu_clk_get_rate,
8701 + .set_rate = cpu_clk_set_rate,
8702 + .users = 1,
8703 +};
8704 +static struct clk hsb_clk = {
8705 + .name = "hsb",
8706 + .parent = &cpu_clk,
8707 + .get_rate = hsb_clk_get_rate,
8708 +};
8709 +static struct clk pba_clk = {
8710 + .name = "pba",
8711 + .parent = &hsb_clk,
8712 + .mode = hsb_clk_mode,
8713 + .get_rate = pba_clk_get_rate,
8714 + .index = 1,
8715 +};
8716 +static struct clk pbb_clk = {
8717 + .name = "pbb",
8718 + .parent = &hsb_clk,
8719 + .mode = hsb_clk_mode,
8720 + .get_rate = pbb_clk_get_rate,
8721 + .users = 1,
8722 + .index = 2,
8723 +};
8724 +
8725 +/* --------------------------------------------------------------------
8726 + * Generic Clock operations
8727 + * -------------------------------------------------------------------- */
8728 +
8729 +static void genclk_mode(struct clk *clk, int enabled)
8730 +{
8731 + u32 control;
8732 +
8733 + control = pm_readl(GCCTRL(clk->index));
8734 + if (enabled)
8735 + control |= PM_BIT(CEN);
8736 + else
8737 + control &= ~PM_BIT(CEN);
8738 + pm_writel(GCCTRL(clk->index), control);
8739 +}
8740 +
8741 +static unsigned long genclk_get_rate(struct clk *clk)
8742 +{
8743 + u32 control;
8744 + unsigned long div = 1;
8745 +
8746 + control = pm_readl(GCCTRL(clk->index));
8747 + if (control & PM_BIT(DIVEN))
8748 + div = 2 * (PM_BFEXT(DIV, control) + 1);
8749 +
8750 + return clk->parent->get_rate(clk->parent) / div;
8751 +}
8752 +
8753 +static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
8754 +{
8755 + u32 control;
8756 + unsigned long parent_rate, actual_rate, div;
8757 +
8758 + parent_rate = clk->parent->get_rate(clk->parent);
8759 + control = pm_readl(GCCTRL(clk->index));
8760 +
8761 + if (rate > 3 * parent_rate / 4) {
8762 + actual_rate = parent_rate;
8763 + control &= ~PM_BIT(DIVEN);
8764 + } else {
8765 + div = (parent_rate + rate) / (2 * rate) - 1;
8766 + control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
8767 + actual_rate = parent_rate / (2 * (div + 1));
8768 + }
8769 +
8770 + dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
8771 + clk->name, rate, actual_rate);
8772 +
8773 + if (apply)
8774 + pm_writel(GCCTRL(clk->index), control);
8775 +
8776 + return actual_rate;
8777 +}
8778 +
8779 +int genclk_set_parent(struct clk *clk, struct clk *parent)
8780 +{
8781 + u32 control;
8782 +
8783 + dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
8784 + clk->name, parent->name, clk->parent->name);
8785 +
8786 + control = pm_readl(GCCTRL(clk->index));
8787 +
8788 + if (parent == &osc1 || parent == &pll1)
8789 + control |= PM_BIT(OSCSEL);
8790 + else if (parent == &osc0 || parent == &pll0)
8791 + control &= ~PM_BIT(OSCSEL);
8792 + else
8793 + return -EINVAL;
8794 +
8795 + if (parent == &pll0 || parent == &pll1)
8796 + control |= PM_BIT(PLLSEL);
8797 + else
8798 + control &= ~PM_BIT(PLLSEL);
8799 +
8800 + pm_writel(GCCTRL(clk->index), control);
8801 + clk->parent = parent;
8802 +
8803 + return 0;
8804 +}
8805 +
8806 +static void __init genclk_init_parent(struct clk *clk)
8807 +{
8808 + u32 control;
8809 + struct clk *parent;
8810 +
8811 + BUG_ON(clk->index > 7);
8812 +
8813 + control = pm_readl(GCCTRL(clk->index));
8814 + if (control & PM_BIT(OSCSEL))
8815 + parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
8816 + else
8817 + parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
8818 +
8819 + clk->parent = parent;
8820 +}
8821 +
8822 +/* --------------------------------------------------------------------
8823 + * System peripherals
8824 + * -------------------------------------------------------------------- */
8825 +static struct resource at32_pm0_resource[] = {
8826 + {
8827 + .start = 0xfff00000,
8828 + .end = 0xfff0007f,
8829 + .flags = IORESOURCE_MEM,
8830 + },
8831 + IRQ(20),
8832 +};
8833 +
8834 +static struct resource at32ap700x_rtc0_resource[] = {
8835 + {
8836 + .start = 0xfff00080,
8837 + .end = 0xfff000af,
8838 + .flags = IORESOURCE_MEM,
8839 + },
8840 + IRQ(21),
8841 +};
8842 +
8843 +static struct resource at32_wdt0_resource[] = {
8844 + {
8845 + .start = 0xfff000b0,
8846 + .end = 0xfff000cf,
8847 + .flags = IORESOURCE_MEM,
8848 + },
8849 +};
8850 +
8851 +static struct resource at32_eic0_resource[] = {
8852 + {
8853 + .start = 0xfff00100,
8854 + .end = 0xfff0013f,
8855 + .flags = IORESOURCE_MEM,
8856 + },
8857 + IRQ(19),
8858 +};
8859 +
8860 +DEFINE_DEV(at32_pm, 0);
8861 +DEFINE_DEV(at32ap700x_rtc, 0);
8862 +DEFINE_DEV(at32_wdt, 0);
8863 +DEFINE_DEV(at32_eic, 0);
8864 +
8865 +/*
8866 + * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
8867 + * is always running.
8868 + */
8869 +static struct clk at32_pm_pclk = {
8870 + .name = "pclk",
8871 + .dev = &at32_pm0_device.dev,
8872 + .parent = &pbb_clk,
8873 + .mode = pbb_clk_mode,
8874 + .get_rate = pbb_clk_get_rate,
8875 + .users = 1,
8876 + .index = 0,
8877 +};
8878 +
8879 +static struct resource intc0_resource[] = {
8880 + PBMEM(0xfff00400),
8881 +};
8882 +struct platform_device at32_intc0_device = {
8883 + .name = "intc",
8884 + .id = 0,
8885 + .resource = intc0_resource,
8886 + .num_resources = ARRAY_SIZE(intc0_resource),
8887 +};
8888 +DEV_CLK(pclk, at32_intc0, pbb, 1);
8889 +
8890 +static struct clk ebi_clk = {
8891 + .name = "ebi",
8892 + .parent = &hsb_clk,
8893 + .mode = hsb_clk_mode,
8894 + .get_rate = hsb_clk_get_rate,
8895 + .users = 1,
8896 +};
8897 +static struct clk hramc_clk = {
8898 + .name = "hramc",
8899 + .parent = &hsb_clk,
8900 + .mode = hsb_clk_mode,
8901 + .get_rate = hsb_clk_get_rate,
8902 + .users = 1,
8903 + .index = 3,
8904 +};
8905 +
8906 +static struct resource smc0_resource[] = {
8907 + PBMEM(0xfff03400),
8908 +};
8909 +DEFINE_DEV(smc, 0);
8910 +DEV_CLK(pclk, smc0, pbb, 13);
8911 +DEV_CLK(mck, smc0, hsb, 0);
8912 +
8913 +static struct platform_device pdc_device = {
8914 + .name = "pdc",
8915 + .id = 0,
8916 +};
8917 +DEV_CLK(hclk, pdc, hsb, 4);
8918 +DEV_CLK(pclk, pdc, pba, 16);
8919 +
8920 +static struct clk pico_clk = {
8921 + .name = "pico",
8922 + .parent = &cpu_clk,
8923 + .mode = cpu_clk_mode,
8924 + .get_rate = cpu_clk_get_rate,
8925 + .users = 1,
8926 +};
8927 +
8928 +static struct resource dmaca0_resource[] = {
8929 + {
8930 + .start = 0xff200000,
8931 + .end = 0xff20ffff,
8932 + .flags = IORESOURCE_MEM,
8933 + },
8934 + IRQ(2),
8935 +};
8936 +DEFINE_DEV(dmaca, 0);
8937 +DEV_CLK(hclk, dmaca0, hsb, 10);
8938 +
8939 +/* --------------------------------------------------------------------
8940 + * HMATRIX
8941 + * -------------------------------------------------------------------- */
8942 +
8943 +static struct clk hmatrix_clk = {
8944 + .name = "hmatrix_clk",
8945 + .parent = &pbb_clk,
8946 + .mode = pbb_clk_mode,
8947 + .get_rate = pbb_clk_get_rate,
8948 + .index = 2,
8949 + .users = 1,
8950 +};
8951 +#define HMATRIX_BASE ((void __iomem *)0xfff00800)
8952 +
8953 +#define hmatrix_readl(reg) \
8954 + __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
8955 +#define hmatrix_writel(reg,value) \
8956 + __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
8957 +
8958 +/*
8959 + * Set bits in the HMATRIX Special Function Register (SFR) used by the
8960 + * External Bus Interface (EBI). This can be used to enable special
8961 + * features like CompactFlash support, NAND Flash support, etc. on
8962 + * certain chipselects.
8963 + */
8964 +static inline void set_ebi_sfr_bits(u32 mask)
8965 +{
8966 + u32 sfr;
8967 +
8968 + clk_enable(&hmatrix_clk);
8969 + sfr = hmatrix_readl(SFR4);
8970 + sfr |= mask;
8971 + hmatrix_writel(SFR4, sfr);
8972 + clk_disable(&hmatrix_clk);
8973 +}
8974 +
8975 +/* --------------------------------------------------------------------
8976 + * Timer/Counter (TC)
8977 + * -------------------------------------------------------------------- */
8978 +
8979 +static struct resource at32_tcb0_resource[] = {
8980 + PBMEM(0xfff00c00),
8981 + IRQ(22),
8982 +};
8983 +static struct platform_device at32_tcb0_device = {
8984 + .name = "atmel_tcb",
8985 + .id = 0,
8986 + .resource = at32_tcb0_resource,
8987 + .num_resources = ARRAY_SIZE(at32_tcb0_resource),
8988 +};
8989 +DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
8990 +
8991 +static struct resource at32_tcb1_resource[] = {
8992 + PBMEM(0xfff01000),
8993 + IRQ(23),
8994 +};
8995 +static struct platform_device at32_tcb1_device = {
8996 + .name = "atmel_tcb",
8997 + .id = 1,
8998 + .resource = at32_tcb1_resource,
8999 + .num_resources = ARRAY_SIZE(at32_tcb1_resource),
9000 +};
9001 +DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
9002 +
9003 +/* --------------------------------------------------------------------
9004 + * PIO
9005 + * -------------------------------------------------------------------- */
9006 +
9007 +static struct resource pio0_resource[] = {
9008 + PBMEM(0xffe02800),
9009 + IRQ(13),
9010 +};
9011 +DEFINE_DEV(pio, 0);
9012 +DEV_CLK(mck, pio0, pba, 10);
9013 +
9014 +static struct resource pio1_resource[] = {
9015 + PBMEM(0xffe02c00),
9016 + IRQ(14),
9017 +};
9018 +DEFINE_DEV(pio, 1);
9019 +DEV_CLK(mck, pio1, pba, 11);
9020 +
9021 +static struct resource pio2_resource[] = {
9022 + PBMEM(0xffe03000),
9023 + IRQ(15),
9024 +};
9025 +DEFINE_DEV(pio, 2);
9026 +DEV_CLK(mck, pio2, pba, 12);
9027 +
9028 +static struct resource pio3_resource[] = {
9029 + PBMEM(0xffe03400),
9030 + IRQ(16),
9031 +};
9032 +DEFINE_DEV(pio, 3);
9033 +DEV_CLK(mck, pio3, pba, 13);
9034 +
9035 +static struct resource pio4_resource[] = {
9036 + PBMEM(0xffe03800),
9037 + IRQ(17),
9038 +};
9039 +DEFINE_DEV(pio, 4);
9040 +DEV_CLK(mck, pio4, pba, 14);
9041 +
9042 +void __init at32_add_system_devices(void)
9043 +{
9044 + platform_device_register(&at32_pm0_device);
9045 + platform_device_register(&at32_intc0_device);
9046 + platform_device_register(&at32ap700x_rtc0_device);
9047 + platform_device_register(&at32_wdt0_device);
9048 + platform_device_register(&at32_eic0_device);
9049 + platform_device_register(&smc0_device);
9050 + platform_device_register(&pdc_device);
9051 + platform_device_register(&dmaca0_device);
9052 +
9053 + platform_device_register(&at32_tcb0_device);
9054 + platform_device_register(&at32_tcb1_device);
9055 +
9056 + platform_device_register(&pio0_device);
9057 + platform_device_register(&pio1_device);
9058 + platform_device_register(&pio2_device);
9059 + platform_device_register(&pio3_device);
9060 + platform_device_register(&pio4_device);
9061 +}
9062 +
9063 +/* --------------------------------------------------------------------
9064 + * PSIF
9065 + * -------------------------------------------------------------------- */
9066 +static struct resource atmel_psif0_resource[] __initdata = {
9067 + {
9068 + .start = 0xffe03c00,
9069 + .end = 0xffe03cff,
9070 + .flags = IORESOURCE_MEM,
9071 + },
9072 + IRQ(18),
9073 +};
9074 +static struct clk atmel_psif0_pclk = {
9075 + .name = "pclk",
9076 + .parent = &pba_clk,
9077 + .mode = pba_clk_mode,
9078 + .get_rate = pba_clk_get_rate,
9079 + .index = 15,
9080 +};
9081 +
9082 +static struct resource atmel_psif1_resource[] __initdata = {
9083 + {
9084 + .start = 0xffe03d00,
9085 + .end = 0xffe03dff,
9086 + .flags = IORESOURCE_MEM,
9087 + },
9088 + IRQ(18),
9089 +};
9090 +static struct clk atmel_psif1_pclk = {
9091 + .name = "pclk",
9092 + .parent = &pba_clk,
9093 + .mode = pba_clk_mode,
9094 + .get_rate = pba_clk_get_rate,
9095 + .index = 15,
9096 +};
9097 +
9098 +struct platform_device *__init at32_add_device_psif(unsigned int id)
9099 +{
9100 + struct platform_device *pdev;
9101 +
9102 + if (!(id == 0 || id == 1))
9103 + return NULL;
9104 +
9105 + pdev = platform_device_alloc("atmel_psif", id);
9106 + if (!pdev)
9107 + return NULL;
9108 +
9109 + switch (id) {
9110 + case 0:
9111 + if (platform_device_add_resources(pdev, atmel_psif0_resource,
9112 + ARRAY_SIZE(atmel_psif0_resource)))
9113 + goto err_add_resources;
9114 + atmel_psif0_pclk.dev = &pdev->dev;
9115 + select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
9116 + select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
9117 + break;
9118 + case 1:
9119 + if (platform_device_add_resources(pdev, atmel_psif1_resource,
9120 + ARRAY_SIZE(atmel_psif1_resource)))
9121 + goto err_add_resources;
9122 + atmel_psif1_pclk.dev = &pdev->dev;
9123 + select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
9124 + select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
9125 + break;
9126 + default:
9127 + return NULL;
9128 + }
9129 +
9130 + platform_device_add(pdev);
9131 + return pdev;
9132 +
9133 +err_add_resources:
9134 + platform_device_put(pdev);
9135 + return NULL;
9136 +}
9137 +
9138 +/* --------------------------------------------------------------------
9139 + * USART
9140 + * -------------------------------------------------------------------- */
9141 +
9142 +static struct atmel_uart_data atmel_usart0_data = {
9143 + .use_dma_tx = 1,
9144 + .use_dma_rx = 1,
9145 +};
9146 +static struct resource atmel_usart0_resource[] = {
9147 + PBMEM(0xffe00c00),
9148 + IRQ(6),
9149 +};
9150 +DEFINE_DEV_DATA(atmel_usart, 0);
9151 +DEV_CLK(usart, atmel_usart0, pba, 3);
9152 +
9153 +static struct atmel_uart_data atmel_usart1_data = {
9154 + .use_dma_tx = 1,
9155 + .use_dma_rx = 1,
9156 +};
9157 +static struct resource atmel_usart1_resource[] = {
9158 + PBMEM(0xffe01000),
9159 + IRQ(7),
9160 +};
9161 +DEFINE_DEV_DATA(atmel_usart, 1);
9162 +DEV_CLK(usart, atmel_usart1, pba, 4);
9163 +
9164 +static struct atmel_uart_data atmel_usart2_data = {
9165 + .use_dma_tx = 1,
9166 + .use_dma_rx = 1,
9167 +};
9168 +static struct resource atmel_usart2_resource[] = {
9169 + PBMEM(0xffe01400),
9170 + IRQ(8),
9171 +};
9172 +DEFINE_DEV_DATA(atmel_usart, 2);
9173 +DEV_CLK(usart, atmel_usart2, pba, 5);
9174 +
9175 +static struct atmel_uart_data atmel_usart3_data = {
9176 + .use_dma_tx = 1,
9177 + .use_dma_rx = 1,
9178 +};
9179 +static struct resource atmel_usart3_resource[] = {
9180 + PBMEM(0xffe01800),
9181 + IRQ(9),
9182 +};
9183 +DEFINE_DEV_DATA(atmel_usart, 3);
9184 +DEV_CLK(usart, atmel_usart3, pba, 6);
9185 +
9186 +static inline void configure_usart0_pins(void)
9187 +{
9188 + select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
9189 + select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
9190 +}
9191 +
9192 +static inline void configure_usart1_pins(void)
9193 +{
9194 + select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
9195 + select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
9196 +}
9197 +
9198 +static inline void configure_usart2_pins(void)
9199 +{
9200 + select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
9201 + select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
9202 +}
9203 +
9204 +static inline void configure_usart3_pins(void)
9205 +{
9206 + select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
9207 + select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
9208 +}
9209 +
9210 +static struct platform_device *__initdata at32_usarts[4];
9211 +
9212 +void __init at32_map_usart(unsigned int hw_id, unsigned int line)
9213 +{
9214 + struct platform_device *pdev;
9215 +
9216 + switch (hw_id) {
9217 + case 0:
9218 + pdev = &atmel_usart0_device;
9219 + configure_usart0_pins();
9220 + break;
9221 + case 1:
9222 + pdev = &atmel_usart1_device;
9223 + configure_usart1_pins();
9224 + break;
9225 + case 2:
9226 + pdev = &atmel_usart2_device;
9227 + configure_usart2_pins();
9228 + break;
9229 + case 3:
9230 + pdev = &atmel_usart3_device;
9231 + configure_usart3_pins();
9232 + break;
9233 + default:
9234 + return;
9235 + }
9236 +
9237 + if (PXSEG(pdev->resource[0].start) == P4SEG) {
9238 + /* Addresses in the P4 segment are permanently mapped 1:1 */
9239 + struct atmel_uart_data *data = pdev->dev.platform_data;
9240 + data->regs = (void __iomem *)pdev->resource[0].start;
9241 + }
9242 +
9243 + pdev->id = line;
9244 + at32_usarts[line] = pdev;
9245 +}
9246 +
9247 +struct platform_device *__init at32_add_device_usart(unsigned int id)
9248 +{
9249 + platform_device_register(at32_usarts[id]);
9250 + return at32_usarts[id];
9251 +}
9252 +
9253 +struct platform_device *atmel_default_console_device;
9254 +
9255 +void __init at32_setup_serial_console(unsigned int usart_id)
9256 +{
9257 + atmel_default_console_device = at32_usarts[usart_id];
9258 +}
9259 +
9260 +/* --------------------------------------------------------------------
9261 + * Ethernet
9262 + * -------------------------------------------------------------------- */
9263 +
9264 +#ifdef CONFIG_CPU_AT32AP7000
9265 +static struct eth_platform_data macb0_data;
9266 +static struct resource macb0_resource[] = {
9267 + PBMEM(0xfff01800),
9268 + IRQ(25),
9269 +};
9270 +DEFINE_DEV_DATA(macb, 0);
9271 +DEV_CLK(hclk, macb0, hsb, 8);
9272 +DEV_CLK(pclk, macb0, pbb, 6);
9273 +
9274 +static struct eth_platform_data macb1_data;
9275 +static struct resource macb1_resource[] = {
9276 + PBMEM(0xfff01c00),
9277 + IRQ(26),
9278 +};
9279 +DEFINE_DEV_DATA(macb, 1);
9280 +DEV_CLK(hclk, macb1, hsb, 9);
9281 +DEV_CLK(pclk, macb1, pbb, 7);
9282 +
9283 +struct platform_device *__init
9284 +at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
9285 +{
9286 + struct platform_device *pdev;
9287 +
9288 + switch (id) {
9289 + case 0:
9290 + pdev = &macb0_device;
9291 +
9292 + select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
9293 + select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
9294 + select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
9295 + select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
9296 + select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
9297 + select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
9298 + select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
9299 + select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
9300 + select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
9301 + select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
9302 +
9303 + if (!data->is_rmii) {
9304 + select_peripheral(PC(0), PERIPH_A, 0); /* COL */
9305 + select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
9306 + select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
9307 + select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
9308 + select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
9309 + select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
9310 + select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
9311 + select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
9312 + select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
9313 + }
9314 + break;
9315 +
9316 + case 1:
9317 + pdev = &macb1_device;
9318 +
9319 + select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
9320 + select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
9321 + select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
9322 + select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
9323 + select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
9324 + select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
9325 + select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
9326 + select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
9327 + select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
9328 + select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
9329 +
9330 + if (!data->is_rmii) {
9331 + select_peripheral(PC(19), PERIPH_B, 0); /* COL */
9332 + select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
9333 + select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
9334 + select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
9335 + select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
9336 + select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
9337 + select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
9338 + select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
9339 + select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
9340 + }
9341 + break;
9342 +
9343 + default:
9344 + return NULL;
9345 + }
9346 +
9347 + memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
9348 + platform_device_register(pdev);
9349 +
9350 + return pdev;
9351 +}
9352 +#endif
9353 +
9354 +/* --------------------------------------------------------------------
9355 + * SPI
9356 + * -------------------------------------------------------------------- */
9357 +static struct resource atmel_spi0_resource[] = {
9358 + PBMEM(0xffe00000),
9359 + IRQ(3),
9360 +};
9361 +DEFINE_DEV(atmel_spi, 0);
9362 +DEV_CLK(spi_clk, atmel_spi0, pba, 0);
9363 +
9364 +static struct resource atmel_spi1_resource[] = {
9365 + PBMEM(0xffe00400),
9366 + IRQ(4),
9367 +};
9368 +DEFINE_DEV(atmel_spi, 1);
9369 +DEV_CLK(spi_clk, atmel_spi1, pba, 1);
9370 +
9371 +static void __init
9372 +at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
9373 + unsigned int n, const u8 *pins)
9374 +{
9375 + unsigned int pin, mode;
9376 +
9377 + for (; n; n--, b++) {
9378 + b->bus_num = bus_num;
9379 + if (b->chip_select >= 4)
9380 + continue;
9381 + pin = (unsigned)b->controller_data;
9382 + if (!pin) {
9383 + pin = pins[b->chip_select];
9384 + b->controller_data = (void *)pin;
9385 + }
9386 + mode = AT32_GPIOF_OUTPUT;
9387 + if (!(b->mode & SPI_CS_HIGH))
9388 + mode |= AT32_GPIOF_HIGH;
9389 + at32_select_gpio(pin, mode);
9390 + }
9391 +}
9392 +
9393 +struct platform_device *__init
9394 +at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
9395 +{
9396 + /*
9397 + * Manage the chipselects as GPIOs, normally using the same pins
9398 + * the SPI controller expects; but boards can use other pins.
9399 + */
9400 + static u8 __initdata spi0_pins[] =
9401 + { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
9402 + GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
9403 + static u8 __initdata spi1_pins[] =
9404 + { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
9405 + GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
9406 + struct platform_device *pdev;
9407 +
9408 + switch (id) {
9409 + case 0:
9410 + pdev = &atmel_spi0_device;
9411 + select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
9412 + select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
9413 + select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
9414 + at32_spi_setup_slaves(0, b, n, spi0_pins);
9415 + break;
9416 +
9417 + case 1:
9418 + pdev = &atmel_spi1_device;
9419 + select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
9420 + select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
9421 + select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
9422 + at32_spi_setup_slaves(1, b, n, spi1_pins);
9423 + break;
9424 +
9425 + default:
9426 + return NULL;
9427 + }
9428 +
9429 + spi_register_board_info(b, n);
9430 + platform_device_register(pdev);
9431 + return pdev;
9432 +}
9433 +
9434 +/* --------------------------------------------------------------------
9435 + * TWI
9436 + * -------------------------------------------------------------------- */
9437 +static struct resource atmel_twi0_resource[] __initdata = {
9438 + PBMEM(0xffe00800),
9439 + IRQ(5),
9440 +};
9441 +static struct clk atmel_twi0_pclk = {
9442 + .name = "twi_pclk",
9443 + .parent = &pba_clk,
9444 + .mode = pba_clk_mode,
9445 + .get_rate = pba_clk_get_rate,
9446 + .index = 2,
9447 +};
9448 +
9449 +struct platform_device *__init at32_add_device_twi(unsigned int id,
9450 + struct i2c_board_info *b,
9451 + unsigned int n)
9452 +{
9453 + struct platform_device *pdev;
9454 +
9455 + if (id != 0)
9456 + return NULL;
9457 +
9458 + pdev = platform_device_alloc("atmel_twi", id);
9459 + if (!pdev)
9460 + return NULL;
9461 +
9462 + if (platform_device_add_resources(pdev, atmel_twi0_resource,
9463 + ARRAY_SIZE(atmel_twi0_resource)))
9464 + goto err_add_resources;
9465 +
9466 + select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
9467 + select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
9468 +
9469 + atmel_twi0_pclk.dev = &pdev->dev;
9470 +
9471 + if (b)
9472 + i2c_register_board_info(id, b, n);
9473 +
9474 + platform_device_add(pdev);
9475 + return pdev;
9476 +
9477 +err_add_resources:
9478 + platform_device_put(pdev);
9479 + return NULL;
9480 +}
9481 +
9482 +/* --------------------------------------------------------------------
9483 + * MMC
9484 + * -------------------------------------------------------------------- */
9485 +static struct resource atmel_mci0_resource[] __initdata = {
9486 + PBMEM(0xfff02400),
9487 + IRQ(28),
9488 +};
9489 +static struct clk atmel_mci0_pclk = {
9490 + .name = "mci_clk",
9491 + .parent = &pbb_clk,
9492 + .mode = pbb_clk_mode,
9493 + .get_rate = pbb_clk_get_rate,
9494 + .index = 9,
9495 +};
9496 +
9497 +struct platform_device *__init
9498 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
9499 +{
9500 + struct platform_device *pdev;
9501 +
9502 + if (id != 0)
9503 + return NULL;
9504 +
9505 + pdev = platform_device_alloc("atmel_mci", id);
9506 + if (!pdev)
9507 + goto fail;
9508 +
9509 + if (platform_device_add_resources(pdev, atmel_mci0_resource,
9510 + ARRAY_SIZE(atmel_mci0_resource)))
9511 + goto fail;
9512 +
9513 + if (data && platform_device_add_data(pdev, data,
9514 + sizeof(struct mci_platform_data)))
9515 + goto fail;
9516 +
9517 + select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
9518 + select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
9519 + select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
9520 + select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
9521 + select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
9522 + select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
9523 +
9524 + if (data) {
9525 + if (data->detect_pin != GPIO_PIN_NONE)
9526 + at32_select_gpio(data->detect_pin, 0);
9527 + if (data->wp_pin != GPIO_PIN_NONE)
9528 + at32_select_gpio(data->wp_pin, 0);
9529 + }
9530 +
9531 + atmel_mci0_pclk.dev = &pdev->dev;
9532 +
9533 + platform_device_add(pdev);
9534 + return pdev;
9535 +
9536 +fail:
9537 + platform_device_put(pdev);
9538 + return NULL;
9539 +}
9540 +
9541 +/* --------------------------------------------------------------------
9542 + * LCDC
9543 + * -------------------------------------------------------------------- */
9544 +#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
9545 +static struct atmel_lcdfb_info atmel_lcdfb0_data;
9546 +static struct resource atmel_lcdfb0_resource[] = {
9547 + {
9548 + .start = 0xff000000,
9549 + .end = 0xff000fff,
9550 + .flags = IORESOURCE_MEM,
9551 + },
9552 + IRQ(1),
9553 + {
9554 + /* Placeholder for pre-allocated fb memory */
9555 + .start = 0x00000000,
9556 + .end = 0x00000000,
9557 + .flags = 0,
9558 + },
9559 +};
9560 +DEFINE_DEV_DATA(atmel_lcdfb, 0);
9561 +DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
9562 +static struct clk atmel_lcdfb0_pixclk = {
9563 + .name = "lcdc_clk",
9564 + .dev = &atmel_lcdfb0_device.dev,
9565 + .mode = genclk_mode,
9566 + .get_rate = genclk_get_rate,
9567 + .set_rate = genclk_set_rate,
9568 + .set_parent = genclk_set_parent,
9569 + .index = 7,
9570 +};
9571 +
9572 +struct platform_device *__init
9573 +at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
9574 + unsigned long fbmem_start, unsigned long fbmem_len)
9575 +{
9576 + struct platform_device *pdev;
9577 + struct atmel_lcdfb_info *info;
9578 + struct fb_monspecs *monspecs;
9579 + struct fb_videomode *modedb;
9580 + unsigned int modedb_size;
9581 +
9582 + /*
9583 + * Do a deep copy of the fb data, monspecs and modedb. Make
9584 + * sure all allocations are done before setting up the
9585 + * portmux.
9586 + */
9587 + monspecs = kmemdup(data->default_monspecs,
9588 + sizeof(struct fb_monspecs), GFP_KERNEL);
9589 + if (!monspecs)
9590 + return NULL;
9591 +
9592 + modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
9593 + modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
9594 + if (!modedb)
9595 + goto err_dup_modedb;
9596 + monspecs->modedb = modedb;
9597 +
9598 + switch (id) {
9599 + case 0:
9600 + pdev = &atmel_lcdfb0_device;
9601 + select_peripheral(PC(19), PERIPH_A, 0); /* CC */
9602 + select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
9603 + select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
9604 + select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
9605 + select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
9606 + select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
9607 + select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
9608 + select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
9609 + select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
9610 + select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
9611 + select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
9612 + select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
9613 + select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
9614 + select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
9615 + select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
9616 + select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
9617 + select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
9618 + select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
9619 + select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
9620 + select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
9621 + select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
9622 + select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
9623 + select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
9624 + select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
9625 + select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
9626 + select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
9627 + select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
9628 + select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
9629 + select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
9630 + select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
9631 + select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
9632 +
9633 + clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
9634 + clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
9635 + break;
9636 +
9637 + default:
9638 + goto err_invalid_id;
9639 + }
9640 +
9641 + if (fbmem_len) {
9642 + pdev->resource[2].start = fbmem_start;
9643 + pdev->resource[2].end = fbmem_start + fbmem_len - 1;
9644 + pdev->resource[2].flags = IORESOURCE_MEM;
9645 + }
9646 +
9647 + info = pdev->dev.platform_data;
9648 + memcpy(info, data, sizeof(struct atmel_lcdfb_info));
9649 + info->default_monspecs = monspecs;
9650 +
9651 + platform_device_register(pdev);
9652 + return pdev;
9653 +
9654 +err_invalid_id:
9655 + kfree(modedb);
9656 +err_dup_modedb:
9657 + kfree(monspecs);
9658 + return NULL;
9659 +}
9660 +#endif
9661 +
9662 +/* --------------------------------------------------------------------
9663 + * PWM
9664 + * -------------------------------------------------------------------- */
9665 +static struct resource atmel_pwm0_resource[] __initdata = {
9666 + PBMEM(0xfff01400),
9667 + IRQ(24),
9668 +};
9669 +static struct clk atmel_pwm0_mck = {
9670 + .name = "mck",
9671 + .parent = &pbb_clk,
9672 + .mode = pbb_clk_mode,
9673 + .get_rate = pbb_clk_get_rate,
9674 + .index = 5,
9675 +};
9676 +
9677 +struct platform_device *__init at32_add_device_pwm(u32 mask)
9678 +{
9679 + struct platform_device *pdev;
9680 +
9681 + if (!mask)
9682 + return NULL;
9683 +
9684 + pdev = platform_device_alloc("atmel_pwm", 0);
9685 + if (!pdev)
9686 + return NULL;
9687 +
9688 + if (platform_device_add_resources(pdev, atmel_pwm0_resource,
9689 + ARRAY_SIZE(atmel_pwm0_resource)))
9690 + goto out_free_pdev;
9691 +
9692 + if (platform_device_add_data(pdev, &mask, sizeof(mask)))
9693 + goto out_free_pdev;
9694 +
9695 + if (mask & (1 << 0))
9696 + select_peripheral(PA(28), PERIPH_A, 0);
9697 + if (mask & (1 << 1))
9698 + select_peripheral(PA(29), PERIPH_A, 0);
9699 + if (mask & (1 << 2))
9700 + select_peripheral(PA(21), PERIPH_B, 0);
9701 + if (mask & (1 << 3))
9702 + select_peripheral(PA(22), PERIPH_B, 0);
9703 +
9704 + atmel_pwm0_mck.dev = &pdev->dev;
9705 +
9706 + platform_device_add(pdev);
9707 +
9708 + return pdev;
9709 +
9710 +out_free_pdev:
9711 + platform_device_put(pdev);
9712 + return NULL;
9713 +}
9714 +
9715 +/* --------------------------------------------------------------------
9716 + * SSC
9717 + * -------------------------------------------------------------------- */
9718 +static struct resource ssc0_resource[] = {
9719 + PBMEM(0xffe01c00),
9720 + IRQ(10),
9721 +};
9722 +DEFINE_DEV(ssc, 0);
9723 +DEV_CLK(pclk, ssc0, pba, 7);
9724 +
9725 +static struct resource ssc1_resource[] = {
9726 + PBMEM(0xffe02000),
9727 + IRQ(11),
9728 +};
9729 +DEFINE_DEV(ssc, 1);
9730 +DEV_CLK(pclk, ssc1, pba, 8);
9731 +
9732 +static struct resource ssc2_resource[] = {
9733 + PBMEM(0xffe02400),
9734 + IRQ(12),
9735 +};
9736 +DEFINE_DEV(ssc, 2);
9737 +DEV_CLK(pclk, ssc2, pba, 9);
9738 +
9739 +struct platform_device *__init
9740 +at32_add_device_ssc(unsigned int id, unsigned int flags)
9741 +{
9742 + struct platform_device *pdev;
9743 +
9744 + switch (id) {
9745 + case 0:
9746 + pdev = &ssc0_device;
9747 + if (flags & ATMEL_SSC_RF)
9748 + select_peripheral(PA(21), PERIPH_A, 0); /* RF */
9749 + if (flags & ATMEL_SSC_RK)
9750 + select_peripheral(PA(22), PERIPH_A, 0); /* RK */
9751 + if (flags & ATMEL_SSC_TK)
9752 + select_peripheral(PA(23), PERIPH_A, 0); /* TK */
9753 + if (flags & ATMEL_SSC_TF)
9754 + select_peripheral(PA(24), PERIPH_A, 0); /* TF */
9755 + if (flags & ATMEL_SSC_TD)
9756 + select_peripheral(PA(25), PERIPH_A, 0); /* TD */
9757 + if (flags & ATMEL_SSC_RD)
9758 + select_peripheral(PA(26), PERIPH_A, 0); /* RD */
9759 + break;
9760 + case 1:
9761 + pdev = &ssc1_device;
9762 + if (flags & ATMEL_SSC_RF)
9763 + select_peripheral(PA(0), PERIPH_B, 0); /* RF */
9764 + if (flags & ATMEL_SSC_RK)
9765 + select_peripheral(PA(1), PERIPH_B, 0); /* RK */
9766 + if (flags & ATMEL_SSC_TK)
9767 + select_peripheral(PA(2), PERIPH_B, 0); /* TK */
9768 + if (flags & ATMEL_SSC_TF)
9769 + select_peripheral(PA(3), PERIPH_B, 0); /* TF */
9770 + if (flags & ATMEL_SSC_TD)
9771 + select_peripheral(PA(4), PERIPH_B, 0); /* TD */
9772 + if (flags & ATMEL_SSC_RD)
9773 + select_peripheral(PA(5), PERIPH_B, 0); /* RD */
9774 + break;
9775 + case 2:
9776 + pdev = &ssc2_device;
9777 + if (flags & ATMEL_SSC_TD)
9778 + select_peripheral(PB(13), PERIPH_A, 0); /* TD */
9779 + if (flags & ATMEL_SSC_RD)
9780 + select_peripheral(PB(14), PERIPH_A, 0); /* RD */
9781 + if (flags & ATMEL_SSC_TK)
9782 + select_peripheral(PB(15), PERIPH_A, 0); /* TK */
9783 + if (flags & ATMEL_SSC_TF)
9784 + select_peripheral(PB(16), PERIPH_A, 0); /* TF */
9785 + if (flags & ATMEL_SSC_RF)
9786 + select_peripheral(PB(17), PERIPH_A, 0); /* RF */
9787 + if (flags & ATMEL_SSC_RK)
9788 + select_peripheral(PB(18), PERIPH_A, 0); /* RK */
9789 + break;
9790 + default:
9791 + return NULL;
9792 + }
9793 +
9794 + platform_device_register(pdev);
9795 + return pdev;
9796 +}
9797 +
9798 +/* --------------------------------------------------------------------
9799 + * USB Device Controller
9800 + * -------------------------------------------------------------------- */
9801 +static struct resource usba0_resource[] __initdata = {
9802 + {
9803 + .start = 0xff300000,
9804 + .end = 0xff3fffff,
9805 + .flags = IORESOURCE_MEM,
9806 + }, {
9807 + .start = 0xfff03000,
9808 + .end = 0xfff033ff,
9809 + .flags = IORESOURCE_MEM,
9810 + },
9811 + IRQ(31),
9812 +};
9813 +static struct clk usba0_pclk = {
9814 + .name = "pclk",
9815 + .parent = &pbb_clk,
9816 + .mode = pbb_clk_mode,
9817 + .get_rate = pbb_clk_get_rate,
9818 + .index = 12,
9819 +};
9820 +static struct clk usba0_hclk = {
9821 + .name = "hclk",
9822 + .parent = &hsb_clk,
9823 + .mode = hsb_clk_mode,
9824 + .get_rate = hsb_clk_get_rate,
9825 + .index = 6,
9826 +};
9827 +
9828 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
9829 + [idx] = { \
9830 + .name = nam, \
9831 + .index = idx, \
9832 + .fifo_size = maxpkt, \
9833 + .nr_banks = maxbk, \
9834 + .can_dma = dma, \
9835 + .can_isoc = isoc, \
9836 + }
9837 +
9838 +static struct usba_ep_data at32_usba_ep[] __initdata = {
9839 + EP("ep0", 0, 64, 1, 0, 0),
9840 + EP("ep1", 1, 512, 2, 1, 1),
9841 + EP("ep2", 2, 512, 2, 1, 1),
9842 + EP("ep3-int", 3, 64, 3, 1, 0),
9843 + EP("ep4-int", 4, 64, 3, 1, 0),
9844 + EP("ep5", 5, 1024, 3, 1, 1),
9845 + EP("ep6", 6, 1024, 3, 1, 1),
9846 +};
9847 +
9848 +#undef EP
9849 +
9850 +struct platform_device *__init
9851 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
9852 +{
9853 + /*
9854 + * pdata doesn't have room for any endpoints, so we need to
9855 + * append room for the ones we need right after it.
9856 + */
9857 + struct {
9858 + struct usba_platform_data pdata;
9859 + struct usba_ep_data ep[7];
9860 + } usba_data;
9861 + struct platform_device *pdev;
9862 +
9863 + if (id != 0)
9864 + return NULL;
9865 +
9866 + pdev = platform_device_alloc("atmel_usba_udc", 0);
9867 + if (!pdev)
9868 + return NULL;
9869 +
9870 + if (platform_device_add_resources(pdev, usba0_resource,
9871 + ARRAY_SIZE(usba0_resource)))
9872 + goto out_free_pdev;
9873 +
9874 + if (data)
9875 + usba_data.pdata.vbus_pin = data->vbus_pin;
9876 + else
9877 + usba_data.pdata.vbus_pin = -EINVAL;
9878 +
9879 + data = &usba_data.pdata;
9880 + data->num_ep = ARRAY_SIZE(at32_usba_ep);
9881 + memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
9882 +
9883 + if (platform_device_add_data(pdev, data, sizeof(usba_data)))
9884 + goto out_free_pdev;
9885 +
9886 + if (data->vbus_pin >= 0)
9887 + at32_select_gpio(data->vbus_pin, 0);
9888 +
9889 + usba0_pclk.dev = &pdev->dev;
9890 + usba0_hclk.dev = &pdev->dev;
9891 +
9892 + platform_device_add(pdev);
9893 +
9894 + return pdev;
9895 +
9896 +out_free_pdev:
9897 + platform_device_put(pdev);
9898 + return NULL;
9899 +}
9900 +
9901 +/* --------------------------------------------------------------------
9902 + * IDE / CompactFlash
9903 + * -------------------------------------------------------------------- */
9904 +#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
9905 +static struct resource at32_smc_cs4_resource[] __initdata = {
9906 + {
9907 + .start = 0x04000000,
9908 + .end = 0x07ffffff,
9909 + .flags = IORESOURCE_MEM,
9910 + },
9911 + IRQ(~0UL), /* Magic IRQ will be overridden */
9912 +};
9913 +static struct resource at32_smc_cs5_resource[] __initdata = {
9914 + {
9915 + .start = 0x20000000,
9916 + .end = 0x23ffffff,
9917 + .flags = IORESOURCE_MEM,
9918 + },
9919 + IRQ(~0UL), /* Magic IRQ will be overridden */
9920 +};
9921 +
9922 +static int __init at32_init_ide_or_cf(struct platform_device *pdev,
9923 + unsigned int cs, unsigned int extint)
9924 +{
9925 + static unsigned int extint_pin_map[4] __initdata = {
9926 + GPIO_PIN_PB(25),
9927 + GPIO_PIN_PB(26),
9928 + GPIO_PIN_PB(27),
9929 + GPIO_PIN_PB(28),
9930 + };
9931 + static bool common_pins_initialized __initdata = false;
9932 + unsigned int extint_pin;
9933 + int ret;
9934 +
9935 + if (extint >= ARRAY_SIZE(extint_pin_map))
9936 + return -EINVAL;
9937 + extint_pin = extint_pin_map[extint];
9938 +
9939 + switch (cs) {
9940 + case 4:
9941 + ret = platform_device_add_resources(pdev,
9942 + at32_smc_cs4_resource,
9943 + ARRAY_SIZE(at32_smc_cs4_resource));
9944 + if (ret)
9945 + return ret;
9946 +
9947 + select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
9948 + set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
9949 + break;
9950 + case 5:
9951 + ret = platform_device_add_resources(pdev,
9952 + at32_smc_cs5_resource,
9953 + ARRAY_SIZE(at32_smc_cs5_resource));
9954 + if (ret)
9955 + return ret;
9956 +
9957 + select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
9958 + set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
9959 + break;
9960 + default:
9961 + return -EINVAL;
9962 + }
9963 +
9964 + if (!common_pins_initialized) {
9965 + select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
9966 + select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
9967 + select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
9968 + select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
9969 + common_pins_initialized = true;
9970 + }
9971 +
9972 + at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
9973 +
9974 + pdev->resource[1].start = EIM_IRQ_BASE + extint;
9975 + pdev->resource[1].end = pdev->resource[1].start;
9976 +
9977 + return 0;
9978 +}
9979 +
9980 +struct platform_device *__init
9981 +at32_add_device_ide(unsigned int id, unsigned int extint,
9982 + struct ide_platform_data *data)
9983 +{
9984 + struct platform_device *pdev;
9985 +
9986 + pdev = platform_device_alloc("at32_ide", id);
9987 + if (!pdev)
9988 + goto fail;
9989 +
9990 + if (platform_device_add_data(pdev, data,
9991 + sizeof(struct ide_platform_data)))
9992 + goto fail;
9993 +
9994 + if (at32_init_ide_or_cf(pdev, data->cs, extint))
9995 + goto fail;
9996 +
9997 + platform_device_add(pdev);
9998 + return pdev;
9999 +
10000 +fail:
10001 + platform_device_put(pdev);
10002 + return NULL;
10003 +}
10004 +
10005 +struct platform_device *__init
10006 +at32_add_device_cf(unsigned int id, unsigned int extint,
10007 + struct cf_platform_data *data)
10008 +{
10009 + struct platform_device *pdev;
10010 +
10011 + pdev = platform_device_alloc("at32_cf", id);
10012 + if (!pdev)
10013 + goto fail;
10014 +
10015 + if (platform_device_add_data(pdev, data,
10016 + sizeof(struct cf_platform_data)))
10017 + goto fail;
10018 +
10019 + if (at32_init_ide_or_cf(pdev, data->cs, extint))
10020 + goto fail;
10021 +
10022 + if (data->detect_pin != GPIO_PIN_NONE)
10023 + at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
10024 + if (data->reset_pin != GPIO_PIN_NONE)
10025 + at32_select_gpio(data->reset_pin, 0);
10026 + if (data->vcc_pin != GPIO_PIN_NONE)
10027 + at32_select_gpio(data->vcc_pin, 0);
10028 + /* READY is used as extint, so we can't select it as gpio */
10029 +
10030 + platform_device_add(pdev);
10031 + return pdev;
10032 +
10033 +fail:
10034 + platform_device_put(pdev);
10035 + return NULL;
10036 +}
10037 +#endif
10038 +
10039 +/* --------------------------------------------------------------------
10040 + * AC97C
10041 + * -------------------------------------------------------------------- */
10042 +static struct resource atmel_ac97c0_resource[] __initdata = {
10043 + PBMEM(0xfff02800),
10044 + IRQ(29),
10045 +};
10046 +static struct clk atmel_ac97c0_pclk = {
10047 + .name = "pclk",
10048 + .parent = &pbb_clk,
10049 + .mode = pbb_clk_mode,
10050 + .get_rate = pbb_clk_get_rate,
10051 + .index = 10,
10052 +};
10053 +
10054 +struct platform_device *__init at32_add_device_ac97c(unsigned int id)
10055 +{
10056 + struct platform_device *pdev;
10057 +
10058 + if (id != 0)
10059 + return NULL;
10060 +
10061 + pdev = platform_device_alloc("atmel_ac97c", id);
10062 + if (!pdev)
10063 + return NULL;
10064 +
10065 + if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
10066 + ARRAY_SIZE(atmel_ac97c0_resource)))
10067 + goto err_add_resources;
10068 +
10069 + select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
10070 + select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
10071 + select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
10072 + select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
10073 +
10074 + atmel_ac97c0_pclk.dev = &pdev->dev;
10075 +
10076 + platform_device_add(pdev);
10077 + return pdev;
10078 +
10079 +err_add_resources:
10080 + platform_device_put(pdev);
10081 + return NULL;
10082 +}
10083 +
10084 +/* --------------------------------------------------------------------
10085 + * ABDAC
10086 + * -------------------------------------------------------------------- */
10087 +static struct resource abdac0_resource[] __initdata = {
10088 + PBMEM(0xfff02000),
10089 + IRQ(27),
10090 +};
10091 +static struct clk abdac0_pclk = {
10092 + .name = "pclk",
10093 + .parent = &pbb_clk,
10094 + .mode = pbb_clk_mode,
10095 + .get_rate = pbb_clk_get_rate,
10096 + .index = 8,
10097 +};
10098 +static struct clk abdac0_sample_clk = {
10099 + .name = "sample_clk",
10100 + .mode = genclk_mode,
10101 + .get_rate = genclk_get_rate,
10102 + .set_rate = genclk_set_rate,
10103 + .set_parent = genclk_set_parent,
10104 + .index = 6,
10105 +};
10106 +
10107 +struct platform_device *__init at32_add_device_abdac(unsigned int id)
10108 +{
10109 + struct platform_device *pdev;
10110 +
10111 + if (id != 0)
10112 + return NULL;
10113 +
10114 + pdev = platform_device_alloc("abdac", id);
10115 + if (!pdev)
10116 + return NULL;
10117 +
10118 + if (platform_device_add_resources(pdev, abdac0_resource,
10119 + ARRAY_SIZE(abdac0_resource)))
10120 + goto err_add_resources;
10121 +
10122 + select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
10123 + select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
10124 + select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
10125 + select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
10126 +
10127 + abdac0_pclk.dev = &pdev->dev;
10128 + abdac0_sample_clk.dev = &pdev->dev;
10129 +
10130 + platform_device_add(pdev);
10131 + return pdev;
10132 +
10133 +err_add_resources:
10134 + platform_device_put(pdev);
10135 + return NULL;
10136 +}
10137 +
10138 +/* --------------------------------------------------------------------
10139 + * GCLK
10140 + * -------------------------------------------------------------------- */
10141 +static struct clk gclk0 = {
10142 + .name = "gclk0",
10143 + .mode = genclk_mode,
10144 + .get_rate = genclk_get_rate,
10145 + .set_rate = genclk_set_rate,
10146 + .set_parent = genclk_set_parent,
10147 + .index = 0,
10148 +};
10149 +static struct clk gclk1 = {
10150 + .name = "gclk1",
10151 + .mode = genclk_mode,
10152 + .get_rate = genclk_get_rate,
10153 + .set_rate = genclk_set_rate,
10154 + .set_parent = genclk_set_parent,
10155 + .index = 1,
10156 +};
10157 +static struct clk gclk2 = {
10158 + .name = "gclk2",
10159 + .mode = genclk_mode,
10160 + .get_rate = genclk_get_rate,
10161 + .set_rate = genclk_set_rate,
10162 + .set_parent = genclk_set_parent,
10163 + .index = 2,
10164 +};
10165 +static struct clk gclk3 = {
10166 + .name = "gclk3",
10167 + .mode = genclk_mode,
10168 + .get_rate = genclk_get_rate,
10169 + .set_rate = genclk_set_rate,
10170 + .set_parent = genclk_set_parent,
10171 + .index = 3,
10172 +};
10173 +static struct clk gclk4 = {
10174 + .name = "gclk4",
10175 + .mode = genclk_mode,
10176 + .get_rate = genclk_get_rate,
10177 + .set_rate = genclk_set_rate,
10178 + .set_parent = genclk_set_parent,
10179 + .index = 4,
10180 +};
10181 +
10182 +struct clk *at32_clock_list[] = {
10183 + &osc32k,
10184 + &osc0,
10185 + &osc1,
10186 + &pll0,
10187 + &pll1,
10188 + &cpu_clk,
10189 + &hsb_clk,
10190 + &pba_clk,
10191 + &pbb_clk,
10192 + &at32_pm_pclk,
10193 + &at32_intc0_pclk,
10194 + &hmatrix_clk,
10195 + &ebi_clk,
10196 + &hramc_clk,
10197 + &smc0_pclk,
10198 + &smc0_mck,
10199 + &pdc_hclk,
10200 + &pdc_pclk,
10201 + &dmaca0_hclk,
10202 + &pico_clk,
10203 + &pio0_mck,
10204 + &pio1_mck,
10205 + &pio2_mck,
10206 + &pio3_mck,
10207 + &pio4_mck,
10208 + &at32_tcb0_t0_clk,
10209 + &at32_tcb1_t0_clk,
10210 + &atmel_psif0_pclk,
10211 + &atmel_psif1_pclk,
10212 + &atmel_usart0_usart,
10213 + &atmel_usart1_usart,
10214 + &atmel_usart2_usart,
10215 + &atmel_usart3_usart,
10216 + &atmel_pwm0_mck,
10217 +#if defined(CONFIG_CPU_AT32AP7000)
10218 + &macb0_hclk,
10219 + &macb0_pclk,
10220 + &macb1_hclk,
10221 + &macb1_pclk,
10222 +#endif
10223 + &atmel_spi0_spi_clk,
10224 + &atmel_spi1_spi_clk,
10225 + &atmel_twi0_pclk,
10226 + &atmel_mci0_pclk,
10227 +#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
10228 + &atmel_lcdfb0_hck1,
10229 + &atmel_lcdfb0_pixclk,
10230 +#endif
10231 + &ssc0_pclk,
10232 + &ssc1_pclk,
10233 + &ssc2_pclk,
10234 + &usba0_hclk,
10235 + &usba0_pclk,
10236 + &atmel_ac97c0_pclk,
10237 + &abdac0_pclk,
10238 + &abdac0_sample_clk,
10239 + &gclk0,
10240 + &gclk1,
10241 + &gclk2,
10242 + &gclk3,
10243 + &gclk4,
10244 +};
10245 +unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
10246 +
10247 +void __init at32_portmux_init(void)
10248 +{
10249 + at32_init_pio(&pio0_device);
10250 + at32_init_pio(&pio1_device);
10251 + at32_init_pio(&pio2_device);
10252 + at32_init_pio(&pio3_device);
10253 + at32_init_pio(&pio4_device);
10254 +}
10255 +
10256 +void __init at32_clock_init(void)
10257 +{
10258 + u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
10259 + int i;
10260 +
10261 + if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
10262 + main_clock = &pll0;
10263 + cpu_clk.parent = &pll0;
10264 + } else {
10265 + main_clock = &osc0;
10266 + cpu_clk.parent = &osc0;
10267 + }
10268 +
10269 + if (pm_readl(PLL0) & PM_BIT(PLLOSC))
10270 + pll0.parent = &osc1;
10271 + if (pm_readl(PLL1) & PM_BIT(PLLOSC))
10272 + pll1.parent = &osc1;
10273 +
10274 + genclk_init_parent(&gclk0);
10275 + genclk_init_parent(&gclk1);
10276 + genclk_init_parent(&gclk2);
10277 + genclk_init_parent(&gclk3);
10278 + genclk_init_parent(&gclk4);
10279 +#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
10280 + genclk_init_parent(&atmel_lcdfb0_pixclk);
10281 +#endif
10282 + genclk_init_parent(&abdac0_sample_clk);
10283 +
10284 + /*
10285 + * Turn on all clocks that have at least one user already, and
10286 + * turn off everything else. We only do this for module
10287 + * clocks, and even though it isn't particularly pretty to
10288 + * check the address of the mode function, it should do the
10289 + * trick...
10290 + */
10291 + for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
10292 + struct clk *clk = at32_clock_list[i];
10293 +
10294 + if (clk->users == 0)
10295 + continue;
10296 +
10297 + if (clk->mode == &cpu_clk_mode)
10298 + cpu_mask |= 1 << clk->index;
10299 + else if (clk->mode == &hsb_clk_mode)
10300 + hsb_mask |= 1 << clk->index;
10301 + else if (clk->mode == &pba_clk_mode)
10302 + pba_mask |= 1 << clk->index;
10303 + else if (clk->mode == &pbb_clk_mode)
10304 + pbb_mask |= 1 << clk->index;
10305 + }
10306 +
10307 + pm_writel(CPU_MASK, cpu_mask);
10308 + pm_writel(HSB_MASK, hsb_mask);
10309 + pm_writel(PBA_MASK, pba_mask);
10310 + pm_writel(PBB_MASK, pbb_mask);
10311 +}
10312 --- a/arch/avr32/mach-at32ap/extint.c
10313 +++ b/arch/avr32/mach-at32ap/extint.c
10314 @@ -26,16 +26,10 @@
10315 #define EIC_MODE 0x0014
10316 #define EIC_EDGE 0x0018
10317 #define EIC_LEVEL 0x001c
10318 -#define EIC_TEST 0x0020
10319 #define EIC_NMIC 0x0024
10320
10321 -/* Bitfields in TEST */
10322 -#define EIC_TESTEN_OFFSET 31
10323 -#define EIC_TESTEN_SIZE 1
10324 -
10325 /* Bitfields in NMIC */
10326 -#define EIC_EN_OFFSET 0
10327 -#define EIC_EN_SIZE 1
10328 +#define EIC_NMIC_ENABLE (1 << 0)
10329
10330 /* Bit manipulation macros */
10331 #define EIC_BIT(name) \
10332 @@ -63,6 +57,9 @@
10333 unsigned int first_irq;
10334 };
10335
10336 +static struct eic *nmi_eic;
10337 +static bool nmi_enabled;
10338 +
10339 static void eic_ack_irq(unsigned int irq)
10340 {
10341 struct eic *eic = get_irq_chip_data(irq);
10342 @@ -133,8 +130,11 @@
10343 eic_writel(eic, EDGE, edge);
10344 eic_writel(eic, LEVEL, level);
10345
10346 - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
10347 + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
10348 flow_type |= IRQ_LEVEL;
10349 + __set_irq_handler_unlocked(irq, handle_level_irq);
10350 + } else
10351 + __set_irq_handler_unlocked(irq, handle_edge_irq);
10352 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
10353 desc->status |= flow_type;
10354 }
10355 @@ -154,9 +154,8 @@
10356 static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
10357 {
10358 struct eic *eic = desc->handler_data;
10359 - struct irq_desc *ext_desc;
10360 unsigned long status, pending;
10361 - unsigned int i, ext_irq;
10362 + unsigned int i;
10363
10364 status = eic_readl(eic, ISR);
10365 pending = status & eic_readl(eic, IMR);
10366 @@ -165,15 +164,28 @@
10367 i = fls(pending) - 1;
10368 pending &= ~(1 << i);
10369
10370 - ext_irq = i + eic->first_irq;
10371 - ext_desc = irq_desc + ext_irq;
10372 - if (ext_desc->status & IRQ_LEVEL)
10373 - handle_level_irq(ext_irq, ext_desc);
10374 - else
10375 - handle_edge_irq(ext_irq, ext_desc);
10376 + generic_handle_irq(i + eic->first_irq);
10377 }
10378 }
10379
10380 +int nmi_enable(void)
10381 +{
10382 + nmi_enabled = true;
10383 +
10384 + if (nmi_eic)
10385 + eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
10386 +
10387 + return 0;
10388 +}
10389 +
10390 +void nmi_disable(void)
10391 +{
10392 + if (nmi_eic)
10393 + eic_writel(nmi_eic, NMIC, 0);
10394 +
10395 + nmi_enabled = false;
10396 +}
10397 +
10398 static int __init eic_probe(struct platform_device *pdev)
10399 {
10400 struct eic *eic;
10401 @@ -214,14 +226,13 @@
10402 pattern = eic_readl(eic, MODE);
10403 nr_irqs = fls(pattern);
10404
10405 - /* Trigger on falling edge unless overridden by driver */
10406 - eic_writel(eic, MODE, 0UL);
10407 + /* Trigger on low level unless overridden by driver */
10408 eic_writel(eic, EDGE, 0UL);
10409 + eic_writel(eic, LEVEL, 0UL);
10410
10411 eic->chip = &eic_chip;
10412
10413 for (i = 0; i < nr_irqs; i++) {
10414 - /* NOTE the handler we set here is ignored by the demux */
10415 set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
10416 handle_level_irq);
10417 set_irq_chip_data(eic->first_irq + i, eic);
10418 @@ -230,6 +241,16 @@
10419 set_irq_chained_handler(int_irq, demux_eic_irq);
10420 set_irq_data(int_irq, eic);
10421
10422 + if (pdev->id == 0) {
10423 + nmi_eic = eic;
10424 + if (nmi_enabled)
10425 + /*
10426 + * Someone tried to enable NMI before we were
10427 + * ready. Do it now.
10428 + */
10429 + nmi_enable();
10430 + }
10431 +
10432 dev_info(&pdev->dev,
10433 "External Interrupt Controller at 0x%p, IRQ %u\n",
10434 eic->regs, int_irq);
10435 --- /dev/null
10436 +++ b/arch/avr32/mach-at32ap/gpio-dev.c
10437 @@ -0,0 +1,573 @@
10438 +/*
10439 + * GPIO /dev and configfs interface
10440 + *
10441 + * Copyright (C) 2006-2007 Atmel Corporation
10442 + *
10443 + * This program is free software; you can redistribute it and/or modify
10444 + * it under the terms of the GNU General Public License version 2 as
10445 + * published by the Free Software Foundation.
10446 + */
10447 +#include <linux/kernel.h>
10448 +#include <linux/configfs.h>
10449 +#include <linux/cdev.h>
10450 +#include <linux/device.h>
10451 +#include <linux/fs.h>
10452 +#include <linux/interrupt.h>
10453 +#include <linux/module.h>
10454 +#include <linux/poll.h>
10455 +#include <linux/uaccess.h>
10456 +#include <linux/wait.h>
10457 +
10458 +#include <asm/gpio.h>
10459 +#include <asm/arch/portmux.h>
10460 +
10461 +#define GPIO_DEV_MAX 8
10462 +
10463 +static struct class *gpio_dev_class;
10464 +static dev_t gpio_devt;
10465 +
10466 +struct gpio_item {
10467 + spinlock_t lock;
10468 +
10469 + int enabled;
10470 + int initialized;
10471 + int port;
10472 + u32 pin_mask;
10473 + u32 oe_mask;
10474 +
10475 + /* Pin state last time we read it (for blocking reads) */
10476 + u32 pin_state;
10477 + int changed;
10478 +
10479 + wait_queue_head_t change_wq;
10480 + struct fasync_struct *async_queue;
10481 +
10482 + int id;
10483 + struct class_device *gpio_dev;
10484 + struct cdev char_dev;
10485 + struct config_item item;
10486 +};
10487 +
10488 +struct gpio_attribute {
10489 + struct configfs_attribute attr;
10490 + ssize_t (*show)(struct gpio_item *, char *);
10491 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
10492 +};
10493 +
10494 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
10495 +{
10496 + struct gpio_item *gpio = dev_id;
10497 + u32 old_state, new_state;
10498 +
10499 + old_state = gpio->pin_state;
10500 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
10501 + gpio->pin_state = new_state;
10502 +
10503 + if (new_state != old_state) {
10504 + gpio->changed = 1;
10505 + wake_up_interruptible(&gpio->change_wq);
10506 +
10507 + if (gpio->async_queue)
10508 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
10509 + }
10510 +
10511 + return IRQ_HANDLED;
10512 +}
10513 +
10514 +static int gpio_dev_open(struct inode *inode, struct file *file)
10515 +{
10516 + struct gpio_item *gpio = container_of(inode->i_cdev,
10517 + struct gpio_item,
10518 + char_dev);
10519 + unsigned int irq;
10520 + unsigned int i;
10521 + int ret;
10522 +
10523 + nonseekable_open(inode, file);
10524 + config_item_get(&gpio->item);
10525 + file->private_data = gpio;
10526 +
10527 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
10528 + gpio->pin_mask);
10529 + gpio->changed = 1;
10530 +
10531 + for (i = 0; i < 32; i++) {
10532 + if (gpio->pin_mask & (1 << i)) {
10533 + irq = gpio_to_irq(32 * gpio->port + i);
10534 + ret = request_irq(irq, gpio_dev_interrupt, 0,
10535 + "gpio-dev", gpio);
10536 + if (ret)
10537 + goto err_irq;
10538 + }
10539 + }
10540 +
10541 + return 0;
10542 +
10543 +err_irq:
10544 + while (i--) {
10545 + if (gpio->pin_mask & (1 << i)) {
10546 + irq = gpio_to_irq(32 * gpio->port + i);
10547 + free_irq(irq, gpio);
10548 + }
10549 + }
10550 +
10551 + config_item_put(&gpio->item);
10552 +
10553 + return ret;
10554 +}
10555 +
10556 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
10557 +{
10558 + struct gpio_item *gpio = file->private_data;
10559 +
10560 + return fasync_helper(fd, file, mode, &gpio->async_queue);
10561 +}
10562 +
10563 +static int gpio_dev_release(struct inode *inode, struct file *file)
10564 +{
10565 + struct gpio_item *gpio = file->private_data;
10566 + unsigned int irq;
10567 + unsigned int i;
10568 +
10569 + gpio_dev_fasync(-1, file, 0);
10570 +
10571 + for (i = 0; i < 32; i++) {
10572 + if (gpio->pin_mask & (1 << i)) {
10573 + irq = gpio_to_irq(32 * gpio->port + i);
10574 + free_irq(irq, gpio);
10575 + }
10576 + }
10577 +
10578 + config_item_put(&gpio->item);
10579 +
10580 + return 0;
10581 +}
10582 +
10583 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
10584 +{
10585 + struct gpio_item *gpio = file->private_data;
10586 + unsigned int mask = 0;
10587 +
10588 + poll_wait(file, &gpio->change_wq, wait);
10589 + if (gpio->changed)
10590 + mask |= POLLIN | POLLRDNORM;
10591 +
10592 + return mask;
10593 +}
10594 +
10595 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
10596 + size_t count, loff_t *offset)
10597 +{
10598 + struct gpio_item *gpio = file->private_data;
10599 + u32 value;
10600 +
10601 + spin_lock_irq(&gpio->lock);
10602 + while (!gpio->changed) {
10603 + spin_unlock_irq(&gpio->lock);
10604 +
10605 + if (file->f_flags & O_NONBLOCK)
10606 + return -EAGAIN;
10607 +
10608 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
10609 + return -ERESTARTSYS;
10610 +
10611 + spin_lock_irq(&gpio->lock);
10612 + }
10613 +
10614 + gpio->changed = 0;
10615 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
10616 +
10617 + spin_unlock_irq(&gpio->lock);
10618 +
10619 + count = min(count, (size_t)4);
10620 + if (copy_to_user(buf, &value, count))
10621 + return -EFAULT;
10622 +
10623 + return count;
10624 +}
10625 +
10626 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
10627 + size_t count, loff_t *offset)
10628 +{
10629 + struct gpio_item *gpio = file->private_data;
10630 + u32 value = 0;
10631 + u32 mask = ~0UL;
10632 +
10633 + count = min(count, (size_t)4);
10634 + if (copy_from_user(&value, buf, count))
10635 + return -EFAULT;
10636 +
10637 + /* Assuming big endian */
10638 + mask <<= (4 - count) * 8;
10639 + mask &= gpio->pin_mask;
10640 +
10641 + at32_gpio_set_value_multiple(gpio->port, value, mask);
10642 +
10643 + return count;
10644 +}
10645 +
10646 +static struct file_operations gpio_dev_fops = {
10647 + .owner = THIS_MODULE,
10648 + .llseek = no_llseek,
10649 + .open = gpio_dev_open,
10650 + .release = gpio_dev_release,
10651 + .fasync = gpio_dev_fasync,
10652 + .poll = gpio_dev_poll,
10653 + .read = gpio_dev_read,
10654 + .write = gpio_dev_write,
10655 +};
10656 +
10657 +static struct gpio_item *to_gpio_item(struct config_item *item)
10658 +{
10659 + return item ? container_of(item, struct gpio_item, item) : NULL;
10660 +}
10661 +
10662 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
10663 +{
10664 + return sprintf(page, "%d\n", gpio->port);
10665 +}
10666 +
10667 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
10668 + const char *page, size_t count)
10669 +{
10670 + unsigned long id;
10671 + char *p = (char *)page;
10672 + ssize_t ret = -EINVAL;
10673 +
10674 + id = simple_strtoul(p, &p, 0);
10675 + if (!p || (*p && (*p != '\n')))
10676 + return -EINVAL;
10677 +
10678 + /* Switching PIO is not allowed when live... */
10679 + spin_lock(&gpio->lock);
10680 + if (!gpio->enabled) {
10681 + ret = -ENXIO;
10682 + if (at32_gpio_port_is_valid(id)) {
10683 + gpio->port = id;
10684 + ret = count;
10685 + }
10686 + }
10687 + spin_unlock(&gpio->lock);
10688 +
10689 + return ret;
10690 +}
10691 +
10692 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
10693 +{
10694 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
10695 +}
10696 +
10697 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
10698 + const char *page, size_t count)
10699 +{
10700 + u32 new_mask;
10701 + char *p = (char *)page;
10702 + ssize_t ret = -EINVAL;
10703 +
10704 + new_mask = simple_strtoul(p, &p, 0);
10705 + if (!p || (*p && (*p != '\n')))
10706 + return -EINVAL;
10707 +
10708 + /* Can't update the pin mask while live. */
10709 + spin_lock(&gpio->lock);
10710 + if (!gpio->enabled) {
10711 + gpio->oe_mask &= new_mask;
10712 + gpio->pin_mask = new_mask;
10713 + ret = count;
10714 + }
10715 + spin_unlock(&gpio->lock);
10716 +
10717 + return ret;
10718 +}
10719 +
10720 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
10721 +{
10722 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
10723 +}
10724 +
10725 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
10726 + const char *page, size_t count)
10727 +{
10728 + u32 mask;
10729 + char *p = (char *)page;
10730 + ssize_t ret = -EINVAL;
10731 +
10732 + mask = simple_strtoul(p, &p, 0);
10733 + if (!p || (*p && (*p != '\n')))
10734 + return -EINVAL;
10735 +
10736 + spin_lock(&gpio->lock);
10737 + if (!gpio->enabled) {
10738 + gpio->oe_mask = mask & gpio->pin_mask;
10739 + ret = count;
10740 + }
10741 + spin_unlock(&gpio->lock);
10742 +
10743 + return ret;
10744 +}
10745 +
10746 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
10747 +{
10748 + return sprintf(page, "%d\n", gpio->enabled);
10749 +}
10750 +
10751 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
10752 + const char *page, size_t count)
10753 +{
10754 + char *p = (char *)page;
10755 + int enabled;
10756 + int ret;
10757 +
10758 + enabled = simple_strtoul(p, &p, 0);
10759 + if (!p || (*p && (*p != '\n')))
10760 + return -EINVAL;
10761 +
10762 + /* make it a boolean value */
10763 + enabled = !!enabled;
10764 +
10765 + if (gpio->enabled == enabled)
10766 + /* No change; do nothing. */
10767 + return count;
10768 +
10769 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
10770 +
10771 + if (!enabled) {
10772 + class_device_unregister(gpio->gpio_dev);
10773 + cdev_del(&gpio->char_dev);
10774 + at32_deselect_pins(gpio->port, gpio->pin_mask);
10775 + gpio->initialized = 0;
10776 + } else {
10777 + if (gpio->port < 0 || !gpio->pin_mask)
10778 + return -ENODEV;
10779 + }
10780 +
10781 + /* Disallow any updates to gpio_id or pin_mask */
10782 + spin_lock(&gpio->lock);
10783 + gpio->enabled = enabled;
10784 + spin_unlock(&gpio->lock);
10785 +
10786 + if (!enabled)
10787 + return count;
10788 +
10789 + /* Now, try to allocate the pins */
10790 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
10791 + if (ret)
10792 + goto err_alloc_pins;
10793 +
10794 + gpio->initialized = 1;
10795 +
10796 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
10797 + gpio->char_dev.owner = THIS_MODULE;
10798 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
10799 + if (ret < 0)
10800 + goto err_cdev_add;
10801 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
10802 + MKDEV(MAJOR(gpio_devt), gpio->id),
10803 + NULL,
10804 + "gpio%d", gpio->id);
10805 + if (IS_ERR(gpio->gpio_dev)) {
10806 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
10807 + ret = PTR_ERR(gpio->gpio_dev);
10808 + goto err_class_dev;
10809 + }
10810 +
10811 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
10812 + gpio->id, gpio->port, gpio->pin_mask,
10813 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
10814 +
10815 + return 0;
10816 +
10817 +err_class_dev:
10818 + cdev_del(&gpio->char_dev);
10819 +err_cdev_add:
10820 + at32_deselect_pins(gpio->port, gpio->pin_mask);
10821 + gpio->initialized = 0;
10822 +err_alloc_pins:
10823 + spin_lock(&gpio->lock);
10824 + gpio->enabled = 0;
10825 + spin_unlock(&gpio->lock);
10826 +
10827 + return ret;
10828 +}
10829 +
10830 +static struct gpio_attribute gpio_item_attr_gpio_id = {
10831 + .attr = {
10832 + .ca_owner = THIS_MODULE,
10833 + .ca_name = "gpio_id",
10834 + .ca_mode = S_IRUGO | S_IWUSR,
10835 + },
10836 + .show = gpio_show_gpio_id,
10837 + .store = gpio_store_gpio_id,
10838 +};
10839 +static struct gpio_attribute gpio_item_attr_pin_mask = {
10840 + .attr = {
10841 + .ca_owner = THIS_MODULE,
10842 + .ca_name = "pin_mask",
10843 + .ca_mode = S_IRUGO | S_IWUSR,
10844 + },
10845 + .show = gpio_show_pin_mask,
10846 + .store = gpio_store_pin_mask,
10847 +};
10848 +static struct gpio_attribute gpio_item_attr_oe_mask = {
10849 + .attr = {
10850 + .ca_owner = THIS_MODULE,
10851 + .ca_name = "oe_mask",
10852 + .ca_mode = S_IRUGO | S_IWUSR,
10853 + },
10854 + .show = gpio_show_oe_mask,
10855 + .store = gpio_store_oe_mask,
10856 +};
10857 +static struct gpio_attribute gpio_item_attr_enabled = {
10858 + .attr = {
10859 + .ca_owner = THIS_MODULE,
10860 + .ca_name = "enabled",
10861 + .ca_mode = S_IRUGO | S_IWUSR,
10862 + },
10863 + .show = gpio_show_enabled,
10864 + .store = gpio_store_enabled,
10865 +};
10866 +
10867 +static struct configfs_attribute *gpio_item_attrs[] = {
10868 + &gpio_item_attr_gpio_id.attr,
10869 + &gpio_item_attr_pin_mask.attr,
10870 + &gpio_item_attr_oe_mask.attr,
10871 + &gpio_item_attr_enabled.attr,
10872 + NULL,
10873 +};
10874 +
10875 +static ssize_t gpio_show_attr(struct config_item *item,
10876 + struct configfs_attribute *attr,
10877 + char *page)
10878 +{
10879 + struct gpio_item *gpio_item = to_gpio_item(item);
10880 + struct gpio_attribute *gpio_attr
10881 + = container_of(attr, struct gpio_attribute, attr);
10882 + ssize_t ret = 0;
10883 +
10884 + if (gpio_attr->show)
10885 + ret = gpio_attr->show(gpio_item, page);
10886 + return ret;
10887 +}
10888 +
10889 +static ssize_t gpio_store_attr(struct config_item *item,
10890 + struct configfs_attribute *attr,
10891 + const char *page, size_t count)
10892 +{
10893 + struct gpio_item *gpio_item = to_gpio_item(item);
10894 + struct gpio_attribute *gpio_attr
10895 + = container_of(attr, struct gpio_attribute, attr);
10896 + ssize_t ret = -EINVAL;
10897 +
10898 + if (gpio_attr->store)
10899 + ret = gpio_attr->store(gpio_item, page, count);
10900 + return ret;
10901 +}
10902 +
10903 +static void gpio_release(struct config_item *item)
10904 +{
10905 + kfree(to_gpio_item(item));
10906 +}
10907 +
10908 +static struct configfs_item_operations gpio_item_ops = {
10909 + .release = gpio_release,
10910 + .show_attribute = gpio_show_attr,
10911 + .store_attribute = gpio_store_attr,
10912 +};
10913 +
10914 +static struct config_item_type gpio_item_type = {
10915 + .ct_item_ops = &gpio_item_ops,
10916 + .ct_attrs = gpio_item_attrs,
10917 + .ct_owner = THIS_MODULE,
10918 +};
10919 +
10920 +static struct config_item *gpio_make_item(struct config_group *group,
10921 + const char *name)
10922 +{
10923 + static int next_id;
10924 + struct gpio_item *gpio;
10925 +
10926 + if (next_id >= GPIO_DEV_MAX)
10927 + return NULL;
10928 +
10929 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
10930 + if (!gpio)
10931 + return NULL;
10932 +
10933 + gpio->id = next_id++;
10934 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
10935 + spin_lock_init(&gpio->lock);
10936 + init_waitqueue_head(&gpio->change_wq);
10937 +
10938 + return &gpio->item;
10939 +}
10940 +
10941 +static void gpio_drop_item(struct config_group *group,
10942 + struct config_item *item)
10943 +{
10944 + struct gpio_item *gpio = to_gpio_item(item);
10945 +
10946 + spin_lock(&gpio->lock);
10947 + if (gpio->enabled) {
10948 + class_device_unregister(gpio->gpio_dev);
10949 + cdev_del(&gpio->char_dev);
10950 + }
10951 +
10952 + if (gpio->initialized) {
10953 + at32_deselect_pins(gpio->port, gpio->pin_mask);
10954 + gpio->initialized = 0;
10955 + gpio->enabled = 0;
10956 + }
10957 + spin_unlock(&gpio->lock);
10958 +}
10959 +
10960 +static struct configfs_group_operations gpio_group_ops = {
10961 + .make_item = gpio_make_item,
10962 + .drop_item = gpio_drop_item,
10963 +};
10964 +
10965 +static struct config_item_type gpio_group_type = {
10966 + .ct_group_ops = &gpio_group_ops,
10967 + .ct_owner = THIS_MODULE,
10968 +};
10969 +
10970 +static struct configfs_subsystem gpio_subsys = {
10971 + .su_group = {
10972 + .cg_item = {
10973 + .ci_namebuf = "gpio",
10974 + .ci_type = &gpio_group_type,
10975 + },
10976 + },
10977 +};
10978 +
10979 +static int __init gpio_dev_init(void)
10980 +{
10981 + int err;
10982 +
10983 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
10984 + if (IS_ERR(gpio_dev_class)) {
10985 + err = PTR_ERR(gpio_dev_class);
10986 + goto err_class_create;
10987 + }
10988 +
10989 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
10990 + if (err < 0)
10991 + goto err_alloc_chrdev;
10992 +
10993 + /* Configfs initialization */
10994 + config_group_init(&gpio_subsys.su_group);
10995 + mutex_init(&gpio_subsys.su_mutex);
10996 + err = configfs_register_subsystem(&gpio_subsys);
10997 + if (err)
10998 + goto err_register_subsys;
10999 +
11000 + return 0;
11001 +
11002 +err_register_subsys:
11003 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
11004 +err_alloc_chrdev:
11005 + class_destroy(gpio_dev_class);
11006 +err_class_create:
11007 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
11008 + return err;
11009 +}
11010 +late_initcall(gpio_dev_init);
11011 --- a/arch/avr32/mach-at32ap/intc.c
11012 +++ b/arch/avr32/mach-at32ap/intc.c
11013 @@ -13,7 +13,6 @@
11014 #include <linux/irq.h>
11015 #include <linux/platform_device.h>
11016
11017 -#include <asm/intc.h>
11018 #include <asm/io.h>
11019
11020 #include "intc.h"
11021 --- a/arch/avr32/mach-at32ap/Kconfig
11022 +++ b/arch/avr32/mach-at32ap/Kconfig
11023 @@ -3,9 +3,9 @@
11024 menu "Atmel AVR32 AP options"
11025
11026 choice
11027 - prompt "AT32AP7000 static memory bus width"
11028 - depends on CPU_AT32AP7000
11029 - default AP7000_16_BIT_SMC
11030 + prompt "AT32AP700x static memory bus width"
11031 + depends on CPU_AT32AP700X
11032 + default AP700X_16_BIT_SMC
11033 help
11034 Define the width of the AP7000 external static memory interface.
11035 This is used to determine how to mangle the address and/or data
11036 @@ -15,17 +15,24 @@
11037 width for all chip selects, excluding the flash (which is using
11038 raw access and is thus not affected by any of this.)
11039
11040 -config AP7000_32_BIT_SMC
11041 +config AP700X_32_BIT_SMC
11042 bool "32 bit"
11043
11044 -config AP7000_16_BIT_SMC
11045 +config AP700X_16_BIT_SMC
11046 bool "16 bit"
11047
11048 -config AP7000_8_BIT_SMC
11049 +config AP700X_8_BIT_SMC
11050 bool "8 bit"
11051
11052 endchoice
11053
11054 +config GPIO_DEV
11055 + bool "GPIO /dev interface"
11056 + select CONFIGFS_FS
11057 + default n
11058 + help
11059 + Say `Y' to enable a /dev interface to the GPIO pins.
11060 +
11061 endmenu
11062
11063 endif # PLATFORM_AT32AP
11064 --- a/arch/avr32/mach-at32ap/Makefile
11065 +++ b/arch/avr32/mach-at32ap/Makefile
11066 @@ -1,4 +1,4 @@
11067 obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
11068 -obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
11069 -obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
11070 +obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
11071 obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
11072 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
11073 --- a/arch/avr32/mach-at32ap/pio.c
11074 +++ b/arch/avr32/mach-at32ap/pio.c
11075 @@ -162,6 +162,82 @@
11076 dump_stack();
11077 }
11078
11079 +#ifdef CONFIG_GPIO_DEV
11080 +
11081 +/* Gang allocators and accessors; used by the GPIO /dev driver */
11082 +int at32_gpio_port_is_valid(unsigned int port)
11083 +{
11084 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
11085 +}
11086 +
11087 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
11088 +{
11089 + struct pio_device *pio;
11090 + u32 old, new;
11091 +
11092 + pio = &pio_dev[port];
11093 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
11094 +
11095 + /* Try to allocate the pins */
11096 + do {
11097 + old = pio->pinmux_mask;
11098 + if (old & pins)
11099 + return -EBUSY;
11100 +
11101 + new = old | pins;
11102 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
11103 +
11104 + /* That went well, now configure the port */
11105 + pio_writel(pio, OER, oe_mask);
11106 + pio_writel(pio, PER, pins);
11107 +
11108 + return 0;
11109 +}
11110 +
11111 +void at32_deselect_pins(unsigned int port, u32 pins)
11112 +{
11113 + struct pio_device *pio;
11114 + u32 old, new;
11115 +
11116 + pio = &pio_dev[port];
11117 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
11118 +
11119 + /* Return to a "safe" mux configuration */
11120 + pio_writel(pio, PUER, pins);
11121 + pio_writel(pio, ODR, pins);
11122 +
11123 + /* Deallocate the pins */
11124 + do {
11125 + old = pio->pinmux_mask;
11126 + new = old & ~pins;
11127 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
11128 +}
11129 +
11130 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
11131 +{
11132 + struct pio_device *pio;
11133 +
11134 + pio = &pio_dev[port];
11135 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
11136 +
11137 + return pio_readl(pio, PDSR) & pins;
11138 +}
11139 +
11140 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
11141 +{
11142 + struct pio_device *pio;
11143 +
11144 + pio = &pio_dev[port];
11145 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
11146 +
11147 + /* No atomic updates for now... */
11148 + pio_writel(pio, CODR, ~value & mask);
11149 + pio_writel(pio, SODR, value & mask);
11150 +}
11151 +
11152 +#endif /* CONFIG_GPIO_DEV */
11153 +
11154 +
11155 /*--------------------------------------------------------------------------*/
11156
11157 /* GPIO API */
11158 --- /dev/null
11159 +++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
11160 @@ -0,0 +1,66 @@
11161 +/*
11162 + * Low-level Power Management code.
11163 + *
11164 + * Copyright (C) 2008 Atmel Corporation
11165 + *
11166 + * This program is free software; you can redistribute it and/or modify
11167 + * it under the terms of the GNU General Public License version 2 as
11168 + * published by the Free Software Foundation.
11169 + */
11170 +#include <asm/asm.h>
11171 +#include <asm/asm-offsets.h>
11172 +#include <asm/thread_info.h>
11173 +#include <asm/arch/pm.h>
11174 +
11175 + .section .bss, "wa", @nobits
11176 + .global disable_idle_sleep
11177 + .type disable_idle_sleep, @object
11178 +disable_idle_sleep:
11179 + .int 4
11180 + .size disable_idle_sleep, . - disable_idle_sleep
11181 +
11182 + /* Keep this close to the irq handlers */
11183 + .section .irq.text, "ax", @progbits
11184 +
11185 + /*
11186 + * void cpu_enter_idle(void)
11187 + *
11188 + * Put the CPU into "idle" mode, in which it will consume
11189 + * significantly less power.
11190 + *
11191 + * If an interrupt comes along in the window between
11192 + * unmask_interrupts and the sleep instruction below, the
11193 + * interrupt code will adjust the return address so that we
11194 + * never execute the sleep instruction. This is required
11195 + * because the AP7000 doesn't unmask interrupts when entering
11196 + * sleep modes; later CPUs may not need this workaround.
11197 + */
11198 + .global cpu_enter_idle
11199 + .type cpu_enter_idle, @function
11200 +cpu_enter_idle:
11201 + mask_interrupts
11202 + get_thread_info r8
11203 + ld.w r9, r8[TI_flags]
11204 + bld r9, TIF_NEED_RESCHED
11205 + brcs .Lret_from_sleep
11206 + sbr r9, TIF_CPU_GOING_TO_SLEEP
11207 + st.w r8[TI_flags], r9
11208 + unmask_interrupts
11209 + sleep CPU_SLEEP_IDLE
11210 + .size cpu_idle_sleep, . - cpu_idle_sleep
11211 +
11212 + /*
11213 + * Common return path for PM functions that don't run from
11214 + * SRAM.
11215 + */
11216 + .global cpu_idle_skip_sleep
11217 + .type cpu_idle_skip_sleep, @function
11218 +cpu_idle_skip_sleep:
11219 + mask_interrupts
11220 + ld.w r9, r8[TI_flags]
11221 + cbr r9, TIF_CPU_GOING_TO_SLEEP
11222 + st.w r8[TI_flags], r9
11223 +.Lret_from_sleep:
11224 + unmask_interrupts
11225 + retal r12
11226 + .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
11227 --- a/arch/avr32/mach-at32ap/time-tc.c
11228 +++ /dev/null
11229 @@ -1,218 +0,0 @@
11230 -/*
11231 - * Copyright (C) 2004-2007 Atmel Corporation
11232 - *
11233 - * Based on MIPS implementation arch/mips/kernel/time.c
11234 - * Copyright 2001 MontaVista Software Inc.
11235 - *
11236 - * This program is free software; you can redistribute it and/or modify
11237 - * it under the terms of the GNU General Public License version 2 as
11238 - * published by the Free Software Foundation.
11239 - */
11240 -
11241 -#include <linux/clk.h>
11242 -#include <linux/clocksource.h>
11243 -#include <linux/time.h>
11244 -#include <linux/module.h>
11245 -#include <linux/interrupt.h>
11246 -#include <linux/irq.h>
11247 -#include <linux/kernel_stat.h>
11248 -#include <linux/errno.h>
11249 -#include <linux/init.h>
11250 -#include <linux/profile.h>
11251 -#include <linux/sysdev.h>
11252 -#include <linux/err.h>
11253 -
11254 -#include <asm/div64.h>
11255 -#include <asm/sysreg.h>
11256 -#include <asm/io.h>
11257 -#include <asm/sections.h>
11258 -
11259 -#include <asm/arch/time.h>
11260 -
11261 -/* how many counter cycles in a jiffy? */
11262 -static u32 cycles_per_jiffy;
11263 -
11264 -/* the count value for the next timer interrupt */
11265 -static u32 expirelo;
11266 -
11267 -/* the I/O registers of the TC module */
11268 -static void __iomem *ioregs;
11269 -
11270 -cycle_t read_cycle_count(void)
11271 -{
11272 - return (cycle_t)timer_read(ioregs, 0, CV);
11273 -}
11274 -
11275 -struct clocksource clocksource_avr32 = {
11276 - .name = "avr32",
11277 - .rating = 342,
11278 - .read = read_cycle_count,
11279 - .mask = CLOCKSOURCE_MASK(16),
11280 - .shift = 16,
11281 - .flags = CLOCK_SOURCE_IS_CONTINUOUS,
11282 -};
11283 -
11284 -static void avr32_timer_ack(void)
11285 -{
11286 - u16 count = expirelo;
11287 -
11288 - /* Ack this timer interrupt and set the next one, use a u16
11289 - * variable so it will wrap around correctly */
11290 - count += cycles_per_jiffy;
11291 - expirelo = count;
11292 - timer_write(ioregs, 0, RC, expirelo);
11293 -
11294 - /* Check to see if we have missed any timer interrupts */
11295 - count = timer_read(ioregs, 0, CV);
11296 - if ((count - expirelo) < 0x7fff) {
11297 - expirelo = count + cycles_per_jiffy;
11298 - timer_write(ioregs, 0, RC, expirelo);
11299 - }
11300 -}
11301 -
11302 -u32 avr32_hpt_read(void)
11303 -{
11304 - return timer_read(ioregs, 0, CV);
11305 -}
11306 -
11307 -static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
11308 -{
11309 - unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
11310 - unsigned int divs[] = { 4, 8, 16, 32 };
11311 - int divs_size = ARRAY_SIZE(divs);
11312 - int i = 0;
11313 - unsigned long count_hz;
11314 - unsigned long shift;
11315 - unsigned long mult;
11316 - int clock_div = -1;
11317 - u64 tmp;
11318 -
11319 - shift = clocksource_avr32.shift;
11320 -
11321 - do {
11322 - count_hz = clk_get_rate(pclk) / divs[i];
11323 - mult = clocksource_hz2mult(count_hz, shift);
11324 - clocksource_avr32.mult = mult;
11325 -
11326 - tmp = TICK_NSEC;
11327 - tmp <<= shift;
11328 - tmp += mult / 2;
11329 - do_div(tmp, mult);
11330 -
11331 - cycles_per_jiffy = tmp;
11332 - } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
11333 -
11334 - clock_div = i + 1;
11335 -
11336 - if (clock_div > divs_size) {
11337 - pr_debug("timer: could not calculate clock divider\n");
11338 - return -EFAULT;
11339 - }
11340 -
11341 - /* Set the clock divider */
11342 - timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
11343 -
11344 - return 0;
11345 -}
11346 -
11347 -int avr32_hpt_init(unsigned int count)
11348 -{
11349 - struct resource *regs;
11350 - struct clk *pclk;
11351 - int irq = -1;
11352 - int ret = 0;
11353 -
11354 - ret = -ENXIO;
11355 -
11356 - irq = platform_get_irq(&at32_systc0_device, 0);
11357 - if (irq < 0) {
11358 - pr_debug("timer: could not get irq\n");
11359 - goto out_error;
11360 - }
11361 -
11362 - pclk = clk_get(&at32_systc0_device.dev, "pclk");
11363 - if (IS_ERR(pclk)) {
11364 - pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
11365 - goto out_error;
11366 - }
11367 - clk_enable(pclk);
11368 -
11369 - regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
11370 - if (!regs) {
11371 - pr_debug("timer: could not get resource\n");
11372 - goto out_error_clk;
11373 - }
11374 -
11375 - ioregs = ioremap(regs->start, regs->end - regs->start + 1);
11376 - if (!ioregs) {
11377 - pr_debug("timer: could not get ioregs\n");
11378 - goto out_error_clk;
11379 - }
11380 -
11381 - ret = avr32_timer_calc_div_and_set_jiffies(pclk);
11382 - if (ret)
11383 - goto out_error_io;
11384 -
11385 - ret = setup_irq(irq, &timer_irqaction);
11386 - if (ret) {
11387 - pr_debug("timer: could not request irq %d: %d\n",
11388 - irq, ret);
11389 - goto out_error_io;
11390 - }
11391 -
11392 - expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
11393 - * cycles_per_jiffy;
11394 -
11395 - /* Enable clock and interrupts on RC compare */
11396 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
11397 - timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
11398 - /* Set cycles to first interrupt */
11399 - timer_write(ioregs, 0, RC, expirelo);
11400 -
11401 - printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
11402 - ioregs, irq);
11403 -
11404 - return 0;
11405 -
11406 -out_error_io:
11407 - iounmap(ioregs);
11408 -out_error_clk:
11409 - clk_put(pclk);
11410 -out_error:
11411 - return ret;
11412 -}
11413 -
11414 -int avr32_hpt_start(void)
11415 -{
11416 - timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
11417 - return 0;
11418 -}
11419 -
11420 -irqreturn_t timer_interrupt(int irq, void *dev_id)
11421 -{
11422 - unsigned int sr = timer_read(ioregs, 0, SR);
11423 -
11424 - if (sr & TIMER_BIT(SR_CPCS)) {
11425 - /* ack timer interrupt and try to set next interrupt */
11426 - avr32_timer_ack();
11427 -
11428 - /*
11429 - * Call the generic timer interrupt handler
11430 - */
11431 - write_seqlock(&xtime_lock);
11432 - do_timer(1);
11433 - write_sequnlock(&xtime_lock);
11434 -
11435 - /*
11436 - * In UP mode, we call local_timer_interrupt() to do profiling
11437 - * and process accounting.
11438 - *
11439 - * SMP is not supported yet.
11440 - */
11441 - local_timer_interrupt(irq, dev_id);
11442 -
11443 - return IRQ_HANDLED;
11444 - }
11445 -
11446 - return IRQ_NONE;
11447 -}
11448 --- a/arch/avr32/Makefile
11449 +++ b/arch/avr32/Makefile
11450 @@ -16,7 +16,7 @@
11451 CFLAGS_MODULE += -mno-relax
11452 LDFLAGS_vmlinux += --relax
11453
11454 -cpuflags-$(CONFIG_CPU_AT32AP7000) += -mcpu=ap7000
11455 +cpuflags-$(CONFIG_PLATFORM_AT32AP) += -march=ap
11456
11457 KBUILD_CFLAGS += $(cpuflags-y)
11458 KBUILD_AFLAGS += $(cpuflags-y)
11459 @@ -31,6 +31,8 @@
11460 core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
11461 core-y += arch/avr32/kernel/
11462 core-y += arch/avr32/mm/
11463 +drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
11464 +drivers-y += arch/avr32/drivers/
11465 libs-y += arch/avr32/lib/
11466
11467 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
11468 --- a/arch/avr32/mm/dma-coherent.c
11469 +++ b/arch/avr32/mm/dma-coherent.c
11470 @@ -41,6 +41,13 @@
11471 struct page *page, *free, *end;
11472 int order;
11473
11474 + /* Following is a work-around (a.k.a. hack) to prevent pages
11475 + * with __GFP_COMP being passed to split_page() which cannot
11476 + * handle them. The real problem is that this flag probably
11477 + * should be 0 on AVR32 as it is not supported on this
11478 + * platform--see CONFIG_HUGETLB_PAGE. */
11479 + gfp &= ~(__GFP_COMP);
11480 +
11481 size = PAGE_ALIGN(size);
11482 order = get_order(size);
11483
11484 --- a/arch/avr32/mm/fault.c
11485 +++ b/arch/avr32/mm/fault.c
11486 @@ -189,6 +189,8 @@
11487
11488 page = sysreg_read(PTBR);
11489 printk(KERN_ALERT "ptbr = %08lx", page);
11490 + if (address >= TASK_SIZE)
11491 + page = (unsigned long)swapper_pg_dir;
11492 if (page) {
11493 page = ((unsigned long *)page)[address >> 22];
11494 printk(" pgd = %08lx", page);
11495 --- a/arch/avr32/mm/tlb.c
11496 +++ b/arch/avr32/mm/tlb.c
11497 @@ -348,7 +348,7 @@
11498 return 0;
11499 }
11500
11501 -static struct seq_operations tlb_ops = {
11502 +static const struct seq_operations tlb_ops = {
11503 .start = tlb_start,
11504 .next = tlb_next,
11505 .stop = tlb_stop,
11506 --- /dev/null
11507 +++ b/arch/avr32/oprofile/Makefile
11508 @@ -0,0 +1,8 @@
11509 +obj-$(CONFIG_OPROFILE) += oprofile.o
11510 +
11511 +oprofile-y := $(addprefix ../../../drivers/oprofile/, \
11512 + oprof.o cpu_buffer.o buffer_sync.o \
11513 + event_buffer.o oprofile_files.o \
11514 + oprofilefs.o oprofile_stats.o \
11515 + timer_int.o)
11516 +oprofile-y += op_model_avr32.o
11517 --- /dev/null
11518 +++ b/arch/avr32/oprofile/op_model_avr32.c
11519 @@ -0,0 +1,234 @@
11520 +/*
11521 + * AVR32 Performance Counter Driver
11522 + *
11523 + * Copyright (C) 2005-2007 Atmel Corporation
11524 + *
11525 + * This program is free software; you can redistribute it and/or modify
11526 + * it under the terms of the GNU General Public License version 2 as
11527 + * published by the Free Software Foundation.
11528 + *
11529 + * Author: Ronny Pedersen
11530 + */
11531 +#include <linux/errno.h>
11532 +#include <linux/interrupt.h>
11533 +#include <linux/irq.h>
11534 +#include <linux/oprofile.h>
11535 +#include <linux/sched.h>
11536 +#include <linux/types.h>
11537 +
11538 +#include <asm/sysreg.h>
11539 +#include <asm/system.h>
11540 +
11541 +#define AVR32_PERFCTR_IRQ_GROUP 0
11542 +#define AVR32_PERFCTR_IRQ_LINE 1
11543 +
11544 +enum { PCCNT, PCNT0, PCNT1, NR_counter };
11545 +
11546 +struct avr32_perf_counter {
11547 + unsigned long enabled;
11548 + unsigned long event;
11549 + unsigned long count;
11550 + unsigned long unit_mask;
11551 + unsigned long kernel;
11552 + unsigned long user;
11553 +
11554 + u32 ie_mask;
11555 + u32 flag_mask;
11556 +};
11557 +
11558 +static struct avr32_perf_counter counter[NR_counter] = {
11559 + {
11560 + .ie_mask = SYSREG_BIT(IEC),
11561 + .flag_mask = SYSREG_BIT(FC),
11562 + }, {
11563 + .ie_mask = SYSREG_BIT(IE0),
11564 + .flag_mask = SYSREG_BIT(F0),
11565 + }, {
11566 + .ie_mask = SYSREG_BIT(IE1),
11567 + .flag_mask = SYSREG_BIT(F1),
11568 + },
11569 +};
11570 +
11571 +static void avr32_perf_counter_reset(void)
11572 +{
11573 + /* Reset all counter and disable/clear all interrupts */
11574 + sysreg_write(PCCR, (SYSREG_BIT(PCCR_R)
11575 + | SYSREG_BIT(PCCR_C)
11576 + | SYSREG_BIT(FC)
11577 + | SYSREG_BIT(F0)
11578 + | SYSREG_BIT(F1)));
11579 +}
11580 +
11581 +static irqreturn_t avr32_perf_counter_interrupt(int irq, void *dev_id)
11582 +{
11583 + struct avr32_perf_counter *ctr = dev_id;
11584 + struct pt_regs *regs;
11585 + u32 pccr;
11586 +
11587 + if (likely(!(intc_get_pending(AVR32_PERFCTR_IRQ_GROUP)
11588 + & (1 << AVR32_PERFCTR_IRQ_LINE))))
11589 + return IRQ_NONE;
11590 +
11591 + regs = get_irq_regs();
11592 + pccr = sysreg_read(PCCR);
11593 +
11594 + /* Clear the interrupt flags we're about to handle */
11595 + sysreg_write(PCCR, pccr);
11596 +
11597 + /* PCCNT */
11598 + if (ctr->enabled && (pccr & ctr->flag_mask)) {
11599 + sysreg_write(PCCNT, -ctr->count);
11600 + oprofile_add_sample(regs, PCCNT);
11601 + }
11602 + ctr++;
11603 + /* PCNT0 */
11604 + if (ctr->enabled && (pccr & ctr->flag_mask)) {
11605 + sysreg_write(PCNT0, -ctr->count);
11606 + oprofile_add_sample(regs, PCNT0);
11607 + }
11608 + ctr++;
11609 + /* PCNT1 */
11610 + if (ctr->enabled && (pccr & ctr->flag_mask)) {
11611 + sysreg_write(PCNT1, -ctr->count);
11612 + oprofile_add_sample(regs, PCNT1);
11613 + }
11614 +
11615 + return IRQ_HANDLED;
11616 +}
11617 +
11618 +static int avr32_perf_counter_create_files(struct super_block *sb,
11619 + struct dentry *root)
11620 +{
11621 + struct dentry *dir;
11622 + unsigned int i;
11623 + char filename[4];
11624 +
11625 + for (i = 0; i < NR_counter; i++) {
11626 + snprintf(filename, sizeof(filename), "%u", i);
11627 + dir = oprofilefs_mkdir(sb, root, filename);
11628 +
11629 + oprofilefs_create_ulong(sb, dir, "enabled",
11630 + &counter[i].enabled);
11631 + oprofilefs_create_ulong(sb, dir, "event",
11632 + &counter[i].event);
11633 + oprofilefs_create_ulong(sb, dir, "count",
11634 + &counter[i].count);
11635 +
11636 + /* Dummy entries */
11637 + oprofilefs_create_ulong(sb, dir, "kernel",
11638 + &counter[i].kernel);
11639 + oprofilefs_create_ulong(sb, dir, "user",
11640 + &counter[i].user);
11641 + oprofilefs_create_ulong(sb, dir, "unit_mask",
11642 + &counter[i].unit_mask);
11643 + }
11644 +
11645 + return 0;
11646 +}
11647 +
11648 +static int avr32_perf_counter_setup(void)
11649 +{
11650 + struct avr32_perf_counter *ctr;
11651 + u32 pccr;
11652 + int ret;
11653 + int i;
11654 +
11655 + pr_debug("avr32_perf_counter_setup\n");
11656 +
11657 + if (sysreg_read(PCCR) & SYSREG_BIT(PCCR_E)) {
11658 + printk(KERN_ERR
11659 + "oprofile: setup: perf counter already enabled\n");
11660 + return -EBUSY;
11661 + }
11662 +
11663 + ret = request_irq(AVR32_PERFCTR_IRQ_GROUP,
11664 + avr32_perf_counter_interrupt, IRQF_SHARED,
11665 + "oprofile", counter);
11666 + if (ret)
11667 + return ret;
11668 +
11669 + avr32_perf_counter_reset();
11670 +
11671 + pccr = 0;
11672 + for (i = PCCNT; i < NR_counter; i++) {
11673 + ctr = &counter[i];
11674 + if (!ctr->enabled)
11675 + continue;
11676 +
11677 + pr_debug("enabling counter %d...\n", i);
11678 +
11679 + pccr |= ctr->ie_mask;
11680 +
11681 + switch (i) {
11682 + case PCCNT:
11683 + /* PCCNT always counts cycles, so no events */
11684 + sysreg_write(PCCNT, -ctr->count);
11685 + break;
11686 + case PCNT0:
11687 + pccr |= SYSREG_BF(CONF0, ctr->event);
11688 + sysreg_write(PCNT0, -ctr->count);
11689 + break;
11690 + case PCNT1:
11691 + pccr |= SYSREG_BF(CONF1, ctr->event);
11692 + sysreg_write(PCNT1, -ctr->count);
11693 + break;
11694 + }
11695 + }
11696 +
11697 + pr_debug("oprofile: writing 0x%x to PCCR...\n", pccr);
11698 +
11699 + sysreg_write(PCCR, pccr);
11700 +
11701 + return 0;
11702 +}
11703 +
11704 +static void avr32_perf_counter_shutdown(void)
11705 +{
11706 + pr_debug("avr32_perf_counter_shutdown\n");
11707 +
11708 + avr32_perf_counter_reset();
11709 + free_irq(AVR32_PERFCTR_IRQ_GROUP, counter);
11710 +}
11711 +
11712 +static int avr32_perf_counter_start(void)
11713 +{
11714 + pr_debug("avr32_perf_counter_start\n");
11715 +
11716 + sysreg_write(PCCR, sysreg_read(PCCR) | SYSREG_BIT(PCCR_E));
11717 +
11718 + return 0;
11719 +}
11720 +
11721 +static void avr32_perf_counter_stop(void)
11722 +{
11723 + pr_debug("avr32_perf_counter_stop\n");
11724 +
11725 + sysreg_write(PCCR, sysreg_read(PCCR) & ~SYSREG_BIT(PCCR_E));
11726 +}
11727 +
11728 +static struct oprofile_operations avr32_perf_counter_ops __initdata = {
11729 + .create_files = avr32_perf_counter_create_files,
11730 + .setup = avr32_perf_counter_setup,
11731 + .shutdown = avr32_perf_counter_shutdown,
11732 + .start = avr32_perf_counter_start,
11733 + .stop = avr32_perf_counter_stop,
11734 + .cpu_type = "avr32",
11735 +};
11736 +
11737 +int __init oprofile_arch_init(struct oprofile_operations *ops)
11738 +{
11739 + if (!(current_cpu_data.features & AVR32_FEATURE_PCTR))
11740 + return -ENODEV;
11741 +
11742 + memcpy(ops, &avr32_perf_counter_ops,
11743 + sizeof(struct oprofile_operations));
11744 +
11745 + printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n");
11746 +
11747 + return 0;
11748 +}
11749 +
11750 +void oprofile_arch_exit(void)
11751 +{
11752 +
11753 +}
11754 --- a/Documentation/kernel-parameters.txt
11755 +++ b/Documentation/kernel-parameters.txt
11756 @@ -34,6 +34,7 @@
11757 ALSA ALSA sound support is enabled.
11758 APIC APIC support is enabled.
11759 APM Advanced Power Management support is enabled.
11760 + AVR32 AVR32 architecture is enabled.
11761 AX25 Appropriate AX.25 support is enabled.
11762 BLACKFIN Blackfin architecture is enabled.
11763 DRM Direct Rendering Management support is enabled.
11764 @@ -1124,6 +1125,10 @@
11765 of returning the full 64-bit number.
11766 The default is to return 64-bit inode numbers.
11767
11768 + nmi_debug= [KNL,AVR32] Specify one or more actions to take
11769 + when a NMI is triggered.
11770 + Format: [state][,regs][,debounce][,die]
11771 +
11772 nmi_watchdog= [KNL,BUGS=X86-32] Debugging features for SMP kernels
11773
11774 no387 [BUGS=X86-32] Tells the kernel to use the 387 maths
11775 --- a/drivers/clocksource/Makefile
11776 +++ b/drivers/clocksource/Makefile
11777 @@ -1,3 +1,4 @@
11778 +obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
11779 obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
11780 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
11781 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
11782 --- /dev/null
11783 +++ b/drivers/clocksource/tcb_clksrc.c
11784 @@ -0,0 +1,305 @@
11785 +#include <linux/init.h>
11786 +#include <linux/clocksource.h>
11787 +#include <linux/clockchips.h>
11788 +#include <linux/interrupt.h>
11789 +#include <linux/irq.h>
11790 +
11791 +#include <linux/clk.h>
11792 +#include <linux/err.h>
11793 +#include <linux/ioport.h>
11794 +#include <linux/io.h>
11795 +#include <linux/platform_device.h>
11796 +#include <linux/atmel_tc.h>
11797 +
11798 +
11799 +/*
11800 + * We're configured to use a specific TC block, one that's not hooked
11801 + * up to external hardware, to provide a time solution:
11802 + *
11803 + * - Two channels combine to create a free-running 32 bit counter
11804 + * with a base rate of 5+ MHz, packaged as a clocksource (with
11805 + * resolution better than 200 nsec).
11806 + *
11807 + * - The third channel may be used to provide a 16-bit clockevent
11808 + * source, used in either periodic or oneshot mode. This runs
11809 + * at 32 KiHZ, and can handle delays of up to two seconds.
11810 + *
11811 + * A boot clocksource and clockevent source are also currently needed,
11812 + * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
11813 + * this code can be used when init_timers() is called, well before most
11814 + * devices are set up. (Some low end AT91 parts, which can run uClinux,
11815 + * have only the timers in one TC block... they currently don't support
11816 + * the tclib code, because of that initialization issue.)
11817 + *
11818 + * REVISIT behavior during system suspend states... we should disable
11819 + * all clocks and save the power. Easily done for clockevent devices,
11820 + * but clocksources won't necessarily get the needed notifications.
11821 + * For deeper system sleep states, this will be mandatory...
11822 + */
11823 +
11824 +static void __iomem *tcaddr;
11825 +
11826 +static cycle_t tc_get_cycles(void)
11827 +{
11828 + unsigned long flags;
11829 + u32 lower, upper;
11830 +
11831 + raw_local_irq_save(flags);
11832 + do {
11833 + upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
11834 + lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
11835 + } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
11836 +
11837 + raw_local_irq_restore(flags);
11838 + return (upper << 16) | lower;
11839 +}
11840 +
11841 +static struct clocksource clksrc = {
11842 + .name = "tcb_clksrc",
11843 + .rating = 200,
11844 + .read = tc_get_cycles,
11845 + .mask = CLOCKSOURCE_MASK(32),
11846 + .shift = 18,
11847 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
11848 +};
11849 +
11850 +#ifdef CONFIG_GENERIC_CLOCKEVENTS
11851 +
11852 +struct tc_clkevt_device {
11853 + struct clock_event_device clkevt;
11854 + struct clk *clk;
11855 + void __iomem *regs;
11856 +};
11857 +
11858 +static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
11859 +{
11860 + return container_of(clkevt, struct tc_clkevt_device, clkevt);
11861 +}
11862 +
11863 +/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
11864 + * because using one of the divided clocks would usually mean the
11865 + * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
11866 + *
11867 + * A divided clock could be good for high resolution timers, since
11868 + * 30.5 usec resolution can seem "low".
11869 + */
11870 +static u32 timer_clock;
11871 +
11872 +static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
11873 +{
11874 + struct tc_clkevt_device *tcd = to_tc_clkevt(d);
11875 + void __iomem *regs = tcd->regs;
11876 +
11877 + if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
11878 + || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
11879 + __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
11880 + __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
11881 + clk_disable(tcd->clk);
11882 + }
11883 +
11884 + switch (m) {
11885 +
11886 + /* By not making the gentime core emulate periodic mode on top
11887 + * of oneshot, we get lower overhead and improved accuracy.
11888 + */
11889 + case CLOCK_EVT_MODE_PERIODIC:
11890 + clk_enable(tcd->clk);
11891 +
11892 + /* slow clock, count up to RC, then irq and restart */
11893 + __raw_writel(timer_clock
11894 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
11895 + regs + ATMEL_TC_REG(2, CMR));
11896 + __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
11897 +
11898 + /* Enable clock and interrupts on RC compare */
11899 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
11900 +
11901 + /* go go gadget! */
11902 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
11903 + regs + ATMEL_TC_REG(2, CCR));
11904 + break;
11905 +
11906 + case CLOCK_EVT_MODE_ONESHOT:
11907 + clk_enable(tcd->clk);
11908 +
11909 + /* slow clock, count up to RC, then irq and stop */
11910 + __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
11911 + | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
11912 + regs + ATMEL_TC_REG(2, CMR));
11913 + __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
11914 +
11915 + /* set_next_event() configures and starts the timer */
11916 + break;
11917 +
11918 + default:
11919 + break;
11920 + }
11921 +}
11922 +
11923 +static int tc_next_event(unsigned long delta, struct clock_event_device *d)
11924 +{
11925 + __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
11926 +
11927 + /* go go gadget! */
11928 + __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
11929 + tcaddr + ATMEL_TC_REG(2, CCR));
11930 + return 0;
11931 +}
11932 +
11933 +static struct tc_clkevt_device clkevt = {
11934 + .clkevt = {
11935 + .name = "tc_clkevt",
11936 + .features = CLOCK_EVT_FEAT_PERIODIC
11937 + | CLOCK_EVT_FEAT_ONESHOT,
11938 + .shift = 32,
11939 + /* Should be lower than at91rm9200's system timer */
11940 + .rating = 125,
11941 + .cpumask = CPU_MASK_CPU0,
11942 + .set_next_event = tc_next_event,
11943 + .set_mode = tc_mode,
11944 + },
11945 +};
11946 +
11947 +static irqreturn_t ch2_irq(int irq, void *handle)
11948 +{
11949 + struct tc_clkevt_device *dev = handle;
11950 + unsigned int sr;
11951 +
11952 + sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
11953 + if (sr & ATMEL_TC_CPCS) {
11954 + dev->clkevt.event_handler(&dev->clkevt);
11955 + return IRQ_HANDLED;
11956 + }
11957 +
11958 + return IRQ_NONE;
11959 +}
11960 +
11961 +static struct irqaction tc_irqaction = {
11962 + .name = "tc_clkevt",
11963 + .flags = IRQF_TIMER | IRQF_DISABLED,
11964 + .handler = ch2_irq,
11965 +};
11966 +
11967 +static void __init setup_clkevents(struct atmel_tc *tc,
11968 + struct clk *t0_clk, int clk32k_divisor_idx)
11969 +{
11970 + struct platform_device *pdev = tc->pdev;
11971 + struct clk *t2_clk = tc->clk[2];
11972 + int irq = tc->irq[2];
11973 +
11974 + clkevt.regs = tc->regs;
11975 + clkevt.clk = t2_clk;
11976 + tc_irqaction.dev_id = &clkevt;
11977 +
11978 + timer_clock = clk32k_divisor_idx;
11979 +
11980 + clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
11981 + clkevt.clkevt.max_delta_ns
11982 + = clockevent_delta2ns(0xffff, &clkevt.clkevt);
11983 + clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
11984 +
11985 + setup_irq(irq, &tc_irqaction);
11986 +
11987 + clockevents_register_device(&clkevt.clkevt);
11988 +}
11989 +
11990 +#else /* !CONFIG_GENERIC_CLOCKEVENTS */
11991 +
11992 +static void __init setup_clkevents(struct atmel_tc *tc,
11993 + struct clk *t0_clk, int clk32k_divisor_idx)
11994 +{
11995 + /* NOTHING */
11996 +}
11997 +
11998 +#endif
11999 +
12000 +static int __init tcb_clksrc_init(void)
12001 +{
12002 + static char bootinfo[] __initdata
12003 + = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
12004 +
12005 + struct platform_device *pdev;
12006 + struct atmel_tc *tc;
12007 + struct clk *t0_clk, *t1_clk;
12008 + u32 rate, divided_rate = 0;
12009 + int best_divisor_idx = -1;
12010 + int clk32k_divisor_idx = -1;
12011 + int i;
12012 +
12013 + tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
12014 + if (!tc) {
12015 + pr_debug("can't alloc TC for clocksource\n");
12016 + return -ENODEV;
12017 + }
12018 + tcaddr = tc->regs;
12019 + pdev = tc->pdev;
12020 +
12021 + t0_clk = tc->clk[0];
12022 + clk_enable(t0_clk);
12023 +
12024 + /* How fast will we be counting? Pick something over 5 MHz. */
12025 + rate = (u32) clk_get_rate(t0_clk);
12026 + for (i = 0; i < 5; i++) {
12027 + unsigned divisor = atmel_tc_divisors[i];
12028 + unsigned tmp;
12029 +
12030 + /* remember 32 KiHz clock for later */
12031 + if (!divisor) {
12032 + clk32k_divisor_idx = i;
12033 + continue;
12034 + }
12035 +
12036 + tmp = rate / divisor;
12037 + pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
12038 + if (best_divisor_idx > 0) {
12039 + if (tmp < 5 * 1000 * 1000)
12040 + continue;
12041 + }
12042 + divided_rate = tmp;
12043 + best_divisor_idx = i;
12044 + }
12045 +
12046 + clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
12047 +
12048 + printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
12049 + divided_rate / 1000000,
12050 + ((divided_rate + 500000) % 1000000) / 1000);
12051 +
12052 + /* tclib will give us three clocks no matter what the
12053 + * underlying platform supports.
12054 + */
12055 + clk_enable(tc->clk[1]);
12056 +
12057 + /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
12058 + __raw_writel(best_divisor_idx /* likely divide-by-8 */
12059 + | ATMEL_TC_WAVE
12060 + | ATMEL_TC_WAVESEL_UP /* free-run */
12061 + | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
12062 + | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
12063 + tcaddr + ATMEL_TC_REG(0, CMR));
12064 + __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
12065 + __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
12066 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
12067 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
12068 +
12069 + /* channel 1: waveform mode, input TIOA0 */
12070 + __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
12071 + | ATMEL_TC_WAVE
12072 + | ATMEL_TC_WAVESEL_UP, /* free-run */
12073 + tcaddr + ATMEL_TC_REG(1, CMR));
12074 + __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
12075 + __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
12076 +
12077 + /* chain channel 0 to channel 1, then reset all the timers */
12078 + __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
12079 + __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
12080 +
12081 + /* and away we go! */
12082 + clocksource_register(&clksrc);
12083 +
12084 + /* channel 2: periodic and oneshot timer support */
12085 + setup_clkevents(tc, t0_clk, clk32k_divisor_idx);
12086 +
12087 + return 0;
12088 +}
12089 +arch_initcall(tcb_clksrc_init);
12090 --- /dev/null
12091 +++ b/drivers/i2c/busses/i2c-atmeltwi.c
12092 @@ -0,0 +1,436 @@
12093 +/*
12094 + * i2c Support for Atmel's Two-Wire Interface (TWI)
12095 + *
12096 + * Based on the work of Copyright (C) 2004 Rick Bronson
12097 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
12098 + * Ported to AVR32 and heavily modified by Espen Krangnes
12099 + * <ekrangnes at atmel.com>
12100 + *
12101 + * Copyright (C) 2006 Atmel Corporation
12102 + *
12103 + * Borrowed heavily from the original work by:
12104 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
12105 + *
12106 + * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
12107 + * bugs removed, interrupt routine markedly rewritten
12108 + *
12109 + * This program is free software; you can redistribute it and/or modify
12110 + * it under the terms of the GNU General Public License as published by
12111 + * the Free Software Foundation; either version 2 of the License, or
12112 + * (at your option) any later version.
12113 + */
12114 +#undef VERBOSE_DEBUG
12115 +
12116 +#include <linux/module.h>
12117 +#include <linux/slab.h>
12118 +#include <linux/i2c.h>
12119 +#include <linux/init.h>
12120 +#include <linux/clk.h>
12121 +#include <linux/err.h>
12122 +#include <linux/interrupt.h>
12123 +#include <linux/platform_device.h>
12124 +#include <linux/completion.h>
12125 +#include <linux/io.h>
12126 +
12127 +#include "i2c-atmeltwi.h"
12128 +
12129 +static unsigned int baudrate = 100 * 1000;
12130 +module_param(baudrate, uint, S_IRUGO);
12131 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
12132 +
12133 +
12134 +struct atmel_twi {
12135 + void __iomem *regs;
12136 + struct i2c_adapter adapter;
12137 + struct clk *pclk;
12138 + struct completion comp;
12139 + u32 mask;
12140 + u8 *buf;
12141 + u16 len;
12142 + u16 acks_left;
12143 + int status;
12144 + unsigned int irq;
12145 +
12146 +};
12147 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
12148 +
12149 +/*
12150 + * (Re)Initialize the TWI hardware registers.
12151 + */
12152 +static int twi_hwinit(struct atmel_twi *twi)
12153 +{
12154 + unsigned long cdiv, ckdiv = 0;
12155 +
12156 + /* REVISIT: wait till SCL is high before resetting; otherwise,
12157 + * some versions will wedge forever.
12158 + */
12159 +
12160 + twi_writel(twi, IDR, ~0UL);
12161 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
12162 + twi_readl(twi, SR);
12163 +
12164 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
12165 +
12166 + while (cdiv > 255) {
12167 + ckdiv++;
12168 + cdiv = cdiv >> 1;
12169 + }
12170 +
12171 + /* REVISIT: there are various errata to consider re CDIV and CHDIV
12172 + * here, at least on at91 parts.
12173 + */
12174 +
12175 + if (ckdiv > 7)
12176 + return -EINVAL;
12177 + else
12178 + twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
12179 + | TWI_BF(CHDIV, cdiv)
12180 + | TWI_BF(CLDIV, cdiv));
12181 + return 0;
12182 +}
12183 +
12184 +/*
12185 + * Waits for the i2c status register to set the specified bitmask
12186 + * Returns 0 if timed out ... ~100ms is much longer than the SMBus
12187 + * limit, but I2C has no limit at all.
12188 + */
12189 +static int twi_complete(struct atmel_twi *twi, u32 mask)
12190 +{
12191 + int timeout = msecs_to_jiffies(100);
12192 +
12193 + mask |= TWI_BIT(TXCOMP);
12194 + twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
12195 + init_completion(&twi->comp);
12196 +
12197 + twi_writel(twi, IER, mask);
12198 +
12199 + if (!wait_for_completion_timeout(&twi->comp, timeout)) {
12200 + /* RESET TWI interface */
12201 + twi_writel(twi, CR, TWI_BIT(SWRST));
12202 +
12203 + /* Reinitialize TWI */
12204 + twi_hwinit(twi);
12205 +
12206 + return -ETIMEDOUT;
12207 + }
12208 + return 0;
12209 +}
12210 +
12211 +/*
12212 + * Generic i2c master transfer entrypoint.
12213 + */
12214 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
12215 +{
12216 + struct atmel_twi *twi = to_atmel_twi(adap);
12217 + int i;
12218 +
12219 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
12220 +
12221 + twi->status = 0;
12222 + for (i = 0; i < num; i++, pmsg++) {
12223 + twi->len = pmsg->len;
12224 + twi->buf = pmsg->buf;
12225 + twi->acks_left = pmsg->len;
12226 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
12227 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
12228 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
12229 +
12230 + dev_dbg(&adap->dev,
12231 + "#%d: %s %d byte%s %s dev 0x%02x\n",
12232 + i,
12233 + pmsg->flags & I2C_M_RD ? "reading" : "writing",
12234 + pmsg->len,
12235 + pmsg->len > 1 ? "s" : "",
12236 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
12237 +
12238 + /* enable */
12239 + twi_writel(twi, CR, TWI_BIT(MSEN));
12240 +
12241 + if (pmsg->flags & I2C_M_RD) {
12242 + /* cleanup after previous RX overruns */
12243 + while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
12244 + twi_readl(twi, RHR);
12245 +
12246 + if (twi->len == 1)
12247 + twi_writel(twi, CR,
12248 + TWI_BIT(START) | TWI_BIT(STOP));
12249 + else
12250 + twi_writel(twi, CR, TWI_BIT(START));
12251 +
12252 + if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
12253 + dev_dbg(&adap->dev, "RX[%d] timeout. "
12254 + "Stopped with %d bytes left\n",
12255 + i, twi->acks_left);
12256 + return -ETIMEDOUT;
12257 + }
12258 + } else {
12259 + twi_writel(twi, THR, twi->buf[0]);
12260 + twi->acks_left--;
12261 + /* REVISIT: some chips don't start automagically:
12262 + * twi_writel(twi, CR, TWI_BIT(START));
12263 + */
12264 + if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
12265 + dev_dbg(&adap->dev, "TX[%d] timeout. "
12266 + "Stopped with %d bytes left\n",
12267 + i, twi->acks_left);
12268 + return -ETIMEDOUT;
12269 + }
12270 + /* REVISIT: an erratum workaround may be needed here;
12271 + * see sam9261 "STOP not generated" (START either).
12272 + */
12273 + }
12274 +
12275 + /* Disable TWI interface */
12276 + twi_writel(twi, CR, TWI_BIT(MSDIS));
12277 +
12278 + if (twi->status)
12279 + return twi->status;
12280 +
12281 + /* WARNING: This driver lies about properly supporting
12282 + * repeated start, or it would *ALWAYS* return here. It
12283 + * has issued a STOP. Continuing is a false claim -- that
12284 + * a second (or third, etc.) message is part of the same
12285 + * "combined" (no STOPs between parts) message.
12286 + */
12287 +
12288 + } /* end cur msg */
12289 +
12290 + return i;
12291 +}
12292 +
12293 +
12294 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
12295 +{
12296 + struct atmel_twi *twi = dev_id;
12297 + int status = twi_readl(twi, SR);
12298 +
12299 + /* Save state for later debug prints */
12300 + int old_status = status;
12301 +
12302 + if (twi->mask & status) {
12303 +
12304 + status &= twi->mask;
12305 +
12306 + if (status & TWI_BIT(RXRDY)) {
12307 + if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
12308 + /* Note weakness in fault reporting model:
12309 + * we can't say "the first N of these data
12310 + * bytes are valid".
12311 + */
12312 + dev_err(&twi->adapter.dev,
12313 + "OVERRUN RX! %04x, lost %d\n",
12314 + old_status, twi->acks_left);
12315 + twi->acks_left = 0;
12316 + twi_writel(twi, CR, TWI_BIT(STOP));
12317 + twi->status = -EOVERFLOW;
12318 + } else if (twi->acks_left > 0) {
12319 + twi->buf[twi->len - twi->acks_left] =
12320 + twi_readl(twi, RHR);
12321 + twi->acks_left--;
12322 + }
12323 + if (status & TWI_BIT(TXCOMP))
12324 + goto done;
12325 + if (twi->acks_left == 1)
12326 + twi_writel(twi, CR, TWI_BIT(STOP));
12327 +
12328 + } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
12329 + goto done;
12330 +
12331 + } else if (status & TWI_BIT(TXRDY)) {
12332 + if (twi->acks_left > 0) {
12333 + twi_writel(twi, THR,
12334 + twi->buf[twi->len - twi->acks_left]);
12335 + twi->acks_left--;
12336 + } else
12337 + twi_writel(twi, CR, TWI_BIT(STOP));
12338 + }
12339 +
12340 + if (twi->acks_left == 0)
12341 + twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
12342 + }
12343 +
12344 + /* enabling this message helps trigger overruns/underruns ... */
12345 + dev_vdbg(&twi->adapter.dev,
12346 + "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
12347 + old_status,
12348 + twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
12349 + twi->acks_left);
12350 +
12351 + return IRQ_HANDLED;
12352 +
12353 +done:
12354 + /* Note weak fault reporting model: we can't report how many
12355 + * bytes we sent before the NAK, or let upper layers choose
12356 + * whether to continue. The I2C stack doesn't allow that...
12357 + */
12358 + if (status & TWI_BIT(NACK)) {
12359 + dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
12360 + twi->acks_left);
12361 + twi->status = -EPIPE;
12362 +
12363 + /* TX underrun morphs automagically into a premature STOP;
12364 + * we'll probably observe UVRE even when it's not documented.
12365 + */
12366 + } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
12367 + dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
12368 + old_status, twi->acks_left);
12369 + twi->status = -ENOSR;
12370 + }
12371 +
12372 + twi_writel(twi, IDR, ~0UL);
12373 + complete(&twi->comp);
12374 +
12375 + dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
12376 + old_status, twi->acks_left, twi->status);
12377 +
12378 + return IRQ_HANDLED;
12379 +}
12380 +
12381 +
12382 +/*
12383 + * Return list of supported functionality.
12384 + *
12385 + * NOTE: see warning above about repeated starts; this driver is falsely
12386 + * claiming to support "combined" transfers. The mid-message STOPs mean
12387 + * some slaves will never work with this driver. (Use i2c-gpio...)
12388 + */
12389 +static u32 twi_func(struct i2c_adapter *adapter)
12390 +{
12391 + return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
12392 + & ~I2C_FUNC_SMBUS_QUICK;
12393 +}
12394 +
12395 +static struct i2c_algorithm twi_algorithm = {
12396 + .master_xfer = twi_xfer,
12397 + .functionality = twi_func,
12398 +};
12399 +
12400 +/*
12401 + * Main initialization routine.
12402 + */
12403 +static int __init twi_probe(struct platform_device *pdev)
12404 +{
12405 + struct atmel_twi *twi;
12406 + struct resource *regs;
12407 + struct clk *pclk;
12408 + struct i2c_adapter *adapter;
12409 + int rc, irq;
12410 +
12411 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12412 + if (!regs)
12413 + return -ENXIO;
12414 +
12415 + pclk = clk_get(&pdev->dev, "twi_pclk");
12416 + if (IS_ERR(pclk))
12417 + return PTR_ERR(pclk);
12418 + clk_enable(pclk);
12419 +
12420 + rc = -ENOMEM;
12421 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
12422 + if (!twi) {
12423 + dev_dbg(&pdev->dev, "can't allocate interface!\n");
12424 + goto err_alloc_twi;
12425 + }
12426 +
12427 + twi->pclk = pclk;
12428 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
12429 + if (!twi->regs)
12430 + goto err_ioremap;
12431 +
12432 + irq = platform_get_irq(pdev, 0);
12433 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
12434 + if (rc) {
12435 + dev_dbg(&pdev->dev, "can't bind irq!\n");
12436 + goto err_irq;
12437 + }
12438 + twi->irq = irq;
12439 +
12440 + rc = twi_hwinit(twi);
12441 + if (rc) {
12442 + dev_err(&pdev->dev, "Unable to set baudrate\n");
12443 + goto err_hw_init;
12444 + }
12445 +
12446 + adapter = &twi->adapter;
12447 + sprintf(adapter->name, "TWI");
12448 + adapter->algo = &twi_algorithm;
12449 + adapter->class = I2C_CLASS_ALL;
12450 + adapter->nr = pdev->id;
12451 + adapter->dev.parent = &pdev->dev;
12452 +
12453 + platform_set_drvdata(pdev, twi);
12454 +
12455 + rc = i2c_add_numbered_adapter(adapter);
12456 + if (rc) {
12457 + dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
12458 + adapter->name);
12459 + goto err_register;
12460 + }
12461 +
12462 + dev_info(&pdev->dev,
12463 + "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
12464 + baudrate/1000, (unsigned long)regs->start);
12465 +
12466 + return 0;
12467 +
12468 +
12469 +err_register:
12470 + platform_set_drvdata(pdev, NULL);
12471 +
12472 +err_hw_init:
12473 + free_irq(irq, twi);
12474 +
12475 +err_irq:
12476 + iounmap(twi->regs);
12477 +
12478 +err_ioremap:
12479 + kfree(twi);
12480 +
12481 +err_alloc_twi:
12482 + clk_disable(pclk);
12483 + clk_put(pclk);
12484 +
12485 + return rc;
12486 +}
12487 +
12488 +static int __exit twi_remove(struct platform_device *pdev)
12489 +{
12490 + struct atmel_twi *twi = platform_get_drvdata(pdev);
12491 + int res;
12492 +
12493 + platform_set_drvdata(pdev, NULL);
12494 + res = i2c_del_adapter(&twi->adapter);
12495 + twi_writel(twi, CR, TWI_BIT(MSDIS));
12496 + iounmap(twi->regs);
12497 + clk_disable(twi->pclk);
12498 + clk_put(twi->pclk);
12499 + free_irq(twi->irq, twi);
12500 + kfree(twi);
12501 +
12502 + return res;
12503 +}
12504 +
12505 +static struct platform_driver twi_driver = {
12506 + .remove = __exit_p(twi_remove),
12507 + .driver = {
12508 + .name = "atmel_twi",
12509 + .owner = THIS_MODULE,
12510 + },
12511 +};
12512 +
12513 +static int __init atmel_twi_init(void)
12514 +{
12515 + return platform_driver_probe(&twi_driver, twi_probe);
12516 +}
12517 +
12518 +static void __exit atmel_twi_exit(void)
12519 +{
12520 + platform_driver_unregister(&twi_driver);
12521 +}
12522 +
12523 +module_init(atmel_twi_init);
12524 +module_exit(atmel_twi_exit);
12525 +
12526 +MODULE_AUTHOR("Espen Krangnes");
12527 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
12528 +MODULE_LICENSE("GPL");
12529 --- /dev/null
12530 +++ b/drivers/i2c/busses/i2c-atmeltwi.h
12531 @@ -0,0 +1,117 @@
12532 +/*
12533 + * Register definitions for the Atmel Two-Wire Interface
12534 + */
12535 +
12536 +#ifndef __ATMELTWI_H__
12537 +#define __ATMELTWI_H__
12538 +
12539 +/* TWI register offsets */
12540 +#define TWI_CR 0x0000
12541 +#define TWI_MMR 0x0004
12542 +#define TWI_SMR 0x0008
12543 +#define TWI_IADR 0x000c
12544 +#define TWI_CWGR 0x0010
12545 +#define TWI_SR 0x0020
12546 +#define TWI_IER 0x0024
12547 +#define TWI_IDR 0x0028
12548 +#define TWI_IMR 0x002c
12549 +#define TWI_RHR 0x0030
12550 +#define TWI_THR 0x0034
12551 +
12552 +/* Bitfields in CR */
12553 +#define TWI_START_OFFSET 0
12554 +#define TWI_START_SIZE 1
12555 +#define TWI_STOP_OFFSET 1
12556 +#define TWI_STOP_SIZE 1
12557 +#define TWI_MSEN_OFFSET 2
12558 +#define TWI_MSEN_SIZE 1
12559 +#define TWI_MSDIS_OFFSET 3
12560 +#define TWI_MSDIS_SIZE 1
12561 +#define TWI_SVEN_OFFSET 4
12562 +#define TWI_SVEN_SIZE 1
12563 +#define TWI_SVDIS_OFFSET 5
12564 +#define TWI_SVDIS_SIZE 1
12565 +#define TWI_SWRST_OFFSET 7
12566 +#define TWI_SWRST_SIZE 1
12567 +
12568 +/* Bitfields in MMR */
12569 +#define TWI_IADRSZ_OFFSET 8
12570 +#define TWI_IADRSZ_SIZE 2
12571 +#define TWI_MREAD_OFFSET 12
12572 +#define TWI_MREAD_SIZE 1
12573 +#define TWI_DADR_OFFSET 16
12574 +#define TWI_DADR_SIZE 7
12575 +
12576 +/* Bitfields in SMR */
12577 +#define TWI_SADR_OFFSET 16
12578 +#define TWI_SADR_SIZE 7
12579 +
12580 +/* Bitfields in IADR */
12581 +#define TWI_IADR_OFFSET 0
12582 +#define TWI_IADR_SIZE 24
12583 +
12584 +/* Bitfields in CWGR */
12585 +#define TWI_CLDIV_OFFSET 0
12586 +#define TWI_CLDIV_SIZE 8
12587 +#define TWI_CHDIV_OFFSET 8
12588 +#define TWI_CHDIV_SIZE 8
12589 +#define TWI_CKDIV_OFFSET 16
12590 +#define TWI_CKDIV_SIZE 3
12591 +
12592 +/* Bitfields in SR */
12593 +#define TWI_TXCOMP_OFFSET 0
12594 +#define TWI_TXCOMP_SIZE 1
12595 +#define TWI_RXRDY_OFFSET 1
12596 +#define TWI_RXRDY_SIZE 1
12597 +#define TWI_TXRDY_OFFSET 2
12598 +#define TWI_TXRDY_SIZE 1
12599 +#define TWI_SVDIR_OFFSET 3
12600 +#define TWI_SVDIR_SIZE 1
12601 +#define TWI_SVACC_OFFSET 4
12602 +#define TWI_SVACC_SIZE 1
12603 +#define TWI_GCACC_OFFSET 5
12604 +#define TWI_GCACC_SIZE 1
12605 +#define TWI_OVRE_OFFSET 6
12606 +#define TWI_OVRE_SIZE 1
12607 +#define TWI_UNRE_OFFSET 7
12608 +#define TWI_UNRE_SIZE 1
12609 +#define TWI_NACK_OFFSET 8
12610 +#define TWI_NACK_SIZE 1
12611 +#define TWI_ARBLST_OFFSET 9
12612 +#define TWI_ARBLST_SIZE 1
12613 +
12614 +/* Bitfields in RHR */
12615 +#define TWI_RXDATA_OFFSET 0
12616 +#define TWI_RXDATA_SIZE 8
12617 +
12618 +/* Bitfields in THR */
12619 +#define TWI_TXDATA_OFFSET 0
12620 +#define TWI_TXDATA_SIZE 8
12621 +
12622 +/* Constants for IADRSZ */
12623 +#define TWI_IADRSZ_NO_ADDR 0
12624 +#define TWI_IADRSZ_ONE_BYTE 1
12625 +#define TWI_IADRSZ_TWO_BYTES 2
12626 +#define TWI_IADRSZ_THREE_BYTES 3
12627 +
12628 +/* Bit manipulation macros */
12629 +#define TWI_BIT(name) \
12630 + (1 << TWI_##name##_OFFSET)
12631 +#define TWI_BF(name, value) \
12632 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
12633 + << TWI_##name##_OFFSET)
12634 +#define TWI_BFEXT(name, value) \
12635 + (((value) >> TWI_##name##_OFFSET) \
12636 + & ((1 << TWI_##name##_SIZE) - 1))
12637 +#define TWI_BFINS(name, value, old) \
12638 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
12639 + << TWI_##name##_OFFSET)) \
12640 + | TWI_BF(name, (value)))
12641 +
12642 +/* Register access macros */
12643 +#define twi_readl(port, reg) \
12644 + __raw_readl((port)->regs + TWI_##reg)
12645 +#define twi_writel(port, reg, value) \
12646 + __raw_writel((value), (port)->regs + TWI_##reg)
12647 +
12648 +#endif /* __ATMELTWI_H__ */
12649 --- a/drivers/i2c/busses/Kconfig
12650 +++ b/drivers/i2c/busses/Kconfig
12651 @@ -88,6 +88,14 @@
12652 to support combined I2C messages. Use the i2c-gpio driver
12653 unless your system can cope with those limitations.
12654
12655 +config I2C_ATMELTWI
12656 + tristate "Atmel Two-Wire Interface (TWI)"
12657 + depends on I2C && (ARCH_AT91 || PLATFORM_AT32AP)
12658 + help
12659 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
12660 + AT91-based device and want to use its built-in TWI
12661 + functionality.
12662 +
12663 config I2C_AU1550
12664 tristate "Au1550/Au1200 SMBus interface"
12665 depends on SOC_AU1550 || SOC_AU1200
12666 --- a/drivers/i2c/busses/Makefile
12667 +++ b/drivers/i2c/busses/Makefile
12668 @@ -53,6 +53,7 @@
12669 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
12670 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
12671 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
12672 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
12673
12674 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
12675 EXTRA_CFLAGS += -DDEBUG
12676 --- /dev/null
12677 +++ b/drivers/input/serio/at32psif.c
12678 @@ -0,0 +1,351 @@
12679 +/*
12680 + * Copyright (C) 2007 Atmel Corporation
12681 + *
12682 + * Driver for the AT32AP700X PS/2 controller (PSIF).
12683 + *
12684 + * This program is free software; you can redistribute it and/or modify it
12685 + * under the terms of the GNU General Public License version 2 as published
12686 + * by the Free Software Foundation.
12687 + */
12688 +#include <linux/kernel.h>
12689 +#include <linux/module.h>
12690 +#include <linux/device.h>
12691 +#include <linux/init.h>
12692 +#include <linux/serio.h>
12693 +#include <linux/timer.h>
12694 +#include <linux/interrupt.h>
12695 +#include <linux/err.h>
12696 +#include <linux/io.h>
12697 +#include <linux/clk.h>
12698 +#include <linux/platform_device.h>
12699 +
12700 +#include "at32psif.h"
12701 +
12702 +#define PSIF_BUF_SIZE 16
12703 +
12704 +#define ring_is_empty(_psif) (_psif->head == _psif->tail)
12705 +#define ring_next_head(_psif) ((_psif->head + 1) & (PSIF_BUF_SIZE - 1))
12706 +#define ring_next_tail(_psif) ((_psif->tail + 1) & (PSIF_BUF_SIZE - 1))
12707 +
12708 +struct psif {
12709 + struct platform_device *pdev;
12710 + struct clk *pclk;
12711 + struct serio *io;
12712 + struct timer_list tx_timer;
12713 + void __iomem *regs;
12714 + unsigned int irq;
12715 + unsigned int open;
12716 + /* Prevent concurrent writes to circular buffer. */
12717 + spinlock_t lock;
12718 + unsigned int head;
12719 + unsigned int tail;
12720 + unsigned char buffer[PSIF_BUF_SIZE];
12721 +};
12722 +
12723 +static irqreturn_t psif_interrupt(int irq, void *_ptr)
12724 +{
12725 + struct psif *psif = _ptr;
12726 + int retval = IRQ_NONE;
12727 + unsigned int io_flags = 0;
12728 + unsigned long status;
12729 +
12730 + status = psif_readl(psif, SR);
12731 +
12732 + if (status & PSIF_BIT(RXRDY)) {
12733 + unsigned char val = (unsigned char) psif_readl(psif, RHR);
12734 +
12735 + if (status & PSIF_BIT(PARITY))
12736 + io_flags |= SERIO_PARITY;
12737 + if (status & PSIF_BIT(OVRUN))
12738 + dev_err(&psif->pdev->dev, "overrun read error\n");
12739 +
12740 + serio_interrupt(psif->io, val, io_flags);
12741 +
12742 + retval = IRQ_HANDLED;
12743 + }
12744 +
12745 + spin_lock(&psif->lock);
12746 +
12747 + if (status & PSIF_BIT(TXEMPTY)) {
12748 + if (status & PSIF_BIT(NACK))
12749 + dev_err(&psif->pdev->dev, "NACK error\n");
12750 +
12751 + psif_writel(psif, IDR, PSIF_BIT(TXEMPTY));
12752 +
12753 + if (!ring_is_empty(psif))
12754 + mod_timer(&psif->tx_timer,
12755 + jiffies + msecs_to_jiffies(1));
12756 +
12757 + retval = IRQ_HANDLED;
12758 + }
12759 +
12760 + spin_unlock(&psif->lock);
12761 +
12762 + return retval;
12763 +}
12764 +
12765 +static void psif_transmit_data(unsigned long data)
12766 +{
12767 + struct psif *psif = (struct psif *)data;
12768 + unsigned long flags;
12769 +
12770 + spin_lock_irqsave(&psif->lock, flags);
12771 +
12772 + psif_writel(psif, THR, psif->buffer[psif->tail]);
12773 + psif->tail = ring_next_tail(psif);
12774 +
12775 + if (!ring_is_empty(psif))
12776 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
12777 +
12778 + spin_unlock_irqrestore(&psif->lock, flags);
12779 +}
12780 +
12781 +static int psif_write(struct serio *io, unsigned char val)
12782 +{
12783 + struct psif *psif = io->port_data;
12784 + unsigned long flags;
12785 + unsigned int head;
12786 +
12787 + spin_lock_irqsave(&psif->lock, flags);
12788 +
12789 + head = ring_next_head(psif);
12790 +
12791 + if (head != psif->tail) {
12792 + psif->buffer[psif->head] = val;
12793 + psif->head = head;
12794 + } else {
12795 + dev_err(&psif->pdev->dev, "underrun write error\n");
12796 + }
12797 +
12798 + spin_unlock_irqrestore(&psif->lock, flags);
12799 +
12800 + /* Make sure TXEMPTY interrupt is enabled. */
12801 + psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
12802 +
12803 + return 0;
12804 +}
12805 +
12806 +static int psif_open(struct serio *io)
12807 +{
12808 + struct psif *psif = io->port_data;
12809 + int retval;
12810 +
12811 + retval = clk_enable(psif->pclk);
12812 + if (retval)
12813 + goto out;
12814 +
12815 + psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
12816 + psif_writel(psif, IER, PSIF_BIT(RXRDY));
12817 +
12818 + psif->open = 1;
12819 +out:
12820 + return retval;
12821 +}
12822 +
12823 +static void psif_close(struct serio *io)
12824 +{
12825 + struct psif *psif = io->port_data;
12826 +
12827 + psif->open = 0;
12828 +
12829 + psif_writel(psif, IDR, ~0UL);
12830 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
12831 +
12832 + clk_disable(psif->pclk);
12833 +}
12834 +
12835 +static void psif_set_prescaler(struct psif *psif)
12836 +{
12837 + unsigned long prscv;
12838 + unsigned long rate = clk_get_rate(psif->pclk);
12839 +
12840 + /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
12841 + prscv = 100 * (rate / 1000000UL);
12842 +
12843 + if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
12844 + prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
12845 + dev_dbg(&psif->pdev->dev, "pclk too fast, "
12846 + "prescaler set to max\n");
12847 + }
12848 +
12849 + clk_enable(psif->pclk);
12850 + psif_writel(psif, PSR, prscv);
12851 + clk_disable(psif->pclk);
12852 +}
12853 +
12854 +static int __init psif_probe(struct platform_device *pdev)
12855 +{
12856 + struct resource *regs;
12857 + struct psif *psif;
12858 + struct serio *io;
12859 + struct clk *pclk;
12860 + int irq;
12861 + int ret;
12862 +
12863 + psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
12864 + if (!psif) {
12865 + dev_dbg(&pdev->dev, "out of memory\n");
12866 + ret = -ENOMEM;
12867 + goto out;
12868 + }
12869 + psif->pdev = pdev;
12870 +
12871 + io = kzalloc(sizeof(struct serio), GFP_KERNEL);
12872 + if (!io) {
12873 + dev_dbg(&pdev->dev, "out of memory\n");
12874 + ret = -ENOMEM;
12875 + goto out_free_psif;
12876 + }
12877 + psif->io = io;
12878 +
12879 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
12880 + if (!regs) {
12881 + dev_dbg(&pdev->dev, "no mmio resources defined\n");
12882 + ret = -ENOMEM;
12883 + goto out_free_io;
12884 + }
12885 +
12886 + psif->regs = ioremap(regs->start, regs->end - regs->start + 1);
12887 + if (!psif->regs) {
12888 + ret = -ENOMEM;
12889 + dev_dbg(&pdev->dev, "could not map I/O memory\n");
12890 + goto out_free_io;
12891 + }
12892 +
12893 + pclk = clk_get(&pdev->dev, "pclk");
12894 + if (IS_ERR(pclk)) {
12895 + dev_dbg(&pdev->dev, "could not get peripheral clock\n");
12896 + ret = PTR_ERR(pclk);
12897 + goto out_iounmap;
12898 + }
12899 + psif->pclk = pclk;
12900 +
12901 + /* Reset the PSIF to enter at a known state. */
12902 + ret = clk_enable(pclk);
12903 + if (ret) {
12904 + dev_dbg(&pdev->dev, "could not enable pclk\n");
12905 + goto out_put_clk;
12906 + }
12907 + psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
12908 + clk_disable(pclk);
12909 +
12910 + setup_timer(&psif->tx_timer, psif_transmit_data, (unsigned long)psif);
12911 +
12912 + irq = platform_get_irq(pdev, 0);
12913 + if (irq < 0) {
12914 + dev_dbg(&pdev->dev, "could not get irq\n");
12915 + ret = -ENXIO;
12916 + goto out_put_clk;
12917 + }
12918 + ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
12919 + if (ret) {
12920 + dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
12921 + goto out_put_clk;
12922 + }
12923 + psif->irq = irq;
12924 +
12925 + io->id.type = SERIO_8042;
12926 + io->write = psif_write;
12927 + io->open = psif_open;
12928 + io->close = psif_close;
12929 + strlcpy(io->name, pdev->dev.bus_id, sizeof(io->name));
12930 + strlcpy(io->phys, pdev->dev.bus_id, sizeof(io->phys));
12931 + io->port_data = psif;
12932 + io->dev.parent = &pdev->dev;
12933 +
12934 + psif_set_prescaler(psif);
12935 +
12936 + spin_lock_init(&psif->lock);
12937 + serio_register_port(psif->io);
12938 + platform_set_drvdata(pdev, psif);
12939 +
12940 + dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
12941 + (int)psif->regs, psif->irq);
12942 +
12943 + return 0;
12944 +
12945 +out_put_clk:
12946 + clk_put(psif->pclk);
12947 +out_iounmap:
12948 + iounmap(psif->regs);
12949 +out_free_io:
12950 + kfree(io);
12951 +out_free_psif:
12952 + kfree(psif);
12953 +out:
12954 + return ret;
12955 +}
12956 +
12957 +static int __exit psif_remove(struct platform_device *pdev)
12958 +{
12959 + struct psif *psif = platform_get_drvdata(pdev);
12960 +
12961 + psif_writel(psif, IDR, ~0UL);
12962 + psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
12963 +
12964 + serio_unregister_port(psif->io);
12965 + iounmap(psif->regs);
12966 + free_irq(psif->irq, psif);
12967 + clk_put(psif->pclk);
12968 + kfree(psif);
12969 +
12970 + platform_set_drvdata(pdev, NULL);
12971 +
12972 + return 0;
12973 +}
12974 +
12975 +#ifdef CONFIG_PM
12976 +static int psif_suspend(struct platform_device *pdev, pm_message_t state)
12977 +{
12978 + struct psif *psif = platform_get_drvdata(pdev);
12979 +
12980 + if (psif->open) {
12981 + psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
12982 + clk_disable(psif->pclk);
12983 + }
12984 +
12985 + return 0;
12986 +}
12987 +
12988 +static int psif_resume(struct platform_device *pdev)
12989 +{
12990 + struct psif *psif = platform_get_drvdata(pdev);
12991 +
12992 + if (psif->open) {
12993 + clk_enable(psif->pclk);
12994 + psif_set_prescaler(psif);
12995 + psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
12996 + }
12997 +
12998 + return 0;
12999 +}
13000 +#else
13001 +#define psif_suspend NULL
13002 +#define psif_resume NULL
13003 +#endif
13004 +
13005 +static struct platform_driver psif_driver = {
13006 + .remove = __exit_p(psif_remove),
13007 + .driver = {
13008 + .name = "atmel_psif",
13009 + },
13010 + .suspend = psif_suspend,
13011 + .resume = psif_resume,
13012 +};
13013 +
13014 +static int __init psif_init(void)
13015 +{
13016 + return platform_driver_probe(&psif_driver, psif_probe);
13017 +}
13018 +
13019 +static void __exit psif_exit(void)
13020 +{
13021 + platform_driver_unregister(&psif_driver);
13022 +}
13023 +
13024 +module_init(psif_init);
13025 +module_exit(psif_exit);
13026 +
13027 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
13028 +MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
13029 +MODULE_LICENSE("GPL");
13030 --- /dev/null
13031 +++ b/drivers/input/serio/at32psif.h
13032 @@ -0,0 +1,82 @@
13033 +/*
13034 + * Copyright (C) 2007 Atmel Corporation
13035 + *
13036 + * Driver for the AT32AP700X PS/2 controller (PSIF).
13037 + *
13038 + * This program is free software; you can redistribute it and/or modify it
13039 + * under the terms of the GNU General Public License version 2 as published
13040 + * by the Free Software Foundation.
13041 + */
13042 +
13043 +#ifndef _AT32PSIF_H
13044 +#define _AT32PSIF_H
13045 +
13046 +/* PSIF register offsets */
13047 +#define PSIF_CR 0x00
13048 +#define PSIF_RHR 0x04
13049 +#define PSIF_THR 0x08
13050 +#define PSIF_SR 0x10
13051 +#define PSIF_IER 0x14
13052 +#define PSIF_IDR 0x18
13053 +#define PSIF_IMR 0x1c
13054 +#define PSIF_PSR 0x24
13055 +
13056 +/* Bitfields in control register. */
13057 +#define PSIF_CR_RXDIS_OFFSET 1
13058 +#define PSIF_CR_RXDIS_SIZE 1
13059 +#define PSIF_CR_RXEN_OFFSET 0
13060 +#define PSIF_CR_RXEN_SIZE 1
13061 +#define PSIF_CR_SWRST_OFFSET 15
13062 +#define PSIF_CR_SWRST_SIZE 1
13063 +#define PSIF_CR_TXDIS_OFFSET 9
13064 +#define PSIF_CR_TXDIS_SIZE 1
13065 +#define PSIF_CR_TXEN_OFFSET 8
13066 +#define PSIF_CR_TXEN_SIZE 1
13067 +
13068 +/* Bitfields in interrupt disable, enable, mask and status register. */
13069 +#define PSIF_NACK_OFFSET 8
13070 +#define PSIF_NACK_SIZE 1
13071 +#define PSIF_OVRUN_OFFSET 5
13072 +#define PSIF_OVRUN_SIZE 1
13073 +#define PSIF_PARITY_OFFSET 9
13074 +#define PSIF_PARITY_SIZE 1
13075 +#define PSIF_RXRDY_OFFSET 4
13076 +#define PSIF_RXRDY_SIZE 1
13077 +#define PSIF_TXEMPTY_OFFSET 1
13078 +#define PSIF_TXEMPTY_SIZE 1
13079 +#define PSIF_TXRDY_OFFSET 0
13080 +#define PSIF_TXRDY_SIZE 1
13081 +
13082 +/* Bitfields in prescale register. */
13083 +#define PSIF_PSR_PRSCV_OFFSET 0
13084 +#define PSIF_PSR_PRSCV_SIZE 12
13085 +
13086 +/* Bitfields in receive hold register. */
13087 +#define PSIF_RHR_RXDATA_OFFSET 0
13088 +#define PSIF_RHR_RXDATA_SIZE 8
13089 +
13090 +/* Bitfields in transmit hold register. */
13091 +#define PSIF_THR_TXDATA_OFFSET 0
13092 +#define PSIF_THR_TXDATA_SIZE 8
13093 +
13094 +/* Bit manipulation macros */
13095 +#define PSIF_BIT(name) \
13096 + (1 << PSIF_##name##_OFFSET)
13097 +#define PSIF_BF(name, value) \
13098 + (((value) & ((1 << PSIF_##name##_SIZE) - 1)) \
13099 + << PSIF_##name##_OFFSET)
13100 +#define PSIF_BFEXT(name, value)\
13101 + (((value) >> PSIF_##name##_OFFSET) \
13102 + & ((1 << PSIF_##name##_SIZE) - 1))
13103 +#define PSIF_BFINS(name, value, old) \
13104 + (((old) & ~(((1 << PSIF_##name##_SIZE) - 1) \
13105 + << PSIF_##name##_OFFSET)) \
13106 + | PSIF_BF(name, value))
13107 +
13108 +/* Register access macros */
13109 +#define psif_readl(port, reg) \
13110 + __raw_readl((port)->regs + PSIF_##reg)
13111 +#define psif_writel(port, reg, value) \
13112 + __raw_writel((value), (port)->regs + PSIF_##reg)
13113 +
13114 +#endif /* _AT32PSIF_H */
13115 --- a/drivers/input/serio/Kconfig
13116 +++ b/drivers/input/serio/Kconfig
13117 @@ -88,6 +88,17 @@
13118 To compile this driver as a module, choose M here: the
13119 module will be called rpckbd.
13120
13121 +config SERIO_AT32PSIF
13122 + tristate "AVR32 PSIF PS/2 keyboard and mouse controller"
13123 + depends on AVR32
13124 + default n
13125 + help
13126 + Say Y here if you want to use the PSIF peripheral on AVR32 devices
13127 + and connect a PS/2 keyboard and/or mouse to it.
13128 +
13129 + To compile this driver as a module, choose M here: the module will
13130 + be called at32psif.
13131 +
13132 config SERIO_AMBAKMI
13133 tristate "AMBA KMI keyboard controller"
13134 depends on ARM_AMBA
13135 --- a/drivers/input/serio/Makefile
13136 +++ b/drivers/input/serio/Makefile
13137 @@ -12,6 +12,7 @@
13138 obj-$(CONFIG_SERIO_RPCKBD) += rpckbd.o
13139 obj-$(CONFIG_SERIO_SA1111) += sa1111ps2.o
13140 obj-$(CONFIG_SERIO_AMBAKMI) += ambakmi.o
13141 +obj-$(CONFIG_SERIO_AT32PSIF) += at32psif.o
13142 obj-$(CONFIG_SERIO_Q40KBD) += q40kbd.o
13143 obj-$(CONFIG_SERIO_GSCPS2) += gscps2.o
13144 obj-$(CONFIG_HP_SDC) += hp_sdc.o
13145 --- a/drivers/leds/Kconfig
13146 +++ b/drivers/leds/Kconfig
13147 @@ -18,6 +18,13 @@
13148
13149 comment "LED drivers"
13150
13151 +config LEDS_ATMEL_PWM
13152 + tristate "LED Support using Atmel PWM outputs"
13153 + depends on LEDS_CLASS && ATMEL_PWM
13154 + help
13155 + This option enables support for LEDs driven using outputs
13156 + of the dedicated PWM controller found on newer Atmel SOCs.
13157 +
13158 config LEDS_CORGI
13159 tristate "LED Support for the Sharp SL-C7x0 series"
13160 depends on LEDS_CLASS && PXA_SHARP_C7xx
13161 --- /dev/null
13162 +++ b/drivers/leds/leds-atmel-pwm.c
13163 @@ -0,0 +1,155 @@
13164 +#include <linux/kernel.h>
13165 +#include <linux/platform_device.h>
13166 +#include <linux/leds.h>
13167 +#include <linux/io.h>
13168 +#include <linux/atmel_pwm.h>
13169 +
13170 +
13171 +struct pwmled {
13172 + struct led_classdev cdev;
13173 + struct pwm_channel pwmc;
13174 + struct gpio_led *desc;
13175 + u32 mult;
13176 + u8 active_low;
13177 +};
13178 +
13179 +
13180 +/*
13181 + * For simplicity, we use "brightness" as if it were a linear function
13182 + * of PWM duty cycle. However, a logarithmic function of duty cycle is
13183 + * probably a better match for perceived brightness: two is half as bright
13184 + * as four, four is half as bright as eight, etc
13185 + */
13186 +static void pwmled_brightness(struct led_classdev *cdev, enum led_brightness b)
13187 +{
13188 + struct pwmled *led;
13189 +
13190 + /* update the duty cycle for the *next* period */
13191 + led = container_of(cdev, struct pwmled, cdev);
13192 + pwm_channel_writel(&led->pwmc, PWM_CUPD, led->mult * (unsigned) b);
13193 +}
13194 +
13195 +/*
13196 + * NOTE: we reuse the platform_data structure of GPIO leds,
13197 + * but repurpose its "gpio" number as a PWM channel number.
13198 + */
13199 +static int __init pwmled_probe(struct platform_device *pdev)
13200 +{
13201 + const struct gpio_led_platform_data *pdata;
13202 + struct pwmled *leds;
13203 + unsigned i;
13204 + int status;
13205 +
13206 + pdata = pdev->dev.platform_data;
13207 + if (!pdata || pdata->num_leds < 1)
13208 + return -ENODEV;
13209 +
13210 + leds = kcalloc(pdata->num_leds, sizeof(*leds), GFP_KERNEL);
13211 + if (!leds)
13212 + return -ENOMEM;
13213 +
13214 + for (i = 0; i < pdata->num_leds; i++) {
13215 + struct pwmled *led = leds + i;
13216 + const struct gpio_led *dat = pdata->leds + i;
13217 + u32 tmp;
13218 +
13219 + led->cdev.name = dat->name;
13220 + led->cdev.brightness = LED_OFF;
13221 + led->cdev.brightness_set = pwmled_brightness;
13222 + led->cdev.default_trigger = dat->default_trigger;
13223 +
13224 + led->active_low = dat->active_low;
13225 +
13226 + status = pwm_channel_alloc(dat->gpio, &led->pwmc);
13227 + if (status < 0)
13228 + goto err;
13229 +
13230 + /*
13231 + * Prescale clock by 2^x, so PWM counts in low MHz.
13232 + * Start each cycle with the LED active, so increasing
13233 + * the duty cycle gives us more time on (== brighter).
13234 + */
13235 + tmp = 5;
13236 + if (!led->active_low)
13237 + tmp |= PWM_CPR_CPOL;
13238 + pwm_channel_writel(&led->pwmc, PWM_CMR, tmp);
13239 +
13240 + /*
13241 + * Pick a period so PWM cycles at 100+ Hz; and a multiplier
13242 + * for scaling duty cycle: brightness * mult.
13243 + */
13244 + tmp = (led->pwmc.mck / (1 << 5)) / 100;
13245 + tmp /= 255;
13246 + led->mult = tmp;
13247 + pwm_channel_writel(&led->pwmc, PWM_CDTY,
13248 + led->cdev.brightness * 255);
13249 + pwm_channel_writel(&led->pwmc, PWM_CPRD,
13250 + LED_FULL * tmp);
13251 +
13252 + pwm_channel_enable(&led->pwmc);
13253 +
13254 + /* Hand it over to the LED framework */
13255 + status = led_classdev_register(&pdev->dev, &led->cdev);
13256 + if (status < 0) {
13257 + pwm_channel_free(&led->pwmc);
13258 + goto err;
13259 + }
13260 + }
13261 +
13262 + platform_set_drvdata(pdev, leds);
13263 + return 0;
13264 +
13265 +err:
13266 + while (i-- > 0) {
13267 + led_classdev_unregister(&leds[i].cdev);
13268 + pwm_channel_free(&leds[i].pwmc);
13269 + }
13270 + kfree(leds);
13271 +
13272 + return status;
13273 +}
13274 +
13275 +static int __exit pwmled_remove(struct platform_device *pdev)
13276 +{
13277 + const struct gpio_led_platform_data *pdata;
13278 + struct pwmled *leds;
13279 + unsigned i;
13280 +
13281 + pdata = pdev->dev.platform_data;
13282 + leds = platform_get_drvdata(pdev);
13283 +
13284 + for (i = 0; i < pdata->num_leds; i++) {
13285 + struct pwmled *led = leds + i;
13286 +
13287 + led_classdev_unregister(&led->cdev);
13288 + pwm_channel_free(&led->pwmc);
13289 + }
13290 +
13291 + kfree(leds);
13292 + platform_set_drvdata(pdev, NULL);
13293 + return 0;
13294 +}
13295 +
13296 +static struct platform_driver pwmled_driver = {
13297 + .driver = {
13298 + .name = "leds-atmel-pwm",
13299 + .owner = THIS_MODULE,
13300 + },
13301 + /* REVISIT add suspend() and resume() methods */
13302 + .remove = __exit_p(pwmled_remove),
13303 +};
13304 +
13305 +static int __init modinit(void)
13306 +{
13307 + return platform_driver_probe(&pwmled_driver, pwmled_probe);
13308 +}
13309 +module_init(modinit);
13310 +
13311 +static void __exit modexit(void)
13312 +{
13313 + platform_driver_unregister(&pwmled_driver);
13314 +}
13315 +module_exit(modexit);
13316 +
13317 +MODULE_DESCRIPTION("Driver for LEDs with PWM-controlled brightness");
13318 +MODULE_LICENSE("GPL");
13319 --- a/drivers/leds/Makefile
13320 +++ b/drivers/leds/Makefile
13321 @@ -5,6 +5,7 @@
13322 obj-$(CONFIG_LEDS_TRIGGERS) += led-triggers.o
13323
13324 # LED Platform Drivers
13325 +obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o
13326 obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o
13327 obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o
13328 obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o
13329 --- /dev/null
13330 +++ b/drivers/misc/atmel_pwm.c
13331 @@ -0,0 +1,409 @@
13332 +#include <linux/module.h>
13333 +#include <linux/clk.h>
13334 +#include <linux/err.h>
13335 +#include <linux/io.h>
13336 +#include <linux/interrupt.h>
13337 +#include <linux/platform_device.h>
13338 +#include <linux/atmel_pwm.h>
13339 +
13340 +
13341 +/*
13342 + * This is a simple driver for the PWM controller found in various newer
13343 + * Atmel SOCs, including the AVR32 series and the AT91sam9263.
13344 + *
13345 + * Chips with current Linux ports have only 4 PWM channels, out of max 32.
13346 + * AT32UC3A and AT32UC3B chips have 7 channels (but currently no Linux).
13347 + * Docs are inconsistent about the width of the channel counter registers;
13348 + * it's at least 16 bits, but several places say 20 bits.
13349 + */
13350 +#define PWM_NCHAN 4 /* max 32 */
13351 +
13352 +struct pwm {
13353 + spinlock_t lock;
13354 + struct platform_device *pdev;
13355 + u32 mask;
13356 + int irq;
13357 + void __iomem *base;
13358 + struct clk *clk;
13359 + struct pwm_channel *channel[PWM_NCHAN];
13360 + void (*handler[PWM_NCHAN])(struct pwm_channel *);
13361 +};
13362 +
13363 +
13364 +/* global PWM controller registers */
13365 +#define PWM_MR 0x00
13366 +#define PWM_ENA 0x04
13367 +#define PWM_DIS 0x08
13368 +#define PWM_SR 0x0c
13369 +#define PWM_IER 0x10
13370 +#define PWM_IDR 0x14
13371 +#define PWM_IMR 0x18
13372 +#define PWM_ISR 0x1c
13373 +
13374 +static inline void pwm_writel(const struct pwm *p, unsigned offset, u32 val)
13375 +{
13376 + __raw_writel(val, p->base + offset);
13377 +}
13378 +
13379 +static inline u32 pwm_readl(const struct pwm *p, unsigned offset)
13380 +{
13381 + return __raw_readl(p->base + offset);
13382 +}
13383 +
13384 +static inline void __iomem *pwmc_regs(const struct pwm *p, int index)
13385 +{
13386 + return p->base + 0x200 + index * 0x20;
13387 +}
13388 +
13389 +static struct pwm *pwm;
13390 +
13391 +static void pwm_dumpregs(struct pwm_channel *ch, char *tag)
13392 +{
13393 + struct device *dev = &pwm->pdev->dev;
13394 +
13395 + dev_dbg(dev, "%s: mr %08x, sr %08x, imr %08x\n",
13396 + tag,
13397 + pwm_readl(pwm, PWM_MR),
13398 + pwm_readl(pwm, PWM_SR),
13399 + pwm_readl(pwm, PWM_IMR));
13400 + dev_dbg(dev,
13401 + "pwm ch%d - mr %08x, dty %u, prd %u, cnt %u\n",
13402 + ch->index,
13403 + pwm_channel_readl(ch, PWM_CMR),
13404 + pwm_channel_readl(ch, PWM_CDTY),
13405 + pwm_channel_readl(ch, PWM_CPRD),
13406 + pwm_channel_readl(ch, PWM_CCNT));
13407 +}
13408 +
13409 +
13410 +/**
13411 + * pwm_channel_alloc - allocate an unused PWM channel
13412 + * @index: identifies the channel
13413 + * @ch: structure to be initialized
13414 + *
13415 + * Drivers allocate PWM channels according to the board's wiring, and
13416 + * matching board-specific setup code. Returns zero or negative errno.
13417 + */
13418 +int pwm_channel_alloc(int index, struct pwm_channel *ch)
13419 +{
13420 + unsigned long flags;
13421 + int status = 0;
13422 +
13423 + /* insist on PWM init, with this signal pinned out */
13424 + if (!pwm || !(pwm->mask & 1 << index))
13425 + return -ENODEV;
13426 +
13427 + if (index < 0 || index >= PWM_NCHAN || !ch)
13428 + return -EINVAL;
13429 + memset(ch, 0, sizeof *ch);
13430 +
13431 + spin_lock_irqsave(&pwm->lock, flags);
13432 + if (pwm->channel[index])
13433 + status = -EBUSY;
13434 + else {
13435 + clk_enable(pwm->clk);
13436 +
13437 + ch->regs = pwmc_regs(pwm, index);
13438 + ch->index = index;
13439 +
13440 + /* REVISIT: ap7000 seems to go 2x as fast as we expect!! */
13441 + ch->mck = clk_get_rate(pwm->clk);
13442 +
13443 + pwm->channel[index] = ch;
13444 + pwm->handler[index] = NULL;
13445 +
13446 + /* channel and irq are always disabled when we return */
13447 + pwm_writel(pwm, PWM_DIS, 1 << index);
13448 + pwm_writel(pwm, PWM_IDR, 1 << index);
13449 + }
13450 + spin_unlock_irqrestore(&pwm->lock, flags);
13451 + return status;
13452 +}
13453 +EXPORT_SYMBOL(pwm_channel_alloc);
13454 +
13455 +static int pwmcheck(struct pwm_channel *ch)
13456 +{
13457 + int index;
13458 +
13459 + if (!pwm)
13460 + return -ENODEV;
13461 + if (!ch)
13462 + return -EINVAL;
13463 + index = ch->index;
13464 + if (index < 0 || index >= PWM_NCHAN || pwm->channel[index] != ch)
13465 + return -EINVAL;
13466 +
13467 + return index;
13468 +}
13469 +
13470 +/**
13471 + * pwm_channel_free - release a previously allocated channel
13472 + * @ch: the channel being released
13473 + *
13474 + * The channel is completely shut down (counter and IRQ disabled),
13475 + * and made available for re-use. Returns zero, or negative errno.
13476 + */
13477 +int pwm_channel_free(struct pwm_channel *ch)
13478 +{
13479 + unsigned long flags;
13480 + int t;
13481 +
13482 + spin_lock_irqsave(&pwm->lock, flags);
13483 + t = pwmcheck(ch);
13484 + if (t >= 0) {
13485 + pwm->channel[t] = NULL;
13486 + pwm->handler[t] = NULL;
13487 +
13488 + /* channel and irq are always disabled when we return */
13489 + pwm_writel(pwm, PWM_DIS, 1 << t);
13490 + pwm_writel(pwm, PWM_IDR, 1 << t);
13491 +
13492 + clk_disable(pwm->clk);
13493 + t = 0;
13494 + }
13495 + spin_unlock_irqrestore(&pwm->lock, flags);
13496 + return t;
13497 +}
13498 +EXPORT_SYMBOL(pwm_channel_free);
13499 +
13500 +int __pwm_channel_onoff(struct pwm_channel *ch, int enabled)
13501 +{
13502 + unsigned long flags;
13503 + int t;
13504 +
13505 + /* OMITTED FUNCTIONALITY: starting several channels in synch */
13506 +
13507 + spin_lock_irqsave(&pwm->lock, flags);
13508 + t = pwmcheck(ch);
13509 + if (t >= 0) {
13510 + pwm_writel(pwm, enabled ? PWM_ENA : PWM_DIS, 1 << t);
13511 + t = 0;
13512 + pwm_dumpregs(ch, enabled ? "enable" : "disable");
13513 + }
13514 + spin_unlock_irqrestore(&pwm->lock, flags);
13515 +
13516 + return t;
13517 +}
13518 +EXPORT_SYMBOL(__pwm_channel_onoff);
13519 +
13520 +/**
13521 + * pwm_clk_alloc - allocate and configure CLKA or CLKB
13522 + * @prescale: from 0..10, the power of two used to divide MCK
13523 + * @div: from 1..255, the linear divisor to use
13524 + *
13525 + * Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated
13526 + * clock will run with a period of (2^prescale * div) / MCK, or twice as
13527 + * long if center aligned PWM output is used. The clock must later be
13528 + * deconfigured using pwm_clk_free().
13529 + */
13530 +int pwm_clk_alloc(unsigned prescale, unsigned div)
13531 +{
13532 + unsigned long flags;
13533 + u32 mr;
13534 + u32 val = (prescale << 8) | div;
13535 + int ret = -EBUSY;
13536 +
13537 + if (prescale >= 10 || div == 0 || div > 255)
13538 + return -EINVAL;
13539 +
13540 + spin_lock_irqsave(&pwm->lock, flags);
13541 + mr = pwm_readl(pwm, PWM_MR);
13542 + if ((mr & 0xffff) == 0) {
13543 + mr |= val;
13544 + ret = PWM_CPR_CLKA;
13545 + }
13546 + if ((mr & (0xffff << 16)) == 0) {
13547 + mr |= val << 16;
13548 + ret = PWM_CPR_CLKB;
13549 + }
13550 + if (ret > 0)
13551 + pwm_writel(pwm, PWM_MR, mr);
13552 + spin_unlock_irqrestore(&pwm->lock, flags);
13553 + return ret;
13554 +}
13555 +EXPORT_SYMBOL(pwm_clk_alloc);
13556 +
13557 +/**
13558 + * pwm_clk_free - deconfigure and release CLKA or CLKB
13559 + *
13560 + * Reverses the effect of pwm_clk_alloc().
13561 + */
13562 +void pwm_clk_free(unsigned clk)
13563 +{
13564 + unsigned long flags;
13565 + u32 mr;
13566 +
13567 + spin_lock_irqsave(&pwm->lock, flags);
13568 + mr = pwm_readl(pwm, PWM_MR);
13569 + if (clk == PWM_CPR_CLKA)
13570 + pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 0));
13571 + if (clk == PWM_CPR_CLKB)
13572 + pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 16));
13573 + spin_unlock_irqrestore(&pwm->lock, flags);
13574 +}
13575 +EXPORT_SYMBOL(pwm_clk_free);
13576 +
13577 +/**
13578 + * pwm_channel_handler - manage channel's IRQ handler
13579 + * @ch: the channel
13580 + * @handler: the handler to use, possibly NULL
13581 + *
13582 + * If the handler is non-null, the handler will be called after every
13583 + * period of this PWM channel. If the handler is null, this channel
13584 + * won't generate an IRQ.
13585 + */
13586 +int pwm_channel_handler(struct pwm_channel *ch,
13587 + void (*handler)(struct pwm_channel *ch))
13588 +{
13589 + unsigned long flags;
13590 + int t;
13591 +
13592 + spin_lock_irqsave(&pwm->lock, flags);
13593 + t = pwmcheck(ch);
13594 + if (t >= 0) {
13595 + pwm->handler[t] = handler;
13596 + pwm_writel(pwm, handler ? PWM_IER : PWM_IDR, 1 << t);
13597 + t = 0;
13598 + }
13599 + spin_unlock_irqrestore(&pwm->lock, flags);
13600 +
13601 + return t;
13602 +}
13603 +EXPORT_SYMBOL(pwm_channel_handler);
13604 +
13605 +static irqreturn_t pwm_irq(int id, void *_pwm)
13606 +{
13607 + struct pwm *p = _pwm;
13608 + irqreturn_t handled = IRQ_NONE;
13609 + u32 irqstat;
13610 + int index;
13611 +
13612 + spin_lock(&p->lock);
13613 +
13614 + /* ack irqs, then handle them */
13615 + irqstat = pwm_readl(pwm, PWM_ISR);
13616 +
13617 + while (irqstat) {
13618 + struct pwm_channel *ch;
13619 + void (*handler)(struct pwm_channel *ch);
13620 +
13621 + index = ffs(irqstat) - 1;
13622 + irqstat &= ~(1 << index);
13623 + ch = pwm->channel[index];
13624 + handler = pwm->handler[index];
13625 + if (handler && ch) {
13626 + spin_unlock(&p->lock);
13627 + handler(ch);
13628 + spin_lock(&p->lock);
13629 + handled = IRQ_HANDLED;
13630 + }
13631 + }
13632 +
13633 + spin_unlock(&p->lock);
13634 + return handled;
13635 +}
13636 +
13637 +static int __init pwm_probe(struct platform_device *pdev)
13638 +{
13639 + struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
13640 + int irq = platform_get_irq(pdev, 0);
13641 + u32 *mp = pdev->dev.platform_data;
13642 + struct pwm *p;
13643 + int status = -EIO;
13644 +
13645 + if (pwm)
13646 + return -EBUSY;
13647 + if (!r || irq < 0 || !mp || !*mp)
13648 + return -ENODEV;
13649 + if (*mp & ~((1<<PWM_NCHAN)-1)) {
13650 + dev_warn(&pdev->dev, "mask 0x%x ... more than %d channels\n",
13651 + *mp, PWM_NCHAN);
13652 + return -EINVAL;
13653 + }
13654 +
13655 + p = kzalloc(sizeof(*p), GFP_KERNEL);
13656 + if (!p)
13657 + return -ENOMEM;
13658 +
13659 + spin_lock_init(&p->lock);
13660 + p->pdev = pdev;
13661 + p->mask = *mp;
13662 + p->irq = irq;
13663 + p->base = ioremap(r->start, r->end - r->start + 1);
13664 + if (!p->base)
13665 + goto fail;
13666 + p->clk = clk_get(&pdev->dev, "mck");
13667 + if (IS_ERR(p->clk)) {
13668 + status = PTR_ERR(p->clk);
13669 + p->clk = NULL;
13670 + goto fail;
13671 + }
13672 +
13673 + status = request_irq(irq, pwm_irq, 0, pdev->name, p);
13674 + if (status < 0)
13675 + goto fail;
13676 +
13677 + pwm = p;
13678 + platform_set_drvdata(pdev, p);
13679 +
13680 + return 0;
13681 +
13682 +fail:
13683 + if (p->clk)
13684 + clk_put(p->clk);
13685 + if (p->base)
13686 + iounmap(p->base);
13687 +
13688 + kfree(p);
13689 + return status;
13690 +}
13691 +
13692 +static int __exit pwm_remove(struct platform_device *pdev)
13693 +{
13694 + struct pwm *p = platform_get_drvdata(pdev);
13695 +
13696 + if (p != pwm)
13697 + return -EINVAL;
13698 +
13699 + clk_enable(pwm->clk);
13700 + pwm_writel(pwm, PWM_DIS, (1 << PWM_NCHAN) - 1);
13701 + pwm_writel(pwm, PWM_IDR, (1 << PWM_NCHAN) - 1);
13702 + clk_disable(pwm->clk);
13703 +
13704 + pwm = NULL;
13705 +
13706 + free_irq(p->irq, p);
13707 + clk_put(p->clk);
13708 + iounmap(p->base);
13709 + kfree(p);
13710 +
13711 + return 0;
13712 +}
13713 +
13714 +static struct platform_driver atmel_pwm_driver = {
13715 + .driver = {
13716 + .name = "atmel_pwm",
13717 + .owner = THIS_MODULE,
13718 + },
13719 + .remove = __exit_p(pwm_remove),
13720 +
13721 + /* NOTE: PWM can keep running in AVR32 "idle" and "frozen" states;
13722 + * and all AT91sam9263 states, albeit at reduced clock rate if
13723 + * MCK becomes the slow clock (i.e. what Linux labels STR).
13724 + */
13725 +};
13726 +
13727 +static int __init pwm_init(void)
13728 +{
13729 + return platform_driver_probe(&atmel_pwm_driver, pwm_probe);
13730 +}
13731 +module_init(pwm_init);
13732 +
13733 +static void __exit pwm_exit(void)
13734 +{
13735 + platform_driver_unregister(&atmel_pwm_driver);
13736 +}
13737 +module_exit(pwm_exit);
13738 +
13739 +MODULE_DESCRIPTION("Driver for AT32/AT91 PWM module");
13740 +MODULE_LICENSE("GPL");
13741 --- /dev/null
13742 +++ b/drivers/misc/atmel_tclib.c
13743 @@ -0,0 +1,161 @@
13744 +#include <linux/atmel_tc.h>
13745 +#include <linux/clk.h>
13746 +#include <linux/err.h>
13747 +#include <linux/init.h>
13748 +#include <linux/io.h>
13749 +#include <linux/ioport.h>
13750 +#include <linux/kernel.h>
13751 +#include <linux/platform_device.h>
13752 +
13753 +/* Number of bytes to reserve for the iomem resource */
13754 +#define ATMEL_TC_IOMEM_SIZE 256
13755 +
13756 +
13757 +/*
13758 + * This is a thin library to solve the problem of how to portably allocate
13759 + * one of the TC blocks. For simplicity, it doesn't currently expect to
13760 + * share individual timers between different drivers.
13761 + */
13762 +
13763 +#if defined(CONFIG_AVR32)
13764 +/* AVR32 has these divide PBB */
13765 +const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
13766 +EXPORT_SYMBOL(atmel_tc_divisors);
13767 +
13768 +#elif defined(CONFIG_ARCH_AT91)
13769 +/* AT91 has these divide MCK */
13770 +const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
13771 +EXPORT_SYMBOL(atmel_tc_divisors);
13772 +
13773 +#endif
13774 +
13775 +static DEFINE_SPINLOCK(tc_list_lock);
13776 +static LIST_HEAD(tc_list);
13777 +
13778 +/**
13779 + * atmel_tc_alloc - allocate a specified TC block
13780 + * @block: which block to allocate
13781 + * @name: name to be associated with the iomem resource
13782 + *
13783 + * Caller allocates a block. If it is available, a pointer to a
13784 + * pre-initialized struct atmel_tc is returned. The caller can access
13785 + * the registers directly through the "regs" field.
13786 + */
13787 +struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
13788 +{
13789 + struct atmel_tc *tc;
13790 + struct platform_device *pdev = NULL;
13791 + struct resource *r;
13792 +
13793 + spin_lock(&tc_list_lock);
13794 + list_for_each_entry(tc, &tc_list, node) {
13795 + if (tc->pdev->id == block) {
13796 + pdev = tc->pdev;
13797 + break;
13798 + }
13799 + }
13800 +
13801 + if (!pdev || tc->iomem)
13802 + goto fail;
13803 +
13804 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
13805 + r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
13806 + if (!r)
13807 + goto fail;
13808 +
13809 + tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
13810 + if (!tc->regs)
13811 + goto fail_ioremap;
13812 +
13813 + tc->iomem = r;
13814 +
13815 +out:
13816 + spin_unlock(&tc_list_lock);
13817 + return tc;
13818 +
13819 +fail_ioremap:
13820 + release_resource(r);
13821 +fail:
13822 + tc = NULL;
13823 + goto out;
13824 +}
13825 +EXPORT_SYMBOL_GPL(atmel_tc_alloc);
13826 +
13827 +/**
13828 + * atmel_tc_free - release a specified TC block
13829 + * @tc: Timer/counter block that was returned by atmel_tc_alloc()
13830 + *
13831 + * This reverses the effect of atmel_tc_alloc(), unmapping the I/O
13832 + * registers, invalidating the resource returned by that routine and
13833 + * making the TC available to other drivers.
13834 + */
13835 +void atmel_tc_free(struct atmel_tc *tc)
13836 +{
13837 + spin_lock(&tc_list_lock);
13838 + if (tc->regs) {
13839 + iounmap(tc->regs);
13840 + release_resource(tc->iomem);
13841 + tc->regs = NULL;
13842 + tc->iomem = NULL;
13843 + }
13844 + spin_unlock(&tc_list_lock);
13845 +}
13846 +EXPORT_SYMBOL_GPL(atmel_tc_free);
13847 +
13848 +static int __init tc_probe(struct platform_device *pdev)
13849 +{
13850 + struct atmel_tc *tc;
13851 + struct clk *clk;
13852 + int irq;
13853 +
13854 + if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
13855 + return -EINVAL;
13856 +
13857 + irq = platform_get_irq(pdev, 0);
13858 + if (irq < 0)
13859 + return -EINVAL;
13860 +
13861 + tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
13862 + if (!tc)
13863 + return -ENOMEM;
13864 +
13865 + tc->pdev = pdev;
13866 +
13867 + clk = clk_get(&pdev->dev, "t0_clk");
13868 + if (IS_ERR(clk)) {
13869 + kfree(tc);
13870 + return -EINVAL;
13871 + }
13872 +
13873 + tc->clk[0] = clk;
13874 + tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
13875 + if (IS_ERR(tc->clk[1]))
13876 + tc->clk[1] = clk;
13877 + tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
13878 + if (IS_ERR(tc->clk[2]))
13879 + tc->clk[2] = clk;
13880 +
13881 + tc->irq[0] = irq;
13882 + tc->irq[1] = platform_get_irq(pdev, 1);
13883 + if (tc->irq[1] < 0)
13884 + tc->irq[1] = irq;
13885 + tc->irq[2] = platform_get_irq(pdev, 2);
13886 + if (tc->irq[2] < 0)
13887 + tc->irq[2] = irq;
13888 +
13889 + spin_lock(&tc_list_lock);
13890 + list_add_tail(&tc->node, &tc_list);
13891 + spin_unlock(&tc_list_lock);
13892 +
13893 + return 0;
13894 +}
13895 +
13896 +static struct platform_driver tc_driver = {
13897 + .driver.name = "atmel_tcb",
13898 +};
13899 +
13900 +static int __init tc_init(void)
13901 +{
13902 + return platform_driver_probe(&tc_driver, tc_probe);
13903 +}
13904 +arch_initcall(tc_init);
13905 --- a/drivers/misc/Kconfig
13906 +++ b/drivers/misc/Kconfig
13907 @@ -13,6 +13,48 @@
13908
13909 if MISC_DEVICES
13910
13911 +config ATMEL_PWM
13912 + tristate "Atmel AT32/AT91 PWM support"
13913 + depends on AVR32 || ARCH_AT91
13914 + help
13915 + This option enables device driver support for the PWM channels
13916 + on certain Atmel prcoessors. Pulse Width Modulation is used for
13917 + purposes including software controlled power-efficent backlights
13918 + on LCD displays, motor control, and waveform generation.
13919 +
13920 +config ATMEL_TCLIB
13921 + bool "Atmel AT32/AT91 Timer/Counter Library"
13922 + depends on (AVR32 || ARCH_AT91)
13923 + help
13924 + Select this if you want a library to allocate the Timer/Counter
13925 + blocks found on many Atmel processors. This facilitates using
13926 + these blocks by different drivers despite processor differences.
13927 +
13928 +config ATMEL_TCB_CLKSRC
13929 + bool "TC Block Clocksource"
13930 + depends on ATMEL_TCLIB && GENERIC_TIME
13931 + default y
13932 + help
13933 + Select this to get a high precision clocksource based on a
13934 + TC block with a 5+ MHz base clock rate. Two timer channels
13935 + are combined to make a single 32-bit timer.
13936 +
13937 + When GENERIC_CLOCKEVENTS is defined, the third timer channel
13938 + may be used as a clock event device supporting oneshot mode
13939 + (delays of up to two seconds) based on the 32 KiHz clock.
13940 +
13941 +config ATMEL_TCB_CLKSRC_BLOCK
13942 + int
13943 + depends on ATMEL_TCB_CLKSRC
13944 + prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
13945 + default 0
13946 + range 0 1
13947 + help
13948 + Some chips provide more than one TC block, so you have the
13949 + choice of which one to use for the clock framework. The other
13950 + TC can be used for other purposes, such as PWM generation and
13951 + interval timing.
13952 +
13953 config IBM_ASM
13954 tristate "Device driver for IBM RSA service processor"
13955 depends on X86 && PCI && INPUT && EXPERIMENTAL
13956 --- a/drivers/misc/Makefile
13957 +++ b/drivers/misc/Makefile
13958 @@ -7,7 +7,9 @@
13959 obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
13960 obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
13961 obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
13962 +obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
13963 obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
13964 +obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
13965 obj-$(CONFIG_LKDTM) += lkdtm.o
13966 obj-$(CONFIG_TIFM_CORE) += tifm_core.o
13967 obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
13968 --- /dev/null
13969 +++ b/drivers/mmc/host/atmel-mci.c
13970 @@ -0,0 +1,1220 @@
13971 +/*
13972 + * Atmel MultiMedia Card Interface driver
13973 + *
13974 + * Copyright (C) 2004-2006 Atmel Corporation
13975 + *
13976 + * This program is free software; you can redistribute it and/or modify
13977 + * it under the terms of the GNU General Public License version 2 as
13978 + * published by the Free Software Foundation.
13979 + */
13980 +#include <linux/blkdev.h>
13981 +#include <linux/clk.h>
13982 +#include <linux/device.h>
13983 +#include <linux/dma-mapping.h>
13984 +#include <linux/init.h>
13985 +#include <linux/interrupt.h>
13986 +#include <linux/ioport.h>
13987 +#include <linux/module.h>
13988 +#include <linux/platform_device.h>
13989 +
13990 +#include <linux/mmc/host.h>
13991 +
13992 +#include <asm/dma-controller.h>
13993 +#include <asm/io.h>
13994 +#include <asm/arch/board.h>
13995 +#include <asm/arch/gpio.h>
13996 +
13997 +#include "atmel-mci.h"
13998 +
13999 +#define DRIVER_NAME "atmel_mci"
14000 +
14001 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
14002 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
14003 +
14004 +enum {
14005 + EVENT_CMD_COMPLETE = 0,
14006 + EVENT_DATA_COMPLETE,
14007 + EVENT_DATA_ERROR,
14008 + EVENT_STOP_SENT,
14009 + EVENT_STOP_COMPLETE,
14010 + EVENT_DMA_COMPLETE,
14011 + EVENT_DMA_ERROR,
14012 +};
14013 +
14014 +struct atmel_mci_dma {
14015 + struct dma_request_sg req;
14016 + unsigned short rx_periph_id;
14017 + unsigned short tx_periph_id;
14018 +};
14019 +
14020 +struct atmel_mci {
14021 + struct mmc_host *mmc;
14022 + void __iomem *regs;
14023 + struct atmel_mci_dma dma;
14024 +
14025 + struct mmc_request *mrq;
14026 + struct mmc_command *cmd;
14027 + struct mmc_data *data;
14028 +
14029 + u32 cmd_status;
14030 + u32 data_status;
14031 + u32 stop_status;
14032 + u32 stop_cmdr;
14033 +
14034 + struct tasklet_struct tasklet;
14035 + unsigned long pending_events;
14036 + unsigned long completed_events;
14037 +
14038 + int present;
14039 + int detect_pin;
14040 + int wp_pin;
14041 +
14042 + /* For detect pin debouncing */
14043 + struct timer_list detect_timer;
14044 +
14045 + unsigned long bus_hz;
14046 + unsigned long mapbase;
14047 + struct clk *mck;
14048 + struct platform_device *pdev;
14049 +
14050 +#ifdef CONFIG_DEBUG_FS
14051 + struct dentry *debugfs_root;
14052 + struct dentry *debugfs_regs;
14053 + struct dentry *debugfs_req;
14054 + struct dentry *debugfs_pending_events;
14055 + struct dentry *debugfs_completed_events;
14056 +#endif
14057 +};
14058 +
14059 +/* Those printks take an awful lot of time... */
14060 +#ifndef DEBUG
14061 +static unsigned int fmax = 15000000U;
14062 +#else
14063 +static unsigned int fmax = 1000000U;
14064 +#endif
14065 +module_param(fmax, uint, 0444);
14066 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
14067 +
14068 +/* Test bit macros for completed events */
14069 +#define mci_cmd_is_complete(host) \
14070 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
14071 +#define mci_data_is_complete(host) \
14072 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
14073 +#define mci_data_error_is_complete(host) \
14074 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
14075 +#define mci_stop_sent_is_complete(host) \
14076 + test_bit(EVENT_STOP_SENT, &host->completed_events)
14077 +#define mci_stop_is_complete(host) \
14078 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
14079 +#define mci_dma_is_complete(host) \
14080 + test_bit(EVENT_DMA_COMPLETE, &host->completed_events)
14081 +#define mci_dma_error_is_complete(host) \
14082 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
14083 +
14084 +/* Test and clear bit macros for pending events */
14085 +#define mci_clear_cmd_is_pending(host) \
14086 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
14087 +#define mci_clear_data_is_pending(host) \
14088 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
14089 +#define mci_clear_data_error_is_pending(host) \
14090 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
14091 +#define mci_clear_stop_sent_is_pending(host) \
14092 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
14093 +#define mci_clear_stop_is_pending(host) \
14094 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
14095 +#define mci_clear_dma_error_is_pending(host) \
14096 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
14097 +
14098 +/* Test and set bit macros for completed events */
14099 +#define mci_set_cmd_is_completed(host) \
14100 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
14101 +#define mci_set_data_is_completed(host) \
14102 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
14103 +#define mci_set_data_error_is_completed(host) \
14104 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
14105 +#define mci_set_stop_sent_is_completed(host) \
14106 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
14107 +#define mci_set_stop_is_completed(host) \
14108 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
14109 +#define mci_set_dma_error_is_completed(host) \
14110 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
14111 +
14112 +/* Set bit macros for completed events */
14113 +#define mci_set_cmd_complete(host) \
14114 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
14115 +#define mci_set_data_complete(host) \
14116 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
14117 +#define mci_set_data_error_complete(host) \
14118 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
14119 +#define mci_set_stop_sent_complete(host) \
14120 + set_bit(EVENT_STOP_SENT, &host->completed_events)
14121 +#define mci_set_stop_complete(host) \
14122 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
14123 +#define mci_set_dma_complete(host) \
14124 + set_bit(EVENT_DMA_COMPLETE, &host->completed_events)
14125 +#define mci_set_dma_error_complete(host) \
14126 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
14127 +
14128 +/* Set bit macros for pending events */
14129 +#define mci_set_cmd_pending(host) \
14130 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
14131 +#define mci_set_data_pending(host) \
14132 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
14133 +#define mci_set_data_error_pending(host) \
14134 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
14135 +#define mci_set_stop_sent_pending(host) \
14136 + set_bit(EVENT_STOP_SENT, &host->pending_events)
14137 +#define mci_set_stop_pending(host) \
14138 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
14139 +#define mci_set_dma_error_pending(host) \
14140 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
14141 +
14142 +/* Clear bit macros for pending events */
14143 +#define mci_clear_cmd_pending(host) \
14144 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
14145 +#define mci_clear_data_pending(host) \
14146 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
14147 +#define mci_clear_data_error_pending(host) \
14148 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
14149 +#define mci_clear_stop_sent_pending(host) \
14150 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
14151 +#define mci_clear_stop_pending(host) \
14152 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
14153 +#define mci_clear_dma_error_pending(host) \
14154 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
14155 +
14156 +
14157 +#ifdef CONFIG_DEBUG_FS
14158 +#include <linux/debugfs.h>
14159 +
14160 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
14161 +
14162 +struct req_dbg_data {
14163 + unsigned int nbytes;
14164 + char str[DBG_REQ_BUF_SIZE];
14165 +};
14166 +
14167 +static int req_dbg_open(struct inode *inode, struct file *file)
14168 +{
14169 + struct atmel_mci *host;
14170 + struct mmc_request *mrq;
14171 + struct mmc_command *cmd, *stop;
14172 + struct mmc_data *data;
14173 + struct req_dbg_data *priv;
14174 + char *str;
14175 + unsigned long n = 0;
14176 +
14177 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
14178 + if (!priv)
14179 + return -ENOMEM;
14180 + str = priv->str;
14181 +
14182 + mutex_lock(&inode->i_mutex);
14183 + host = inode->i_private;
14184 +
14185 + spin_lock_irq(&host->mmc->lock);
14186 + mrq = host->mrq;
14187 + if (mrq) {
14188 + cmd = mrq->cmd;
14189 + data = mrq->data;
14190 + stop = mrq->stop;
14191 + n = snprintf(str, DBG_REQ_BUF_SIZE,
14192 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
14193 + cmd->opcode, cmd->arg, cmd->flags,
14194 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
14195 + cmd->resp[3], cmd->error);
14196 + if (n < DBG_REQ_BUF_SIZE && data)
14197 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
14198 + "DATA %u * %u (%u) %x (err %u)\n",
14199 + data->blocks, data->blksz,
14200 + data->bytes_xfered, data->flags,
14201 + data->error);
14202 + if (n < DBG_REQ_BUF_SIZE && stop)
14203 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
14204 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
14205 + stop->opcode, stop->arg, stop->flags,
14206 + stop->resp[0], stop->resp[1],
14207 + stop->resp[2], stop->resp[3],
14208 + stop->error);
14209 + }
14210 + spin_unlock_irq(&host->mmc->lock);
14211 + mutex_unlock(&inode->i_mutex);
14212 +
14213 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
14214 + file->private_data = priv;
14215 +
14216 + return 0;
14217 +}
14218 +
14219 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
14220 + size_t nbytes, loff_t *ppos)
14221 +{
14222 + struct req_dbg_data *priv = file->private_data;
14223 +
14224 + return simple_read_from_buffer(buf, nbytes, ppos,
14225 + priv->str, priv->nbytes);
14226 +}
14227 +
14228 +static int req_dbg_release(struct inode *inode, struct file *file)
14229 +{
14230 + kfree(file->private_data);
14231 + return 0;
14232 +}
14233 +
14234 +static const struct file_operations req_dbg_fops = {
14235 + .owner = THIS_MODULE,
14236 + .open = req_dbg_open,
14237 + .llseek = no_llseek,
14238 + .read = req_dbg_read,
14239 + .release = req_dbg_release,
14240 +};
14241 +
14242 +static int regs_dbg_open(struct inode *inode, struct file *file)
14243 +{
14244 + struct atmel_mci *host;
14245 + unsigned int i;
14246 + u32 *data;
14247 + int ret = -ENOMEM;
14248 +
14249 + mutex_lock(&inode->i_mutex);
14250 + host = inode->i_private;
14251 + data = kmalloc(inode->i_size, GFP_KERNEL);
14252 + if (!data)
14253 + goto out;
14254 +
14255 + spin_lock_irq(&host->mmc->lock);
14256 + for (i = 0; i < inode->i_size / 4; i++)
14257 + data[i] = __raw_readl(host->regs + i * 4);
14258 + spin_unlock_irq(&host->mmc->lock);
14259 +
14260 + file->private_data = data;
14261 + ret = 0;
14262 +
14263 +out:
14264 + mutex_unlock(&inode->i_mutex);
14265 +
14266 + return ret;
14267 +}
14268 +
14269 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
14270 + size_t nbytes, loff_t *ppos)
14271 +{
14272 + struct inode *inode = file->f_dentry->d_inode;
14273 + int ret;
14274 +
14275 + mutex_lock(&inode->i_mutex);
14276 + ret = simple_read_from_buffer(buf, nbytes, ppos,
14277 + file->private_data,
14278 + file->f_dentry->d_inode->i_size);
14279 + mutex_unlock(&inode->i_mutex);
14280 +
14281 + return ret;
14282 +}
14283 +
14284 +static int regs_dbg_release(struct inode *inode, struct file *file)
14285 +{
14286 + kfree(file->private_data);
14287 + return 0;
14288 +}
14289 +
14290 +static const struct file_operations regs_dbg_fops = {
14291 + .owner = THIS_MODULE,
14292 + .open = regs_dbg_open,
14293 + .llseek = generic_file_llseek,
14294 + .read = regs_dbg_read,
14295 + .release = regs_dbg_release,
14296 +};
14297 +
14298 +static void atmci_init_debugfs(struct atmel_mci *host)
14299 +{
14300 + struct mmc_host *mmc;
14301 + struct dentry *root, *regs;
14302 + struct resource *res;
14303 +
14304 + mmc = host->mmc;
14305 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
14306 + if (IS_ERR(root) || !root)
14307 + goto err_root;
14308 + host->debugfs_root = root;
14309 +
14310 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
14311 + if (!regs)
14312 + goto err_regs;
14313 +
14314 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
14315 + regs->d_inode->i_size = res->end - res->start + 1;
14316 + host->debugfs_regs = regs;
14317 +
14318 + host->debugfs_req = debugfs_create_file("req", 0400, root,
14319 + host, &req_dbg_fops);
14320 + if (!host->debugfs_req)
14321 + goto err_req;
14322 +
14323 + host->debugfs_pending_events
14324 + = debugfs_create_u32("pending_events", 0400, root,
14325 + (u32 *)&host->pending_events);
14326 + if (!host->debugfs_pending_events)
14327 + goto err_pending_events;
14328 +
14329 + host->debugfs_completed_events
14330 + = debugfs_create_u32("completed_events", 0400, root,
14331 + (u32 *)&host->completed_events);
14332 + if (!host->debugfs_completed_events)
14333 + goto err_completed_events;
14334 +
14335 + return;
14336 +
14337 +err_completed_events:
14338 + debugfs_remove(host->debugfs_pending_events);
14339 +err_pending_events:
14340 + debugfs_remove(host->debugfs_req);
14341 +err_req:
14342 + debugfs_remove(host->debugfs_regs);
14343 +err_regs:
14344 + debugfs_remove(host->debugfs_root);
14345 +err_root:
14346 + host->debugfs_root = NULL;
14347 + dev_err(&host->pdev->dev,
14348 + "failed to initialize debugfs for %s\n",
14349 + mmc_hostname(mmc));
14350 +}
14351 +
14352 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
14353 +{
14354 + if (host->debugfs_root) {
14355 + debugfs_remove(host->debugfs_completed_events);
14356 + debugfs_remove(host->debugfs_pending_events);
14357 + debugfs_remove(host->debugfs_req);
14358 + debugfs_remove(host->debugfs_regs);
14359 + debugfs_remove(host->debugfs_root);
14360 + host->debugfs_root = NULL;
14361 + }
14362 +}
14363 +#else
14364 +static inline void atmci_init_debugfs(struct atmel_mci *host)
14365 +{
14366 +
14367 +}
14368 +
14369 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
14370 +{
14371 +
14372 +}
14373 +#endif /* CONFIG_DEBUG_FS */
14374 +
14375 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
14376 + unsigned int ns)
14377 +{
14378 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
14379 +}
14380 +
14381 +static void atmci_set_timeout(struct atmel_mci *host,
14382 + struct mmc_data *data)
14383 +{
14384 + static unsigned dtomul_to_shift[] = {
14385 + 0, 4, 7, 8, 10, 12, 16, 20
14386 + };
14387 + unsigned timeout;
14388 + unsigned dtocyc, dtomul;
14389 +
14390 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
14391 +
14392 + for (dtomul = 0; dtomul < 8; dtomul++) {
14393 + unsigned shift = dtomul_to_shift[dtomul];
14394 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
14395 + if (dtocyc < 15)
14396 + break;
14397 + }
14398 +
14399 + if (dtomul >= 8) {
14400 + dtomul = 7;
14401 + dtocyc = 15;
14402 + }
14403 +
14404 + dev_dbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
14405 + dtocyc << dtomul_to_shift[dtomul]);
14406 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
14407 + | MCI_BF(DTOCYC, dtocyc)));
14408 +}
14409 +
14410 +/*
14411 + * Return mask with command flags to be enabled for this command.
14412 + */
14413 +static u32 atmci_prepare_command(struct mmc_host *mmc,
14414 + struct mmc_command *cmd)
14415 +{
14416 + u32 cmdr;
14417 +
14418 + cmd->error = 0;
14419 +
14420 + cmdr = MCI_BF(CMDNB, cmd->opcode);
14421 +
14422 + if (cmd->flags & MMC_RSP_PRESENT) {
14423 + if (cmd->flags & MMC_RSP_136)
14424 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
14425 + else
14426 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
14427 + }
14428 +
14429 + /*
14430 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
14431 + * it's too difficult to determine whether this is an ACMD or
14432 + * not. Better make it 64.
14433 + */
14434 + cmdr |= MCI_BIT(MAXLAT);
14435 +
14436 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
14437 + cmdr |= MCI_BIT(OPDCMD);
14438 +
14439 + dev_dbg(&mmc->class_dev,
14440 + "cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
14441 + cmd->opcode, cmd->arg, cmd->flags, (unsigned long)cmdr);
14442 +
14443 + return cmdr;
14444 +}
14445 +
14446 +static void atmci_start_command(struct atmel_mci *host,
14447 + struct mmc_command *cmd,
14448 + u32 cmd_flags)
14449 +{
14450 + WARN_ON(host->cmd);
14451 + host->cmd = cmd;
14452 +
14453 + mci_writel(host, ARGR, cmd->arg);
14454 + mci_writel(host, CMDR, cmd_flags);
14455 +
14456 + if (cmd->data)
14457 + dma_start_request(host->dma.req.req.dmac,
14458 + host->dma.req.req.channel);
14459 +}
14460 +
14461 +/*
14462 + * Returns a mask of flags to be set in the command register when the
14463 + * command to start the transfer is to be sent.
14464 + */
14465 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
14466 +{
14467 + struct atmel_mci *host = mmc_priv(mmc);
14468 + u32 cmd_flags;
14469 +
14470 + WARN_ON(host->data);
14471 + host->data = data;
14472 +
14473 + atmci_set_timeout(host, data);
14474 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
14475 + | MCI_BF(BLKLEN, data->blksz)));
14476 + host->dma.req.block_size = data->blksz;
14477 + host->dma.req.nr_blocks = data->blocks;
14478 +
14479 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
14480 + if (data->flags & MMC_DATA_STREAM)
14481 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
14482 + else if (data->blocks > 1)
14483 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
14484 + else
14485 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
14486 +
14487 + if (data->flags & MMC_DATA_READ) {
14488 + cmd_flags |= MCI_BIT(TRDIR);
14489 + host->dma.req.nr_sg
14490 + = dma_map_sg(&host->pdev->dev, data->sg,
14491 + data->sg_len, DMA_FROM_DEVICE);
14492 + host->dma.req.periph_id = host->dma.rx_periph_id;
14493 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
14494 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
14495 + } else {
14496 + host->dma.req.nr_sg
14497 + = dma_map_sg(&host->pdev->dev, data->sg,
14498 + data->sg_len, DMA_TO_DEVICE);
14499 + host->dma.req.periph_id = host->dma.tx_periph_id;
14500 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
14501 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
14502 + }
14503 + host->dma.req.sg = data->sg;
14504 +
14505 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
14506 +
14507 + return cmd_flags;
14508 +}
14509 +
14510 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
14511 +{
14512 + struct atmel_mci *host = mmc_priv(mmc);
14513 + struct mmc_data *data = mrq->data;
14514 + u32 iflags;
14515 + u32 cmdflags = 0;
14516 +
14517 + iflags = mci_readl(host, IMR);
14518 + if (iflags)
14519 + dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
14520 + mci_readl(host, IMR));
14521 +
14522 + WARN_ON(host->mrq != NULL);
14523 +
14524 + /*
14525 + * We may "know" the card is gone even though there's still an
14526 + * electrical connection. If so, we really need to communicate
14527 + * this to the MMC core since there won't be any more
14528 + * interrupts as the card is completely removed. Otherwise,
14529 + * the MMC core might believe the card is still there even
14530 + * though the card was just removed very slowly.
14531 + */
14532 + if (!host->present) {
14533 + mrq->cmd->error = -ENOMEDIUM;
14534 + mmc_request_done(mmc, mrq);
14535 + return;
14536 + }
14537 +
14538 + host->mrq = mrq;
14539 + host->pending_events = 0;
14540 + host->completed_events = 0;
14541 +
14542 + iflags = MCI_BIT(CMDRDY);
14543 + cmdflags = atmci_prepare_command(mmc, mrq->cmd);
14544 +
14545 + if (mrq->stop) {
14546 + WARN_ON(!data);
14547 +
14548 + host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
14549 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
14550 + if (!(data->flags & MMC_DATA_WRITE))
14551 + host->stop_cmdr |= MCI_BIT(TRDIR);
14552 + if (data->flags & MMC_DATA_STREAM)
14553 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
14554 + else
14555 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
14556 + }
14557 + if (data) {
14558 + cmdflags |= atmci_prepare_data(mmc, data);
14559 + iflags |= MCI_DATA_ERROR_FLAGS;
14560 + }
14561 +
14562 + atmci_start_command(host, mrq->cmd, cmdflags);
14563 + mci_writel(host, IER, iflags);
14564 +}
14565 +
14566 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
14567 +{
14568 + struct atmel_mci *host = mmc_priv(mmc);
14569 + u32 mr;
14570 +
14571 + if (ios->clock) {
14572 + u32 clkdiv;
14573 +
14574 + /* Set clock rate */
14575 + clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
14576 + if (clkdiv > 255) {
14577 + dev_warn(&mmc->class_dev,
14578 + "clock %u too slow; using %lu\n",
14579 + ios->clock, host->bus_hz / (2 * 256));
14580 + clkdiv = 255;
14581 + }
14582 +
14583 + mr = mci_readl(host, MR);
14584 + mr = MCI_BFINS(CLKDIV, clkdiv, mr)
14585 + | MCI_BIT(WRPROOF) | MCI_BIT(RDPROOF);
14586 + mci_writel(host, MR, mr);
14587 +
14588 + /* Enable the MCI controller */
14589 + mci_writel(host, CR, MCI_BIT(MCIEN));
14590 + } else {
14591 + /* Disable the MCI controller */
14592 + mci_writel(host, CR, MCI_BIT(MCIDIS));
14593 + }
14594 +
14595 + switch (ios->bus_width) {
14596 + case MMC_BUS_WIDTH_1:
14597 + mci_writel(host, SDCR, 0);
14598 + break;
14599 + case MMC_BUS_WIDTH_4:
14600 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
14601 + break;
14602 + }
14603 +
14604 + switch (ios->power_mode) {
14605 + case MMC_POWER_ON:
14606 + /* Send init sequence (74 clock cycles) */
14607 + mci_writel(host, IDR, ~0UL);
14608 + mci_writel(host, CMDR, MCI_BF(SPCMD, MCI_SPCMD_INIT_CMD));
14609 + while (!(mci_readl(host, SR) & MCI_BIT(CMDRDY)))
14610 + cpu_relax();
14611 + break;
14612 + default:
14613 + /*
14614 + * TODO: None of the currently available AVR32-based
14615 + * boards allow MMC power to be turned off. Implement
14616 + * power control when this can be tested properly.
14617 + */
14618 + break;
14619 + }
14620 +}
14621 +
14622 +static int atmci_get_ro(struct mmc_host *mmc)
14623 +{
14624 + int read_only = 0;
14625 + struct atmel_mci *host = mmc_priv(mmc);
14626 +
14627 + if (host->wp_pin >= 0) {
14628 + read_only = gpio_get_value(host->wp_pin);
14629 + dev_dbg(&mmc->class_dev, "card is %s\n",
14630 + read_only ? "read-only" : "read-write");
14631 + } else {
14632 + dev_dbg(&mmc->class_dev,
14633 + "no pin for checking read-only switch."
14634 + " Assuming write-enable.\n");
14635 + }
14636 +
14637 + return read_only;
14638 +}
14639 +
14640 +static struct mmc_host_ops atmci_ops = {
14641 + .request = atmci_request,
14642 + .set_ios = atmci_set_ios,
14643 + .get_ro = atmci_get_ro,
14644 +};
14645 +
14646 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
14647 +{
14648 + struct atmel_mci *host = mmc_priv(mmc);
14649 +
14650 + WARN_ON(host->cmd || host->data);
14651 + host->mrq = NULL;
14652 +
14653 + mmc_request_done(mmc, mrq);
14654 +}
14655 +
14656 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
14657 + u32 flags)
14658 +{
14659 + struct atmel_mci *host = mmc_priv(mmc);
14660 +
14661 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
14662 + mci_writel(host, IER, MCI_BIT(CMDRDY));
14663 +}
14664 +
14665 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
14666 +{
14667 + host->data = NULL;
14668 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
14669 + ((data->flags & MMC_DATA_WRITE)
14670 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
14671 +
14672 + /*
14673 + * Data might complete before command for very short transfers
14674 + * (like READ_SCR)
14675 + */
14676 + if (mci_cmd_is_complete(host)
14677 + && (!data->stop || mci_stop_is_complete(host)))
14678 + atmci_request_end(host->mmc, data->mrq);
14679 +}
14680 +
14681 +static void atmci_command_complete(struct atmel_mci *host,
14682 + struct mmc_command *cmd, u32 status)
14683 +{
14684 + if (status & MCI_BIT(RTOE))
14685 + cmd->error = -ETIMEDOUT;
14686 + else if ((cmd->flags & MMC_RSP_CRC)
14687 + && (status & MCI_BIT(RCRCE)))
14688 + cmd->error = -EILSEQ;
14689 + else if (status & (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | MCI_BIT(RENDE)))
14690 + cmd->error = -EIO;
14691 +
14692 + if (cmd->error) {
14693 + dev_dbg(&host->mmc->class_dev,
14694 + "command error: op=0x%x status=0x%08x\n",
14695 + cmd->opcode, status);
14696 +
14697 + if (cmd->data) {
14698 + dma_stop_request(host->dma.req.req.dmac,
14699 + host->dma.req.req.channel);
14700 + mci_writel(host, IDR, MCI_BIT(NOTBUSY)
14701 + | MCI_DATA_ERROR_FLAGS);
14702 + host->data = NULL;
14703 + }
14704 + }
14705 +}
14706 +
14707 +static void atmci_detect_change(unsigned long data)
14708 +{
14709 + struct atmel_mci *host = (struct atmel_mci *)data;
14710 + struct mmc_request *mrq = host->mrq;
14711 + int present;
14712 +
14713 + /*
14714 + * atmci_remove() sets detect_pin to -1 before freeing the
14715 + * interrupt. We must not re-enable the interrupt if it has
14716 + * been freed.
14717 + */
14718 + smp_rmb();
14719 + if (host->detect_pin < 0)
14720 + return;
14721 +
14722 + enable_irq(gpio_to_irq(host->detect_pin));
14723 + present = !gpio_get_value(host->detect_pin);
14724 +
14725 + dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
14726 + present, host->present);
14727 +
14728 + if (present != host->present) {
14729 + dev_dbg(&host->mmc->class_dev, "card %s\n",
14730 + present ? "inserted" : "removed");
14731 + host->present = present;
14732 +
14733 + /* Reset controller if card is gone */
14734 + if (!present) {
14735 + mci_writel(host, CR, MCI_BIT(SWRST));
14736 + mci_writel(host, IDR, ~0UL);
14737 + mci_writel(host, CR, MCI_BIT(MCIEN));
14738 + }
14739 +
14740 + /* Clean up queue if present */
14741 + if (mrq) {
14742 + if (!mci_cmd_is_complete(host))
14743 + mrq->cmd->error = -ENOMEDIUM;
14744 + if (mrq->data && !mci_data_is_complete(host)
14745 + && !mci_data_error_is_complete(host)) {
14746 + dma_stop_request(host->dma.req.req.dmac,
14747 + host->dma.req.req.channel);
14748 + host->data->error = -ENOMEDIUM;
14749 + atmci_data_complete(host, host->data);
14750 + }
14751 + if (mrq->stop && !mci_stop_is_complete(host))
14752 + mrq->stop->error = -ENOMEDIUM;
14753 +
14754 + host->cmd = NULL;
14755 + atmci_request_end(host->mmc, mrq);
14756 + }
14757 +
14758 + mmc_detect_change(host->mmc, 0);
14759 + }
14760 +}
14761 +
14762 +static void atmci_tasklet_func(unsigned long priv)
14763 +{
14764 + struct mmc_host *mmc = (struct mmc_host *)priv;
14765 + struct atmel_mci *host = mmc_priv(mmc);
14766 + struct mmc_request *mrq = host->mrq;
14767 + struct mmc_data *data = host->data;
14768 +
14769 + dev_vdbg(&mmc->class_dev,
14770 + "tasklet: pending/completed/mask %lx/%lx/%x\n",
14771 + host->pending_events, host->completed_events,
14772 + mci_readl(host, IMR));
14773 +
14774 + if (mci_clear_cmd_is_pending(host)) {
14775 + mci_set_cmd_complete(host);
14776 + atmci_command_complete(host, mrq->cmd, host->cmd_status);
14777 + if (!host->data || mci_data_is_complete(host)
14778 + || mci_data_error_is_complete(host))
14779 + atmci_request_end(mmc, mrq);
14780 + }
14781 + if (mci_clear_stop_is_pending(host)) {
14782 + mci_set_stop_complete(host);
14783 + atmci_command_complete(host, mrq->stop, host->stop_status);
14784 + if (mci_data_is_complete(host)
14785 + || mci_data_error_is_complete(host))
14786 + atmci_request_end(mmc, mrq);
14787 + }
14788 + if (mci_clear_dma_error_is_pending(host)) {
14789 + mci_set_dma_error_complete(host);
14790 + mci_clear_data_pending(host);
14791 +
14792 + /* DMA controller got bus error => invalid address */
14793 + data->error = -EIO;
14794 +
14795 + dev_dbg(&mmc->class_dev, "dma error after %u bytes xfered\n",
14796 + host->data->bytes_xfered);
14797 +
14798 + if (data->stop
14799 + && !mci_set_stop_sent_is_completed(host))
14800 + /* TODO: Check if card is still present */
14801 + send_stop_cmd(host->mmc, data, 0);
14802 +
14803 + atmci_data_complete(host, data);
14804 + }
14805 + if (mci_clear_data_error_is_pending(host)) {
14806 + u32 status = host->data_status;
14807 +
14808 + mci_set_data_error_complete(host);
14809 + mci_clear_data_pending(host);
14810 +
14811 + dma_stop_request(host->dma.req.req.dmac,
14812 + host->dma.req.req.channel);
14813 +
14814 + if (status & MCI_BIT(DCRCE)) {
14815 + dev_dbg(&mmc->class_dev, "data CRC error\n");
14816 + data->error = -EILSEQ;
14817 + } else if (status & MCI_BIT(DTOE)) {
14818 + dev_dbg(&mmc->class_dev, "data timeout error\n");
14819 + data->error = -ETIMEDOUT;
14820 + } else {
14821 + dev_dbg(&mmc->class_dev, "data FIFO error\n");
14822 + data->error = -EIO;
14823 + }
14824 + dev_dbg(&mmc->class_dev, "bytes xfered: %u\n",
14825 + data->bytes_xfered);
14826 +
14827 + if (data->stop
14828 + && !mci_set_stop_sent_is_completed(host))
14829 + /* TODO: Check if card is still present */
14830 + send_stop_cmd(host->mmc, data, 0);
14831 +
14832 + atmci_data_complete(host, data);
14833 + }
14834 + if (mci_clear_data_is_pending(host)) {
14835 + mci_set_data_complete(host);
14836 + data->bytes_xfered = data->blocks * data->blksz;
14837 + atmci_data_complete(host, data);
14838 + }
14839 +}
14840 +
14841 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
14842 +{
14843 + struct atmel_mci *host = mmc_priv(mmc);
14844 + struct mmc_command *cmd = host->cmd;
14845 +
14846 + /*
14847 + * Read the response now so that we're free to send a new
14848 + * command immediately.
14849 + */
14850 + cmd->resp[0] = mci_readl(host, RSPR);
14851 + cmd->resp[1] = mci_readl(host, RSPR);
14852 + cmd->resp[2] = mci_readl(host, RSPR);
14853 + cmd->resp[3] = mci_readl(host, RSPR);
14854 +
14855 + mci_writel(host, IDR, MCI_BIT(CMDRDY));
14856 + host->cmd = NULL;
14857 +
14858 + if (mci_stop_sent_is_complete(host)) {
14859 + host->stop_status = status;
14860 + mci_set_stop_pending(host);
14861 + } else {
14862 + struct mmc_request *mrq = host->mrq;
14863 +
14864 + if (mrq->stop && mci_dma_is_complete(host)
14865 + && !mci_set_stop_sent_is_completed(host))
14866 + send_stop_cmd(host->mmc, mrq->data, 0);
14867 + host->cmd_status = status;
14868 + mci_set_cmd_pending(host);
14869 + }
14870 +
14871 + tasklet_schedule(&host->tasklet);
14872 +}
14873 +
14874 +static void atmci_xfer_complete(struct dma_request *_req)
14875 +{
14876 + struct dma_request_sg *req = to_dma_request_sg(_req);
14877 + struct atmel_mci_dma *dma;
14878 + struct atmel_mci *host;
14879 + struct mmc_data *data;
14880 +
14881 + dma = container_of(req, struct atmel_mci_dma, req);
14882 + host = container_of(dma, struct atmel_mci, dma);
14883 + data = host->data;
14884 +
14885 + /*
14886 + * This callback may be called before we see the CMDRDY
14887 + * interrupt under heavy irq load (possibly caused by other
14888 + * drivers) or when interrupts are disabled for a long time.
14889 + */
14890 + mci_set_dma_complete(host);
14891 + if (data->stop && mci_cmd_is_complete(host)
14892 + && !mci_set_stop_sent_is_completed(host))
14893 + send_stop_cmd(host->mmc, data, 0);
14894 +
14895 + /*
14896 + * Regardless of what the documentation says, we have to wait
14897 + * for NOTBUSY even after block read operations.
14898 + *
14899 + * When the DMA transfer is complete, the controller may still
14900 + * be reading the CRC from the card, i.e. the data transfer is
14901 + * still in progress and we haven't seen all the potential
14902 + * error bits yet.
14903 + */
14904 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
14905 +}
14906 +
14907 +static void atmci_dma_error(struct dma_request *_req)
14908 +{
14909 + struct dma_request_sg *req = to_dma_request_sg(_req);
14910 + struct atmel_mci_dma *dma;
14911 + struct atmel_mci *host;
14912 +
14913 + dma = container_of(req, struct atmel_mci_dma, req);
14914 + host = container_of(dma, struct atmel_mci, dma);
14915 +
14916 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
14917 + | MCI_DATA_ERROR_FLAGS));
14918 +
14919 + mci_set_dma_error_pending(host);
14920 + tasklet_schedule(&host->tasklet);
14921 +}
14922 +
14923 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
14924 +{
14925 + struct mmc_host *mmc = dev_id;
14926 + struct atmel_mci *host = mmc_priv(mmc);
14927 + u32 status, mask, pending;
14928 +
14929 + spin_lock(&mmc->lock);
14930 +
14931 + status = mci_readl(host, SR);
14932 + mask = mci_readl(host, IMR);
14933 + pending = status & mask;
14934 +
14935 + do {
14936 + if (pending & MCI_DATA_ERROR_FLAGS) {
14937 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
14938 + | MCI_DATA_ERROR_FLAGS));
14939 + host->data_status = status;
14940 + mci_set_data_error_pending(host);
14941 + tasklet_schedule(&host->tasklet);
14942 + break;
14943 + }
14944 + if (pending & MCI_BIT(CMDRDY))
14945 + atmci_cmd_interrupt(mmc, status);
14946 + if (pending & MCI_BIT(NOTBUSY)) {
14947 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
14948 + | MCI_DATA_ERROR_FLAGS));
14949 + mci_set_data_pending(host);
14950 + tasklet_schedule(&host->tasklet);
14951 + }
14952 +
14953 + status = mci_readl(host, SR);
14954 + mask = mci_readl(host, IMR);
14955 + pending = status & mask;
14956 + } while (pending);
14957 +
14958 + spin_unlock(&mmc->lock);
14959 +
14960 + return IRQ_HANDLED;
14961 +}
14962 +
14963 +static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
14964 +{
14965 + struct mmc_host *mmc = dev_id;
14966 + struct atmel_mci *host = mmc_priv(mmc);
14967 +
14968 + /*
14969 + * Disable interrupts until the pin has stabilized and check
14970 + * the state then. Use mod_timer() since we may be in the
14971 + * middle of the timer routine when this interrupt triggers.
14972 + */
14973 + disable_irq_nosync(irq);
14974 + mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
14975 +
14976 + return IRQ_HANDLED;
14977 +}
14978 +
14979 +static int __devinit atmci_probe(struct platform_device *pdev)
14980 +{
14981 + struct mci_platform_data *board;
14982 + struct atmel_mci *host;
14983 + struct mmc_host *mmc;
14984 + struct resource *regs;
14985 + int irq;
14986 + int ret;
14987 +
14988 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
14989 + if (!regs)
14990 + return -ENXIO;
14991 + irq = platform_get_irq(pdev, 0);
14992 + if (irq < 0)
14993 + return irq;
14994 +
14995 + board = pdev->dev.platform_data;
14996 +
14997 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
14998 + if (!mmc)
14999 + return -ENOMEM;
15000 +
15001 + host = mmc_priv(mmc);
15002 + host->pdev = pdev;
15003 + host->mmc = mmc;
15004 + if (board) {
15005 + host->detect_pin = board->detect_pin;
15006 + host->wp_pin = board->wp_pin;
15007 + } else {
15008 + host->detect_pin = -1;
15009 + host->wp_pin = -1;
15010 + }
15011 +
15012 + host->mck = clk_get(&pdev->dev, "mci_clk");
15013 + if (IS_ERR(host->mck)) {
15014 + ret = PTR_ERR(host->mck);
15015 + goto out_free_host;
15016 + }
15017 + clk_enable(host->mck);
15018 +
15019 + ret = -ENOMEM;
15020 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
15021 + if (!host->regs)
15022 + goto out_disable_clk;
15023 +
15024 + host->bus_hz = clk_get_rate(host->mck);
15025 + host->mapbase = regs->start;
15026 +
15027 + mmc->ops = &atmci_ops;
15028 + mmc->f_min = (host->bus_hz + 511) / 512;
15029 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
15030 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
15031 + mmc->caps |= MMC_CAP_4_BIT_DATA;
15032 +
15033 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
15034 +
15035 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
15036 + if (ret)
15037 + goto out_unmap;
15038 +
15039 + /* Assume card is present if we don't have a detect pin */
15040 + host->present = 1;
15041 + if (host->detect_pin >= 0) {
15042 + if (gpio_request(host->detect_pin, "mmc_detect")) {
15043 + dev_dbg(&mmc->class_dev, "no detect pin available\n");
15044 + host->detect_pin = -1;
15045 + } else {
15046 + host->present = !gpio_get_value(host->detect_pin);
15047 + }
15048 + }
15049 + if (host->wp_pin >= 0) {
15050 + if (gpio_request(host->wp_pin, "mmc_wp")) {
15051 + dev_dbg(&mmc->class_dev, "no WP pin available\n");
15052 + host->wp_pin = -1;
15053 + }
15054 + }
15055 +
15056 + /* TODO: Get this information from platform data */
15057 + ret = -ENOMEM;
15058 + host->dma.req.req.dmac = find_dma_controller(0);
15059 + if (!host->dma.req.req.dmac) {
15060 + dev_dbg(&mmc->class_dev, "no DMA controller available\n");
15061 + goto out_free_irq;
15062 + }
15063 + ret = dma_alloc_channel(host->dma.req.req.dmac);
15064 + if (ret < 0) {
15065 + dev_dbg(&mmc->class_dev, "unable to allocate DMA channel\n");
15066 + goto out_free_irq;
15067 + }
15068 + host->dma.req.req.channel = ret;
15069 + host->dma.req.width = DMA_WIDTH_32BIT;
15070 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
15071 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
15072 + host->dma.req.req.error = atmci_dma_error;
15073 + host->dma.rx_periph_id = 0;
15074 + host->dma.tx_periph_id = 1;
15075 +
15076 + mci_writel(host, CR, MCI_BIT(SWRST));
15077 + mci_writel(host, IDR, ~0UL);
15078 +
15079 + platform_set_drvdata(pdev, host);
15080 +
15081 + mmc_add_host(mmc);
15082 +
15083 + if (host->detect_pin >= 0) {
15084 + setup_timer(&host->detect_timer, atmci_detect_change,
15085 + (unsigned long)host);
15086 +
15087 + ret = request_irq(gpio_to_irq(host->detect_pin),
15088 + atmci_detect_interrupt,
15089 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
15090 + DRIVER_NAME, mmc);
15091 + if (ret) {
15092 + dev_dbg(&mmc->class_dev,
15093 + "could not request IRQ %d for detect pin\n",
15094 + gpio_to_irq(host->detect_pin));
15095 + gpio_free(host->detect_pin);
15096 + host->detect_pin = -1;
15097 + }
15098 + }
15099 +
15100 + dev_info(&mmc->class_dev, "Atmel MCI controller at 0x%08lx irq %d\n",
15101 + host->mapbase, irq);
15102 +
15103 + atmci_init_debugfs(host);
15104 +
15105 + return 0;
15106 +
15107 +out_free_irq:
15108 + if (host->detect_pin >= 0)
15109 + gpio_free(host->detect_pin);
15110 + if (host->wp_pin >= 0)
15111 + gpio_free(host->wp_pin);
15112 + free_irq(irq, mmc);
15113 +out_unmap:
15114 + iounmap(host->regs);
15115 +out_disable_clk:
15116 + clk_disable(host->mck);
15117 + clk_put(host->mck);
15118 +out_free_host:
15119 + mmc_free_host(mmc);
15120 + return ret;
15121 +}
15122 +
15123 +static int __devexit atmci_remove(struct platform_device *pdev)
15124 +{
15125 + struct atmel_mci *host = platform_get_drvdata(pdev);
15126 +
15127 + platform_set_drvdata(pdev, NULL);
15128 +
15129 + if (host) {
15130 + atmci_cleanup_debugfs(host);
15131 +
15132 + if (host->detect_pin >= 0) {
15133 + int pin = host->detect_pin;
15134 +
15135 + /* Make sure our timer doesn't enable the interrupt */
15136 + host->detect_pin = -1;
15137 + smp_wmb();
15138 +
15139 + free_irq(gpio_to_irq(pin), host->mmc);
15140 + del_timer_sync(&host->detect_timer);
15141 + cancel_delayed_work(&host->mmc->detect);
15142 + gpio_free(pin);
15143 + }
15144 +
15145 + mmc_remove_host(host->mmc);
15146 +
15147 + mci_writel(host, IDR, ~0UL);
15148 + mci_writel(host, CR, MCI_BIT(MCIDIS));
15149 + mci_readl(host, SR);
15150 +
15151 + dma_release_channel(host->dma.req.req.dmac,
15152 + host->dma.req.req.channel);
15153 +
15154 + if (host->wp_pin >= 0)
15155 + gpio_free(host->wp_pin);
15156 +
15157 + free_irq(platform_get_irq(pdev, 0), host->mmc);
15158 + iounmap(host->regs);
15159 +
15160 + clk_disable(host->mck);
15161 + clk_put(host->mck);
15162 +
15163 + mmc_free_host(host->mmc);
15164 + }
15165 + return 0;
15166 +}
15167 +
15168 +static struct platform_driver atmci_driver = {
15169 + .probe = atmci_probe,
15170 + .remove = __devexit_p(atmci_remove),
15171 + .driver = {
15172 + .name = DRIVER_NAME,
15173 + },
15174 +};
15175 +
15176 +static int __init atmci_init(void)
15177 +{
15178 + return platform_driver_register(&atmci_driver);
15179 +}
15180 +
15181 +static void __exit atmci_exit(void)
15182 +{
15183 + platform_driver_unregister(&atmci_driver);
15184 +}
15185 +
15186 +module_init(atmci_init);
15187 +module_exit(atmci_exit);
15188 +
15189 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
15190 +MODULE_LICENSE("GPL");
15191 --- /dev/null
15192 +++ b/drivers/mmc/host/atmel-mci.h
15193 @@ -0,0 +1,192 @@
15194 +/*
15195 + * Atmel MultiMedia Card Interface driver
15196 + *
15197 + * Copyright (C) 2004-2006 Atmel Corporation
15198 + *
15199 + * This program is free software; you can redistribute it and/or modify
15200 + * it under the terms of the GNU General Public License version 2 as
15201 + * published by the Free Software Foundation.
15202 + */
15203 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
15204 +#define __DRIVERS_MMC_ATMEL_MCI_H__
15205 +
15206 +/* MCI register offsets */
15207 +#define MCI_CR 0x0000
15208 +#define MCI_MR 0x0004
15209 +#define MCI_DTOR 0x0008
15210 +#define MCI_SDCR 0x000c
15211 +#define MCI_ARGR 0x0010
15212 +#define MCI_CMDR 0x0014
15213 +#define MCI_BLKR 0x0018
15214 +#define MCI_RSPR 0x0020
15215 +#define MCI_RSPR1 0x0024
15216 +#define MCI_RSPR2 0x0028
15217 +#define MCI_RSPR3 0x002c
15218 +#define MCI_RDR 0x0030
15219 +#define MCI_TDR 0x0034
15220 +#define MCI_SR 0x0040
15221 +#define MCI_IER 0x0044
15222 +#define MCI_IDR 0x0048
15223 +#define MCI_IMR 0x004c
15224 +
15225 +/* Bitfields in CR */
15226 +#define MCI_MCIEN_OFFSET 0
15227 +#define MCI_MCIEN_SIZE 1
15228 +#define MCI_MCIDIS_OFFSET 1
15229 +#define MCI_MCIDIS_SIZE 1
15230 +#define MCI_PWSEN_OFFSET 2
15231 +#define MCI_PWSEN_SIZE 1
15232 +#define MCI_PWSDIS_OFFSET 3
15233 +#define MCI_PWSDIS_SIZE 1
15234 +#define MCI_SWRST_OFFSET 7
15235 +#define MCI_SWRST_SIZE 1
15236 +
15237 +/* Bitfields in MR */
15238 +#define MCI_CLKDIV_OFFSET 0
15239 +#define MCI_CLKDIV_SIZE 8
15240 +#define MCI_PWSDIV_OFFSET 8
15241 +#define MCI_PWSDIV_SIZE 3
15242 +#define MCI_RDPROOF_OFFSET 11
15243 +#define MCI_RDPROOF_SIZE 1
15244 +#define MCI_WRPROOF_OFFSET 12
15245 +#define MCI_WRPROOF_SIZE 1
15246 +#define MCI_DMAPADV_OFFSET 14
15247 +#define MCI_DMAPADV_SIZE 1
15248 +#define MCI_BLKLEN_OFFSET 16
15249 +#define MCI_BLKLEN_SIZE 16
15250 +
15251 +/* Bitfields in DTOR */
15252 +#define MCI_DTOCYC_OFFSET 0
15253 +#define MCI_DTOCYC_SIZE 4
15254 +#define MCI_DTOMUL_OFFSET 4
15255 +#define MCI_DTOMUL_SIZE 3
15256 +
15257 +/* Bitfields in SDCR */
15258 +#define MCI_SDCSEL_OFFSET 0
15259 +#define MCI_SDCSEL_SIZE 4
15260 +#define MCI_SDCBUS_OFFSET 7
15261 +#define MCI_SDCBUS_SIZE 1
15262 +
15263 +/* Bitfields in ARGR */
15264 +#define MCI_ARG_OFFSET 0
15265 +#define MCI_ARG_SIZE 32
15266 +
15267 +/* Bitfields in CMDR */
15268 +#define MCI_CMDNB_OFFSET 0
15269 +#define MCI_CMDNB_SIZE 6
15270 +#define MCI_RSPTYP_OFFSET 6
15271 +#define MCI_RSPTYP_SIZE 2
15272 +#define MCI_SPCMD_OFFSET 8
15273 +#define MCI_SPCMD_SIZE 3
15274 +#define MCI_OPDCMD_OFFSET 11
15275 +#define MCI_OPDCMD_SIZE 1
15276 +#define MCI_MAXLAT_OFFSET 12
15277 +#define MCI_MAXLAT_SIZE 1
15278 +#define MCI_TRCMD_OFFSET 16
15279 +#define MCI_TRCMD_SIZE 2
15280 +#define MCI_TRDIR_OFFSET 18
15281 +#define MCI_TRDIR_SIZE 1
15282 +#define MCI_TRTYP_OFFSET 19
15283 +#define MCI_TRTYP_SIZE 2
15284 +
15285 +/* Bitfields in BLKR */
15286 +#define MCI_BCNT_OFFSET 0
15287 +#define MCI_BCNT_SIZE 16
15288 +
15289 +/* Bitfields in RSPRn */
15290 +#define MCI_RSP_OFFSET 0
15291 +#define MCI_RSP_SIZE 32
15292 +
15293 +/* Bitfields in SR/IER/IDR/IMR */
15294 +#define MCI_CMDRDY_OFFSET 0
15295 +#define MCI_CMDRDY_SIZE 1
15296 +#define MCI_RXRDY_OFFSET 1
15297 +#define MCI_RXRDY_SIZE 1
15298 +#define MCI_TXRDY_OFFSET 2
15299 +#define MCI_TXRDY_SIZE 1
15300 +#define MCI_BLKE_OFFSET 3
15301 +#define MCI_BLKE_SIZE 1
15302 +#define MCI_DTIP_OFFSET 4
15303 +#define MCI_DTIP_SIZE 1
15304 +#define MCI_NOTBUSY_OFFSET 5
15305 +#define MCI_NOTBUSY_SIZE 1
15306 +#define MCI_ENDRX_OFFSET 6
15307 +#define MCI_ENDRX_SIZE 1
15308 +#define MCI_ENDTX_OFFSET 7
15309 +#define MCI_ENDTX_SIZE 1
15310 +#define MCI_RXBUFF_OFFSET 14
15311 +#define MCI_RXBUFF_SIZE 1
15312 +#define MCI_TXBUFE_OFFSET 15
15313 +#define MCI_TXBUFE_SIZE 1
15314 +#define MCI_RINDE_OFFSET 16
15315 +#define MCI_RINDE_SIZE 1
15316 +#define MCI_RDIRE_OFFSET 17
15317 +#define MCI_RDIRE_SIZE 1
15318 +#define MCI_RCRCE_OFFSET 18
15319 +#define MCI_RCRCE_SIZE 1
15320 +#define MCI_RENDE_OFFSET 19
15321 +#define MCI_RENDE_SIZE 1
15322 +#define MCI_RTOE_OFFSET 20
15323 +#define MCI_RTOE_SIZE 1
15324 +#define MCI_DCRCE_OFFSET 21
15325 +#define MCI_DCRCE_SIZE 1
15326 +#define MCI_DTOE_OFFSET 22
15327 +#define MCI_DTOE_SIZE 1
15328 +#define MCI_OVRE_OFFSET 30
15329 +#define MCI_OVRE_SIZE 1
15330 +#define MCI_UNRE_OFFSET 31
15331 +#define MCI_UNRE_SIZE 1
15332 +
15333 +/* Constants for DTOMUL */
15334 +#define MCI_DTOMUL_1_CYCLE 0
15335 +#define MCI_DTOMUL_16_CYCLES 1
15336 +#define MCI_DTOMUL_128_CYCLES 2
15337 +#define MCI_DTOMUL_256_CYCLES 3
15338 +#define MCI_DTOMUL_1024_CYCLES 4
15339 +#define MCI_DTOMUL_4096_CYCLES 5
15340 +#define MCI_DTOMUL_65536_CYCLES 6
15341 +#define MCI_DTOMUL_1048576_CYCLES 7
15342 +
15343 +/* Constants for RSPTYP */
15344 +#define MCI_RSPTYP_NO_RESP 0
15345 +#define MCI_RSPTYP_48_BIT 1
15346 +#define MCI_RSPTYP_136_BIT 2
15347 +
15348 +/* Constants for SPCMD */
15349 +#define MCI_SPCMD_NO_SPEC_CMD 0
15350 +#define MCI_SPCMD_INIT_CMD 1
15351 +#define MCI_SPCMD_SYNC_CMD 2
15352 +#define MCI_SPCMD_INT_CMD 4
15353 +#define MCI_SPCMD_INT_RESP 5
15354 +
15355 +/* Constants for TRCMD */
15356 +#define MCI_TRCMD_NO_TRANS 0
15357 +#define MCI_TRCMD_START_TRANS 1
15358 +#define MCI_TRCMD_STOP_TRANS 2
15359 +
15360 +/* Constants for TRTYP */
15361 +#define MCI_TRTYP_BLOCK 0
15362 +#define MCI_TRTYP_MULTI_BLOCK 1
15363 +#define MCI_TRTYP_STREAM 2
15364 +
15365 +/* Bit manipulation macros */
15366 +#define MCI_BIT(name) \
15367 + (1 << MCI_##name##_OFFSET)
15368 +#define MCI_BF(name,value) \
15369 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
15370 + << MCI_##name##_OFFSET)
15371 +#define MCI_BFEXT(name,value) \
15372 + (((value) >> MCI_##name##_OFFSET) \
15373 + & ((1 << MCI_##name##_SIZE) - 1))
15374 +#define MCI_BFINS(name,value,old) \
15375 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
15376 + << MCI_##name##_OFFSET)) \
15377 + | MCI_BF(name,value))
15378 +
15379 +/* Register access macros */
15380 +#define mci_readl(port,reg) \
15381 + __raw_readl((port)->regs + MCI_##reg)
15382 +#define mci_writel(port,reg,value) \
15383 + __raw_writel((value), (port)->regs + MCI_##reg)
15384 +
15385 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
15386 --- a/drivers/mmc/host/Kconfig
15387 +++ b/drivers/mmc/host/Kconfig
15388 @@ -91,6 +91,16 @@
15389
15390 If unsure, say N.
15391
15392 +config MMC_ATMELMCI
15393 + tristate "Atmel Multimedia Card Interface support"
15394 + depends on AVR32 && MMC
15395 + help
15396 + This selects the Atmel Multimedia Card Interface. If you have
15397 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
15398 + slot, say Y or M here.
15399 +
15400 + If unsure, say N.
15401 +
15402 config MMC_IMX
15403 tristate "Motorola i.MX Multimedia Card Interface support"
15404 depends on ARCH_IMX
15405 --- a/drivers/mmc/host/Makefile
15406 +++ b/drivers/mmc/host/Makefile
15407 @@ -15,6 +15,7 @@
15408 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
15409 obj-$(CONFIG_MMC_OMAP) += omap.o
15410 obj-$(CONFIG_MMC_AT91) += at91_mci.o
15411 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
15412 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
15413 obj-$(CONFIG_MMC_SPI) += mmc_spi.o
15414
15415 --- a/drivers/mtd/chips/cfi_cmdset_0001.c
15416 +++ b/drivers/mtd/chips/cfi_cmdset_0001.c
15417 @@ -50,6 +50,7 @@
15418 #define I82802AC 0x00ac
15419 #define MANUFACTURER_ST 0x0020
15420 #define M50LPW080 0x002F
15421 +#define AT49BV640D 0x02de
15422
15423 static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
15424 static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
15425 @@ -157,6 +158,47 @@
15426 }
15427 #endif
15428
15429 +/* Atmel chips don't use the same PRI format as Intel chips */
15430 +static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
15431 +{
15432 + struct map_info *map = mtd->priv;
15433 + struct cfi_private *cfi = map->fldrv_priv;
15434 + struct cfi_pri_intelext *extp = cfi->cmdset_priv;
15435 + struct cfi_pri_atmel atmel_pri;
15436 + uint32_t features = 0;
15437 +
15438 + /* Reverse byteswapping */
15439 + extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
15440 + extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
15441 + extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
15442 +
15443 + memcpy(&atmel_pri, extp, sizeof(atmel_pri));
15444 + memset((char *)extp + 5, 0, sizeof(*extp) - 5);
15445 +
15446 + printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
15447 +
15448 + if (atmel_pri.Features & 0x01) /* chip erase supported */
15449 + features |= (1<<0);
15450 + if (atmel_pri.Features & 0x02) /* erase suspend supported */
15451 + features |= (1<<1);
15452 + if (atmel_pri.Features & 0x04) /* program suspend supported */
15453 + features |= (1<<2);
15454 + if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
15455 + features |= (1<<9);
15456 + if (atmel_pri.Features & 0x20) /* page mode read supported */
15457 + features |= (1<<7);
15458 + if (atmel_pri.Features & 0x40) /* queued erase supported */
15459 + features |= (1<<4);
15460 + if (atmel_pri.Features & 0x80) /* Protection bits supported */
15461 + features |= (1<<6);
15462 +
15463 + extp->FeatureSupport = features;
15464 +
15465 + /* burst write mode not supported */
15466 + cfi->cfiq->BufWriteTimeoutTyp = 0;
15467 + cfi->cfiq->BufWriteTimeoutMax = 0;
15468 +}
15469 +
15470 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
15471 /* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
15472 static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
15473 @@ -234,6 +276,7 @@
15474 }
15475
15476 static struct cfi_fixup cfi_fixup_table[] = {
15477 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
15478 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
15479 { CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
15480 #endif
15481 --- a/drivers/mtd/chips/cfi_cmdset_0002.c
15482 +++ b/drivers/mtd/chips/cfi_cmdset_0002.c
15483 @@ -186,6 +186,10 @@
15484 extp->TopBottom = 2;
15485 else
15486 extp->TopBottom = 3;
15487 +
15488 + /* burst write mode not supported */
15489 + cfi->cfiq->BufWriteTimeoutTyp = 0;
15490 + cfi->cfiq->BufWriteTimeoutMax = 0;
15491 }
15492
15493 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
15494 @@ -218,6 +222,7 @@
15495 }
15496
15497 static struct cfi_fixup cfi_fixup_table[] = {
15498 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
15499 #ifdef AMD_BOOTLOC_BUG
15500 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
15501 #endif
15502 @@ -230,7 +235,6 @@
15503 #if !FORCE_WORD_WRITE
15504 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
15505 #endif
15506 - { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
15507 { 0, 0, NULL, NULL }
15508 };
15509 static struct cfi_fixup jedec_fixup_table[] = {
15510 --- /dev/null
15511 +++ b/drivers/pcmcia/at32_cf.c
15512 @@ -0,0 +1,533 @@
15513 +/*
15514 + * Driver for AVR32 Static Memory Controller: CompactFlash support
15515 + *
15516 + * Copyright (C) 2006 Atmel Norway
15517 + *
15518 + * This program is free software; you can redistribute it and/or
15519 + * modify it under the terms of the GNU General Public License as
15520 + * published by the Free Software Foundation; either version 2 of the
15521 + * License, or (at your option) any later version.
15522 + *
15523 + * This program is distributed in the hope that it will be useful, but
15524 + * WITHOUT ANY WARRANTY; without even the implied warranty of
15525 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15526 + * General Public License for more details.
15527 + *
15528 + * You should have received a copy of the GNU General Public License
15529 + * along with this program; if not, write to the Free Software
15530 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
15531 + * 02111-1307, USA.
15532 + *
15533 + * The full GNU General Public License is included in this
15534 + * distribution in the file called COPYING.
15535 + */
15536 +#include <linux/module.h>
15537 +#include <linux/kernel.h>
15538 +#include <linux/platform_device.h>
15539 +#include <linux/init.h>
15540 +#include <linux/device.h>
15541 +#include <linux/delay.h>
15542 +#include <linux/interrupt.h>
15543 +#include <linux/err.h>
15544 +#include <linux/clk.h>
15545 +#include <linux/dma-mapping.h>
15546 +
15547 +#include <pcmcia/ss.h>
15548 +
15549 +#include <asm/gpio.h>
15550 +#include <asm/io.h>
15551 +#include <asm/arch/board.h>
15552 +
15553 +#include <asm/arch/smc.h>
15554 +
15555 +struct at32_cf_socket {
15556 + struct pcmcia_socket socket;
15557 + int detect_pin;
15558 + int reset_pin;
15559 + int vcc_pin;
15560 + int ready_pin;
15561 + struct resource res_attr;
15562 + struct resource res_mem;
15563 + struct resource res_io;
15564 + struct smc_config smc;
15565 + unsigned int irq;
15566 + unsigned int cf_cs;
15567 + socket_state_t state;
15568 + unsigned present:1;
15569 +};
15570 +#define to_at32_cf(sock) container_of(sock, struct at32_cf_socket, socket)
15571 +
15572 +/*
15573 + * We have the following memory layout relative to the base address:
15574 + *
15575 + * Alt IDE Mode: 00e0 0000 -> 00ff ffff
15576 + * True IDE Mode: 00c0 0000 -> 00df ffff
15577 + * I/O memory: 0080 0000 -> 00bf ffff
15578 + * Common memory: 0040 0000 -> 007f ffff
15579 + * Attribute memory: 0000 0000 -> 003f ffff
15580 + */
15581 +#define CF_ATTR_OFFSET 0x00000000
15582 +#define CF_MEM_OFFSET 0x00400000
15583 +#define CF_IO_OFFSET 0x00800000
15584 +#define CF_RES_SIZE 4096
15585 +
15586 +#ifdef DEBUG
15587 +
15588 +static int pc_debug;
15589 +module_param(pc_debug, int, 0644);
15590 +
15591 +static void at32_cf_debug(struct at32_cf_socket *cf, const char *func,
15592 + int level, const char *fmt, ...)
15593 +{
15594 + va_list args;
15595 +
15596 + if (pc_debug > level) {
15597 + printk(KERN_DEBUG "at32_cf/%u: %s: ", cf->cf_cs, func);
15598 + va_start(args, fmt);
15599 + vprintk(fmt, args);
15600 + va_end(args);
15601 + }
15602 +}
15603 +
15604 +#define debug(cf, lvl, fmt, arg...) \
15605 + at32_cf_debug(cf, __func__, lvl, fmt, ##arg)
15606 +
15607 +#else
15608 +#define debug(cf, lvl, fmt, arg...) do { } while (0)
15609 +#endif
15610 +
15611 +static inline int at32_cf_present(struct at32_cf_socket *cf)
15612 +{
15613 + int present = 1;
15614 +
15615 + /* If we don't have a detect pin, assume the card is present */
15616 + if (cf->detect_pin >= 0)
15617 + present = !gpio_get_value(cf->detect_pin);
15618 +
15619 + return present;
15620 +}
15621 +
15622 +static irqreturn_t at32_cf_irq(int irq, void *dev_id)
15623 +{
15624 + struct at32_cf_socket *cf = dev_id;
15625 + unsigned int present;
15626 +
15627 + present = at32_cf_present(cf);
15628 + if (present != cf->present) {
15629 + cf->present = present;
15630 + debug(cf, 3, "card %s\n", present ? "present" : "gone");
15631 + pcmcia_parse_events(&cf->socket, SS_DETECT);
15632 + }
15633 +
15634 + return IRQ_HANDLED;
15635 +}
15636 +
15637 +static int at32_cf_get_status(struct pcmcia_socket *sock, u_int *value)
15638 +{
15639 + struct at32_cf_socket *cf;
15640 + u_int status = 0;
15641 +
15642 + cf = container_of(sock, struct at32_cf_socket, socket);
15643 +
15644 + if (at32_cf_present(cf)) {
15645 + /* NOTE: gpio on AP7xxx is 3.3V */
15646 + status = SS_DETECT | SS_3VCARD;
15647 + if (cf->ready_pin < 0 || gpio_get_value(cf->ready_pin))
15648 + status |= SS_READY;
15649 + if (cf->vcc_pin < 0 || gpio_get_value(cf->vcc_pin))
15650 + status |= SS_POWERON;
15651 + }
15652 +
15653 + *value = status;
15654 + return 0;
15655 +}
15656 +
15657 +static int at32_cf_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
15658 +{
15659 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
15660 +
15661 + debug(cf, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
15662 + (state->csc_mask==0)?"<NONE> ":"",
15663 + (state->csc_mask&SS_DETECT)?"DETECT ":"",
15664 + (state->csc_mask&SS_READY)?"READY ":"",
15665 + (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
15666 + (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
15667 + (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
15668 + (state->flags==0)?"<NONE> ":"",
15669 + (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
15670 + (state->flags&SS_IOCARD)?"IOCARD ":"",
15671 + (state->flags&SS_RESET)?"RESET ":"",
15672 + (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
15673 + (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
15674 + state->Vcc, state->Vpp, state->io_irq);
15675 +
15676 + /*
15677 + * TODO: Allow boards to override this in case they have level
15678 + * converters.
15679 + */
15680 + switch (state->Vcc) {
15681 + case 0:
15682 + if (cf->vcc_pin >= 0)
15683 + gpio_set_value(cf->vcc_pin, 0);
15684 + break;
15685 + case 33:
15686 + if (cf->vcc_pin >= 0)
15687 + gpio_set_value(cf->vcc_pin, 1);
15688 + break;
15689 + default:
15690 + return -EINVAL;
15691 + }
15692 +
15693 + if (cf->reset_pin >= 0)
15694 + gpio_set_value(cf->reset_pin, state->flags & SS_RESET);
15695 +
15696 + cf->state = *state;
15697 +
15698 + return 0;
15699 +}
15700 +
15701 +static int at32_cf_socket_init(struct pcmcia_socket *sock)
15702 +{
15703 + debug(to_at32_cf(sock), 2, "called\n");
15704 +
15705 + return 0;
15706 +}
15707 +
15708 +static int at32_cf_suspend(struct pcmcia_socket *sock)
15709 +{
15710 + debug(to_at32_cf(sock), 2, "called\n");
15711 +
15712 + at32_cf_set_socket(sock, &dead_socket);
15713 +
15714 + return 0;
15715 +}
15716 +
15717 +static int at32_cf_set_io_map(struct pcmcia_socket *sock,
15718 + struct pccard_io_map *map)
15719 +{
15720 + struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
15721 + int retval;
15722 +
15723 + debug(cf, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
15724 + map->map, map->speed, map->start, map->stop);
15725 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
15726 + (map->flags == 0) ? "<NONE>":"",
15727 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
15728 + (map->flags & MAP_16BIT) ? "16BIT " : "",
15729 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
15730 + (map->flags & MAP_0WS) ? "0WS " : "",
15731 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
15732 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
15733 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
15734 +
15735 + map->flags &= MAP_ACTIVE | MAP_16BIT | MAP_USE_WAIT;
15736 +
15737 + if (map->flags & MAP_16BIT)
15738 + cf->smc.bus_width = 2;
15739 + else
15740 + cf->smc.bus_width = 1;
15741 +
15742 + if (map->flags & MAP_USE_WAIT)
15743 + cf->smc.nwait_mode = 3;
15744 + else
15745 + cf->smc.nwait_mode = 0;
15746 +
15747 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
15748 + if (retval) {
15749 + printk(KERN_ERR "at32_cf: could not set up SMC for I/O\n");
15750 + return retval;
15751 + }
15752 +
15753 + map->start = cf->socket.io_offset;
15754 + map->stop = map->start + CF_RES_SIZE - 1;
15755 +
15756 + return 0;
15757 +}
15758 +
15759 +static int
15760 +at32_cf_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
15761 +{
15762 + struct at32_cf_socket *cf;
15763 + struct resource *res;
15764 + int retval;
15765 +
15766 + cf = container_of(sock, struct at32_cf_socket, socket);
15767 +
15768 + debug(cf, 2, "map %u speed %u card_start %08x\n",
15769 + map->map, map->speed, map->card_start);
15770 + debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
15771 + (map->flags==0)?"<NONE>":"",
15772 + (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
15773 + (map->flags&MAP_16BIT)?"16BIT ":"",
15774 + (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
15775 + (map->flags&MAP_0WS)?"0WS ":"",
15776 + (map->flags&MAP_WRPROT)?"WRPROT ":"",
15777 + (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
15778 + (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
15779 +
15780 + if (map->card_start)
15781 + return -EINVAL;
15782 +
15783 + map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT | MAP_USE_WAIT;
15784 +
15785 + if (map->flags & MAP_ATTRIB) {
15786 + res = &cf->res_attr;
15787 +
15788 + /* Linksys WCF12 seems to use WAIT when reading CIS */
15789 + map->flags |= MAP_USE_WAIT;
15790 + } else {
15791 + res = &cf->res_mem;
15792 + }
15793 +
15794 + if (map->flags & MAP_USE_WAIT)
15795 + cf->smc.nwait_mode = 3;
15796 + else
15797 + cf->smc.nwait_mode = 0;
15798 +
15799 + retval = smc_set_configuration(cf->cf_cs, &cf->smc);
15800 + if (retval) {
15801 + printk(KERN_ERR "at32_cf: could not set up SMC for mem\n");
15802 + return retval;
15803 + }
15804 +
15805 + map->static_start = res->start;
15806 +
15807 + return 0;
15808 +}
15809 +
15810 +static struct pccard_operations at32_cf_ops = {
15811 + .init = at32_cf_socket_init,
15812 + .suspend = at32_cf_suspend,
15813 + .get_status = at32_cf_get_status,
15814 + .set_socket = at32_cf_set_socket,
15815 + .set_io_map = at32_cf_set_io_map,
15816 + .set_mem_map = at32_cf_set_mem_map,
15817 +};
15818 +
15819 +static int __init request_pin(struct platform_device *pdev,
15820 + unsigned int pin, const char *name)
15821 +{
15822 + if (gpio_request(pin, name)) {
15823 + dev_warn(&pdev->dev, "failed to request %s pin\n", name);
15824 + return -1;
15825 + }
15826 +
15827 + return pin;
15828 +}
15829 +
15830 +static struct smc_timing at32_cf_timing __initdata = {
15831 + .ncs_read_setup = 30,
15832 + .nrd_setup = 100,
15833 + .ncs_write_setup = 30,
15834 + .nwe_setup = 100,
15835 +
15836 + .ncs_read_pulse = 360,
15837 + .nrd_pulse = 290,
15838 + .ncs_write_pulse = 360,
15839 + .nwe_pulse = 290,
15840 +
15841 + .read_cycle = 420,
15842 + .write_cycle = 420,
15843 +};
15844 +
15845 +static int __init at32_cf_probe(struct platform_device *pdev)
15846 +{
15847 + struct at32_cf_socket *cf;
15848 + struct cf_platform_data *board = pdev->dev.platform_data;
15849 + struct resource *res_skt;
15850 + int irq;
15851 + int ret;
15852 +
15853 + dev_dbg(&pdev->dev, "probe");
15854 +
15855 + if (!board)
15856 + return -ENXIO;
15857 +
15858 + res_skt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
15859 + if (!res_skt)
15860 + return -ENXIO;
15861 +
15862 + irq = platform_get_irq(pdev, 0);
15863 + if (irq < 0)
15864 + return irq;
15865 +
15866 + cf = kzalloc(sizeof(struct at32_cf_socket), GFP_KERNEL);
15867 + if (!cf)
15868 + return -ENOMEM;
15869 +
15870 + cf->detect_pin = -1;
15871 + cf->reset_pin = -1;
15872 + cf->vcc_pin = -1;
15873 + cf->ready_pin = -1;
15874 + cf->cf_cs = board->cs;
15875 +
15876 + if (board->detect_pin != GPIO_PIN_NONE)
15877 + cf->detect_pin = request_pin(pdev, board->detect_pin,
15878 + "cf_detect");
15879 + if (board->reset_pin != GPIO_PIN_NONE)
15880 + cf->reset_pin = request_pin(pdev, board->reset_pin,
15881 + "cf_reset");
15882 + if (board->vcc_pin != GPIO_PIN_NONE)
15883 + cf->vcc_pin = request_pin(pdev, board->vcc_pin,
15884 + "cf_vcc");
15885 + if (board->ready_pin != GPIO_PIN_NONE)
15886 + /* READY is also used for irq through EIM */
15887 + cf->ready_pin = board->ready_pin;
15888 +
15889 + debug(cf, 2, "pins: detect=%d reset=%d vcc=%d\n",
15890 + cf->detect_pin, cf->reset_pin, cf->vcc_pin);
15891 +
15892 + cf->socket.pci_irq = irq;
15893 + cf->socket.ops = &at32_cf_ops;
15894 + cf->socket.resource_ops = &pccard_static_ops;
15895 + cf->socket.dev.parent = &pdev->dev;
15896 + cf->socket.owner = THIS_MODULE;
15897 + cf->socket.features =
15898 + SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
15899 + cf->socket.map_size = CF_RES_SIZE;
15900 +
15901 + cf->res_attr.start = res_skt->start + CF_ATTR_OFFSET;
15902 + cf->res_attr.end = cf->res_attr.start + CF_RES_SIZE - 1;
15903 + cf->res_attr.name = "attribute";
15904 + cf->res_attr.flags = IORESOURCE_MEM;
15905 + ret = request_resource(res_skt, &cf->res_attr);
15906 + if (ret)
15907 + goto err_request_res_attr;
15908 +
15909 + cf->res_mem.start = res_skt->start + CF_MEM_OFFSET;
15910 + cf->res_mem.end = cf->res_mem.start + CF_RES_SIZE - 1;
15911 + cf->res_mem.name = "memory";
15912 + cf->res_mem.flags = IORESOURCE_MEM;
15913 + ret = request_resource(res_skt, &cf->res_mem);
15914 + if (ret)
15915 + goto err_request_res_mem;
15916 +
15917 + cf->res_io.start = res_skt->start + CF_IO_OFFSET;
15918 + cf->res_io.end = cf->res_io.start + CF_RES_SIZE - 1;
15919 + cf->res_io.name = "io";
15920 + cf->res_io.flags = IORESOURCE_MEM;
15921 + ret = request_resource(res_skt, &cf->res_io);
15922 + if (ret)
15923 + goto err_request_res_io;
15924 +
15925 + cf->socket.io_offset = cf->res_io.start;
15926 +
15927 + if (cf->detect_pin >= 0) {
15928 + ret = request_irq(gpio_to_irq(cf->detect_pin), at32_cf_irq,
15929 + IRQF_SHARED, "cf_detect", cf);
15930 + if (ret) {
15931 + debug(cf, 1,
15932 + "failed to request cf_detect interrupt\n");
15933 + goto err_detect_irq;
15934 + }
15935 + }
15936 +
15937 + cf->present = at32_cf_present(cf);
15938 +
15939 + /* Setup SMC timings */
15940 + smc_set_timing(&cf->smc, &at32_cf_timing);
15941 +
15942 + cf->smc.bus_width = 2;
15943 + cf->smc.nrd_controlled = 1;
15944 + cf->smc.nwe_controlled = 1;
15945 + cf->smc.nwait_mode = 0;
15946 + cf->smc.byte_write = 0;
15947 + cf->smc.tdf_cycles = 8;
15948 + cf->smc.tdf_mode = 0;
15949 +
15950 + ret = smc_set_configuration(cf->cf_cs, &cf->smc);
15951 + if (ret) {
15952 + debug(cf, 1, "failed to configure SMC\n", ret);
15953 + goto err_smc;
15954 + }
15955 +
15956 + ret = pcmcia_register_socket(&cf->socket);
15957 + if (ret) {
15958 + debug(cf, 1, "failed to register socket: %d\n", ret);
15959 + goto err_register_socket;
15960 + }
15961 +
15962 + if (cf->reset_pin >= 0)
15963 + gpio_direction_output(cf->reset_pin, 0);
15964 +
15965 + platform_set_drvdata(pdev, cf);
15966 +
15967 + dev_info(&pdev->dev, "Atmel SMC CF interface at 0x%08lx\n",
15968 + (unsigned long)res_skt->start);
15969 +
15970 + return 0;
15971 +
15972 +err_register_socket:
15973 +err_smc:
15974 + if (cf->detect_pin >= 0)
15975 + free_irq(gpio_to_irq(cf->detect_pin), cf);
15976 +err_detect_irq:
15977 + release_resource(&cf->res_io);
15978 +err_request_res_io:
15979 + release_resource(&cf->res_mem);
15980 +err_request_res_mem:
15981 + release_resource(&cf->res_attr);
15982 +err_request_res_attr:
15983 + if (cf->vcc_pin >= 0)
15984 + gpio_free(cf->vcc_pin);
15985 + if (cf->reset_pin >= 0)
15986 + gpio_free(cf->reset_pin);
15987 + if (cf->detect_pin >= 0)
15988 + gpio_free(cf->detect_pin);
15989 + kfree(cf);
15990 +
15991 + return ret;
15992 +}
15993 +
15994 +static int __exit at32_cf_remove(struct platform_device *pdev)
15995 +{
15996 + struct at32_cf_socket *cf = platform_get_drvdata(pdev);
15997 +
15998 + pcmcia_unregister_socket(&cf->socket);
15999 + if (cf->detect_pin >= 0) {
16000 + free_irq(gpio_to_irq(cf->detect_pin), cf);
16001 + gpio_free(cf->detect_pin);
16002 + }
16003 + if (cf->vcc_pin >= 0)
16004 + gpio_free(cf->vcc_pin);
16005 + if (cf->reset_pin >= 0)
16006 + gpio_free(cf->reset_pin);
16007 +
16008 + release_resource(&cf->res_io);
16009 + release_resource(&cf->res_mem);
16010 + release_resource(&cf->res_attr);
16011 + kfree(cf);
16012 + platform_set_drvdata(pdev, NULL);
16013 +
16014 + return 0;
16015 +}
16016 +
16017 +static struct platform_driver at32_cf_driver = {
16018 + .remove = __exit_p(at32_cf_remove),
16019 + .driver = {
16020 + .name = "at32_cf",
16021 + .owner = THIS_MODULE,
16022 + },
16023 +};
16024 +
16025 +static int __init at32_cf_init(void)
16026 +{
16027 + int ret;
16028 +
16029 + ret = platform_driver_probe(&at32_cf_driver, at32_cf_probe);
16030 + if (ret)
16031 + printk(KERN_ERR "at32_cf: probe failed: %d\n", ret);
16032 + return ret;
16033 +}
16034 +
16035 +static void __exit at32_cf_exit(void)
16036 +{
16037 + platform_driver_unregister(&at32_cf_driver);
16038 +}
16039 +
16040 +module_init(at32_cf_init);
16041 +module_exit(at32_cf_exit);
16042 +
16043 +MODULE_LICENSE("GPL");
16044 +MODULE_DESCRIPTION("Driver for SMC PCMCIA interface");
16045 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
16046 --- a/drivers/pcmcia/Kconfig
16047 +++ b/drivers/pcmcia/Kconfig
16048 @@ -276,6 +276,13 @@
16049 Say Y here to support the CompactFlash controller on the
16050 PA Semi Electra eval board.
16051
16052 +config AT32_CF
16053 + tristate "AT32AP CompactFlash Controller"
16054 + depends on PCMCIA && AVR32 && PLATFORM_AT32AP
16055 + help
16056 + Say Y here to support the CompactFlash controller on AT32 chips.
16057 + Or choose M to compile the driver as a module named "at32_cf".
16058 +
16059 config PCCARD_NONSTATIC
16060 tristate
16061
16062 --- a/drivers/pcmcia/Makefile
16063 +++ b/drivers/pcmcia/Makefile
16064 @@ -38,6 +38,7 @@
16065 obj-$(CONFIG_OMAP_CF) += omap_cf.o
16066 obj-$(CONFIG_AT91_CF) += at91_cf.o
16067 obj-$(CONFIG_ELECTRA_CF) += electra_cf.o
16068 +obj-$(CONFIG_AT32_CF) += at32_cf.o
16069
16070 sa11xx_core-y += soc_common.o sa11xx_base.o
16071 pxa2xx_core-y += soc_common.o pxa2xx_base.o
16072 --- a/drivers/serial/atmel_serial.c
16073 +++ b/drivers/serial/atmel_serial.c
16074 @@ -7,6 +7,8 @@
16075 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
16076 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
16077 *
16078 + * DMA support added by Chip Coldwell.
16079 + *
16080 * This program is free software; you can redistribute it and/or modify
16081 * it under the terms of the GNU General Public License as published by
16082 * the Free Software Foundation; either version 2 of the License, or
16083 @@ -33,7 +35,9 @@
16084 #include <linux/sysrq.h>
16085 #include <linux/tty_flip.h>
16086 #include <linux/platform_device.h>
16087 +#include <linux/dma-mapping.h>
16088 #include <linux/atmel_pdc.h>
16089 +#include <linux/atmel_serial.h>
16090
16091 #include <asm/io.h>
16092
16093 @@ -45,7 +49,9 @@
16094 #include <asm/arch/gpio.h>
16095 #endif
16096
16097 -#include "atmel_serial.h"
16098 +#define PDC_BUFFER_SIZE 512
16099 +/* Revisit: We should calculate this based on the actual port settings */
16100 +#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
16101
16102 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16103 #define SUPPORT_SYSRQ
16104 @@ -74,6 +80,7 @@
16105
16106 #define ATMEL_ISR_PASS_LIMIT 256
16107
16108 +/* UART registers. CR is write-only, hence no GET macro */
16109 #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
16110 #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
16111 #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
16112 @@ -87,8 +94,6 @@
16113 #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
16114 #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
16115
16116 -// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only
16117 -
16118 /* PDC registers */
16119 #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
16120 #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
16121 @@ -101,12 +106,24 @@
16122
16123 #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
16124 #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
16125 -//#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR)
16126 -//#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR)
16127
16128 static int (*atmel_open_hook)(struct uart_port *);
16129 static void (*atmel_close_hook)(struct uart_port *);
16130
16131 +struct atmel_dma_buffer {
16132 + unsigned char *buf;
16133 + dma_addr_t dma_addr;
16134 + unsigned int dma_size;
16135 + unsigned int ofs;
16136 +};
16137 +
16138 +struct atmel_uart_char {
16139 + u16 status;
16140 + u16 ch;
16141 +};
16142 +
16143 +#define ATMEL_SERIAL_RINGSIZE 1024
16144 +
16145 /*
16146 * We wrap our port structure around the generic uart_port.
16147 */
16148 @@ -115,6 +132,19 @@
16149 struct clk *clk; /* uart clock */
16150 unsigned short suspended; /* is port suspended? */
16151 int break_active; /* break being received */
16152 +
16153 + short use_dma_rx; /* enable PDC receiver */
16154 + short pdc_rx_idx; /* current PDC RX buffer */
16155 + struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
16156 +
16157 + short use_dma_tx; /* enable PDC transmitter */
16158 + struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
16159 +
16160 + struct tasklet_struct tasklet;
16161 + unsigned int irq_status;
16162 + unsigned int irq_status_prev;
16163 +
16164 + struct circ_buf rx_ring;
16165 };
16166
16167 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
16168 @@ -123,6 +153,38 @@
16169 static struct console atmel_console;
16170 #endif
16171
16172 +static inline struct atmel_uart_port *
16173 +to_atmel_uart_port(struct uart_port *uart)
16174 +{
16175 + return container_of(uart, struct atmel_uart_port, uart);
16176 +}
16177 +
16178 +#ifdef CONFIG_SERIAL_ATMEL_PDC
16179 +static bool atmel_use_dma_rx(struct uart_port *port)
16180 +{
16181 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16182 +
16183 + return atmel_port->use_dma_rx;
16184 +}
16185 +
16186 +static bool atmel_use_dma_tx(struct uart_port *port)
16187 +{
16188 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16189 +
16190 + return atmel_port->use_dma_tx;
16191 +}
16192 +#else
16193 +static bool atmel_use_dma_rx(struct uart_port *port)
16194 +{
16195 + return false;
16196 +}
16197 +
16198 +static bool atmel_use_dma_tx(struct uart_port *port)
16199 +{
16200 + return false;
16201 +}
16202 +#endif
16203 +
16204 /*
16205 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
16206 */
16207 @@ -142,8 +204,8 @@
16208 #ifdef CONFIG_ARCH_AT91RM9200
16209 if (cpu_is_at91rm9200()) {
16210 /*
16211 - * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
16212 - * We need to drive the pin manually.
16213 + * AT91RM9200 Errata #39: RTS0 is not internally connected
16214 + * to PA21. We need to drive the pin manually.
16215 */
16216 if (port->mapbase == AT91RM9200_BASE_US0) {
16217 if (mctrl & TIOCM_RTS)
16218 @@ -204,7 +266,12 @@
16219 */
16220 static void atmel_stop_tx(struct uart_port *port)
16221 {
16222 - UART_PUT_IDR(port, ATMEL_US_TXRDY);
16223 + if (atmel_use_dma_tx(port)) {
16224 + /* disable PDC transmit */
16225 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
16226 + UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
16227 + } else
16228 + UART_PUT_IDR(port, ATMEL_US_TXRDY);
16229 }
16230
16231 /*
16232 @@ -212,7 +279,17 @@
16233 */
16234 static void atmel_start_tx(struct uart_port *port)
16235 {
16236 - UART_PUT_IER(port, ATMEL_US_TXRDY);
16237 + if (atmel_use_dma_tx(port)) {
16238 + if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
16239 + /* The transmitter is already running. Yes, we
16240 + really need this.*/
16241 + return;
16242 +
16243 + UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
16244 + /* re-enable PDC transmit */
16245 + UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
16246 + } else
16247 + UART_PUT_IER(port, ATMEL_US_TXRDY);
16248 }
16249
16250 /*
16251 @@ -220,7 +297,12 @@
16252 */
16253 static void atmel_stop_rx(struct uart_port *port)
16254 {
16255 - UART_PUT_IDR(port, ATMEL_US_RXRDY);
16256 + if (atmel_use_dma_rx(port)) {
16257 + /* disable PDC receive */
16258 + UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
16259 + UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
16260 + } else
16261 + UART_PUT_IDR(port, ATMEL_US_RXRDY);
16262 }
16263
16264 /*
16265 @@ -228,7 +310,8 @@
16266 */
16267 static void atmel_enable_ms(struct uart_port *port)
16268 {
16269 - UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
16270 + UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
16271 + | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
16272 }
16273
16274 /*
16275 @@ -243,22 +326,63 @@
16276 }
16277
16278 /*
16279 + * Stores the incoming character in the ring buffer
16280 + */
16281 +static void
16282 +atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
16283 + unsigned int ch)
16284 +{
16285 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16286 + struct circ_buf *ring = &atmel_port->rx_ring;
16287 + struct atmel_uart_char *c;
16288 +
16289 + if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
16290 + /* Buffer overflow, ignore char */
16291 + return;
16292 +
16293 + c = &((struct atmel_uart_char *)ring->buf)[ring->head];
16294 + c->status = status;
16295 + c->ch = ch;
16296 +
16297 + /* Make sure the character is stored before we update head. */
16298 + smp_wmb();
16299 +
16300 + ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
16301 +}
16302 +
16303 +/*
16304 + * Deal with parity, framing and overrun errors.
16305 + */
16306 +static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
16307 +{
16308 + /* clear error */
16309 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
16310 +
16311 + if (status & ATMEL_US_RXBRK) {
16312 + /* ignore side-effect */
16313 + status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
16314 + port->icount.brk++;
16315 + }
16316 + if (status & ATMEL_US_PARE)
16317 + port->icount.parity++;
16318 + if (status & ATMEL_US_FRAME)
16319 + port->icount.frame++;
16320 + if (status & ATMEL_US_OVRE)
16321 + port->icount.overrun++;
16322 +}
16323 +
16324 +/*
16325 * Characters received (called from interrupt handler)
16326 */
16327 static void atmel_rx_chars(struct uart_port *port)
16328 {
16329 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
16330 - struct tty_struct *tty = port->info->tty;
16331 - unsigned int status, ch, flg;
16332 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16333 + unsigned int status, ch;
16334
16335 status = UART_GET_CSR(port);
16336 while (status & ATMEL_US_RXRDY) {
16337 ch = UART_GET_CHAR(port);
16338
16339 - port->icount.rx++;
16340 -
16341 - flg = TTY_NORMAL;
16342 -
16343 /*
16344 * note that the error handling code is
16345 * out of the main execution path
16346 @@ -266,15 +390,14 @@
16347 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
16348 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
16349 || atmel_port->break_active)) {
16350 - UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
16351 +
16352 + /* clear error */
16353 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
16354 +
16355 if (status & ATMEL_US_RXBRK
16356 && !atmel_port->break_active) {
16357 - status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
16358 - port->icount.brk++;
16359 atmel_port->break_active = 1;
16360 UART_PUT_IER(port, ATMEL_US_RXBRK);
16361 - if (uart_handle_break(port))
16362 - goto ignore_char;
16363 } else {
16364 /*
16365 * This is either the end-of-break
16366 @@ -287,52 +410,30 @@
16367 status &= ~ATMEL_US_RXBRK;
16368 atmel_port->break_active = 0;
16369 }
16370 - if (status & ATMEL_US_PARE)
16371 - port->icount.parity++;
16372 - if (status & ATMEL_US_FRAME)
16373 - port->icount.frame++;
16374 - if (status & ATMEL_US_OVRE)
16375 - port->icount.overrun++;
16376 -
16377 - status &= port->read_status_mask;
16378 -
16379 - if (status & ATMEL_US_RXBRK)
16380 - flg = TTY_BREAK;
16381 - else if (status & ATMEL_US_PARE)
16382 - flg = TTY_PARITY;
16383 - else if (status & ATMEL_US_FRAME)
16384 - flg = TTY_FRAME;
16385 }
16386
16387 - if (uart_handle_sysrq_char(port, ch))
16388 - goto ignore_char;
16389 -
16390 - uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg);
16391 -
16392 - ignore_char:
16393 + atmel_buffer_rx_char(port, status, ch);
16394 status = UART_GET_CSR(port);
16395 }
16396
16397 - tty_flip_buffer_push(tty);
16398 + tasklet_schedule(&atmel_port->tasklet);
16399 }
16400
16401 /*
16402 - * Transmit characters (called from interrupt handler)
16403 + * Transmit characters (called from tasklet with TXRDY interrupt
16404 + * disabled)
16405 */
16406 static void atmel_tx_chars(struct uart_port *port)
16407 {
16408 struct circ_buf *xmit = &port->info->xmit;
16409
16410 - if (port->x_char) {
16411 + if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
16412 UART_PUT_CHAR(port, port->x_char);
16413 port->icount.tx++;
16414 port->x_char = 0;
16415 - return;
16416 }
16417 - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
16418 - atmel_stop_tx(port);
16419 + if (uart_circ_empty(xmit) || uart_tx_stopped(port))
16420 return;
16421 - }
16422
16423 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
16424 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
16425 @@ -345,8 +446,88 @@
16426 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
16427 uart_write_wakeup(port);
16428
16429 - if (uart_circ_empty(xmit))
16430 - atmel_stop_tx(port);
16431 + if (!uart_circ_empty(xmit))
16432 + UART_PUT_IER(port, ATMEL_US_TXRDY);
16433 +}
16434 +
16435 +/*
16436 + * receive interrupt handler.
16437 + */
16438 +static void
16439 +atmel_handle_receive(struct uart_port *port, unsigned int pending)
16440 +{
16441 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16442 +
16443 + if (atmel_use_dma_rx(port)) {
16444 + /*
16445 + * PDC receive. Just schedule the tasklet and let it
16446 + * figure out the details.
16447 + *
16448 + * TODO: We're not handling error flags correctly at
16449 + * the moment.
16450 + */
16451 + if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
16452 + UART_PUT_IDR(port, (ATMEL_US_ENDRX
16453 + | ATMEL_US_TIMEOUT));
16454 + tasklet_schedule(&atmel_port->tasklet);
16455 + }
16456 +
16457 + if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
16458 + ATMEL_US_FRAME | ATMEL_US_PARE))
16459 + atmel_pdc_rxerr(port, pending);
16460 + }
16461 +
16462 + /* Interrupt receive */
16463 + if (pending & ATMEL_US_RXRDY)
16464 + atmel_rx_chars(port);
16465 + else if (pending & ATMEL_US_RXBRK) {
16466 + /*
16467 + * End of break detected. If it came along with a
16468 + * character, atmel_rx_chars will handle it.
16469 + */
16470 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
16471 + UART_PUT_IDR(port, ATMEL_US_RXBRK);
16472 + atmel_port->break_active = 0;
16473 + }
16474 +}
16475 +
16476 +/*
16477 + * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
16478 + */
16479 +static void
16480 +atmel_handle_transmit(struct uart_port *port, unsigned int pending)
16481 +{
16482 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16483 +
16484 + if (atmel_use_dma_tx(port)) {
16485 + /* PDC transmit */
16486 + if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
16487 + UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
16488 + tasklet_schedule(&atmel_port->tasklet);
16489 + }
16490 + } else {
16491 + /* Interrupt transmit */
16492 + if (pending & ATMEL_US_TXRDY) {
16493 + UART_PUT_IDR(port, ATMEL_US_TXRDY);
16494 + tasklet_schedule(&atmel_port->tasklet);
16495 + }
16496 + }
16497 +}
16498 +
16499 +/*
16500 + * status flags interrupt handler.
16501 + */
16502 +static void
16503 +atmel_handle_status(struct uart_port *port, unsigned int pending,
16504 + unsigned int status)
16505 +{
16506 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16507 +
16508 + if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
16509 + | ATMEL_US_CTSIC)) {
16510 + atmel_port->irq_status = status;
16511 + tasklet_schedule(&atmel_port->tasklet);
16512 + }
16513 }
16514
16515 /*
16516 @@ -355,47 +536,255 @@
16517 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
16518 {
16519 struct uart_port *port = dev_id;
16520 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
16521 unsigned int status, pending, pass_counter = 0;
16522
16523 - status = UART_GET_CSR(port);
16524 - pending = status & UART_GET_IMR(port);
16525 - while (pending) {
16526 - /* Interrupt receive */
16527 - if (pending & ATMEL_US_RXRDY)
16528 - atmel_rx_chars(port);
16529 - else if (pending & ATMEL_US_RXBRK) {
16530 + do {
16531 + status = UART_GET_CSR(port);
16532 + pending = status & UART_GET_IMR(port);
16533 + if (!pending)
16534 + break;
16535 +
16536 + atmel_handle_receive(port, pending);
16537 + atmel_handle_status(port, pending, status);
16538 + atmel_handle_transmit(port, pending);
16539 + } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
16540 +
16541 + return IRQ_HANDLED;
16542 +}
16543 +
16544 +/*
16545 + * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
16546 + */
16547 +static void atmel_tx_dma(struct uart_port *port)
16548 +{
16549 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16550 + struct circ_buf *xmit = &port->info->xmit;
16551 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
16552 + int count;
16553 +
16554 + xmit->tail += pdc->ofs;
16555 + xmit->tail &= UART_XMIT_SIZE - 1;
16556 +
16557 + port->icount.tx += pdc->ofs;
16558 + pdc->ofs = 0;
16559 +
16560 + if (!uart_circ_empty(xmit)) {
16561 + /* more to transmit - setup next transfer */
16562 +
16563 + /* disable PDC transmit */
16564 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
16565 + dma_sync_single_for_device(port->dev,
16566 + pdc->dma_addr,
16567 + pdc->dma_size,
16568 + DMA_TO_DEVICE);
16569 +
16570 + count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
16571 + pdc->ofs = count;
16572 +
16573 + UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
16574 + UART_PUT_TCR(port, count);
16575 + /* re-enable PDC transmit and interrupts */
16576 + UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
16577 + UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
16578 + } else {
16579 + /* nothing left to transmit - disable the transmitter */
16580 +
16581 + /* disable PDC transmit */
16582 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
16583 + }
16584 +
16585 + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
16586 + uart_write_wakeup(port);
16587 +}
16588 +
16589 +static void atmel_rx_from_ring(struct uart_port *port)
16590 +{
16591 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16592 + struct circ_buf *ring = &atmel_port->rx_ring;
16593 + unsigned int flg;
16594 + unsigned int status;
16595 +
16596 + while (ring->head != ring->tail) {
16597 + struct atmel_uart_char c;
16598 +
16599 + /* Make sure c is loaded after head. */
16600 + smp_rmb();
16601 +
16602 + c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
16603 +
16604 + ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
16605 +
16606 + port->icount.rx++;
16607 + status = c.status;
16608 + flg = TTY_NORMAL;
16609 +
16610 + /*
16611 + * note that the error handling code is
16612 + * out of the main execution path
16613 + */
16614 + if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
16615 + | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
16616 + if (status & ATMEL_US_RXBRK) {
16617 + /* ignore side-effect */
16618 + status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
16619 +
16620 + port->icount.brk++;
16621 + if (uart_handle_break(port))
16622 + continue;
16623 + }
16624 + if (status & ATMEL_US_PARE)
16625 + port->icount.parity++;
16626 + if (status & ATMEL_US_FRAME)
16627 + port->icount.frame++;
16628 + if (status & ATMEL_US_OVRE)
16629 + port->icount.overrun++;
16630 +
16631 + status &= port->read_status_mask;
16632 +
16633 + if (status & ATMEL_US_RXBRK)
16634 + flg = TTY_BREAK;
16635 + else if (status & ATMEL_US_PARE)
16636 + flg = TTY_PARITY;
16637 + else if (status & ATMEL_US_FRAME)
16638 + flg = TTY_FRAME;
16639 + }
16640 +
16641 +
16642 + if (uart_handle_sysrq_char(port, c.ch))
16643 + continue;
16644 +
16645 + uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
16646 + }
16647 +
16648 + /*
16649 + * Drop the lock here since it might end up calling
16650 + * uart_start(), which takes the lock.
16651 + */
16652 + spin_unlock(&port->lock);
16653 + tty_flip_buffer_push(port->info->tty);
16654 + spin_lock(&port->lock);
16655 +}
16656 +
16657 +static void atmel_rx_from_dma(struct uart_port *port)
16658 +{
16659 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16660 + struct tty_struct *tty = port->info->tty;
16661 + struct atmel_dma_buffer *pdc;
16662 + int rx_idx = atmel_port->pdc_rx_idx;
16663 + unsigned int head;
16664 + unsigned int tail;
16665 + unsigned int count;
16666 +
16667 + do {
16668 + /* Reset the UART timeout early so that we don't miss one */
16669 + UART_PUT_CR(port, ATMEL_US_STTTO);
16670 +
16671 + pdc = &atmel_port->pdc_rx[rx_idx];
16672 + head = UART_GET_RPR(port) - pdc->dma_addr;
16673 + tail = pdc->ofs;
16674 +
16675 + /* If the PDC has switched buffers, RPR won't contain
16676 + * any address within the current buffer. Since head
16677 + * is unsigned, we just need a one-way comparison to
16678 + * find out.
16679 + *
16680 + * In this case, we just need to consume the entire
16681 + * buffer and resubmit it for DMA. This will clear the
16682 + * ENDRX bit as well, so that we can safely re-enable
16683 + * all interrupts below.
16684 + */
16685 + head = min(head, pdc->dma_size);
16686 +
16687 + if (likely(head != tail)) {
16688 + dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
16689 + pdc->dma_size, DMA_FROM_DEVICE);
16690 +
16691 /*
16692 - * End of break detected. If it came along
16693 - * with a character, atmel_rx_chars will
16694 - * handle it.
16695 + * head will only wrap around when we recycle
16696 + * the DMA buffer, and when that happens, we
16697 + * explicitly set tail to 0. So head will
16698 + * always be greater than tail.
16699 */
16700 - UART_PUT_CR(port, ATMEL_US_RSTSTA);
16701 - UART_PUT_IDR(port, ATMEL_US_RXBRK);
16702 - atmel_port->break_active = 0;
16703 + count = head - tail;
16704 +
16705 + tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
16706 +
16707 + dma_sync_single_for_device(port->dev, pdc->dma_addr,
16708 + pdc->dma_size, DMA_FROM_DEVICE);
16709 +
16710 + port->icount.rx += count;
16711 + pdc->ofs = head;
16712 + }
16713 +
16714 + /*
16715 + * If the current buffer is full, we need to check if
16716 + * the next one contains any additional data.
16717 + */
16718 + if (head >= pdc->dma_size) {
16719 + pdc->ofs = 0;
16720 + UART_PUT_RNPR(port, pdc->dma_addr);
16721 + UART_PUT_RNCR(port, pdc->dma_size);
16722 +
16723 + rx_idx = !rx_idx;
16724 + atmel_port->pdc_rx_idx = rx_idx;
16725 }
16726 + } while (head >= pdc->dma_size);
16727 +
16728 + /*
16729 + * Drop the lock here since it might end up calling
16730 + * uart_start(), which takes the lock.
16731 + */
16732 + spin_unlock(&port->lock);
16733 + tty_flip_buffer_push(tty);
16734 + spin_lock(&port->lock);
16735 +
16736 + UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
16737 +}
16738
16739 - // TODO: All reads to CSR will clear these interrupts!
16740 - if (pending & ATMEL_US_RIIC) port->icount.rng++;
16741 - if (pending & ATMEL_US_DSRIC) port->icount.dsr++;
16742 - if (pending & ATMEL_US_DCDIC)
16743 +/*
16744 + * tasklet handling tty stuff outside the interrupt handler.
16745 + */
16746 +static void atmel_tasklet_func(unsigned long data)
16747 +{
16748 + struct uart_port *port = (struct uart_port *)data;
16749 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16750 + unsigned int status;
16751 + unsigned int status_change;
16752 +
16753 + /* The interrupt handler does not take the lock */
16754 + spin_lock(&port->lock);
16755 +
16756 + if (atmel_use_dma_tx(port))
16757 + atmel_tx_dma(port);
16758 + else
16759 + atmel_tx_chars(port);
16760 +
16761 + status = atmel_port->irq_status;
16762 + status_change = status ^ atmel_port->irq_status_prev;
16763 +
16764 + if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
16765 + | ATMEL_US_DCD | ATMEL_US_CTS)) {
16766 + /* TODO: All reads to CSR will clear these interrupts! */
16767 + if (status_change & ATMEL_US_RI)
16768 + port->icount.rng++;
16769 + if (status_change & ATMEL_US_DSR)
16770 + port->icount.dsr++;
16771 + if (status_change & ATMEL_US_DCD)
16772 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
16773 - if (pending & ATMEL_US_CTSIC)
16774 + if (status_change & ATMEL_US_CTS)
16775 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
16776 - if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
16777 - wake_up_interruptible(&port->info->delta_msr_wait);
16778 -
16779 - /* Interrupt transmit */
16780 - if (pending & ATMEL_US_TXRDY)
16781 - atmel_tx_chars(port);
16782
16783 - if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
16784 - break;
16785 + wake_up_interruptible(&port->info->delta_msr_wait);
16786
16787 - status = UART_GET_CSR(port);
16788 - pending = status & UART_GET_IMR(port);
16789 + atmel_port->irq_status_prev = status;
16790 }
16791 - return IRQ_HANDLED;
16792 +
16793 + if (atmel_use_dma_rx(port))
16794 + atmel_rx_from_dma(port);
16795 + else
16796 + atmel_rx_from_ring(port);
16797 +
16798 + spin_unlock(&port->lock);
16799 }
16800
16801 /*
16802 @@ -403,6 +792,8 @@
16803 */
16804 static int atmel_startup(struct uart_port *port)
16805 {
16806 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16807 + struct tty_struct *tty = port->info->tty;
16808 int retval;
16809
16810 /*
16811 @@ -415,13 +806,64 @@
16812 /*
16813 * Allocate the IRQ
16814 */
16815 - retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port);
16816 + retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
16817 + tty ? tty->name : "atmel_serial", port);
16818 if (retval) {
16819 printk("atmel_serial: atmel_startup - Can't get irq\n");
16820 return retval;
16821 }
16822
16823 /*
16824 + * Initialize DMA (if necessary)
16825 + */
16826 + if (atmel_use_dma_rx(port)) {
16827 + int i;
16828 +
16829 + for (i = 0; i < 2; i++) {
16830 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
16831 +
16832 + pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
16833 + if (pdc->buf == NULL) {
16834 + if (i != 0) {
16835 + dma_unmap_single(port->dev,
16836 + atmel_port->pdc_rx[0].dma_addr,
16837 + PDC_BUFFER_SIZE,
16838 + DMA_FROM_DEVICE);
16839 + kfree(atmel_port->pdc_rx[0].buf);
16840 + }
16841 + free_irq(port->irq, port);
16842 + return -ENOMEM;
16843 + }
16844 + pdc->dma_addr = dma_map_single(port->dev,
16845 + pdc->buf,
16846 + PDC_BUFFER_SIZE,
16847 + DMA_FROM_DEVICE);
16848 + pdc->dma_size = PDC_BUFFER_SIZE;
16849 + pdc->ofs = 0;
16850 + }
16851 +
16852 + atmel_port->pdc_rx_idx = 0;
16853 +
16854 + UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
16855 + UART_PUT_RCR(port, PDC_BUFFER_SIZE);
16856 +
16857 + UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
16858 + UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
16859 + }
16860 + if (atmel_use_dma_tx(port)) {
16861 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
16862 + struct circ_buf *xmit = &port->info->xmit;
16863 +
16864 + pdc->buf = xmit->buf;
16865 + pdc->dma_addr = dma_map_single(port->dev,
16866 + pdc->buf,
16867 + UART_XMIT_SIZE,
16868 + DMA_TO_DEVICE);
16869 + pdc->dma_size = UART_XMIT_SIZE;
16870 + pdc->ofs = 0;
16871 + }
16872 +
16873 + /*
16874 * If there is a specific "open" function (to register
16875 * control line interrupts)
16876 */
16877 @@ -437,9 +879,21 @@
16878 * Finally, enable the serial port
16879 */
16880 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
16881 - UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
16882 + /* enable xmit & rcvr */
16883 + UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
16884
16885 - UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
16886 + if (atmel_use_dma_rx(port)) {
16887 + /* set UART timeout */
16888 + UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
16889 + UART_PUT_CR(port, ATMEL_US_STTTO);
16890 +
16891 + UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
16892 + /* enable PDC controller */
16893 + UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
16894 + } else {
16895 + /* enable receive only */
16896 + UART_PUT_IER(port, ATMEL_US_RXRDY);
16897 + }
16898
16899 return 0;
16900 }
16901 @@ -449,6 +903,38 @@
16902 */
16903 static void atmel_shutdown(struct uart_port *port)
16904 {
16905 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16906 + /*
16907 + * Ensure everything is stopped.
16908 + */
16909 + atmel_stop_rx(port);
16910 + atmel_stop_tx(port);
16911 +
16912 + /*
16913 + * Shut-down the DMA.
16914 + */
16915 + if (atmel_use_dma_rx(port)) {
16916 + int i;
16917 +
16918 + for (i = 0; i < 2; i++) {
16919 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
16920 +
16921 + dma_unmap_single(port->dev,
16922 + pdc->dma_addr,
16923 + pdc->dma_size,
16924 + DMA_FROM_DEVICE);
16925 + kfree(pdc->buf);
16926 + }
16927 + }
16928 + if (atmel_use_dma_tx(port)) {
16929 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
16930 +
16931 + dma_unmap_single(port->dev,
16932 + pdc->dma_addr,
16933 + pdc->dma_size,
16934 + DMA_TO_DEVICE);
16935 + }
16936 +
16937 /*
16938 * Disable all interrupts, port and break condition.
16939 */
16940 @@ -471,45 +957,48 @@
16941 /*
16942 * Power / Clock management.
16943 */
16944 -static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
16945 +static void atmel_serial_pm(struct uart_port *port, unsigned int state,
16946 + unsigned int oldstate)
16947 {
16948 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
16949 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
16950
16951 switch (state) {
16952 - case 0:
16953 - /*
16954 - * Enable the peripheral clock for this serial port.
16955 - * This is called on uart_open() or a resume event.
16956 - */
16957 - clk_enable(atmel_port->clk);
16958 - break;
16959 - case 3:
16960 - /*
16961 - * Disable the peripheral clock for this serial port.
16962 - * This is called on uart_close() or a suspend event.
16963 - */
16964 - clk_disable(atmel_port->clk);
16965 - break;
16966 - default:
16967 - printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
16968 + case 0:
16969 + /*
16970 + * Enable the peripheral clock for this serial port.
16971 + * This is called on uart_open() or a resume event.
16972 + */
16973 + clk_enable(atmel_port->clk);
16974 + break;
16975 + case 3:
16976 + /*
16977 + * Disable the peripheral clock for this serial port.
16978 + * This is called on uart_close() or a suspend event.
16979 + */
16980 + clk_disable(atmel_port->clk);
16981 + break;
16982 + default:
16983 + printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
16984 }
16985 }
16986
16987 /*
16988 * Change the port parameters
16989 */
16990 -static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
16991 +static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
16992 + struct ktermios *old)
16993 {
16994 unsigned long flags;
16995 unsigned int mode, imr, quot, baud;
16996
16997 /* Get current mode register */
16998 - mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
16999 + mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
17000 + | ATMEL_US_NBSTOP | ATMEL_US_PAR);
17001
17002 - baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
17003 + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
17004 quot = uart_get_divisor(port, baud);
17005
17006 - if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
17007 + if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
17008 quot /= 8;
17009 mode |= ATMEL_US_USCLKS_MCK_DIV8;
17010 }
17011 @@ -536,18 +1025,17 @@
17012
17013 /* parity */
17014 if (termios->c_cflag & PARENB) {
17015 - if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
17016 + /* Mark or Space parity */
17017 + if (termios->c_cflag & CMSPAR) {
17018 if (termios->c_cflag & PARODD)
17019 mode |= ATMEL_US_PAR_MARK;
17020 else
17021 mode |= ATMEL_US_PAR_SPACE;
17022 - }
17023 - else if (termios->c_cflag & PARODD)
17024 + } else if (termios->c_cflag & PARODD)
17025 mode |= ATMEL_US_PAR_ODD;
17026 else
17027 mode |= ATMEL_US_PAR_EVEN;
17028 - }
17029 - else
17030 + } else
17031 mode |= ATMEL_US_PAR_NONE;
17032
17033 spin_lock_irqsave(&port->lock, flags);
17034 @@ -558,6 +1046,10 @@
17035 if (termios->c_iflag & (BRKINT | PARMRK))
17036 port->read_status_mask |= ATMEL_US_RXBRK;
17037
17038 + if (atmel_use_dma_rx(port))
17039 + /* need to enable error interrupts */
17040 + UART_PUT_IER(port, port->read_status_mask);
17041 +
17042 /*
17043 * Characters to ignore
17044 */
17045 @@ -573,16 +1065,16 @@
17046 if (termios->c_iflag & IGNPAR)
17047 port->ignore_status_mask |= ATMEL_US_OVRE;
17048 }
17049 -
17050 - // TODO: Ignore all characters if CREAD is set.
17051 + /* TODO: Ignore all characters if CREAD is set.*/
17052
17053 /* update the per-port timeout */
17054 uart_update_timeout(port, termios->c_cflag, baud);
17055
17056 - /* disable interrupts and drain transmitter */
17057 - imr = UART_GET_IMR(port); /* get interrupt mask */
17058 - UART_PUT_IDR(port, -1); /* disable all interrupts */
17059 - while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); }
17060 + /* save/disable interrupts and drain transmitter */
17061 + imr = UART_GET_IMR(port);
17062 + UART_PUT_IDR(port, -1);
17063 + while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
17064 + cpu_relax();
17065
17066 /* disable receiver and transmitter */
17067 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
17068 @@ -708,7 +1200,8 @@
17069 /*
17070 * Configure the port from the platform device resource info.
17071 */
17072 -static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev)
17073 +static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
17074 + struct platform_device *pdev)
17075 {
17076 struct uart_port *port = &atmel_port->uart;
17077 struct atmel_uart_data *data = pdev->dev.platform_data;
17078 @@ -723,6 +1216,11 @@
17079 port->mapbase = pdev->resource[0].start;
17080 port->irq = pdev->resource[1].start;
17081
17082 + tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
17083 + (unsigned long)port);
17084 +
17085 + memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
17086 +
17087 if (data->regs)
17088 /* Already mapped by setup code */
17089 port->membase = data->regs;
17090 @@ -731,11 +1229,17 @@
17091 port->membase = NULL;
17092 }
17093
17094 - if (!atmel_port->clk) { /* for console, the clock could already be configured */
17095 + /* for console, the clock could already be configured */
17096 + if (!atmel_port->clk) {
17097 atmel_port->clk = clk_get(&pdev->dev, "usart");
17098 clk_enable(atmel_port->clk);
17099 port->uartclk = clk_get_rate(atmel_port->clk);
17100 }
17101 +
17102 + atmel_port->use_dma_rx = data->use_dma_rx;
17103 + atmel_port->use_dma_tx = data->use_dma_tx;
17104 + if (atmel_use_dma_tx(port))
17105 + port->fifosize = PDC_BUFFER_SIZE;
17106 }
17107
17108 /*
17109 @@ -755,12 +1259,11 @@
17110 atmel_pops.set_wake = fns->set_wake;
17111 }
17112
17113 -
17114 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
17115 static void atmel_console_putchar(struct uart_port *port, int ch)
17116 {
17117 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
17118 - barrier();
17119 + cpu_relax();
17120 UART_PUT_CHAR(port, ch);
17121 }
17122
17123 @@ -773,38 +1276,40 @@
17124 unsigned int status, imr;
17125
17126 /*
17127 - * First, save IMR and then disable interrupts
17128 + * First, save IMR and then disable interrupts
17129 */
17130 - imr = UART_GET_IMR(port); /* get interrupt mask */
17131 + imr = UART_GET_IMR(port);
17132 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
17133
17134 uart_console_write(port, s, count, atmel_console_putchar);
17135
17136 /*
17137 - * Finally, wait for transmitter to become empty
17138 - * and restore IMR
17139 + * Finally, wait for transmitter to become empty
17140 + * and restore IMR
17141 */
17142 do {
17143 status = UART_GET_CSR(port);
17144 } while (!(status & ATMEL_US_TXRDY));
17145 - UART_PUT_IER(port, imr); /* set interrupts back the way they were */
17146 + /* set interrupts back the way they were */
17147 + UART_PUT_IER(port, imr);
17148 }
17149
17150 /*
17151 - * If the port was already initialised (eg, by a boot loader), try to determine
17152 - * the current setup.
17153 + * If the port was already initialised (eg, by a boot loader),
17154 + * try to determine the current setup.
17155 */
17156 -static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
17157 +static void __init atmel_console_get_options(struct uart_port *port, int *baud,
17158 + int *parity, int *bits)
17159 {
17160 unsigned int mr, quot;
17161
17162 -// TODO: CR is a write-only register
17163 -// unsigned int cr;
17164 -//
17165 -// cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN);
17166 -// if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) {
17167 -// /* ok, the port was enabled */
17168 -// }
17169 + /*
17170 + * If the baud rate generator isn't running, the port wasn't
17171 + * initialized by the boot loader.
17172 + */
17173 + quot = UART_GET_BRGR(port);
17174 + if (!quot)
17175 + return;
17176
17177 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
17178 if (mr == ATMEL_US_CHRL_8)
17179 @@ -824,7 +1329,6 @@
17180 * lower than one of those, as it would make us fall through
17181 * to a much lower baud rate than we really want.
17182 */
17183 - quot = UART_GET_BRGR(port);
17184 *baud = port->uartclk / (16 * (quot - 1));
17185 }
17186
17187 @@ -836,10 +1340,12 @@
17188 int parity = 'n';
17189 int flow = 'n';
17190
17191 - if (port->membase == 0) /* Port not initialized yet - delay setup */
17192 + if (port->membase == NULL) {
17193 + /* Port not initialized yet - delay setup */
17194 return -ENODEV;
17195 + }
17196
17197 - UART_PUT_IDR(port, -1); /* disable interrupts */
17198 + UART_PUT_IDR(port, -1);
17199 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
17200 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
17201
17202 @@ -871,13 +1377,16 @@
17203 static int __init atmel_console_init(void)
17204 {
17205 if (atmel_default_console_device) {
17206 - add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL);
17207 - atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device);
17208 + add_preferred_console(ATMEL_DEVICENAME,
17209 + atmel_default_console_device->id, NULL);
17210 + atmel_init_port(&atmel_ports[atmel_default_console_device->id],
17211 + atmel_default_console_device);
17212 register_console(&atmel_console);
17213 }
17214
17215 return 0;
17216 }
17217 +
17218 console_initcall(atmel_console_init);
17219
17220 /*
17221 @@ -885,34 +1394,48 @@
17222 */
17223 static int __init atmel_late_console_init(void)
17224 {
17225 - if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED))
17226 + if (atmel_default_console_device
17227 + && !(atmel_console.flags & CON_ENABLED))
17228 register_console(&atmel_console);
17229
17230 return 0;
17231 }
17232 +
17233 core_initcall(atmel_late_console_init);
17234
17235 +static inline bool atmel_is_console_port(struct uart_port *port)
17236 +{
17237 + return port->cons && port->cons->index == port->line;
17238 +}
17239 +
17240 #else
17241 #define ATMEL_CONSOLE_DEVICE NULL
17242 +
17243 +static inline bool atmel_is_console_port(struct uart_port *port)
17244 +{
17245 + return false;
17246 +}
17247 #endif
17248
17249 static struct uart_driver atmel_uart = {
17250 - .owner = THIS_MODULE,
17251 - .driver_name = "atmel_serial",
17252 - .dev_name = ATMEL_DEVICENAME,
17253 - .major = SERIAL_ATMEL_MAJOR,
17254 - .minor = MINOR_START,
17255 - .nr = ATMEL_MAX_UART,
17256 - .cons = ATMEL_CONSOLE_DEVICE,
17257 + .owner = THIS_MODULE,
17258 + .driver_name = "atmel_serial",
17259 + .dev_name = ATMEL_DEVICENAME,
17260 + .major = SERIAL_ATMEL_MAJOR,
17261 + .minor = MINOR_START,
17262 + .nr = ATMEL_MAX_UART,
17263 + .cons = ATMEL_CONSOLE_DEVICE,
17264 };
17265
17266 #ifdef CONFIG_PM
17267 -static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state)
17268 +static int atmel_serial_suspend(struct platform_device *pdev,
17269 + pm_message_t state)
17270 {
17271 struct uart_port *port = platform_get_drvdata(pdev);
17272 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
17273 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
17274
17275 - if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
17276 + if (device_may_wakeup(&pdev->dev)
17277 + && !at91_suspend_entering_slow_clock())
17278 enable_irq_wake(port->irq);
17279 else {
17280 uart_suspend_port(&atmel_uart, port);
17281 @@ -925,13 +1448,12 @@
17282 static int atmel_serial_resume(struct platform_device *pdev)
17283 {
17284 struct uart_port *port = platform_get_drvdata(pdev);
17285 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
17286 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
17287
17288 if (atmel_port->suspended) {
17289 uart_resume_port(&atmel_uart, port);
17290 atmel_port->suspended = 0;
17291 - }
17292 - else
17293 + } else
17294 disable_irq_wake(port->irq);
17295
17296 return 0;
17297 @@ -944,15 +1466,40 @@
17298 static int __devinit atmel_serial_probe(struct platform_device *pdev)
17299 {
17300 struct atmel_uart_port *port;
17301 + void *data;
17302 int ret;
17303
17304 + BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
17305 +
17306 port = &atmel_ports[pdev->id];
17307 atmel_init_port(port, pdev);
17308
17309 + if (!atmel_use_dma_rx(&port->uart)) {
17310 + ret = -ENOMEM;
17311 + data = kmalloc(sizeof(struct atmel_uart_char)
17312 + * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
17313 + if (!data)
17314 + goto err_alloc_ring;
17315 + port->rx_ring.buf = data;
17316 + }
17317 +
17318 ret = uart_add_one_port(&atmel_uart, &port->uart);
17319 - if (!ret) {
17320 - device_init_wakeup(&pdev->dev, 1);
17321 - platform_set_drvdata(pdev, port);
17322 + if (ret)
17323 + goto err_add_port;
17324 +
17325 + device_init_wakeup(&pdev->dev, 1);
17326 + platform_set_drvdata(pdev, port);
17327 +
17328 + return 0;
17329 +
17330 +err_add_port:
17331 + kfree(port->rx_ring.buf);
17332 + port->rx_ring.buf = NULL;
17333 +err_alloc_ring:
17334 + if (!atmel_is_console_port(&port->uart)) {
17335 + clk_disable(port->clk);
17336 + clk_put(port->clk);
17337 + port->clk = NULL;
17338 }
17339
17340 return ret;
17341 @@ -961,19 +1508,21 @@
17342 static int __devexit atmel_serial_remove(struct platform_device *pdev)
17343 {
17344 struct uart_port *port = platform_get_drvdata(pdev);
17345 - struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
17346 + struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
17347 int ret = 0;
17348
17349 - clk_disable(atmel_port->clk);
17350 - clk_put(atmel_port->clk);
17351 -
17352 device_init_wakeup(&pdev->dev, 0);
17353 platform_set_drvdata(pdev, NULL);
17354
17355 - if (port) {
17356 - ret = uart_remove_one_port(&atmel_uart, port);
17357 - kfree(port);
17358 - }
17359 + ret = uart_remove_one_port(&atmel_uart, port);
17360 +
17361 + tasklet_kill(&atmel_port->tasklet);
17362 + kfree(atmel_port->rx_ring.buf);
17363 +
17364 + /* "port" is allocated statically, so we shouldn't free it */
17365 +
17366 + clk_disable(atmel_port->clk);
17367 + clk_put(atmel_port->clk);
17368
17369 return ret;
17370 }
17371 --- a/drivers/serial/atmel_serial.h
17372 +++ /dev/null
17373 @@ -1,127 +0,0 @@
17374 -/*
17375 - * drivers/serial/atmel_serial.h
17376 - *
17377 - * Copyright (C) 2005 Ivan Kokshaysky
17378 - * Copyright (C) SAN People
17379 - *
17380 - * USART registers.
17381 - * Based on AT91RM9200 datasheet revision E.
17382 - *
17383 - * This program is free software; you can redistribute it and/or modify
17384 - * it under the terms of the GNU General Public License as published by
17385 - * the Free Software Foundation; either version 2 of the License, or
17386 - * (at your option) any later version.
17387 - */
17388 -
17389 -#ifndef ATMEL_SERIAL_H
17390 -#define ATMEL_SERIAL_H
17391 -
17392 -#define ATMEL_US_CR 0x00 /* Control Register */
17393 -#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
17394 -#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
17395 -#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
17396 -#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
17397 -#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
17398 -#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
17399 -#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
17400 -#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
17401 -#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
17402 -#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
17403 -#define ATMEL_US_SENDA (1 << 12) /* Send Address */
17404 -#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
17405 -#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
17406 -#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
17407 -#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
17408 -#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
17409 -#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
17410 -#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
17411 -
17412 -#define ATMEL_US_MR 0x04 /* Mode Register */
17413 -#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
17414 -#define ATMEL_US_USMODE_NORMAL 0
17415 -#define ATMEL_US_USMODE_RS485 1
17416 -#define ATMEL_US_USMODE_HWHS 2
17417 -#define ATMEL_US_USMODE_MODEM 3
17418 -#define ATMEL_US_USMODE_ISO7816_T0 4
17419 -#define ATMEL_US_USMODE_ISO7816_T1 6
17420 -#define ATMEL_US_USMODE_IRDA 8
17421 -#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
17422 -#define ATMEL_US_USCLKS_MCK (0 << 4)
17423 -#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
17424 -#define ATMEL_US_USCLKS_SCK (3 << 4)
17425 -#define ATMEL_US_CHRL (3 << 6) /* Character Length */
17426 -#define ATMEL_US_CHRL_5 (0 << 6)
17427 -#define ATMEL_US_CHRL_6 (1 << 6)
17428 -#define ATMEL_US_CHRL_7 (2 << 6)
17429 -#define ATMEL_US_CHRL_8 (3 << 6)
17430 -#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
17431 -#define ATMEL_US_PAR (7 << 9) /* Parity Type */
17432 -#define ATMEL_US_PAR_EVEN (0 << 9)
17433 -#define ATMEL_US_PAR_ODD (1 << 9)
17434 -#define ATMEL_US_PAR_SPACE (2 << 9)
17435 -#define ATMEL_US_PAR_MARK (3 << 9)
17436 -#define ATMEL_US_PAR_NONE (4 << 9)
17437 -#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
17438 -#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
17439 -#define ATMEL_US_NBSTOP_1 (0 << 12)
17440 -#define ATMEL_US_NBSTOP_1_5 (1 << 12)
17441 -#define ATMEL_US_NBSTOP_2 (2 << 12)
17442 -#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
17443 -#define ATMEL_US_CHMODE_NORMAL (0 << 14)
17444 -#define ATMEL_US_CHMODE_ECHO (1 << 14)
17445 -#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
17446 -#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
17447 -#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
17448 -#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
17449 -#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
17450 -#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
17451 -#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
17452 -#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
17453 -#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
17454 -#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
17455 -
17456 -#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
17457 -#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
17458 -#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
17459 -#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
17460 -#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
17461 -#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
17462 -#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
17463 -#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
17464 -#define ATMEL_US_PARE (1 << 7) /* Parity Error */
17465 -#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
17466 -#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
17467 -#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
17468 -#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
17469 -#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
17470 -#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
17471 -#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
17472 -#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
17473 -#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
17474 -#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
17475 -#define ATMEL_US_RI (1 << 20) /* RI */
17476 -#define ATMEL_US_DSR (1 << 21) /* DSR */
17477 -#define ATMEL_US_DCD (1 << 22) /* DCD */
17478 -#define ATMEL_US_CTS (1 << 23) /* CTS */
17479 -
17480 -#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
17481 -#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
17482 -#define ATMEL_US_CSR 0x14 /* Channel Status Register */
17483 -#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
17484 -#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
17485 -#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
17486 -
17487 -#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
17488 -#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
17489 -
17490 -#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
17491 -#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
17492 -
17493 -#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
17494 -#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
17495 -
17496 -#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
17497 -#define ATMEL_US_NER 0x44 /* Number of Errors Register */
17498 -#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
17499 -
17500 -#endif
17501 --- a/drivers/serial/Kconfig
17502 +++ b/drivers/serial/Kconfig
17503 @@ -380,6 +380,21 @@
17504 console is the device which receives all kernel messages and
17505 warnings and which allows logins in single user mode).
17506
17507 +config SERIAL_ATMEL_PDC
17508 + bool "Support DMA transfers on AT91 / AT32 serial port"
17509 + depends on SERIAL_ATMEL
17510 + default y
17511 + help
17512 + Say Y here if you wish to use the PDC to do DMA transfers to
17513 + and from the Atmel AT91 / AT32 serial port. In order to
17514 + actually use DMA transfers, make sure that the use_dma_tx
17515 + and use_dma_rx members in the atmel_uart_data struct is set
17516 + appropriately for each port.
17517 +
17518 + Note that break and error handling currently doesn't work
17519 + properly when DMA is enabled. Make sure that ports where
17520 + this matters don't use DMA.
17521 +
17522 config SERIAL_ATMEL_TTYAT
17523 bool "Install as device ttyATn instead of ttySn"
17524 depends on SERIAL_ATMEL=y
17525 --- a/drivers/spi/atmel_spi.c
17526 +++ b/drivers/spi/atmel_spi.c
17527 @@ -51,7 +51,9 @@
17528 u8 stopping;
17529 struct list_head queue;
17530 struct spi_transfer *current_transfer;
17531 - unsigned long remaining_bytes;
17532 + unsigned long current_remaining_bytes;
17533 + struct spi_transfer *next_transfer;
17534 + unsigned long next_remaining_bytes;
17535
17536 void *buffer;
17537 dma_addr_t buffer_dma;
17538 @@ -113,6 +115,16 @@
17539 unsigned gpio = (unsigned) spi->controller_data;
17540 unsigned active = spi->mode & SPI_CS_HIGH;
17541 u32 mr;
17542 + int i;
17543 + u32 csr;
17544 + u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
17545 +
17546 + /* Make sure clock polarity is correct */
17547 + for (i = 0; i < spi->master->num_chipselect; i++) {
17548 + csr = spi_readl(as, CSR0 + 4 * i);
17549 + if ((csr ^ cpol) & SPI_BIT(CPOL))
17550 + spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
17551 + }
17552
17553 /* only deactivate *this* device; sometimes transfers to
17554 * another device may be active when this routine is called.
17555 @@ -131,6 +143,48 @@
17556 gpio_set_value(gpio, !active);
17557 }
17558
17559 +static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
17560 + struct spi_transfer *xfer)
17561 +{
17562 + return msg->transfers.prev == &xfer->transfer_list;
17563 +}
17564 +
17565 +static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
17566 +{
17567 + return xfer->delay_usecs == 0 && !xfer->cs_change;
17568 +}
17569 +
17570 +static void atmel_spi_next_xfer_data(struct spi_master *master,
17571 + struct spi_transfer *xfer,
17572 + dma_addr_t *tx_dma,
17573 + dma_addr_t *rx_dma,
17574 + u32 *plen)
17575 +{
17576 + struct atmel_spi *as = spi_master_get_devdata(master);
17577 + u32 len = *plen;
17578 +
17579 + /* use scratch buffer only when rx or tx data is unspecified */
17580 + if (xfer->rx_buf)
17581 + *rx_dma = xfer->rx_dma + xfer->len - len;
17582 + else {
17583 + *rx_dma = as->buffer_dma;
17584 + if (len > BUFFER_SIZE)
17585 + len = BUFFER_SIZE;
17586 + }
17587 + if (xfer->tx_buf)
17588 + *tx_dma = xfer->tx_dma + xfer->len - len;
17589 + else {
17590 + *tx_dma = as->buffer_dma;
17591 + if (len > BUFFER_SIZE)
17592 + len = BUFFER_SIZE;
17593 + memset(as->buffer, 0, len);
17594 + dma_sync_single_for_device(&as->pdev->dev,
17595 + as->buffer_dma, len, DMA_TO_DEVICE);
17596 + }
17597 +
17598 + *plen = len;
17599 +}
17600 +
17601 /*
17602 * Submit next transfer for DMA.
17603 * lock is held, spi irq is blocked
17604 @@ -140,53 +194,78 @@
17605 {
17606 struct atmel_spi *as = spi_master_get_devdata(master);
17607 struct spi_transfer *xfer;
17608 - u32 len;
17609 + u32 len, remaining, total;
17610 dma_addr_t tx_dma, rx_dma;
17611
17612 - xfer = as->current_transfer;
17613 - if (!xfer || as->remaining_bytes == 0) {
17614 - if (xfer)
17615 - xfer = list_entry(xfer->transfer_list.next,
17616 - struct spi_transfer, transfer_list);
17617 - else
17618 - xfer = list_entry(msg->transfers.next,
17619 - struct spi_transfer, transfer_list);
17620 - as->remaining_bytes = xfer->len;
17621 - as->current_transfer = xfer;
17622 + if (!as->current_transfer)
17623 + xfer = list_entry(msg->transfers.next,
17624 + struct spi_transfer, transfer_list);
17625 + else if (!as->next_transfer)
17626 + xfer = list_entry(as->current_transfer->transfer_list.next,
17627 + struct spi_transfer, transfer_list);
17628 + else
17629 + xfer = NULL;
17630 +
17631 + if (xfer) {
17632 + len = xfer->len;
17633 + atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
17634 + remaining = xfer->len - len;
17635 +
17636 + spi_writel(as, RPR, rx_dma);
17637 + spi_writel(as, TPR, tx_dma);
17638 +
17639 + if (msg->spi->bits_per_word > 8)
17640 + len >>= 1;
17641 + spi_writel(as, RCR, len);
17642 + spi_writel(as, TCR, len);
17643 +
17644 + dev_dbg(&msg->spi->dev,
17645 + " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
17646 + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
17647 + xfer->rx_buf, xfer->rx_dma);
17648 + } else {
17649 + xfer = as->next_transfer;
17650 + remaining = as->next_remaining_bytes;
17651 }
17652
17653 - len = as->remaining_bytes;
17654 + as->current_transfer = xfer;
17655 + as->current_remaining_bytes = remaining;
17656
17657 - tx_dma = xfer->tx_dma + xfer->len - len;
17658 - rx_dma = xfer->rx_dma + xfer->len - len;
17659 + if (remaining > 0)
17660 + len = remaining;
17661 + else if (!atmel_spi_xfer_is_last(msg, xfer)
17662 + && atmel_spi_xfer_can_be_chained(xfer)) {
17663 + xfer = list_entry(xfer->transfer_list.next,
17664 + struct spi_transfer, transfer_list);
17665 + len = xfer->len;
17666 + } else
17667 + xfer = NULL;
17668
17669 - /* use scratch buffer only when rx or tx data is unspecified */
17670 - if (!xfer->rx_buf) {
17671 - rx_dma = as->buffer_dma;
17672 - if (len > BUFFER_SIZE)
17673 - len = BUFFER_SIZE;
17674 - }
17675 - if (!xfer->tx_buf) {
17676 - tx_dma = as->buffer_dma;
17677 - if (len > BUFFER_SIZE)
17678 - len = BUFFER_SIZE;
17679 - memset(as->buffer, 0, len);
17680 - dma_sync_single_for_device(&as->pdev->dev,
17681 - as->buffer_dma, len, DMA_TO_DEVICE);
17682 - }
17683 + as->next_transfer = xfer;
17684
17685 - spi_writel(as, RPR, rx_dma);
17686 - spi_writel(as, TPR, tx_dma);
17687 + if (xfer) {
17688 + total = len;
17689 + atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
17690 + as->next_remaining_bytes = total - len;
17691 +
17692 + spi_writel(as, RNPR, rx_dma);
17693 + spi_writel(as, TNPR, tx_dma);
17694 +
17695 + if (msg->spi->bits_per_word > 8)
17696 + len >>= 1;
17697 + spi_writel(as, RNCR, len);
17698 + spi_writel(as, TNCR, len);
17699 +
17700 + dev_dbg(&msg->spi->dev,
17701 + " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
17702 + xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
17703 + xfer->rx_buf, xfer->rx_dma);
17704 + } else {
17705 + spi_writel(as, RNCR, 0);
17706 + spi_writel(as, TNCR, 0);
17707 + }
17708
17709 - as->remaining_bytes -= len;
17710 - if (msg->spi->bits_per_word > 8)
17711 - len >>= 1;
17712 -
17713 - /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
17714 - * mechanism might help avoid the IRQ latency between transfers
17715 - * (and improve the nCS0 errata handling on at91rm9200 chips)
17716 - *
17717 - * We're also waiting for ENDRX before we start the next
17718 + /* REVISIT: We're waiting for ENDRX before we start the next
17719 * transfer because we need to handle some difficult timing
17720 * issues otherwise. If we wait for ENDTX in one transfer and
17721 * then starts waiting for ENDRX in the next, it's difficult
17722 @@ -196,17 +275,7 @@
17723 *
17724 * It should be doable, though. Just not now...
17725 */
17726 - spi_writel(as, TNCR, 0);
17727 - spi_writel(as, RNCR, 0);
17728 spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
17729 -
17730 - dev_dbg(&msg->spi->dev,
17731 - " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
17732 - xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
17733 - xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
17734 -
17735 - spi_writel(as, RCR, len);
17736 - spi_writel(as, TCR, len);
17737 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
17738 }
17739
17740 @@ -304,6 +373,7 @@
17741 spin_lock(&as->lock);
17742
17743 as->current_transfer = NULL;
17744 + as->next_transfer = NULL;
17745
17746 /* continue if needed */
17747 if (list_empty(&as->queue) || as->stopping)
17748 @@ -387,7 +457,7 @@
17749
17750 spi_writel(as, IDR, pending);
17751
17752 - if (as->remaining_bytes == 0) {
17753 + if (as->current_remaining_bytes == 0) {
17754 msg->actual_length += xfer->len;
17755
17756 if (!msg->is_dma_mapped)
17757 @@ -397,7 +467,7 @@
17758 if (xfer->delay_usecs)
17759 udelay(xfer->delay_usecs);
17760
17761 - if (msg->transfers.prev == &xfer->transfer_list) {
17762 + if (atmel_spi_xfer_is_last(msg, xfer)) {
17763 /* report completed message */
17764 atmel_spi_msg_done(master, as, msg, 0,
17765 xfer->cs_change);
17766 @@ -500,9 +570,14 @@
17767 if (!(spi->mode & SPI_CPHA))
17768 csr |= SPI_BIT(NCPHA);
17769
17770 - /* TODO: DLYBS and DLYBCT */
17771 - csr |= SPI_BF(DLYBS, 10);
17772 - csr |= SPI_BF(DLYBCT, 10);
17773 + /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
17774 + *
17775 + * DLYBCT would add delays between words, slowing down transfers.
17776 + * It could potentially be useful to cope with DMA bottlenecks, but
17777 + * in those cases it's probably best to just use a lower bitrate.
17778 + */
17779 + csr |= SPI_BF(DLYBS, 0);
17780 + csr |= SPI_BF(DLYBCT, 0);
17781
17782 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
17783 npcs_pin = (unsigned int)spi->controller_data;
17784 --- a/drivers/usb/gadget/atmel_usba_udc.c
17785 +++ b/drivers/usb/gadget/atmel_usba_udc.c
17786 @@ -18,6 +18,7 @@
17787 #include <linux/platform_device.h>
17788 #include <linux/usb/ch9.h>
17789 #include <linux/usb/gadget.h>
17790 +#include <linux/usb/atmel_usba_udc.h>
17791 #include <linux/delay.h>
17792
17793 #include <asm/gpio.h>
17794 @@ -27,6 +28,7 @@
17795
17796
17797 static struct usba_udc the_udc;
17798 +static struct usba_ep *usba_ep;
17799
17800 #ifdef CONFIG_USB_GADGET_DEBUG_FS
17801 #include <linux/debugfs.h>
17802 @@ -324,53 +326,6 @@
17803 return 1;
17804 }
17805
17806 -static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
17807 -{
17808 - unsigned long tmp;
17809 -
17810 - DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
17811 - for (; len > 0; len -= 4, buf += 4, fifo += 4) {
17812 - tmp = *(unsigned long *)buf;
17813 - if (len >= 4) {
17814 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
17815 - __raw_writel(tmp, fifo);
17816 - } else {
17817 - do {
17818 - DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
17819 - __raw_writeb(tmp >> 24, fifo);
17820 - fifo++;
17821 - tmp <<= 8;
17822 - } while (--len);
17823 - break;
17824 - }
17825 - }
17826 -}
17827 -
17828 -static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
17829 -{
17830 - union {
17831 - unsigned long *w;
17832 - unsigned char *b;
17833 - } p;
17834 - unsigned long tmp;
17835 -
17836 - DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
17837 - for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
17838 - if (len >= 4) {
17839 - tmp = __raw_readl(fifo);
17840 - *p.w = tmp;
17841 - DBG(DBG_FIFO, " -> %08lx\n", tmp);
17842 - } else {
17843 - do {
17844 - tmp = __raw_readb(fifo);
17845 - *p.b = tmp;
17846 - DBG(DBG_FIFO, " -> %02lx\n", tmp);
17847 - fifo++, p.b++;
17848 - } while (--len);
17849 - }
17850 - }
17851 -}
17852 -
17853 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
17854 {
17855 unsigned int transaction_len;
17856 @@ -387,7 +342,7 @@
17857 ep->ep.name, req, transaction_len,
17858 req->last_transaction ? ", done" : "");
17859
17860 - copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
17861 + memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
17862 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
17863 req->req.actual += transaction_len;
17864 }
17865 @@ -476,7 +431,7 @@
17866 bytecount = req->req.length - req->req.actual;
17867 }
17868
17869 - copy_from_fifo(req->req.buf + req->req.actual,
17870 + memcpy_fromio(req->req.buf + req->req.actual,
17871 ep->fifo, bytecount);
17872 req->req.actual += bytecount;
17873
17874 @@ -1029,33 +984,6 @@
17875 .set_selfpowered = usba_udc_set_selfpowered,
17876 };
17877
17878 -#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
17879 -{ \
17880 - .ep = { \
17881 - .ops = &usba_ep_ops, \
17882 - .name = nam, \
17883 - .maxpacket = maxpkt, \
17884 - }, \
17885 - .udc = &the_udc, \
17886 - .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
17887 - .fifo_size = maxpkt, \
17888 - .nr_banks = maxbk, \
17889 - .index = idx, \
17890 - .can_dma = dma, \
17891 - .can_isoc = isoc, \
17892 -}
17893 -
17894 -static struct usba_ep usba_ep[] = {
17895 - EP("ep0", 0, 64, 1, 0, 0),
17896 - EP("ep1in-bulk", 1, 512, 2, 1, 1),
17897 - EP("ep2out-bulk", 2, 512, 2, 1, 1),
17898 - EP("ep3in-int", 3, 64, 3, 1, 0),
17899 - EP("ep4out-int", 4, 64, 3, 1, 0),
17900 - EP("ep5in-iso", 5, 1024, 3, 1, 1),
17901 - EP("ep6out-iso", 6, 1024, 3, 1, 1),
17902 -};
17903 -#undef EP
17904 -
17905 static struct usb_endpoint_descriptor usba_ep0_desc = {
17906 .bLength = USB_DT_ENDPOINT_SIZE,
17907 .bDescriptorType = USB_DT_ENDPOINT,
17908 @@ -1074,7 +1002,6 @@
17909 static struct usba_udc the_udc = {
17910 .gadget = {
17911 .ops = &usba_udc_ops,
17912 - .ep0 = &usba_ep[0].ep,
17913 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
17914 .is_dualspeed = 1,
17915 .name = "atmel_usba_udc",
17916 @@ -1231,7 +1158,7 @@
17917 } else {
17918 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
17919 usba_writel(udc, TST, USBA_TST_PKT_MODE);
17920 - copy_to_fifo(ep->fifo, test_packet_buffer,
17921 + memcpy_toio(ep->fifo, test_packet_buffer,
17922 sizeof(test_packet_buffer));
17923 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
17924 dev_info(dev, "Entering Test_Packet mode...\n");
17925 @@ -1539,7 +1466,7 @@
17926 }
17927
17928 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
17929 - copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
17930 + memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
17931
17932 /* Free up one bank in the FIFO so that we can
17933 * generate or receive a reply right away. */
17934 @@ -1911,7 +1838,7 @@
17935
17936 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
17937 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
17938 - if (!regs || !fifo)
17939 + if (!regs || !fifo || !pdata)
17940 return -ENXIO;
17941
17942 irq = platform_get_irq(pdev, 0);
17943 @@ -1959,16 +1886,44 @@
17944 usba_writel(udc, CTRL, 0);
17945 clk_disable(pclk);
17946
17947 + usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
17948 + GFP_KERNEL);
17949 + if (!usba_ep)
17950 + goto err_alloc_ep;
17951 +
17952 + the_udc.gadget.ep0 = &usba_ep[0].ep;
17953 +
17954 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
17955 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
17956 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
17957 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
17958 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
17959 + usba_ep[0].ep.ops = &usba_ep_ops;
17960 + usba_ep[0].ep.name = pdata->ep[0].name;
17961 + usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
17962 + usba_ep[0].udc = &the_udc;
17963 + INIT_LIST_HEAD(&usba_ep[0].queue);
17964 + usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
17965 + usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
17966 + usba_ep[0].index = pdata->ep[0].index;
17967 + usba_ep[0].can_dma = pdata->ep[0].can_dma;
17968 + usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
17969 +
17970 + for (i = 1; i < pdata->num_ep; i++) {
17971 struct usba_ep *ep = &usba_ep[i];
17972
17973 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
17974 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
17975 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
17976 + ep->ep.ops = &usba_ep_ops;
17977 + ep->ep.name = pdata->ep[i].name;
17978 + ep->ep.maxpacket = pdata->ep[i].fifo_size;
17979 + ep->udc = &the_udc;
17980 + INIT_LIST_HEAD(&ep->queue);
17981 + ep->fifo_size = pdata->ep[i].fifo_size;
17982 + ep->nr_banks = pdata->ep[i].nr_banks;
17983 + ep->index = pdata->ep[i].index;
17984 + ep->can_dma = pdata->ep[i].can_dma;
17985 + ep->can_isoc = pdata->ep[i].can_isoc;
17986
17987 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
17988 }
17989 @@ -1987,7 +1942,7 @@
17990 goto err_device_add;
17991 }
17992
17993 - if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
17994 + if (pdata->vbus_pin >= 0) {
17995 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
17996 udc->vbus_pin = pdata->vbus_pin;
17997
17998 @@ -2007,7 +1962,7 @@
17999 }
18000
18001 usba_init_debugfs(udc);
18002 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
18003 + for (i = 1; i < pdata->num_ep; i++)
18004 usba_ep_init_debugfs(udc, &usba_ep[i]);
18005
18006 return 0;
18007 @@ -2015,6 +1970,8 @@
18008 err_device_add:
18009 free_irq(irq, udc);
18010 err_request_irq:
18011 + kfree(usba_ep);
18012 +err_alloc_ep:
18013 iounmap(udc->fifo);
18014 err_map_fifo:
18015 iounmap(udc->regs);
18016 @@ -2032,10 +1989,11 @@
18017 {
18018 struct usba_udc *udc;
18019 int i;
18020 + struct usba_platform_data *pdata = pdev->dev.platform_data;
18021
18022 udc = platform_get_drvdata(pdev);
18023
18024 - for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
18025 + for (i = 1; i < pdata->num_ep; i++)
18026 usba_ep_cleanup_debugfs(&usba_ep[i]);
18027 usba_cleanup_debugfs(udc);
18028
18029 --- a/drivers/video/atmel_lcdfb.c
18030 +++ b/drivers/video/atmel_lcdfb.c
18031 @@ -16,6 +16,7 @@
18032 #include <linux/fb.h>
18033 #include <linux/init.h>
18034 #include <linux/delay.h>
18035 +#include <linux/backlight.h>
18036
18037 #include <asm/arch/board.h>
18038 #include <asm/arch/cpu.h>
18039 @@ -37,7 +38,9 @@
18040 #endif
18041
18042 #if defined(CONFIG_ARCH_AT91)
18043 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
18044 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
18045 + | FBINFO_PARTIAL_PAN_OK \
18046 + | FBINFO_HWACCEL_YPAN)
18047
18048 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
18049 struct fb_var_screeninfo *var)
18050 @@ -69,12 +72,113 @@
18051 }
18052 #endif
18053
18054 +static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
18055 + | ATMEL_LCDC_POL_POSITIVE
18056 + | ATMEL_LCDC_ENA_PWMENABLE;
18057 +
18058 +#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
18059 +
18060 +/* some bl->props field just changed */
18061 +static int atmel_bl_update_status(struct backlight_device *bl)
18062 +{
18063 + struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
18064 + int power = sinfo->bl_power;
18065 + int brightness = bl->props.brightness;
18066 +
18067 + /* REVISIT there may be a meaningful difference between
18068 + * fb_blank and power ... there seem to be some cases
18069 + * this doesn't handle correctly.
18070 + */
18071 + if (bl->props.fb_blank != sinfo->bl_power)
18072 + power = bl->props.fb_blank;
18073 + else if (bl->props.power != sinfo->bl_power)
18074 + power = bl->props.power;
18075 +
18076 + if (brightness < 0 && power == FB_BLANK_UNBLANK)
18077 + brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
18078 + else if (power != FB_BLANK_UNBLANK)
18079 + brightness = 0;
18080 +
18081 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
18082 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
18083 + brightness ? contrast_ctr : 0);
18084 +
18085 + bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
18086 +
18087 + return 0;
18088 +}
18089 +
18090 +static int atmel_bl_get_brightness(struct backlight_device *bl)
18091 +{
18092 + struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
18093 +
18094 + return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
18095 +}
18096 +
18097 +static struct backlight_ops atmel_lcdc_bl_ops = {
18098 + .update_status = atmel_bl_update_status,
18099 + .get_brightness = atmel_bl_get_brightness,
18100 +};
18101 +
18102 +static void init_backlight(struct atmel_lcdfb_info *sinfo)
18103 +{
18104 + struct backlight_device *bl;
18105 +
18106 + sinfo->bl_power = FB_BLANK_UNBLANK;
18107 +
18108 + if (sinfo->backlight)
18109 + return;
18110 +
18111 + bl = backlight_device_register("backlight", &sinfo->pdev->dev,
18112 + sinfo, &atmel_lcdc_bl_ops);
18113 + if (IS_ERR(sinfo->backlight)) {
18114 + dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
18115 + PTR_ERR(bl));
18116 + return;
18117 + }
18118 + sinfo->backlight = bl;
18119 +
18120 + bl->props.power = FB_BLANK_UNBLANK;
18121 + bl->props.fb_blank = FB_BLANK_UNBLANK;
18122 + bl->props.max_brightness = 0xff;
18123 + bl->props.brightness = atmel_bl_get_brightness(bl);
18124 +}
18125 +
18126 +static void exit_backlight(struct atmel_lcdfb_info *sinfo)
18127 +{
18128 + if (sinfo->backlight)
18129 + backlight_device_unregister(sinfo->backlight);
18130 +}
18131 +
18132 +#else
18133 +
18134 +static void init_backlight(struct atmel_lcdfb_info *sinfo)
18135 +{
18136 + dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
18137 +}
18138 +
18139 +static void exit_backlight(struct atmel_lcdfb_info *sinfo)
18140 +{
18141 +}
18142 +
18143 +#endif
18144 +
18145 +static void init_contrast(struct atmel_lcdfb_info *sinfo)
18146 +{
18147 + /* have some default contrast/backlight settings */
18148 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
18149 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
18150 +
18151 + if (sinfo->lcdcon_is_backlight)
18152 + init_backlight(sinfo);
18153 +}
18154 +
18155
18156 static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
18157 .type = FB_TYPE_PACKED_PIXELS,
18158 .visual = FB_VISUAL_TRUECOLOR,
18159 .xpanstep = 0,
18160 - .ypanstep = 0,
18161 + .ypanstep = 1,
18162 .ywrapstep = 0,
18163 .accel = FB_ACCEL_NONE,
18164 };
18165 @@ -148,6 +252,8 @@
18166 return -ENOMEM;
18167 }
18168
18169 + memset(info->screen_base, 0, info->fix.smem_len);
18170 +
18171 return 0;
18172 }
18173
18174 @@ -203,6 +309,26 @@
18175 var->transp.offset = var->transp.length = 0;
18176 var->xoffset = var->yoffset = 0;
18177
18178 + /* Saturate vertical and horizontal timings at maximum values */
18179 + var->vsync_len = min_t(u32, var->vsync_len,
18180 + (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
18181 + var->upper_margin = min_t(u32, var->upper_margin,
18182 + ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
18183 + var->lower_margin = min_t(u32, var->lower_margin,
18184 + ATMEL_LCDC_VFP);
18185 + var->right_margin = min_t(u32, var->right_margin,
18186 + (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
18187 + var->hsync_len = min_t(u32, var->hsync_len,
18188 + (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
18189 + var->left_margin = min_t(u32, var->left_margin,
18190 + ATMEL_LCDC_HBP + 1);
18191 +
18192 + /* Some parameters can't be zero */
18193 + var->vsync_len = max_t(u32, var->vsync_len, 1);
18194 + var->right_margin = max_t(u32, var->right_margin, 1);
18195 + var->hsync_len = max_t(u32, var->hsync_len, 1);
18196 + var->left_margin = max_t(u32, var->left_margin, 1);
18197 +
18198 switch (var->bits_per_pixel) {
18199 case 1:
18200 case 2:
18201 @@ -370,10 +496,6 @@
18202 /* Disable all interrupts */
18203 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
18204
18205 - /* Set contrast */
18206 - value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE;
18207 - lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
18208 - lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
18209 /* ...wait for DMA engine to become idle... */
18210 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
18211 msleep(10);
18212 @@ -516,7 +638,6 @@
18213 struct fb_info *info = sinfo->info;
18214 int ret = 0;
18215
18216 - memset_io(info->screen_base, 0, info->fix.smem_len);
18217 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
18218
18219 dev_info(info->device,
18220 @@ -577,6 +698,7 @@
18221 sinfo->default_monspecs = pdata_sinfo->default_monspecs;
18222 sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
18223 sinfo->guard_time = pdata_sinfo->guard_time;
18224 + sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
18225 } else {
18226 dev_err(dev, "cannot get default configuration\n");
18227 goto free_info;
18228 @@ -645,6 +767,11 @@
18229 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
18230 if (!info->screen_base)
18231 goto release_intmem;
18232 +
18233 + /*
18234 + * Don't clear the framebuffer -- someone may have set
18235 + * up a splash image.
18236 + */
18237 } else {
18238 /* alocate memory buffer */
18239 ret = atmel_lcdfb_alloc_video_memory(sinfo);
18240 @@ -670,6 +797,9 @@
18241 goto release_mem;
18242 }
18243
18244 + /* Initialize PWM for contrast or backlight ("off") */
18245 + init_contrast(sinfo);
18246 +
18247 /* interrupt */
18248 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
18249 if (ret) {
18250 @@ -721,6 +851,7 @@
18251 unregister_irqs:
18252 free_irq(sinfo->irq_base, info);
18253 unmap_mmio:
18254 + exit_backlight(sinfo);
18255 iounmap(sinfo->mmio);
18256 release_mem:
18257 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
18258 @@ -755,6 +886,7 @@
18259 if (!sinfo)
18260 return 0;
18261
18262 + exit_backlight(sinfo);
18263 if (sinfo->atmel_lcdfb_power_control)
18264 sinfo->atmel_lcdfb_power_control(0);
18265 unregister_framebuffer(info);
18266 @@ -781,6 +913,9 @@
18267
18268 static struct platform_driver atmel_lcdfb_driver = {
18269 .remove = __exit_p(atmel_lcdfb_remove),
18270 +
18271 +// FIXME need suspend, resume
18272 +
18273 .driver = {
18274 .name = "atmel_lcdfb",
18275 .owner = THIS_MODULE,
18276 --- a/drivers/video/backlight/Kconfig
18277 +++ b/drivers/video/backlight/Kconfig
18278 @@ -50,6 +50,19 @@
18279 To have support for your specific LCD panel you will have to
18280 select the proper drivers which depend on this option.
18281
18282 +config BACKLIGHT_ATMEL_LCDC
18283 + bool "Atmel LCDC Contrast-as-Backlight control"
18284 + depends on BACKLIGHT_CLASS_DEVICE && FB_ATMEL
18285 + default y if MACH_SAM9261EK || MACH_SAM9263EK
18286 + help
18287 + This provides a backlight control internal to the Atmel LCDC
18288 + driver. If the LCD "contrast control" on your board is wired
18289 + so it controls the backlight brightness, select this option to
18290 + export this as a PWM-based backlight control.
18291 +
18292 + If in doubt, it's safe to enable this option; it doesn't kick
18293 + in unless the board's description says it's wired that way.
18294 +
18295 config BACKLIGHT_CORGI
18296 tristate "Generic (aka Sharp Corgi) Backlight Driver"
18297 depends on BACKLIGHT_CLASS_DEVICE
18298 --- a/drivers/video/console/Kconfig
18299 +++ b/drivers/video/console/Kconfig
18300 @@ -6,7 +6,7 @@
18301
18302 config VGA_CONSOLE
18303 bool "VGA text console" if EMBEDDED || !X86
18304 - depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN
18305 + depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32
18306 default y
18307 help
18308 Saying Y here will allow you to use Linux in text mode through a
18309 --- a/drivers/watchdog/Kconfig
18310 +++ b/drivers/watchdog/Kconfig
18311 @@ -223,7 +223,7 @@
18312
18313 config AT32AP700X_WDT
18314 tristate "AT32AP700x watchdog"
18315 - depends on CPU_AT32AP7000
18316 + depends on CPU_AT32AP700X
18317 help
18318 Watchdog timer embedded into AT32AP700x devices. This will reboot
18319 your system when the timeout is reached.
18320 --- a/include/asm-avr32/arch-at32ap/at32ap7000.h
18321 +++ /dev/null
18322 @@ -1,35 +0,0 @@
18323 -/*
18324 - * Pin definitions for AT32AP7000.
18325 - *
18326 - * Copyright (C) 2006 Atmel Corporation
18327 - *
18328 - * This program is free software; you can redistribute it and/or modify
18329 - * it under the terms of the GNU General Public License version 2 as
18330 - * published by the Free Software Foundation.
18331 - */
18332 -#ifndef __ASM_ARCH_AT32AP7000_H__
18333 -#define __ASM_ARCH_AT32AP7000_H__
18334 -
18335 -#define GPIO_PERIPH_A 0
18336 -#define GPIO_PERIPH_B 1
18337 -
18338 -#define NR_GPIO_CONTROLLERS 4
18339 -
18340 -/*
18341 - * Pin numbers identifying specific GPIO pins on the chip. They can
18342 - * also be converted to IRQ numbers by passing them through
18343 - * gpio_to_irq().
18344 - */
18345 -#define GPIO_PIOA_BASE (0)
18346 -#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
18347 -#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
18348 -#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
18349 -#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
18350 -
18351 -#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
18352 -#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
18353 -#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
18354 -#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
18355 -#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
18356 -
18357 -#endif /* __ASM_ARCH_AT32AP7000_H__ */
18358 --- /dev/null
18359 +++ b/include/asm-avr32/arch-at32ap/at32ap700x.h
18360 @@ -0,0 +1,35 @@
18361 +/*
18362 + * Pin definitions for AT32AP7000.
18363 + *
18364 + * Copyright (C) 2006 Atmel Corporation
18365 + *
18366 + * This program is free software; you can redistribute it and/or modify
18367 + * it under the terms of the GNU General Public License version 2 as
18368 + * published by the Free Software Foundation.
18369 + */
18370 +#ifndef __ASM_ARCH_AT32AP700X_H__
18371 +#define __ASM_ARCH_AT32AP700X_H__
18372 +
18373 +#define GPIO_PERIPH_A 0
18374 +#define GPIO_PERIPH_B 1
18375 +
18376 +#define NR_GPIO_CONTROLLERS 4
18377 +
18378 +/*
18379 + * Pin numbers identifying specific GPIO pins on the chip. They can
18380 + * also be converted to IRQ numbers by passing them through
18381 + * gpio_to_irq().
18382 + */
18383 +#define GPIO_PIOA_BASE (0)
18384 +#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
18385 +#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
18386 +#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
18387 +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
18388 +
18389 +#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
18390 +#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
18391 +#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
18392 +#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
18393 +#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
18394 +
18395 +#endif /* __ASM_ARCH_AT32AP700X_H__ */
18396 --- a/include/asm-avr32/arch-at32ap/board.h
18397 +++ b/include/asm-avr32/arch-at32ap/board.h
18398 @@ -38,9 +38,7 @@
18399 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
18400 unsigned long fbmem_start, unsigned long fbmem_len);
18401
18402 -struct usba_platform_data {
18403 - int vbus_pin;
18404 -};
18405 +struct usba_platform_data;
18406 struct platform_device *
18407 at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
18408
18409 @@ -51,6 +49,9 @@
18410 at32_add_device_ide(unsigned int id, unsigned int extint,
18411 struct ide_platform_data *data);
18412
18413 +/* mask says which PWM channels to mux */
18414 +struct platform_device *at32_add_device_pwm(u32 mask);
18415 +
18416 /* depending on what's hooked up, not all SSC pins will be used */
18417 #define ATMEL_SSC_TK 0x01
18418 #define ATMEL_SSC_TF 0x02
18419 @@ -65,8 +66,17 @@
18420 struct platform_device *
18421 at32_add_device_ssc(unsigned int id, unsigned int flags);
18422
18423 -struct platform_device *at32_add_device_twi(unsigned int id);
18424 -struct platform_device *at32_add_device_mci(unsigned int id);
18425 +struct i2c_board_info;
18426 +struct platform_device *at32_add_device_twi(unsigned int id,
18427 + struct i2c_board_info *b,
18428 + unsigned int n);
18429 +
18430 +struct mci_platform_data {
18431 + int detect_pin;
18432 + int wp_pin;
18433 +};
18434 +struct platform_device *
18435 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
18436 struct platform_device *at32_add_device_ac97c(unsigned int id);
18437 struct platform_device *at32_add_device_abdac(unsigned int id);
18438
18439 @@ -81,4 +91,7 @@
18440 at32_add_device_cf(unsigned int id, unsigned int extint,
18441 struct cf_platform_data *data);
18442
18443 +struct platform_device *
18444 +at32_add_device_psif(unsigned int id);
18445 +
18446 #endif /* __ASM_ARCH_BOARD_H */
18447 --- a/include/asm-avr32/arch-at32ap/cpu.h
18448 +++ b/include/asm-avr32/arch-at32ap/cpu.h
18449 @@ -14,7 +14,7 @@
18450 * Only AT32AP7000 is defined for now. We can identify the specific
18451 * chip at runtime, but I'm not sure if it's really worth it.
18452 */
18453 -#ifdef CONFIG_CPU_AT32AP7000
18454 +#ifdef CONFIG_CPU_AT32AP700X
18455 # define cpu_is_at32ap7000() (1)
18456 #else
18457 # define cpu_is_at32ap7000() (0)
18458 --- a/include/asm-avr32/arch-at32ap/io.h
18459 +++ b/include/asm-avr32/arch-at32ap/io.h
18460 @@ -4,7 +4,7 @@
18461 /* For "bizarre" halfword swapping */
18462 #include <linux/byteorder/swabb.h>
18463
18464 -#if defined(CONFIG_AP7000_32_BIT_SMC)
18465 +#if defined(CONFIG_AP700X_32_BIT_SMC)
18466 # define __swizzle_addr_b(addr) (addr ^ 3UL)
18467 # define __swizzle_addr_w(addr) (addr ^ 2UL)
18468 # define __swizzle_addr_l(addr) (addr)
18469 @@ -14,7 +14,7 @@
18470 # define __mem_ioswabb(a, x) (x)
18471 # define __mem_ioswabw(a, x) swab16(x)
18472 # define __mem_ioswabl(a, x) swab32(x)
18473 -#elif defined(CONFIG_AP7000_16_BIT_SMC)
18474 +#elif defined(CONFIG_AP700X_16_BIT_SMC)
18475 # define __swizzle_addr_b(addr) (addr ^ 1UL)
18476 # define __swizzle_addr_w(addr) (addr)
18477 # define __swizzle_addr_l(addr) (addr)
18478 --- /dev/null
18479 +++ b/include/asm-avr32/arch-at32ap/pm.h
18480 @@ -0,0 +1,48 @@
18481 +/*
18482 + * AVR32 AP Power Management.
18483 + *
18484 + * Copyright (C) 2008 Atmel Corporation
18485 + *
18486 + * This program is free software; you can redistribute it and/or modify
18487 + * it under the terms of the GNU General Public License version 2 as
18488 + * published by the Free Software Foundation.
18489 + */
18490 +#ifndef __ASM_AVR32_ARCH_PM_H
18491 +#define __ASM_AVR32_ARCH_PM_H
18492 +
18493 +/* Possible arguments to the "sleep" instruction */
18494 +#define CPU_SLEEP_IDLE 0
18495 +#define CPU_SLEEP_FROZEN 1
18496 +#define CPU_SLEEP_STANDBY 2
18497 +#define CPU_SLEEP_STOP 3
18498 +#define CPU_SLEEP_STATIC 5
18499 +
18500 +#ifndef __ASSEMBLY__
18501 +extern void cpu_enter_idle(void);
18502 +
18503 +extern bool disable_idle_sleep;
18504 +
18505 +static inline void cpu_disable_idle_sleep(void)
18506 +{
18507 + disable_idle_sleep = true;
18508 +}
18509 +
18510 +static inline void cpu_enable_idle_sleep(void)
18511 +{
18512 + disable_idle_sleep = false;
18513 +}
18514 +
18515 +static inline void cpu_idle_sleep(void)
18516 +{
18517 + /*
18518 + * If we're using the COUNT and COMPARE registers for
18519 + * timekeeping, we can't use the IDLE state.
18520 + */
18521 + if (disable_idle_sleep)
18522 + cpu_relax();
18523 + else
18524 + cpu_enter_idle();
18525 +}
18526 +#endif
18527 +
18528 +#endif /* __ASM_AVR32_ARCH_PM_H */
18529 --- a/include/asm-avr32/arch-at32ap/portmux.h
18530 +++ b/include/asm-avr32/arch-at32ap/portmux.h
18531 @@ -26,4 +26,16 @@
18532 void at32_select_gpio(unsigned int pin, unsigned long flags);
18533 void at32_reserve_pin(unsigned int pin);
18534
18535 +#ifdef CONFIG_GPIO_DEV
18536 +
18537 +/* Gang allocators and accessors; used by the GPIO /dev driver */
18538 +int at32_gpio_port_is_valid(unsigned int port);
18539 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
18540 +void at32_deselect_pins(unsigned int port, u32 pins);
18541 +
18542 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
18543 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
18544 +
18545 +#endif /* CONFIG_GPIO_DEV */
18546 +
18547 #endif /* __ASM_ARCH_PORTMUX_H__ */
18548 --- a/include/asm-avr32/arch-at32ap/time.h
18549 +++ /dev/null
18550 @@ -1,112 +0,0 @@
18551 -/*
18552 - * Copyright (C) 2007 Atmel Corporation
18553 - *
18554 - * This program is free software; you can redistribute it and/or modify
18555 - * it under the terms of the GNU General Public License version 2 as
18556 - * published by the Free Software Foundation.
18557 - */
18558 -
18559 -#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
18560 -#define _ASM_AVR32_ARCH_AT32AP_TIME_H
18561 -
18562 -#include <linux/platform_device.h>
18563 -
18564 -extern struct irqaction timer_irqaction;
18565 -extern struct platform_device at32_systc0_device;
18566 -extern void local_timer_interrupt(int irq, void *dev_id);
18567 -
18568 -#define TIMER_BCR 0x000000c0
18569 -#define TIMER_BCR_SYNC 0
18570 -#define TIMER_BMR 0x000000c4
18571 -#define TIMER_BMR_TC0XC0S 0
18572 -#define TIMER_BMR_TC1XC1S 2
18573 -#define TIMER_BMR_TC2XC2S 4
18574 -#define TIMER_CCR 0x00000000
18575 -#define TIMER_CCR_CLKDIS 1
18576 -#define TIMER_CCR_CLKEN 0
18577 -#define TIMER_CCR_SWTRG 2
18578 -#define TIMER_CMR 0x00000004
18579 -#define TIMER_CMR_ABETRG 10
18580 -#define TIMER_CMR_ACPA 16
18581 -#define TIMER_CMR_ACPC 18
18582 -#define TIMER_CMR_AEEVT 20
18583 -#define TIMER_CMR_ASWTRG 22
18584 -#define TIMER_CMR_BCPB 24
18585 -#define TIMER_CMR_BCPC 26
18586 -#define TIMER_CMR_BEEVT 28
18587 -#define TIMER_CMR_BSWTRG 30
18588 -#define TIMER_CMR_BURST 4
18589 -#define TIMER_CMR_CLKI 3
18590 -#define TIMER_CMR_CPCDIS 7
18591 -#define TIMER_CMR_CPCSTOP 6
18592 -#define TIMER_CMR_CPCTRG 14
18593 -#define TIMER_CMR_EEVT 10
18594 -#define TIMER_CMR_EEVTEDG 8
18595 -#define TIMER_CMR_ENETRG 12
18596 -#define TIMER_CMR_ETRGEDG 8
18597 -#define TIMER_CMR_LDBDIS 7
18598 -#define TIMER_CMR_LDBSTOP 6
18599 -#define TIMER_CMR_LDRA 16
18600 -#define TIMER_CMR_LDRB 18
18601 -#define TIMER_CMR_TCCLKS 0
18602 -#define TIMER_CMR_WAVE 15
18603 -#define TIMER_CMR_WAVSEL 13
18604 -#define TIMER_CV 0x00000010
18605 -#define TIMER_CV_CV 0
18606 -#define TIMER_IDR 0x00000028
18607 -#define TIMER_IDR_COVFS 0
18608 -#define TIMER_IDR_CPAS 2
18609 -#define TIMER_IDR_CPBS 3
18610 -#define TIMER_IDR_CPCS 4
18611 -#define TIMER_IDR_ETRGS 7
18612 -#define TIMER_IDR_LDRAS 5
18613 -#define TIMER_IDR_LDRBS 6
18614 -#define TIMER_IDR_LOVRS 1
18615 -#define TIMER_IER 0x00000024
18616 -#define TIMER_IER_COVFS 0
18617 -#define TIMER_IER_CPAS 2
18618 -#define TIMER_IER_CPBS 3
18619 -#define TIMER_IER_CPCS 4
18620 -#define TIMER_IER_ETRGS 7
18621 -#define TIMER_IER_LDRAS 5
18622 -#define TIMER_IER_LDRBS 6
18623 -#define TIMER_IER_LOVRS 1
18624 -#define TIMER_IMR 0x0000002c
18625 -#define TIMER_IMR_COVFS 0
18626 -#define TIMER_IMR_CPAS 2
18627 -#define TIMER_IMR_CPBS 3
18628 -#define TIMER_IMR_CPCS 4
18629 -#define TIMER_IMR_ETRGS 7
18630 -#define TIMER_IMR_LDRAS 5
18631 -#define TIMER_IMR_LDRBS 6
18632 -#define TIMER_IMR_LOVRS 1
18633 -#define TIMER_RA 0x00000014
18634 -#define TIMER_RA_RA 0
18635 -#define TIMER_RB 0x00000018
18636 -#define TIMER_RB_RB 0
18637 -#define TIMER_RC 0x0000001c
18638 -#define TIMER_RC_RC 0
18639 -#define TIMER_SR 0x00000020
18640 -#define TIMER_SR_CLKSTA 16
18641 -#define TIMER_SR_COVFS 0
18642 -#define TIMER_SR_CPAS 2
18643 -#define TIMER_SR_CPBS 3
18644 -#define TIMER_SR_CPCS 4
18645 -#define TIMER_SR_ETRGS 7
18646 -#define TIMER_SR_LDRAS 5
18647 -#define TIMER_SR_LDRBS 6
18648 -#define TIMER_SR_LOVRS 1
18649 -#define TIMER_SR_MTIOA 17
18650 -#define TIMER_SR_MTIOB 18
18651 -
18652 -/* Bit manipulation macros */
18653 -#define TIMER_BIT(name) (1 << TIMER_##name)
18654 -#define TIMER_BF(name,value) ((value) << TIMER_##name)
18655 -
18656 -/* Register access macros */
18657 -#define timer_read(port,instance,reg) \
18658 - __raw_readl(port + (0x40 * instance) + TIMER_##reg)
18659 -#define timer_write(port,instance,reg,value) \
18660 - __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
18661 -
18662 -#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
18663 --- a/include/asm-avr32/asm.h
18664 +++ b/include/asm-avr32/asm.h
18665 @@ -12,10 +12,10 @@
18666 #include <asm/asm-offsets.h>
18667 #include <asm/thread_info.h>
18668
18669 -#define mask_interrupts ssrf SR_GM_BIT
18670 -#define mask_exceptions ssrf SR_EM_BIT
18671 -#define unmask_interrupts csrf SR_GM_BIT
18672 -#define unmask_exceptions csrf SR_EM_BIT
18673 +#define mask_interrupts ssrf SYSREG_GM_OFFSET
18674 +#define mask_exceptions ssrf SYSREG_EM_OFFSET
18675 +#define unmask_interrupts csrf SYSREG_GM_OFFSET
18676 +#define unmask_exceptions csrf SYSREG_EM_OFFSET
18677
18678 #ifdef CONFIG_FRAME_POINTER
18679 .macro save_fp
18680 --- a/include/asm-avr32/byteorder.h
18681 +++ b/include/asm-avr32/byteorder.h
18682 @@ -12,8 +12,10 @@
18683 extern unsigned short __builtin_bswap_16(unsigned short x);
18684 #endif
18685
18686 +#if 0
18687 #define __arch__swab32(x) __builtin_bswap_32(x)
18688 #define __arch__swab16(x) __builtin_bswap_16(x)
18689 +#endif
18690
18691 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
18692 # define __BYTEORDER_HAS_U64__
18693 --- /dev/null
18694 +++ b/include/asm-avr32/dma-controller.h
18695 @@ -0,0 +1,166 @@
18696 +/*
18697 + * Copyright (C) 2005-2006 Atmel Corporation
18698 + *
18699 + * This program is free software; you can redistribute it and/or modify
18700 + * it under the terms of the GNU General Public License version 2 as
18701 + * published by the Free Software Foundation.
18702 + */
18703 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
18704 +#define __ASM_AVR32_DMA_CONTROLLER_H
18705 +
18706 +#include <linux/device.h>
18707 +
18708 +#define DMA_DIR_MEM_TO_MEM 0x0000
18709 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
18710 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
18711 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
18712 +
18713 +#define DMA_WIDTH_8BIT 0
18714 +#define DMA_WIDTH_16BIT 1
18715 +#define DMA_WIDTH_32BIT 2
18716 +
18717 +struct dma_request {
18718 + struct dma_controller *dmac;
18719 + struct list_head list;
18720 +
18721 + unsigned short channel;
18722 +
18723 + void (*xfer_complete)(struct dma_request *req);
18724 + void (*block_complete)(struct dma_request *req);
18725 + void (*error)(struct dma_request *req);
18726 +};
18727 +
18728 +struct dma_request_sg {
18729 + struct dma_request req;
18730 +
18731 + int nr_sg;
18732 + struct scatterlist *sg;
18733 + unsigned long block_size;
18734 + unsigned int nr_blocks;
18735 +
18736 + dma_addr_t data_reg;
18737 + unsigned short periph_id;
18738 +
18739 + unsigned char direction;
18740 + unsigned char width;
18741 +};
18742 +#define to_dma_request_sg(_req) \
18743 + container_of(_req, struct dma_request_sg, req)
18744 +
18745 +struct dma_request_cyclic {
18746 + struct dma_request req;
18747 +
18748 + int periods;
18749 + unsigned long buffer_size;
18750 +
18751 + dma_addr_t buffer_start;
18752 + dma_addr_t data_reg;
18753 +
18754 + unsigned short periph_id;
18755 + unsigned char direction;
18756 + unsigned char width;
18757 +
18758 + void *dev_id;
18759 +};
18760 +#define to_dma_request_cyclic(_req) \
18761 + container_of(_req, struct dma_request_cyclic, req)
18762 +
18763 +struct dma_request_memcpy {
18764 + struct dma_request req;
18765 +
18766 + dma_addr_t src_addr;
18767 + unsigned int src_width;
18768 + unsigned int src_stride;
18769 +
18770 + dma_addr_t dst_addr;
18771 + unsigned int dst_width;
18772 + unsigned int dst_stride;
18773 +
18774 + size_t length;
18775 +
18776 + unsigned short src_reverse:1;
18777 + unsigned short dst_reverse:1;
18778 +};
18779 +#define to_dma_request_memcpy(_req) \
18780 + container_of(_req, struct dma_request_memcpy, req)
18781 +
18782 +struct dma_controller {
18783 + struct list_head list;
18784 + int id;
18785 + struct device *dev;
18786 +
18787 + int (*alloc_channel)(struct dma_controller *dmac);
18788 + void (*release_channel)(struct dma_controller *dmac,
18789 + int channel);
18790 + int (*prepare_request_sg)(struct dma_controller *dmac,
18791 + struct dma_request_sg *req);
18792 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
18793 + struct dma_request_cyclic *req);
18794 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
18795 + struct dma_request_memcpy *req);
18796 + int (*start_request)(struct dma_controller *dmac,
18797 + unsigned int channel);
18798 + int (*stop_request)(struct dma_controller *dmac,
18799 + unsigned int channel);
18800 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
18801 + unsigned int channel);
18802 +};
18803 +
18804 +static inline int
18805 +dma_alloc_channel(struct dma_controller *dmac)
18806 +{
18807 + return dmac->alloc_channel(dmac);
18808 +}
18809 +
18810 +static inline void
18811 +dma_release_channel(struct dma_controller *dmac, int chan)
18812 +{
18813 + dmac->release_channel(dmac, chan);
18814 +}
18815 +
18816 +static inline int
18817 +dma_prepare_request_sg(struct dma_controller *dmac,
18818 + struct dma_request_sg *req)
18819 +{
18820 + return dmac->prepare_request_sg(dmac, req);
18821 +}
18822 +
18823 +static inline int
18824 +dma_prepare_request_cyclic(struct dma_controller *dmac,
18825 + struct dma_request_cyclic *req)
18826 +{
18827 + return dmac->prepare_request_cyclic(dmac, req);
18828 +}
18829 +
18830 +static inline int
18831 +dma_prepare_request_memcpy(struct dma_controller *dmac,
18832 + struct dma_request_memcpy *req)
18833 +{
18834 + return dmac->prepare_request_memcpy(dmac, req);
18835 +}
18836 +
18837 +static inline int
18838 +dma_start_request(struct dma_controller *dmac,
18839 + unsigned int channel)
18840 +{
18841 + return dmac->start_request(dmac, channel);
18842 +}
18843 +
18844 +static inline int
18845 +dma_stop_request(struct dma_controller *dmac,
18846 + unsigned int channel)
18847 +{
18848 + return dmac->stop_request(dmac, channel);
18849 +}
18850 +
18851 +static inline dma_addr_t
18852 +dma_get_current_pos(struct dma_controller *dmac,
18853 + unsigned int channel)
18854 +{
18855 + return dmac->get_current_pos(dmac, channel);
18856 +}
18857 +
18858 +extern int register_dma_controller(struct dma_controller *dmac);
18859 +extern struct dma_controller *find_dma_controller(int id);
18860 +
18861 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
18862 --- a/include/asm-avr32/intc.h
18863 +++ /dev/null
18864 @@ -1,128 +0,0 @@
18865 -#ifndef __ASM_AVR32_INTC_H
18866 -#define __ASM_AVR32_INTC_H
18867 -
18868 -#include <linux/sysdev.h>
18869 -#include <linux/interrupt.h>
18870 -
18871 -struct irq_controller;
18872 -struct irqaction;
18873 -struct pt_regs;
18874 -
18875 -struct platform_device;
18876 -
18877 -/* Information about the internal interrupt controller */
18878 -struct intc_device {
18879 - /* ioremapped address of configuration block */
18880 - void __iomem *regs;
18881 -
18882 - /* the physical device */
18883 - struct platform_device *pdev;
18884 -
18885 - /* Number of interrupt lines per group. */
18886 - unsigned int irqs_per_group;
18887 -
18888 - /* The highest group ID + 1 */
18889 - unsigned int nr_groups;
18890 -
18891 - /*
18892 - * Bitfield indicating which groups are actually in use. The
18893 - * size of the array is
18894 - * ceil(group_max / (8 * sizeof(unsigned int))).
18895 - */
18896 - unsigned int group_mask[];
18897 -};
18898 -
18899 -struct irq_controller_class {
18900 - /*
18901 - * A short name identifying this kind of controller.
18902 - */
18903 - const char *typename;
18904 - /*
18905 - * Handle the IRQ. Must do any necessary acking and masking.
18906 - */
18907 - irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
18908 - /*
18909 - * Register a new IRQ handler.
18910 - */
18911 - int (*setup)(struct irq_controller *ctrl, unsigned int irq,
18912 - struct irqaction *action);
18913 - /*
18914 - * Unregister a IRQ handler.
18915 - */
18916 - void (*free)(struct irq_controller *ctrl, unsigned int irq,
18917 - void *dev_id);
18918 - /*
18919 - * Mask the IRQ in the interrupt controller.
18920 - */
18921 - void (*mask)(struct irq_controller *ctrl, unsigned int irq);
18922 - /*
18923 - * Unmask the IRQ in the interrupt controller.
18924 - */
18925 - void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
18926 - /*
18927 - * Set the type of the IRQ. See below for possible types.
18928 - * Return -EINVAL if a given type is not supported
18929 - */
18930 - int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
18931 - unsigned int type);
18932 - /*
18933 - * Return the IRQ type currently set
18934 - */
18935 - unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
18936 -};
18937 -
18938 -struct irq_controller {
18939 - struct irq_controller_class *class;
18940 - unsigned int irq_group;
18941 - unsigned int first_irq;
18942 - unsigned int nr_irqs;
18943 - struct list_head list;
18944 -};
18945 -
18946 -struct intc_group_desc {
18947 - struct irq_controller *ctrl;
18948 - irqreturn_t (*handle)(int, void *, struct pt_regs *);
18949 - unsigned long flags;
18950 - void *dev_id;
18951 - const char *devname;
18952 -};
18953 -
18954 -/*
18955 - * The internal interrupt controller. Defined in board/part-specific
18956 - * devices.c.
18957 - * TODO: Should probably be defined per-cpu.
18958 - */
18959 -extern struct intc_device intc;
18960 -
18961 -extern int request_internal_irq(unsigned int irq,
18962 - irqreturn_t (*handler)(int, void *, struct pt_regs *),
18963 - unsigned long irqflags,
18964 - const char *devname, void *dev_id);
18965 -extern void free_internal_irq(unsigned int irq);
18966 -
18967 -/* Only used by time_init() */
18968 -extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
18969 -
18970 -/*
18971 - * Set interrupt priority for a given group. `group' can be found by
18972 - * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
18973 - * (highest). Higher-priority interrupts will preempt lower-priority
18974 - * interrupts (unless interrupts are masked globally).
18975 - *
18976 - * This function does not check for conflicts within a group.
18977 - */
18978 -extern int intc_set_priority(unsigned int group,
18979 - unsigned int priority);
18980 -
18981 -/*
18982 - * Returns a bitmask of pending interrupts in a group.
18983 - */
18984 -extern unsigned long intc_get_pending(unsigned int group);
18985 -
18986 -/*
18987 - * Register a new external interrupt controller. Returns the first
18988 - * external IRQ number that is assigned to the new controller.
18989 - */
18990 -extern int intc_register_controller(struct irq_controller *ctrl);
18991 -
18992 -#endif /* __ASM_AVR32_INTC_H */
18993 --- a/include/asm-avr32/irq.h
18994 +++ b/include/asm-avr32/irq.h
18995 @@ -11,4 +11,14 @@
18996
18997 #define irq_canonicalize(i) (i)
18998
18999 +#ifndef __ASSEMBLER__
19000 +int nmi_enable(void);
19001 +void nmi_disable(void);
19002 +
19003 +/*
19004 + * Returns a bitmask of pending interrupts in a group.
19005 + */
19006 +extern unsigned long intc_get_pending(unsigned int group);
19007 +#endif
19008 +
19009 #endif /* __ASM_AVR32_IOCTLS_H */
19010 --- a/include/asm-avr32/kdebug.h
19011 +++ b/include/asm-avr32/kdebug.h
19012 @@ -5,6 +5,7 @@
19013 enum die_val {
19014 DIE_BREAKPOINT,
19015 DIE_SSTEP,
19016 + DIE_NMI,
19017 };
19018
19019 #endif /* __ASM_AVR32_KDEBUG_H */
19020 --- a/include/asm-avr32/ocd.h
19021 +++ b/include/asm-avr32/ocd.h
19022 @@ -533,6 +533,11 @@
19023 #define ocd_read(reg) __ocd_read(OCD_##reg)
19024 #define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
19025
19026 +struct task_struct;
19027 +
19028 +void ocd_enable(struct task_struct *child);
19029 +void ocd_disable(struct task_struct *child);
19030 +
19031 #endif /* !__ASSEMBLER__ */
19032
19033 #endif /* __ASM_AVR32_OCD_H */
19034 --- a/include/asm-avr32/pgtable.h
19035 +++ b/include/asm-avr32/pgtable.h
19036 @@ -157,6 +157,7 @@
19037 #define _PAGE_S(x) _PAGE_NORMAL(x)
19038
19039 #define PAGE_COPY _PAGE_P(PAGE_WRITE | PAGE_READ)
19040 +#define PAGE_SHARED _PAGE_S(PAGE_WRITE | PAGE_READ)
19041
19042 #ifndef __ASSEMBLY__
19043 /*
19044 --- a/include/asm-avr32/processor.h
19045 +++ b/include/asm-avr32/processor.h
19046 @@ -57,11 +57,25 @@
19047 unsigned short cpu_revision;
19048 enum tlb_config tlb_config;
19049 unsigned long features;
19050 + u32 device_id;
19051
19052 struct cache_info icache;
19053 struct cache_info dcache;
19054 };
19055
19056 +static inline unsigned int avr32_get_manufacturer_id(struct avr32_cpuinfo *cpu)
19057 +{
19058 + return (cpu->device_id >> 1) & 0x7f;
19059 +}
19060 +static inline unsigned int avr32_get_product_number(struct avr32_cpuinfo *cpu)
19061 +{
19062 + return (cpu->device_id >> 12) & 0xffff;
19063 +}
19064 +static inline unsigned int avr32_get_chip_revision(struct avr32_cpuinfo *cpu)
19065 +{
19066 + return (cpu->device_id >> 28) & 0x0f;
19067 +}
19068 +
19069 extern struct avr32_cpuinfo boot_cpu_data;
19070
19071 #ifdef CONFIG_SMP
19072 --- a/include/asm-avr32/ptrace.h
19073 +++ b/include/asm-avr32/ptrace.h
19074 @@ -121,7 +121,15 @@
19075 };
19076
19077 #ifdef __KERNEL__
19078 -# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
19079 +
19080 +#include <asm/ocd.h>
19081 +
19082 +#define arch_ptrace_attach(child) ocd_enable(child)
19083 +
19084 +#define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
19085 +#define instruction_pointer(regs) ((regs)->pc)
19086 +#define profile_pc(regs) instruction_pointer(regs)
19087 +
19088 extern void show_regs (struct pt_regs *);
19089
19090 static __inline__ int valid_user_regs(struct pt_regs *regs)
19091 @@ -141,9 +149,6 @@
19092 return 0;
19093 }
19094
19095 -#define instruction_pointer(regs) ((regs)->pc)
19096 -
19097 -#define profile_pc(regs) instruction_pointer(regs)
19098
19099 #endif /* __KERNEL__ */
19100
19101 --- a/include/asm-avr32/thread_info.h
19102 +++ b/include/asm-avr32/thread_info.h
19103 @@ -88,6 +88,7 @@
19104 #define TIF_MEMDIE 6
19105 #define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
19106 #define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
19107 +#define TIF_DEBUG 30 /* debugging enabled */
19108 #define TIF_USERSPACE 31 /* true if FS sets userspace */
19109
19110 #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
19111 --- /dev/null
19112 +++ b/include/linux/atmel_pwm.h
19113 @@ -0,0 +1,70 @@
19114 +#ifndef __LINUX_ATMEL_PWM_H
19115 +#define __LINUX_ATMEL_PWM_H
19116 +
19117 +/**
19118 + * struct pwm_channel - driver handle to a PWM channel
19119 + * @regs: base of this channel's registers
19120 + * @index: number of this channel (0..31)
19121 + * @mck: base clock rate, which can be prescaled and maybe subdivided
19122 + *
19123 + * Drivers initialize a pwm_channel structure using pwm_channel_alloc().
19124 + * Then they configure its clock rate (derived from MCK), alignment,
19125 + * polarity, and duty cycle by writing directly to the channel registers,
19126 + * before enabling the channel by calling pwm_channel_enable().
19127 + *
19128 + * After emitting a PWM signal for the desired length of time, drivers
19129 + * may then pwm_channel_disable() or pwm_channel_free(). Both of these
19130 + * disable the channel, but when it's freed the IRQ is deconfigured and
19131 + * the channel must later be re-allocated and reconfigured.
19132 + *
19133 + * Note that if the period or duty cycle need to be changed while the
19134 + * PWM channel is operating, drivers must use the PWM_CUPD double buffer
19135 + * mechanism, either polling until they change or getting implicitly
19136 + * notified through a once-per-period interrupt handler.
19137 + */
19138 +struct pwm_channel {
19139 + void __iomem *regs;
19140 + unsigned index;
19141 + unsigned long mck;
19142 +};
19143 +
19144 +extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
19145 +extern int pwm_channel_free(struct pwm_channel *ch);
19146 +
19147 +extern int pwm_clk_alloc(unsigned prescale, unsigned div);
19148 +extern void pwm_clk_free(unsigned clk);
19149 +
19150 +extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
19151 +
19152 +#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
19153 +#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
19154 +
19155 +/* periodic interrupts, mostly for CUPD changes to period or cycle */
19156 +extern int pwm_channel_handler(struct pwm_channel *ch,
19157 + void (*handler)(struct pwm_channel *ch));
19158 +
19159 +/* per-channel registers (banked at pwm_channel->regs) */
19160 +#define PWM_CMR 0x00 /* mode register */
19161 +#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
19162 +#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
19163 +#define PWM_CPR_CALG (1 << 8) /* set: center align */
19164 +#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
19165 +#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
19166 +#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
19167 +#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
19168 +#define PWM_CPRD 0x08 /* period (count up from zero) */
19169 +#define PWM_CCNT 0x0c /* counter (20 bits?) */
19170 +#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
19171 +
19172 +static inline void
19173 +pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
19174 +{
19175 + __raw_writel(val, pwmc->regs + offset);
19176 +}
19177 +
19178 +static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
19179 +{
19180 + return __raw_readl(pwmc->regs + offset);
19181 +}
19182 +
19183 +#endif /* __LINUX_ATMEL_PWM_H */
19184 --- /dev/null
19185 +++ b/include/linux/atmel_serial.h
19186 @@ -0,0 +1,127 @@
19187 +/*
19188 + * include/linux/atmel_serial.h
19189 + *
19190 + * Copyright (C) 2005 Ivan Kokshaysky
19191 + * Copyright (C) SAN People
19192 + *
19193 + * USART registers.
19194 + * Based on AT91RM9200 datasheet revision E.
19195 + *
19196 + * This program is free software; you can redistribute it and/or modify
19197 + * it under the terms of the GNU General Public License as published by
19198 + * the Free Software Foundation; either version 2 of the License, or
19199 + * (at your option) any later version.
19200 + */
19201 +
19202 +#ifndef ATMEL_SERIAL_H
19203 +#define ATMEL_SERIAL_H
19204 +
19205 +#define ATMEL_US_CR 0x00 /* Control Register */
19206 +#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
19207 +#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
19208 +#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
19209 +#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
19210 +#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
19211 +#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
19212 +#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
19213 +#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
19214 +#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
19215 +#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
19216 +#define ATMEL_US_SENDA (1 << 12) /* Send Address */
19217 +#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
19218 +#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
19219 +#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
19220 +#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
19221 +#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
19222 +#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
19223 +#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
19224 +
19225 +#define ATMEL_US_MR 0x04 /* Mode Register */
19226 +#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
19227 +#define ATMEL_US_USMODE_NORMAL 0
19228 +#define ATMEL_US_USMODE_RS485 1
19229 +#define ATMEL_US_USMODE_HWHS 2
19230 +#define ATMEL_US_USMODE_MODEM 3
19231 +#define ATMEL_US_USMODE_ISO7816_T0 4
19232 +#define ATMEL_US_USMODE_ISO7816_T1 6
19233 +#define ATMEL_US_USMODE_IRDA 8
19234 +#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
19235 +#define ATMEL_US_USCLKS_MCK (0 << 4)
19236 +#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
19237 +#define ATMEL_US_USCLKS_SCK (3 << 4)
19238 +#define ATMEL_US_CHRL (3 << 6) /* Character Length */
19239 +#define ATMEL_US_CHRL_5 (0 << 6)
19240 +#define ATMEL_US_CHRL_6 (1 << 6)
19241 +#define ATMEL_US_CHRL_7 (2 << 6)
19242 +#define ATMEL_US_CHRL_8 (3 << 6)
19243 +#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
19244 +#define ATMEL_US_PAR (7 << 9) /* Parity Type */
19245 +#define ATMEL_US_PAR_EVEN (0 << 9)
19246 +#define ATMEL_US_PAR_ODD (1 << 9)
19247 +#define ATMEL_US_PAR_SPACE (2 << 9)
19248 +#define ATMEL_US_PAR_MARK (3 << 9)
19249 +#define ATMEL_US_PAR_NONE (4 << 9)
19250 +#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
19251 +#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
19252 +#define ATMEL_US_NBSTOP_1 (0 << 12)
19253 +#define ATMEL_US_NBSTOP_1_5 (1 << 12)
19254 +#define ATMEL_US_NBSTOP_2 (2 << 12)
19255 +#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
19256 +#define ATMEL_US_CHMODE_NORMAL (0 << 14)
19257 +#define ATMEL_US_CHMODE_ECHO (1 << 14)
19258 +#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
19259 +#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
19260 +#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
19261 +#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
19262 +#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
19263 +#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
19264 +#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
19265 +#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
19266 +#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
19267 +#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
19268 +
19269 +#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
19270 +#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
19271 +#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
19272 +#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
19273 +#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
19274 +#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
19275 +#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
19276 +#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
19277 +#define ATMEL_US_PARE (1 << 7) /* Parity Error */
19278 +#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
19279 +#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
19280 +#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
19281 +#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
19282 +#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
19283 +#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
19284 +#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
19285 +#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
19286 +#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
19287 +#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
19288 +#define ATMEL_US_RI (1 << 20) /* RI */
19289 +#define ATMEL_US_DSR (1 << 21) /* DSR */
19290 +#define ATMEL_US_DCD (1 << 22) /* DCD */
19291 +#define ATMEL_US_CTS (1 << 23) /* CTS */
19292 +
19293 +#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
19294 +#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
19295 +#define ATMEL_US_CSR 0x14 /* Channel Status Register */
19296 +#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
19297 +#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
19298 +#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
19299 +
19300 +#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
19301 +#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
19302 +
19303 +#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
19304 +#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
19305 +
19306 +#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
19307 +#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
19308 +
19309 +#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
19310 +#define ATMEL_US_NER 0x44 /* Number of Errors Register */
19311 +#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
19312 +
19313 +#endif
19314 --- /dev/null
19315 +++ b/include/linux/atmel_tc.h
19316 @@ -0,0 +1,252 @@
19317 +/*
19318 + * Timer/Counter Unit (TC) registers.
19319 + *
19320 + * This program is free software; you can redistribute it and/or modify
19321 + * it under the terms of the GNU General Public License as published by
19322 + * the Free Software Foundation; either version 2 of the License, or
19323 + * (at your option) any later version.
19324 + */
19325 +
19326 +#ifndef ATMEL_TC_H
19327 +#define ATMEL_TC_H
19328 +
19329 +#include <linux/compiler.h>
19330 +#include <linux/list.h>
19331 +
19332 +/*
19333 + * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
19334 + * three general-purpose 16-bit timers. These timers share one register bank.
19335 + * Depending on the SOC, each timer may have its own clock and IRQ, or those
19336 + * may be shared by the whole TC block.
19337 + *
19338 + * These TC blocks may have up to nine external pins: TCLK0..2 signals for
19339 + * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
19340 + * or triggering. Those pins need to be set up for use with the TC block,
19341 + * else they will be used as GPIOs or for a different controller.
19342 + *
19343 + * Although we expect each TC block to have a platform_device node, those
19344 + * nodes are not what drivers bind to. Instead, they ask for a specific
19345 + * TC block, by number ... which is a common approach on systems with many
19346 + * timers. Then they use clk_get() and platform_get_irq() to get clock and
19347 + * IRQ resources.
19348 + */
19349 +
19350 +struct clk;
19351 +
19352 +/**
19353 + * struct atmel_tc - information about a Timer/Counter Block
19354 + * @pdev: physical device
19355 + * @iomem: resource associated with the I/O register
19356 + * @regs: mapping through which the I/O registers can be accessed
19357 + * @irq: irq for each of the three channels
19358 + * @clk: internal clock source for each of the three channels
19359 + * @node: list node, for tclib internal use
19360 + *
19361 + * On some platforms, each TC channel has its own clocks and IRQs,
19362 + * while on others, all TC channels share the same clock and IRQ.
19363 + * Drivers should clk_enable() all the clocks they need even though
19364 + * all the entries in @clk may point to the same physical clock.
19365 + * Likewise, drivers should request irqs independently for each
19366 + * channel, but they must use IRQF_SHARED in case some of the entries
19367 + * in @irq are actually the same IRQ.
19368 + */
19369 +struct atmel_tc {
19370 + struct platform_device *pdev;
19371 + struct resource *iomem;
19372 + void __iomem *regs;
19373 + int irq[3];
19374 + struct clk *clk[3];
19375 + struct list_head node;
19376 +};
19377 +
19378 +extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
19379 +extern void atmel_tc_free(struct atmel_tc *tc);
19380 +
19381 +/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
19382 +extern const u8 atmel_tc_divisors[5];
19383 +
19384 +
19385 +/*
19386 + * Two registers have block-wide controls. These are: configuring the three
19387 + * "external" clocks (or event sources) used by the timer channels; and
19388 + * synchronizing the timers by resetting them all at once.
19389 + *
19390 + * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
19391 + * signals. Or, it can mean "external to timer", using the TIOA output from
19392 + * one of the other two timers that's being run in waveform mode.
19393 + */
19394 +
19395 +#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
19396 +#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
19397 +
19398 +#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
19399 +#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
19400 +#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
19401 +#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
19402 +#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
19403 +#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
19404 +#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
19405 +#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
19406 +#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
19407 +#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
19408 +#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
19409 +#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
19410 +#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
19411 +#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
19412 +#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
19413 +#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
19414 +
19415 +
19416 +/*
19417 + * Each TC block has three "channels", each with one counter and controls.
19418 + *
19419 + * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
19420 + * when it's not "external") is silicon-specific. AT91 platforms use one
19421 + * set of definitions; AVR32 platforms use a different set. Don't hard-wire
19422 + * such knowledge into your code, use the global "atmel_tc_divisors" ...
19423 + * where index N is the divisor for clock N+1, else zero to indicate it uses
19424 + * the 32 KiHz clock.
19425 + *
19426 + * The timers can be chained in various ways, and operated in "waveform"
19427 + * generation mode (including PWM) or "capture" mode (to time events). In
19428 + * both modes, behavior can be configured in many ways.
19429 + *
19430 + * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
19431 + * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
19432 + * uses them only as inputs.
19433 + */
19434 +#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
19435 +#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
19436 +
19437 +#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
19438 +#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
19439 +#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
19440 +#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
19441 +
19442 +#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
19443 +
19444 +/* Both modes share some CMR bits */
19445 +#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
19446 +#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
19447 +#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
19448 +#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
19449 +#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
19450 +#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
19451 +#define ATMEL_TC_XC0 (5 << 0)
19452 +#define ATMEL_TC_XC1 (6 << 0)
19453 +#define ATMEL_TC_XC2 (7 << 0)
19454 +#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
19455 +#define ATMEL_TC_BURST (3 << 4) /* clock gating */
19456 +#define ATMEL_TC_GATE_NONE (0 << 4)
19457 +#define ATMEL_TC_GATE_XC0 (1 << 4)
19458 +#define ATMEL_TC_GATE_XC1 (2 << 4)
19459 +#define ATMEL_TC_GATE_XC2 (3 << 4)
19460 +#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
19461 +
19462 +/* CAPTURE mode CMR bits */
19463 +#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
19464 +#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
19465 +#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
19466 +#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
19467 +#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
19468 +#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
19469 +#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
19470 +#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
19471 +#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
19472 +#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
19473 +#define ATMEL_TC_LDRA_NONE (0 << 16)
19474 +#define ATMEL_TC_LDRA_RISING (1 << 16)
19475 +#define ATMEL_TC_LDRA_FALLING (2 << 16)
19476 +#define ATMEL_TC_LDRA_BOTH (3 << 16)
19477 +#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
19478 +#define ATMEL_TC_LDRB_NONE (0 << 18)
19479 +#define ATMEL_TC_LDRB_RISING (1 << 18)
19480 +#define ATMEL_TC_LDRB_FALLING (2 << 18)
19481 +#define ATMEL_TC_LDRB_BOTH (3 << 18)
19482 +
19483 +/* WAVEFORM mode CMR bits */
19484 +#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
19485 +#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
19486 +#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
19487 +#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
19488 +#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
19489 +#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
19490 +#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
19491 +#define ATMEL_TC_EEVT (3 << 10) /* external event source */
19492 +#define ATMEL_TC_EEVT_TIOB (0 << 10)
19493 +#define ATMEL_TC_EEVT_XC0 (1 << 10)
19494 +#define ATMEL_TC_EEVT_XC1 (2 << 10)
19495 +#define ATMEL_TC_EEVT_XC2 (3 << 10)
19496 +#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
19497 +#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
19498 +#define ATMEL_TC_WAVESEL_UP (0 << 13)
19499 +#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
19500 +#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
19501 +#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
19502 +#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
19503 +#define ATMEL_TC_ACPA_NONE (0 << 16)
19504 +#define ATMEL_TC_ACPA_SET (1 << 16)
19505 +#define ATMEL_TC_ACPA_CLEAR (2 << 16)
19506 +#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
19507 +#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
19508 +#define ATMEL_TC_ACPC_NONE (0 << 18)
19509 +#define ATMEL_TC_ACPC_SET (1 << 18)
19510 +#define ATMEL_TC_ACPC_CLEAR (2 << 18)
19511 +#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
19512 +#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
19513 +#define ATMEL_TC_AEEVT_NONE (0 << 20)
19514 +#define ATMEL_TC_AEEVT_SET (1 << 20)
19515 +#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
19516 +#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
19517 +#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
19518 +#define ATMEL_TC_ASWTRG_NONE (0 << 22)
19519 +#define ATMEL_TC_ASWTRG_SET (1 << 22)
19520 +#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
19521 +#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
19522 +#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
19523 +#define ATMEL_TC_BCPB_NONE (0 << 24)
19524 +#define ATMEL_TC_BCPB_SET (1 << 24)
19525 +#define ATMEL_TC_BCPB_CLEAR (2 << 24)
19526 +#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
19527 +#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
19528 +#define ATMEL_TC_BCPC_NONE (0 << 26)
19529 +#define ATMEL_TC_BCPC_SET (1 << 26)
19530 +#define ATMEL_TC_BCPC_CLEAR (2 << 26)
19531 +#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
19532 +#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
19533 +#define ATMEL_TC_BEEVT_NONE (0 << 28)
19534 +#define ATMEL_TC_BEEVT_SET (1 << 28)
19535 +#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
19536 +#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
19537 +#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
19538 +#define ATMEL_TC_BSWTRG_NONE (0 << 30)
19539 +#define ATMEL_TC_BSWTRG_SET (1 << 30)
19540 +#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
19541 +#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
19542 +
19543 +#define ATMEL_TC_CV 0x10 /* counter Value */
19544 +#define ATMEL_TC_RA 0x14 /* register A */
19545 +#define ATMEL_TC_RB 0x18 /* register B */
19546 +#define ATMEL_TC_RC 0x1c /* register C */
19547 +
19548 +#define ATMEL_TC_SR 0x20 /* status (read-only) */
19549 +/* Status-only flags */
19550 +#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
19551 +#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
19552 +#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
19553 +
19554 +#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
19555 +#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
19556 +#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
19557 +
19558 +/* Status and IRQ flags */
19559 +#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
19560 +#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
19561 +#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
19562 +#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
19563 +#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
19564 +#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
19565 +#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
19566 +#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
19567 +
19568 +#endif
19569 --- /dev/null
19570 +++ b/include/linux/usb/atmel_usba_udc.h
19571 @@ -0,0 +1,22 @@
19572 +/*
19573 + * Platform data definitions for Atmel USBA gadget driver.
19574 + */
19575 +#ifndef __LINUX_USB_USBA_H
19576 +#define __LINUX_USB_USBA_H
19577 +
19578 +struct usba_ep_data {
19579 + char *name;
19580 + int index;
19581 + int fifo_size;
19582 + int nr_banks;
19583 + int can_dma;
19584 + int can_isoc;
19585 +};
19586 +
19587 +struct usba_platform_data {
19588 + int vbus_pin;
19589 + int num_ep;
19590 + struct usba_ep_data ep[0];
19591 +};
19592 +
19593 +#endif /* __LINUX_USB_USBA_H */
19594 --- a/include/video/atmel_lcdc.h
19595 +++ b/include/video/atmel_lcdc.h
19596 @@ -22,7 +22,7 @@
19597 #ifndef __ATMEL_LCDC_H__
19598 #define __ATMEL_LCDC_H__
19599
19600 - /* LCD Controller info data structure */
19601 + /* LCD Controller info data structure, stored in device platform_data */
19602 struct atmel_lcdfb_info {
19603 spinlock_t lock;
19604 struct fb_info *info;
19605 @@ -33,7 +33,14 @@
19606 struct platform_device *pdev;
19607 struct clk *bus_clk;
19608 struct clk *lcdc_clk;
19609 - unsigned int default_bpp;
19610 +
19611 +#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
19612 + struct backlight_device *backlight;
19613 + u8 bl_power;
19614 +#endif
19615 + bool lcdcon_is_backlight;
19616 +
19617 + u8 default_bpp;
19618 unsigned int default_lcdcon2;
19619 unsigned int default_dmacon;
19620 void (*atmel_lcdfb_power_control)(int on);
19621 @@ -115,20 +122,20 @@
19622 #define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
19623
19624 #define ATMEL_LCDC_TIM1 0x0808
19625 -#define ATMEL_LCDC_VFP (0xff << 0)
19626 +#define ATMEL_LCDC_VFP (0xffU << 0)
19627 #define ATMEL_LCDC_VBP_OFFSET 8
19628 -#define ATMEL_LCDC_VBP (0xff << ATMEL_LCDC_VBP_OFFSET)
19629 +#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
19630 #define ATMEL_LCDC_VPW_OFFSET 16
19631 -#define ATMEL_LCDC_VPW (0x3f << ATMEL_LCDC_VPW_OFFSET)
19632 +#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
19633 #define ATMEL_LCDC_VHDLY_OFFSET 24
19634 -#define ATMEL_LCDC_VHDLY (0xf << ATMEL_LCDC_VHDLY_OFFSET)
19635 +#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
19636
19637 #define ATMEL_LCDC_TIM2 0x080c
19638 -#define ATMEL_LCDC_HBP (0xff << 0)
19639 +#define ATMEL_LCDC_HBP (0xffU << 0)
19640 #define ATMEL_LCDC_HPW_OFFSET 8
19641 -#define ATMEL_LCDC_HPW (0x3f << ATMEL_LCDC_HPW_OFFSET)
19642 +#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
19643 #define ATMEL_LCDC_HFP_OFFSET 21
19644 -#define ATMEL_LCDC_HFP (0x7ff << ATMEL_LCDC_HFP_OFFSET)
19645 +#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
19646
19647 #define ATMEL_LCDC_LCDFRMCFG 0x0810
19648 #define ATMEL_LCDC_LINEVAL (0x7ff << 0)
19649 --- a/init/do_mounts.c
19650 +++ b/init/do_mounts.c
19651 @@ -219,8 +219,14 @@
19652
19653 static int __init rootwait_setup(char *str)
19654 {
19655 - if (*str)
19656 + if (*str && *str != '=')
19657 return 0;
19658 +
19659 + if (*str)
19660 + printk(KERN_WARNING
19661 + "WARNING: \"rootwait=1\" is deprecated, "
19662 + "use \"rootwait\" instead.\n");
19663 +
19664 root_wait = 1;
19665 return 1;
19666 }
19667 --- a/kernel/ptrace.c
19668 +++ b/kernel/ptrace.c
19669 @@ -470,6 +470,8 @@
19670 lock_kernel();
19671 if (request == PTRACE_TRACEME) {
19672 ret = ptrace_traceme();
19673 + if (!ret)
19674 + arch_ptrace_attach(current);
19675 goto out;
19676 }
19677
19678 --- a/MAINTAINERS
19679 +++ b/MAINTAINERS
19680 @@ -671,6 +671,12 @@
19681 W: http://www.at91.com/
19682 S: Maintained
19683
19684 +ATMEL AT91 / AT32 SERIAL DRIVER
19685 +P: Haavard Skinnemoen
19686 +M: hskinnemoen@atmel.com
19687 +L: linux-kernel@vger.kernel.org
19688 +S: Supported
19689 +
19690 ATMEL LCDFB DRIVER
19691 P: Nicolas Ferre
19692 M: nicolas.ferre@atmel.com
19693 --- /dev/null
19694 +++ b/sound/avr32/ac97c.c
19695 @@ -0,0 +1,914 @@
19696 +/*
19697 + * Driver for the Atmel AC97 controller
19698 + *
19699 + * Copyright (C) 2005-2007 Atmel Corporation
19700 + *
19701 + * This program is free software; you can redistribute it and/or modify it
19702 + * under the terms of the GNU General Public License version 2 as published by
19703 + * the Free Software Foundation.
19704 + */
19705 +#include <linux/clk.h>
19706 +#include <linux/delay.h>
19707 +#include <linux/dma-mapping.h>
19708 +#include <linux/init.h>
19709 +#include <linux/interrupt.h>
19710 +#include <linux/module.h>
19711 +#include <linux/platform_device.h>
19712 +#include <linux/mutex.h>
19713 +#include <linux/io.h>
19714 +
19715 +#include <sound/driver.h>
19716 +#include <sound/core.h>
19717 +#include <sound/initval.h>
19718 +#include <sound/pcm.h>
19719 +#include <sound/pcm_params.h>
19720 +#include <sound/ac97_codec.h>
19721 +#include <sound/memalloc.h>
19722 +
19723 +#include <asm/dma-controller.h>
19724 +
19725 +#include "ac97c.h"
19726 +
19727 +/* Serialize access to opened */
19728 +static DEFINE_MUTEX(opened_mutex);
19729 +
19730 +struct atmel_ac97_dma_info {
19731 + struct dma_request_cyclic req_tx;
19732 + struct dma_request_cyclic req_rx;
19733 + unsigned short rx_periph_id;
19734 + unsigned short tx_periph_id;
19735 +};
19736 +
19737 +struct atmel_ac97 {
19738 + /* Serialize access to opened */
19739 + spinlock_t lock;
19740 + void __iomem *regs;
19741 + struct snd_pcm_substream *playback_substream;
19742 + struct snd_pcm_substream *capture_substream;
19743 + struct snd_card *card;
19744 + struct snd_pcm *pcm;
19745 + struct snd_ac97 *ac97;
19746 + struct snd_ac97_bus *ac97_bus;
19747 + int opened;
19748 + int period;
19749 + u64 cur_format;
19750 + unsigned int cur_rate;
19751 + struct clk *mck;
19752 + struct platform_device *pdev;
19753 + struct atmel_ac97_dma_info dma;
19754 +};
19755 +
19756 +#define get_chip(card) ((struct atmel_ac97 *)(card)->private_data)
19757 +
19758 +#define ac97c_writel(chip, reg, val) \
19759 + __raw_writel((val), (chip)->regs + AC97C_##reg)
19760 +#define ac97c_readl(chip, reg) \
19761 + __raw_readl((chip)->regs + AC97C_##reg)
19762 +
19763 +/*
19764 + * PCM part
19765 + */
19766 +static struct snd_pcm_hardware snd_atmel_ac97_playback_hw = {
19767 + .info = (SNDRV_PCM_INFO_INTERLEAVED
19768 + | SNDRV_PCM_INFO_MMAP
19769 + | SNDRV_PCM_INFO_MMAP_VALID
19770 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
19771 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
19772 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
19773 + | SNDRV_PCM_FMTBIT_S16_LE),
19774 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
19775 + .rate_min = 4000,
19776 + .rate_max = 48000,
19777 + .channels_min = 1,
19778 + .channels_max = 6,
19779 + .buffer_bytes_max = 64*1024,
19780 + .period_bytes_min = 512,
19781 + .period_bytes_max = 4095,
19782 + .periods_min = 8,
19783 + .periods_max = 1024,
19784 +};
19785 +
19786 +static struct snd_pcm_hardware snd_atmel_ac97_capture_hw = {
19787 + .info = (SNDRV_PCM_INFO_INTERLEAVED
19788 + | SNDRV_PCM_INFO_MMAP
19789 + | SNDRV_PCM_INFO_MMAP_VALID
19790 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
19791 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
19792 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
19793 + | SNDRV_PCM_FMTBIT_S16_LE),
19794 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
19795 + .rate_min = 4000,
19796 + .rate_max = 48000,
19797 + .channels_min = 1,
19798 + .channels_max = 2,
19799 + .buffer_bytes_max = 64*1024,
19800 + .period_bytes_min = 512,
19801 + .period_bytes_max = 4095,
19802 + .periods_min = 8,
19803 + .periods_max = 1024,
19804 +};
19805 +
19806 +/*
19807 + * PCM functions
19808 + */
19809 +static int
19810 +snd_atmel_ac97_playback_open(struct snd_pcm_substream *substream)
19811 +{
19812 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19813 + struct snd_pcm_runtime *runtime = substream->runtime;
19814 +
19815 + mutex_lock(&opened_mutex);
19816 + chip->opened++;
19817 + runtime->hw = snd_atmel_ac97_playback_hw;
19818 + if (chip->cur_rate) {
19819 + runtime->hw.rate_min = chip->cur_rate;
19820 + runtime->hw.rate_max = chip->cur_rate;
19821 + }
19822 + if (chip->cur_format)
19823 + runtime->hw.formats = (1ULL << chip->cur_format);
19824 + mutex_unlock(&opened_mutex);
19825 + chip->playback_substream = substream;
19826 + chip->period = 0;
19827 + return 0;
19828 +}
19829 +
19830 +static int
19831 +snd_atmel_ac97_capture_open(struct snd_pcm_substream *substream)
19832 +{
19833 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19834 + struct snd_pcm_runtime *runtime = substream->runtime;
19835 +
19836 + mutex_lock(&opened_mutex);
19837 + chip->opened++;
19838 + runtime->hw = snd_atmel_ac97_capture_hw;
19839 + if (chip->cur_rate) {
19840 + runtime->hw.rate_min = chip->cur_rate;
19841 + runtime->hw.rate_max = chip->cur_rate;
19842 + }
19843 + if (chip->cur_format)
19844 + runtime->hw.formats = (1ULL << chip->cur_format);
19845 + mutex_unlock(&opened_mutex);
19846 + chip->capture_substream = substream;
19847 + chip->period = 0;
19848 + return 0;
19849 +}
19850 +
19851 +static int snd_atmel_ac97_playback_close(struct snd_pcm_substream *substream)
19852 +{
19853 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19854 + mutex_lock(&opened_mutex);
19855 + chip->opened--;
19856 + if (!chip->opened) {
19857 + chip->cur_rate = 0;
19858 + chip->cur_format = 0;
19859 + }
19860 + mutex_unlock(&opened_mutex);
19861 + return 0;
19862 +}
19863 +
19864 +static int snd_atmel_ac97_capture_close(struct snd_pcm_substream *substream)
19865 +{
19866 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19867 + mutex_lock(&opened_mutex);
19868 + chip->opened--;
19869 + if (!chip->opened) {
19870 + chip->cur_rate = 0;
19871 + chip->cur_format = 0;
19872 + }
19873 + mutex_unlock(&opened_mutex);
19874 + return 0;
19875 +}
19876 +
19877 +static int
19878 +snd_atmel_ac97_playback_hw_params(struct snd_pcm_substream *substream,
19879 + struct snd_pcm_hw_params *hw_params)
19880 +{
19881 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19882 + int err;
19883 +
19884 + err = snd_pcm_lib_malloc_pages(substream,
19885 + params_buffer_bytes(hw_params));
19886 + if (err < 0)
19887 + return err;
19888 +
19889 + /* Set restrictions to params */
19890 + mutex_lock(&opened_mutex);
19891 + chip->cur_rate = params_rate(hw_params);
19892 + chip->cur_format = params_format(hw_params);
19893 + mutex_unlock(&opened_mutex);
19894 +
19895 + return 0;
19896 +}
19897 +
19898 +static int
19899 +snd_atmel_ac97_capture_hw_params(struct snd_pcm_substream *substream,
19900 + struct snd_pcm_hw_params *hw_params)
19901 +{
19902 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19903 + int err;
19904 +
19905 + err = snd_pcm_lib_malloc_pages(substream,
19906 + params_buffer_bytes(hw_params));
19907 + if (err < 0)
19908 + return err;
19909 +
19910 + /* Set restrictions to params */
19911 + mutex_lock(&opened_mutex);
19912 + chip->cur_rate = params_rate(hw_params);
19913 + chip->cur_format = params_format(hw_params);
19914 + mutex_unlock(&opened_mutex);
19915 +
19916 + return 0;
19917 +}
19918 +
19919 +static int snd_atmel_ac97_playback_hw_free(struct snd_pcm_substream *substream)
19920 +{
19921 + return snd_pcm_lib_free_pages(substream);
19922 +}
19923 +
19924 +static int snd_atmel_ac97_capture_hw_free(struct snd_pcm_substream *substream)
19925 +{
19926 +
19927 + return snd_pcm_lib_free_pages(substream);
19928 +}
19929 +
19930 +static int snd_atmel_ac97_playback_prepare(struct snd_pcm_substream *substream)
19931 +{
19932 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
19933 + struct platform_device *pdev = chip->pdev;
19934 + struct snd_pcm_runtime *runtime = substream->runtime;
19935 + int block_size = frames_to_bytes(runtime, runtime->period_size);
19936 + unsigned long word = 0;
19937 + unsigned long buffer_size = 0;
19938 +
19939 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
19940 + block_size * 2, DMA_TO_DEVICE);
19941 +
19942 + /* Assign slots to channels */
19943 + switch (substream->runtime->channels) {
19944 + case 1:
19945 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
19946 + break;
19947 + case 2:
19948 + /* Assign Left and Right slot to Channel A */
19949 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
19950 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
19951 + break;
19952 + default:
19953 + /* TODO: support more than two channels */
19954 + return -EINVAL;
19955 + break;
19956 + }
19957 + ac97c_writel(chip, OCA, word);
19958 +
19959 + /* Configure sample format and size */
19960 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
19961 +
19962 + switch (runtime->format) {
19963 + case SNDRV_PCM_FORMAT_S16_LE:
19964 + word |= AC97C_CMR_CEM_LITTLE;
19965 + break;
19966 + case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
19967 + default:
19968 + word &= ~AC97C_CMR_CEM_LITTLE;
19969 + break;
19970 + }
19971 +
19972 + ac97c_writel(chip, CAMR, word);
19973 +
19974 + /* Set variable rate if needed */
19975 + if (runtime->rate != 48000) {
19976 + word = ac97c_readl(chip, MR);
19977 + word |= AC97C_MR_VRA;
19978 + ac97c_writel(chip, MR, word);
19979 + } else {
19980 + /* Clear Variable Rate Bit */
19981 + word = ac97c_readl(chip, MR);
19982 + word &= ~AC97C_MR_VRA;
19983 + ac97c_writel(chip, MR, word);
19984 + }
19985 +
19986 + /* Set rate */
19987 + snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
19988 +
19989 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
19990 + runtime->periods;
19991 +
19992 + chip->dma.req_tx.buffer_size = buffer_size;
19993 + chip->dma.req_tx.periods = runtime->periods;
19994 +
19995 + BUG_ON(chip->dma.req_tx.buffer_size !=
19996 + (chip->dma.req_tx.periods *
19997 + frames_to_bytes(runtime, runtime->period_size)));
19998 +
19999 + chip->dma.req_tx.buffer_start = runtime->dma_addr;
20000 + chip->dma.req_tx.data_reg = (dma_addr_t)(chip->regs + AC97C_CATHR + 2);
20001 + chip->dma.req_tx.periph_id = chip->dma.tx_periph_id;
20002 + chip->dma.req_tx.direction = DMA_DIR_MEM_TO_PERIPH;
20003 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
20004 + chip->dma.req_tx.dev_id = chip;
20005 +
20006 + return 0;
20007 +}
20008 +
20009 +static int snd_atmel_ac97_capture_prepare(struct snd_pcm_substream *substream)
20010 +{
20011 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
20012 + struct platform_device *pdev = chip->pdev;
20013 + struct snd_pcm_runtime *runtime = substream->runtime;
20014 + int block_size = frames_to_bytes(runtime, runtime->period_size);
20015 + unsigned long word = 0;
20016 + unsigned long buffer_size = 0;
20017 +
20018 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
20019 + block_size * 2, DMA_FROM_DEVICE);
20020 +
20021 + /* Assign slots to channels */
20022 + switch (substream->runtime->channels) {
20023 + case 1:
20024 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
20025 + break;
20026 + case 2:
20027 + /* Assign Left and Right slot to Channel A */
20028 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
20029 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
20030 + break;
20031 + default:
20032 + /* TODO: support more than two channels */
20033 + return -EINVAL;
20034 + break;
20035 + }
20036 + ac97c_writel(chip, ICA, word);
20037 +
20038 + /* Configure sample format and size */
20039 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
20040 +
20041 + switch (runtime->format) {
20042 + case SNDRV_PCM_FORMAT_S16_LE:
20043 + word |= AC97C_CMR_CEM_LITTLE;
20044 + break;
20045 + case SNDRV_PCM_FORMAT_S16_BE:
20046 + default:
20047 + word &= ~(AC97C_CMR_CEM_LITTLE);
20048 + break;
20049 + }
20050 +
20051 + ac97c_writel(chip, CAMR, word);
20052 +
20053 + /* Set variable rate if needed */
20054 + if (runtime->rate != 48000) {
20055 + word = ac97c_readl(chip, MR);
20056 + word |= AC97C_MR_VRA;
20057 + ac97c_writel(chip, MR, word);
20058 + } else {
20059 + /* Clear Variable Rate Bit */
20060 + word = ac97c_readl(chip, MR);
20061 + word &= ~(AC97C_MR_VRA);
20062 + ac97c_writel(chip, MR, word);
20063 + }
20064 +
20065 + /* Set rate */
20066 + snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
20067 +
20068 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
20069 + runtime->periods;
20070 +
20071 + chip->dma.req_rx.buffer_size = buffer_size;
20072 + chip->dma.req_rx.periods = runtime->periods;
20073 +
20074 + BUG_ON(chip->dma.req_rx.buffer_size !=
20075 + (chip->dma.req_rx.periods *
20076 + frames_to_bytes(runtime, runtime->period_size)));
20077 +
20078 + chip->dma.req_rx.buffer_start = runtime->dma_addr;
20079 + chip->dma.req_rx.data_reg = (dma_addr_t)(chip->regs + AC97C_CARHR + 2);
20080 + chip->dma.req_rx.periph_id = chip->dma.rx_periph_id;
20081 + chip->dma.req_rx.direction = DMA_DIR_PERIPH_TO_MEM;
20082 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
20083 + chip->dma.req_rx.dev_id = chip;
20084 +
20085 + return 0;
20086 +}
20087 +
20088 + static int
20089 +snd_atmel_ac97_playback_trigger(struct snd_pcm_substream *substream, int cmd)
20090 +{
20091 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
20092 + unsigned long camr;
20093 + int flags, err = 0;
20094 +
20095 + spin_lock_irqsave(&chip->lock, flags);
20096 + camr = ac97c_readl(chip, CAMR);
20097 +
20098 + switch (cmd) {
20099 + case SNDRV_PCM_TRIGGER_START:
20100 + err = dma_prepare_request_cyclic(chip->dma.req_tx.req.dmac,
20101 + &chip->dma.req_tx);
20102 + dma_start_request(chip->dma.req_tx.req.dmac,
20103 + chip->dma.req_tx.req.channel);
20104 + camr |= AC97C_CMR_CENA;
20105 + break;
20106 + case SNDRV_PCM_TRIGGER_STOP:
20107 + err = dma_stop_request(chip->dma.req_tx.req.dmac,
20108 + chip->dma.req_tx.req.channel);
20109 + if (chip->opened <= 1)
20110 + camr &= ~AC97C_CMR_CENA;
20111 + break;
20112 + default:
20113 + err = -EINVAL;
20114 + break;
20115 + }
20116 +
20117 + ac97c_writel(chip, CAMR, camr);
20118 +
20119 + spin_unlock_irqrestore(&chip->lock, flags);
20120 + return err;
20121 +}
20122 +
20123 + static int
20124 +snd_atmel_ac97_capture_trigger(struct snd_pcm_substream *substream, int cmd)
20125 +{
20126 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
20127 + unsigned long camr;
20128 + int flags, err = 0;
20129 +
20130 + spin_lock_irqsave(&chip->lock, flags);
20131 + camr = ac97c_readl(chip, CAMR);
20132 +
20133 + switch (cmd) {
20134 + case SNDRV_PCM_TRIGGER_START:
20135 + err = dma_prepare_request_cyclic(chip->dma.req_rx.req.dmac,
20136 + &chip->dma.req_rx);
20137 + dma_start_request(chip->dma.req_rx.req.dmac,
20138 + chip->dma.req_rx.req.channel);
20139 + camr |= AC97C_CMR_CENA;
20140 + break;
20141 + case SNDRV_PCM_TRIGGER_STOP:
20142 + err = dma_stop_request(chip->dma.req_rx.req.dmac,
20143 + chip->dma.req_rx.req.channel);
20144 + mutex_lock(&opened_mutex);
20145 + if (chip->opened <= 1)
20146 + camr &= ~AC97C_CMR_CENA;
20147 + mutex_unlock(&opened_mutex);
20148 + break;
20149 + default:
20150 + err = -EINVAL;
20151 + break;
20152 + }
20153 +
20154 + ac97c_writel(chip, CAMR, camr);
20155 +
20156 + spin_unlock_irqrestore(&chip->lock, flags);
20157 + return err;
20158 +}
20159 +
20160 + static snd_pcm_uframes_t
20161 +snd_atmel_ac97_playback_pointer(struct snd_pcm_substream *substream)
20162 +{
20163 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
20164 + struct snd_pcm_runtime *runtime = substream->runtime;
20165 + snd_pcm_uframes_t pos;
20166 + unsigned long bytes;
20167 +
20168 + bytes = (dma_get_current_pos
20169 + (chip->dma.req_tx.req.dmac,
20170 + chip->dma.req_tx.req.channel) - runtime->dma_addr);
20171 + pos = bytes_to_frames(runtime, bytes);
20172 + if (pos >= runtime->buffer_size)
20173 + pos -= runtime->buffer_size;
20174 +
20175 + return pos;
20176 +}
20177 +
20178 + static snd_pcm_uframes_t
20179 +snd_atmel_ac97_capture_pointer(struct snd_pcm_substream *substream)
20180 +{
20181 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
20182 + struct snd_pcm_runtime *runtime = substream->runtime;
20183 + snd_pcm_uframes_t pos;
20184 + unsigned long bytes;
20185 +
20186 + bytes = (dma_get_current_pos
20187 + (chip->dma.req_rx.req.dmac,
20188 + chip->dma.req_rx.req.channel)
20189 + - runtime->dma_addr);
20190 + pos = bytes_to_frames(runtime, bytes);
20191 + if (pos >= runtime->buffer_size)
20192 + pos -= runtime->buffer_size;
20193 +
20194 +
20195 + return pos;
20196 +}
20197 +
20198 +static struct snd_pcm_ops atmel_ac97_playback_ops = {
20199 + .open = snd_atmel_ac97_playback_open,
20200 + .close = snd_atmel_ac97_playback_close,
20201 + .ioctl = snd_pcm_lib_ioctl,
20202 + .hw_params = snd_atmel_ac97_playback_hw_params,
20203 + .hw_free = snd_atmel_ac97_playback_hw_free,
20204 + .prepare = snd_atmel_ac97_playback_prepare,
20205 + .trigger = snd_atmel_ac97_playback_trigger,
20206 + .pointer = snd_atmel_ac97_playback_pointer,
20207 +};
20208 +
20209 +static struct snd_pcm_ops atmel_ac97_capture_ops = {
20210 + .open = snd_atmel_ac97_capture_open,
20211 + .close = snd_atmel_ac97_capture_close,
20212 + .ioctl = snd_pcm_lib_ioctl,
20213 + .hw_params = snd_atmel_ac97_capture_hw_params,
20214 + .hw_free = snd_atmel_ac97_capture_hw_free,
20215 + .prepare = snd_atmel_ac97_capture_prepare,
20216 + .trigger = snd_atmel_ac97_capture_trigger,
20217 + .pointer = snd_atmel_ac97_capture_pointer,
20218 +};
20219 +
20220 +static struct ac97_pcm atmel_ac97_pcm_defs[] __devinitdata = {
20221 + /* Playback */
20222 + {
20223 + .exclusive = 1,
20224 + .r = { {
20225 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
20226 + | (1 << AC97_SLOT_PCM_RIGHT)
20227 + | (1 << AC97_SLOT_PCM_CENTER)
20228 + | (1 << AC97_SLOT_PCM_SLEFT)
20229 + | (1 << AC97_SLOT_PCM_SRIGHT)
20230 + | (1 << AC97_SLOT_LFE)),
20231 + } }
20232 + },
20233 + /* PCM in */
20234 + {
20235 + .stream = 1,
20236 + .exclusive = 1,
20237 + .r = { {
20238 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
20239 + | (1 << AC97_SLOT_PCM_RIGHT)),
20240 + } }
20241 + },
20242 + /* Mic in */
20243 + {
20244 + .stream = 1,
20245 + .exclusive = 1,
20246 + .r = { {
20247 + .slots = (1<<AC97_SLOT_MIC),
20248 + } }
20249 + },
20250 +};
20251 +
20252 +static int __devinit snd_atmel_ac97_pcm_new(struct atmel_ac97 *chip)
20253 +{
20254 + struct snd_pcm *pcm;
20255 + int err;
20256 +
20257 + err = snd_ac97_pcm_assign(chip->ac97_bus,
20258 + ARRAY_SIZE(atmel_ac97_pcm_defs),
20259 + atmel_ac97_pcm_defs);
20260 + if (err)
20261 + return err;
20262 +
20263 + err = snd_pcm_new(chip->card, "Atmel-AC97", 0, 1, 1, &pcm);
20264 + if (err)
20265 + return err;
20266 +
20267 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
20268 + &atmel_ac97_playback_ops);
20269 +
20270 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
20271 + &atmel_ac97_capture_ops);
20272 +
20273 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
20274 + &chip->pdev->dev,
20275 + 128 * 1024, 128 * 1024);
20276 +
20277 + pcm->private_data = chip;
20278 + pcm->info_flags = 0;
20279 + strcpy(pcm->name, "Atmel-AC97");
20280 + chip->pcm = pcm;
20281 +
20282 + return 0;
20283 +}
20284 +
20285 +/*
20286 + * Mixer part.
20287 + */
20288 +static int snd_atmel_ac97_mixer_new(struct atmel_ac97 *chip)
20289 +{
20290 + int err;
20291 + struct snd_ac97_template template;
20292 +
20293 + memset(&template, 0, sizeof(template));
20294 + template.private_data = chip;
20295 + err = snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
20296 +
20297 + return err;
20298 +}
20299 +
20300 +static void atmel_ac97_error(struct dma_request *_req)
20301 +{
20302 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
20303 + struct atmel_ac97 *chip = req->dev_id;
20304 +
20305 + dev_dbg(&chip->pdev->dev, "DMA Controller error, channel %d\n",
20306 + req->req.channel);
20307 +}
20308 +
20309 +static void atmel_ac97_block_complete(struct dma_request *_req)
20310 +{
20311 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
20312 + struct atmel_ac97 *chip = req->dev_id;
20313 + if (req->periph_id == chip->dma.tx_periph_id)
20314 + snd_pcm_period_elapsed(chip->playback_substream);
20315 + else
20316 + snd_pcm_period_elapsed(chip->capture_substream);
20317 +}
20318 +
20319 +/*
20320 + * Codec part.
20321 + */
20322 +static void snd_atmel_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
20323 + unsigned short val)
20324 +{
20325 + struct atmel_ac97 *chip = get_chip(ac97);
20326 + unsigned long word;
20327 + int timeout = 40;
20328 +
20329 + word = (reg & 0x7f) << 16 | val;
20330 +
20331 + do {
20332 + if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
20333 + ac97c_writel(chip, COTHR, word);
20334 + return;
20335 + }
20336 + udelay(1);
20337 + } while (--timeout);
20338 +
20339 + dev_dbg(&chip->pdev->dev, "codec write timeout\n");
20340 +}
20341 +
20342 +static unsigned short snd_atmel_ac97_read(struct snd_ac97 *ac97,
20343 + unsigned short reg)
20344 +{
20345 + struct atmel_ac97 *chip = get_chip(ac97);
20346 + unsigned long word;
20347 + int timeout = 40;
20348 + int write = 10;
20349 +
20350 + word = (0x80 | (reg & 0x7f)) << 16;
20351 +
20352 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
20353 + ac97c_readl(chip, CORHR);
20354 +
20355 +retry_write:
20356 + timeout = 40;
20357 +
20358 + do {
20359 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
20360 + ac97c_writel(chip, COTHR, word);
20361 + goto read_reg;
20362 + }
20363 + mdelay(10);
20364 + } while (--timeout);
20365 +
20366 + if (!--write)
20367 + goto timed_out;
20368 + goto retry_write;
20369 +
20370 +read_reg:
20371 + do {
20372 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
20373 + unsigned short val = ac97c_readl(chip, CORHR);
20374 + return val;
20375 + }
20376 + mdelay(10);
20377 + } while (--timeout);
20378 +
20379 + if (!--write)
20380 + goto timed_out;
20381 + goto retry_write;
20382 +
20383 +timed_out:
20384 + dev_dbg(&chip->pdev->dev, "codec read timeout\n");
20385 + return 0xffff;
20386 +}
20387 +
20388 +static void snd_atmel_ac97_reset(struct atmel_ac97 *chip)
20389 +{
20390 + ac97c_writel(chip, MR, AC97C_MR_WRST);
20391 + mdelay(1);
20392 + ac97c_writel(chip, MR, AC97C_MR_ENA);
20393 +}
20394 +
20395 +static void snd_atmel_ac97_destroy(struct snd_card *card)
20396 +{
20397 + struct atmel_ac97 *chip = get_chip(card);
20398 +
20399 + if (chip->regs)
20400 + iounmap(chip->regs);
20401 +
20402 + if (chip->mck) {
20403 + clk_disable(chip->mck);
20404 + clk_put(chip->mck);
20405 + }
20406 +
20407 + if (chip->dma.req_tx.req.dmac) {
20408 + dma_release_channel(chip->dma.req_tx.req.dmac,
20409 + chip->dma.req_tx.req.channel);
20410 + }
20411 + if (chip->dma.req_rx.req.dmac) {
20412 + dma_release_channel(chip->dma.req_rx.req.dmac,
20413 + chip->dma.req_rx.req.channel);
20414 + }
20415 +}
20416 +
20417 +static int __devinit snd_atmel_ac97_create(struct snd_card *card,
20418 + struct platform_device *pdev)
20419 +{
20420 + static struct snd_ac97_bus_ops ops = {
20421 + .write = snd_atmel_ac97_write,
20422 + .read = snd_atmel_ac97_read,
20423 + };
20424 + struct atmel_ac97 *chip = get_chip(card);
20425 + struct resource *regs;
20426 + struct clk *mck;
20427 + int err;
20428 +
20429 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
20430 + if (!regs)
20431 + return -ENXIO;
20432 +
20433 + mck = clk_get(&pdev->dev, "pclk");
20434 + if (IS_ERR(mck))
20435 + return PTR_ERR(mck);
20436 + clk_enable(mck);
20437 + chip->mck = mck;
20438 +
20439 + card->private_free = snd_atmel_ac97_destroy;
20440 +
20441 + spin_lock_init(&chip->lock);
20442 + chip->card = card;
20443 + chip->pdev = pdev;
20444 +
20445 + chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
20446 + if (!chip->regs)
20447 + return -ENOMEM;
20448 +
20449 + snd_card_set_dev(card, &pdev->dev);
20450 +
20451 + err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
20452 +
20453 + return err;
20454 +}
20455 +
20456 +static int __devinit snd_atmel_ac97_probe(struct platform_device *pdev)
20457 +{
20458 + static int dev;
20459 + struct snd_card *card;
20460 + struct atmel_ac97 *chip;
20461 + int err;
20462 + int ch;
20463 +
20464 + mutex_init(&opened_mutex);
20465 +
20466 + err = -ENOMEM;
20467 + card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
20468 + THIS_MODULE, sizeof(struct atmel_ac97));
20469 + if (!card)
20470 + goto out;
20471 + chip = get_chip(card);
20472 +
20473 + err = snd_atmel_ac97_create(card, pdev);
20474 + if (err)
20475 + goto out_free_card;
20476 +
20477 + snd_atmel_ac97_reset(chip);
20478 +
20479 + err = snd_atmel_ac97_mixer_new(chip);
20480 + if (err)
20481 + goto out_free_card;
20482 +
20483 + err = snd_atmel_ac97_pcm_new(chip);
20484 + if (err)
20485 + goto out_free_card;
20486 +
20487 + /* TODO: Get this information from the platform device */
20488 + chip->dma.req_tx.req.dmac = find_dma_controller(0);
20489 + if (!chip->dma.req_tx.req.dmac) {
20490 + dev_dbg(&chip->pdev->dev, "DMA controller for TX missing\n");
20491 + err = -ENODEV;
20492 + goto out_free_card;
20493 + }
20494 + chip->dma.req_rx.req.dmac = find_dma_controller(0);
20495 + if (!chip->dma.req_rx.req.dmac) {
20496 + dev_dbg(&chip->pdev->dev, "DMA controller for RX missing\n");
20497 + err = -ENODEV;
20498 + goto out_free_card;
20499 + }
20500 +
20501 + chip->dma.rx_periph_id = 3;
20502 + chip->dma.tx_periph_id = 4;
20503 +
20504 + ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
20505 + if (ch < 0) {
20506 + dev_dbg(&chip->pdev->dev,
20507 + "could not allocate TX DMA channel\n");
20508 + err = ch;
20509 + goto out_free_card;
20510 + }
20511 + chip->dma.req_tx.req.channel = ch;
20512 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
20513 + chip->dma.req_tx.req.block_complete = atmel_ac97_block_complete;
20514 + chip->dma.req_tx.req.error = atmel_ac97_error;
20515 +
20516 + ch = dma_alloc_channel(chip->dma.req_rx.req.dmac);
20517 + if (ch < 0) {
20518 + dev_dbg(&chip->pdev->dev,
20519 + "could not allocate RX DMA channel\n");
20520 + err = ch;
20521 + goto out_free_card;
20522 + }
20523 + chip->dma.req_rx.req.channel = ch;
20524 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
20525 + chip->dma.req_rx.req.block_complete = atmel_ac97_block_complete;
20526 + chip->dma.req_rx.req.error = atmel_ac97_error;
20527 +
20528 + strcpy(card->driver, "atmel_ac97c");
20529 + strcpy(card->shortname, "atmel_ac97c");
20530 + sprintf(card->longname, "Atmel AVR32 AC97 controller");
20531 +
20532 + err = snd_card_register(card);
20533 + if (err)
20534 + goto out_free_card;
20535 +
20536 + platform_set_drvdata(pdev, card);
20537 + dev++;
20538 +
20539 + dev_info(&pdev->dev, "Atmel AVR32 AC97 controller at 0x%p\n",
20540 + chip->regs);
20541 +
20542 + return 0;
20543 +
20544 +out_free_card:
20545 + snd_card_free(card);
20546 +out:
20547 + return err;
20548 +}
20549 +
20550 +#ifdef CONFIG_PM
20551 + static int
20552 +snd_atmel_ac97_suspend(struct platform_device *pdev, pm_message_t msg)
20553 +{
20554 + struct snd_card *card = platform_get_drvdata(pdev);
20555 + struct atmel_ac97 *chip = card->private_data;
20556 +
20557 + clk_disable(chip->mck);
20558 +
20559 + return 0;
20560 +}
20561 +
20562 +static int snd_atmel_ac97_resume(struct platform_device *pdev)
20563 +{
20564 + struct snd_card *card = dev_get_drvdata(pdev);
20565 + struct atmel_ac97 *chip = card->private_data;
20566 +
20567 + clk_enable(chip->mck);
20568 +
20569 + return 0;
20570 +}
20571 +#else
20572 +#define snd_atmel_ac97_suspend NULL
20573 +#define snd_atmel_ac97_resume NULL
20574 +#endif
20575 +
20576 +static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
20577 +{
20578 + struct snd_card *card = platform_get_drvdata(pdev);
20579 +
20580 + snd_card_free(card);
20581 + platform_set_drvdata(pdev, NULL);
20582 + return 0;
20583 +}
20584 +
20585 +static struct platform_driver atmel_ac97_driver = {
20586 + .remove = __devexit_p(snd_atmel_ac97_remove),
20587 + .driver = {
20588 + .name = "atmel_ac97c",
20589 + },
20590 + .suspend = snd_atmel_ac97_suspend,
20591 + .resume = snd_atmel_ac97_resume,
20592 +};
20593 +
20594 +static int __init atmel_ac97_init(void)
20595 +{
20596 + return platform_driver_probe(&atmel_ac97_driver,
20597 + snd_atmel_ac97_probe);
20598 +}
20599 +module_init(atmel_ac97_init);
20600 +
20601 +static void __exit atmel_ac97_exit(void)
20602 +{
20603 + platform_driver_unregister(&atmel_ac97_driver);
20604 +}
20605 +module_exit(atmel_ac97_exit);
20606 +
20607 +MODULE_LICENSE("GPL");
20608 +MODULE_DESCRIPTION("Driver for Atmel AC97 Controller");
20609 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
20610 --- /dev/null
20611 +++ b/sound/avr32/ac97c.h
20612 @@ -0,0 +1,71 @@
20613 +/*
20614 + * Register definitions for the Atmel AC97 Controller.
20615 + *
20616 + * Copyright (C) 2005-2006 Atmel Corporation
20617 + *
20618 + * This program is free software; you can redistribute it and/or modify
20619 + * it under the terms of the GNU General Public License version 2 as
20620 + * published by the Free Software Foundation.
20621 + */
20622 +#ifndef __SOUND_AVR32_AC97C_H
20623 +#define __SOUND_AVR32_AC97C_H
20624 +
20625 +#define AC97C_MR 0x08
20626 +#define AC97C_ICA 0x10
20627 +#define AC97C_OCA 0x14
20628 +#define AC97C_CARHR 0x20
20629 +#define AC97C_CATHR 0x24
20630 +#define AC97C_CASR 0x28
20631 +#define AC97C_CAMR 0x2c
20632 +#define AC97C_CBRHR 0x30
20633 +#define AC97C_CBTHR 0x34
20634 +#define AC97C_CBSR 0x38
20635 +#define AC97C_CBMR 0x3c
20636 +#define AC97C_CORHR 0x40
20637 +#define AC97C_COTHR 0x44
20638 +#define AC97C_COSR 0x48
20639 +#define AC97C_COMR 0x4c
20640 +#define AC97C_SR 0x50
20641 +#define AC97C_IER 0x54
20642 +#define AC97C_IDR 0x58
20643 +#define AC97C_IMR 0x5c
20644 +#define AC97C_VERSION 0xfc
20645 +
20646 +#define AC97C_CATPR PDC_TPR
20647 +#define AC97C_CATCR PDC_TCR
20648 +#define AC97C_CATNPR PDC_TNPR
20649 +#define AC97C_CATNCR PDC_TNCR
20650 +#define AC97C_CARPR PDC_RPR
20651 +#define AC97C_CARCR PDC_RCR
20652 +#define AC97C_CARNPR PDC_RNPR
20653 +#define AC97C_CARNCR PDC_RNCR
20654 +#define AC97C_PTCR PDC_PTCR
20655 +
20656 +#define AC97C_MR_ENA (1 << 0)
20657 +#define AC97C_MR_WRST (1 << 1)
20658 +#define AC97C_MR_VRA (1 << 2)
20659 +
20660 +#define AC97C_CSR_TXRDY (1 << 0)
20661 +#define AC97C_CSR_UNRUN (1 << 2)
20662 +#define AC97C_CSR_RXRDY (1 << 4)
20663 +#define AC97C_CSR_ENDTX (1 << 10)
20664 +#define AC97C_CSR_ENDRX (1 << 14)
20665 +
20666 +#define AC97C_CMR_SIZE_20 (0 << 16)
20667 +#define AC97C_CMR_SIZE_18 (1 << 16)
20668 +#define AC97C_CMR_SIZE_16 (2 << 16)
20669 +#define AC97C_CMR_SIZE_10 (3 << 16)
20670 +#define AC97C_CMR_CEM_LITTLE (1 << 18)
20671 +#define AC97C_CMR_CEM_BIG (0 << 18)
20672 +#define AC97C_CMR_CENA (1 << 21)
20673 +#define AC97C_CMR_PDCEN (1 << 22)
20674 +
20675 +#define AC97C_SR_CAEVT (1 << 3)
20676 +
20677 +#define AC97C_CH_ASSIGN(slot, channel) \
20678 + (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
20679 +#define AC97C_CHANNEL_NONE 0x0
20680 +#define AC97C_CHANNEL_A 0x1
20681 +#define AC97C_CHANNEL_B 0x2
20682 +
20683 +#endif /* __SOUND_AVR32_AC97C_H */
20684 --- /dev/null
20685 +++ b/sound/avr32/Kconfig
20686 @@ -0,0 +1,11 @@
20687 +menu "AVR32 devices"
20688 + depends on SND != n && AVR32
20689 +
20690 +config SND_ATMEL_AC97
20691 + tristate "Atmel AC97 Controller Driver"
20692 + select SND_PCM
20693 + select SND_AC97_CODEC
20694 + help
20695 + ALSA sound driver for the Atmel AC97 controller.
20696 +
20697 +endmenu
20698 --- /dev/null
20699 +++ b/sound/avr32/Makefile
20700 @@ -0,0 +1,3 @@
20701 +snd-atmel-ac97-objs := ac97c.o
20702 +
20703 +obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
20704 --- a/sound/Kconfig
20705 +++ b/sound/Kconfig
20706 @@ -63,6 +63,8 @@
20707
20708 source "sound/arm/Kconfig"
20709
20710 +source "sound/avr32/Kconfig"
20711 +
20712 if SPI
20713 source "sound/spi/Kconfig"
20714 endif
20715 --- a/sound/Makefile
20716 +++ b/sound/Makefile
20717 @@ -6,7 +6,7 @@
20718 obj-$(CONFIG_SOUND_PRIME) += oss/
20719 obj-$(CONFIG_DMASOUND) += oss/
20720 obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
20721 - sparc/ spi/ parisc/ pcmcia/ mips/ soc/
20722 + sparc/ spi/ parisc/ pcmcia/ mips/ soc/ avr32/
20723 obj-$(CONFIG_SND_AOA) += aoa/
20724
20725 # This one must be compilable even if sound is configured out
20726 --- /dev/null
20727 +++ b/sound/oss/at32_abdac.c
20728 @@ -0,0 +1,722 @@
20729 +/*
20730 + * OSS Sound Driver for the Atmel AT32 on-chip DAC.
20731 + *
20732 + * Copyright (C) 2006 Atmel Corporation
20733 + *
20734 + * This program is free software; you can redistribute it and/or modify
20735 + * it under the terms of the GNU General Public License version 2 as
20736 + * published by the Free Software Foundation.
20737 + */
20738 +#include <linux/clk.h>
20739 +#include <linux/dma-mapping.h>
20740 +#include <linux/fs.h>
20741 +#include <linux/init.h>
20742 +#include <linux/interrupt.h>
20743 +#include <linux/kernel.h>
20744 +#include <linux/module.h>
20745 +#include <linux/platform_device.h>
20746 +#include <linux/sound.h>
20747 +#include <linux/soundcard.h>
20748 +
20749 +#include <asm/byteorder.h>
20750 +#include <asm/dma-controller.h>
20751 +#include <asm/io.h>
20752 +#include <asm/uaccess.h>
20753 +
20754 +/* We want to use the "bizarre" swap-bytes-in-each-halfword macro */
20755 +#include <linux/byteorder/swabb.h>
20756 +
20757 +#include "at32_abdac.h"
20758 +
20759 +#define DMA_BUFFER_SIZE 32768
20760 +#define DMA_PERIOD_SHIFT 10
20761 +#define DMA_PERIOD_SIZE (1 << DMA_PERIOD_SHIFT)
20762 +#define DMA_WRITE_THRESHOLD DMA_PERIOD_SIZE
20763 +
20764 +struct sound_settings {
20765 + unsigned int format;
20766 + unsigned int channels;
20767 + unsigned int sample_rate;
20768 + /* log2(bytes per sample) */
20769 + unsigned int input_order;
20770 +};
20771 +
20772 +struct at32_dac {
20773 + spinlock_t lock;
20774 + void __iomem *regs;
20775 +
20776 + /* head and tail refer to number of words */
20777 + struct {
20778 + u32 *buf;
20779 + int head;
20780 + int tail;
20781 + } dma;
20782 +
20783 + struct semaphore sem;
20784 + wait_queue_head_t write_wait;
20785 +
20786 + /*
20787 + * Read at most ucount bytes from ubuf, translate to 2-channel
20788 + * signed 16-bit big endian format and write to the DMA buffer
20789 + * as long as there is room left. Return the number of bytes
20790 + * successfully copied from ubuf, or -EFAULT if the first
20791 + * sample from ubuf couldn't be read. This function is not
20792 + * called unless there is room for at least one sample (4
20793 + * bytes) in the DMA buffer.
20794 + */
20795 + ssize_t (*trans)(struct at32_dac *dac, const char __user *ubuf,
20796 + size_t ucount);
20797 +
20798 + struct sound_settings dsp_settings;
20799 + struct dma_request_cyclic req;
20800 +
20801 + struct clk *mck;
20802 + struct clk *sample_clk;
20803 + struct platform_device *pdev;
20804 + int busy;
20805 + int playing;
20806 + int dev_dsp;
20807 +};
20808 +static struct at32_dac *the_dac;
20809 +
20810 +static inline unsigned int abdac_get_head(struct at32_dac *dac)
20811 +{
20812 + return dac->dma.head & ((DMA_BUFFER_SIZE / 4) - 1);
20813 +}
20814 +
20815 +static inline unsigned int abdac_get_tail(struct at32_dac *dac)
20816 +{
20817 + return dac->dma.tail & ((DMA_BUFFER_SIZE / 4) - 1);
20818 +}
20819 +
20820 +static inline unsigned int abdac_dma_space(struct at32_dac *dac)
20821 +{
20822 + unsigned int space;
20823 +
20824 + space = ((dac->dma.tail - dac->dma.head - 1)
20825 + & ((DMA_BUFFER_SIZE / 4) - 1));
20826 + return space;
20827 +}
20828 +
20829 +static void abdac_update_dma_tail(struct at32_dac *dac)
20830 +{
20831 + dma_addr_t dma_addr;
20832 + unsigned int new_tail;
20833 +
20834 + if (dac->playing) {
20835 + dma_addr = dma_get_current_pos(dac->req.req.dmac,
20836 + dac->req.req.channel);
20837 + new_tail = (dma_addr - dac->req.buffer_start) / 4;
20838 + if (new_tail >= dac->dma.head
20839 + && (dac->dma.tail < dac->dma.head
20840 + || dac->dma.tail > new_tail))
20841 + dev_notice(&dac->pdev->dev, "DMA underrun detected!\n");
20842 + dac->dma.tail = new_tail;
20843 + dev_dbg(&dac->pdev->dev, "update tail: 0x%x - 0x%x = %u\n",
20844 + dma_addr, dac->req.buffer_start, dac->dma.tail);
20845 + }
20846 +}
20847 +
20848 +static int abdac_start(struct at32_dac *dac)
20849 +{
20850 + int ret;
20851 +
20852 + if (dac->playing)
20853 + return 0;
20854 +
20855 + memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
20856 +
20857 + clk_enable(dac->sample_clk);
20858 +
20859 + ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
20860 + if (ret)
20861 + goto out_stop_clock;
20862 +
20863 + dev_dbg(&dac->pdev->dev, "starting DMA...\n");
20864 + ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
20865 + if (ret)
20866 + goto out_stop_request;
20867 +
20868 + dac_writel(dac, CTRL, DAC_BIT(EN));
20869 + dac->playing = 1;
20870 +
20871 + return 0;
20872 +
20873 +out_stop_request:
20874 + dma_stop_request(dac->req.req.dmac,
20875 + dac->req.req.channel);
20876 +out_stop_clock:
20877 + clk_disable(dac->sample_clk);
20878 + return ret;
20879 +}
20880 +
20881 +static int abdac_stop(struct at32_dac *dac)
20882 +{
20883 + if (dac->playing) {
20884 + dma_stop_request(dac->req.req.dmac, dac->req.req.channel);
20885 + dac_writel(dac, DATA, 0);
20886 + dac_writel(dac, CTRL, 0);
20887 + dac->playing = 0;
20888 + clk_disable(dac->sample_clk);
20889 + }
20890 +
20891 + return 0;
20892 +}
20893 +
20894 +static int abdac_dma_prepare(struct at32_dac *dac)
20895 +{
20896 + dac->dma.buf = dma_alloc_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
20897 + &dac->req.buffer_start, GFP_KERNEL);
20898 + if (!dac->dma.buf)
20899 + return -ENOMEM;
20900 +
20901 + dac->dma.head = dac->dma.tail = 0;
20902 + dac->req.periods = DMA_BUFFER_SIZE / DMA_PERIOD_SIZE;
20903 + dac->req.buffer_size = DMA_BUFFER_SIZE;
20904 +
20905 + return 0;
20906 +}
20907 +
20908 +static void abdac_dma_cleanup(struct at32_dac *dac)
20909 +{
20910 + if (dac->dma.buf)
20911 + dma_free_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
20912 + dac->dma.buf, dac->req.buffer_start);
20913 + dac->dma.buf = NULL;
20914 +}
20915 +
20916 +static void abdac_dma_block_complete(struct dma_request *req)
20917 +{
20918 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
20919 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
20920 +
20921 + wake_up(&dac->write_wait);
20922 +}
20923 +
20924 +static void abdac_dma_error(struct dma_request *req)
20925 +{
20926 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
20927 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
20928 +
20929 + dev_err(&dac->pdev->dev, "DMA error\n");
20930 +}
20931 +
20932 +static irqreturn_t abdac_interrupt(int irq, void *dev_id)
20933 +{
20934 + struct at32_dac *dac = dev_id;
20935 + u32 status;
20936 +
20937 + status = dac_readl(dac, INT_STATUS);
20938 + if (status & DAC_BIT(UNDERRUN)) {
20939 + dev_err(&dac->pdev->dev, "Underrun detected!\n");
20940 + dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
20941 + } else {
20942 + dev_err(&dac->pdev->dev, "Spurious interrupt (status=0x%x)\n",
20943 + status);
20944 + dac_writel(dac, INT_CLR, status);
20945 + }
20946 +
20947 + return IRQ_HANDLED;
20948 +}
20949 +
20950 +static ssize_t trans_s16be(struct at32_dac *dac, const char __user *ubuf,
20951 + size_t ucount)
20952 +{
20953 + ssize_t ret;
20954 +
20955 + if (dac->dsp_settings.channels == 2) {
20956 + const u32 __user *up = (const u32 __user *)ubuf;
20957 + u32 sample;
20958 +
20959 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
20960 + if (!abdac_dma_space(dac))
20961 + break;
20962 +
20963 + if (unlikely(__get_user(sample, up++))) {
20964 + if (ret == 0)
20965 + ret = -EFAULT;
20966 + break;
20967 + }
20968 + dac->dma.buf[abdac_get_head(dac)] = sample;
20969 + dac->dma.head++;
20970 + }
20971 + } else {
20972 + const u16 __user *up = (const u16 __user *)ubuf;
20973 + u16 sample;
20974 +
20975 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
20976 + if (!abdac_dma_space(dac))
20977 + break;
20978 +
20979 + if (unlikely(__get_user(sample, up++))) {
20980 + if (ret == 0)
20981 + ret = -EFAULT;
20982 + break;
20983 + }
20984 + dac->dma.buf[abdac_get_head(dac)]
20985 + = (sample << 16) | sample;
20986 + dac->dma.head++;
20987 + }
20988 + }
20989 +
20990 + return ret;
20991 +}
20992 +
20993 +static ssize_t trans_s16le(struct at32_dac *dac, const char __user *ubuf,
20994 + size_t ucount)
20995 +{
20996 + ssize_t ret;
20997 +
20998 + if (dac->dsp_settings.channels == 2) {
20999 + const u32 __user *up = (const u32 __user *)ubuf;
21000 + u32 sample;
21001 +
21002 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
21003 + if (!abdac_dma_space(dac))
21004 + break;
21005 +
21006 + if (unlikely(__get_user(sample, up++))) {
21007 + if (ret == 0)
21008 + ret = -EFAULT;
21009 + break;
21010 + }
21011 + /* Swap bytes in each halfword */
21012 + dac->dma.buf[abdac_get_head(dac)] = swahb32(sample);
21013 + dac->dma.head++;
21014 + }
21015 + } else {
21016 + const u16 __user *up = (const u16 __user *)ubuf;
21017 + u16 sample;
21018 +
21019 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
21020 + if (!abdac_dma_space(dac))
21021 + break;
21022 +
21023 + if (unlikely(__get_user(sample, up++))) {
21024 + if (ret == 0)
21025 + ret = -EFAULT;
21026 + break;
21027 + }
21028 + sample = swab16(sample);
21029 + dac->dma.buf[abdac_get_head(dac)]
21030 + = (sample << 16) | sample;
21031 + dac->dma.head++;
21032 + }
21033 + }
21034 +
21035 + return ret;
21036 +}
21037 +
21038 +static ssize_t abdac_dma_translate_from_user(struct at32_dac *dac,
21039 + const char __user *buffer,
21040 + size_t count)
21041 +{
21042 + /* At least one buffer must be available at this point */
21043 + dev_dbg(&dac->pdev->dev, "copying %zu bytes from user...\n", count);
21044 +
21045 + return dac->trans(dac, buffer, count);
21046 +}
21047 +
21048 +static int abdac_set_format(struct at32_dac *dac, int format)
21049 +{
21050 + unsigned int order;
21051 +
21052 + switch (format) {
21053 + case AFMT_S16_BE:
21054 + order = 1;
21055 + dac->trans = trans_s16be;
21056 + break;
21057 + case AFMT_S16_LE:
21058 + order = 1;
21059 + dac->trans = trans_s16le;
21060 + break;
21061 + default:
21062 + dev_dbg(&dac->pdev->dev, "unsupported format: %d\n", format);
21063 + return -EINVAL;
21064 + }
21065 +
21066 + if (dac->dsp_settings.channels == 2)
21067 + order++;
21068 +
21069 + dac->dsp_settings.input_order = order;
21070 + dac->dsp_settings.format = format;
21071 + return 0;
21072 +}
21073 +
21074 +static int abdac_set_sample_rate(struct at32_dac *dac, unsigned long rate)
21075 +{
21076 + unsigned long new_rate;
21077 + int ret;
21078 +
21079 + ret = clk_set_rate(dac->sample_clk, 256 * rate);
21080 + if (ret < 0)
21081 + return ret;
21082 +
21083 + /* TODO: mplayer seems to have a problem with this */
21084 +#if 0
21085 + new_rate = clk_get_rate(dac->sample_clk);
21086 + dac->dsp_settings.sample_rate = new_rate / 256;
21087 +#else
21088 + dac->dsp_settings.sample_rate = rate;
21089 +#endif
21090 +
21091 + return 0;
21092 +}
21093 +
21094 +static ssize_t abdac_dsp_write(struct file *file,
21095 + const char __user *buffer,
21096 + size_t count, loff_t *ppos)
21097 +{
21098 + struct at32_dac *dac = file->private_data;
21099 + DECLARE_WAITQUEUE(wait, current);
21100 + unsigned int avail;
21101 + ssize_t copied;
21102 + ssize_t ret;
21103 +
21104 + /* Avoid address space checking in the translation functions */
21105 + if (!access_ok(buffer, count, VERIFY_READ))
21106 + return -EFAULT;
21107 +
21108 + down(&dac->sem);
21109 +
21110 + if (!dac->dma.buf) {
21111 + ret = abdac_dma_prepare(dac);
21112 + if (ret)
21113 + goto out;
21114 + }
21115 +
21116 + add_wait_queue(&dac->write_wait, &wait);
21117 + ret = 0;
21118 + while (count > 0) {
21119 + do {
21120 + abdac_update_dma_tail(dac);
21121 + avail = abdac_dma_space(dac);
21122 + set_current_state(TASK_INTERRUPTIBLE);
21123 + if (avail >= DMA_WRITE_THRESHOLD)
21124 + break;
21125 +
21126 + if (file->f_flags & O_NONBLOCK) {
21127 + if (!ret)
21128 + ret = -EAGAIN;
21129 + goto out;
21130 + }
21131 +
21132 + pr_debug("Going to wait (avail = %u, count = %zu)\n",
21133 + avail, count);
21134 +
21135 + up(&dac->sem);
21136 + schedule();
21137 + if (signal_pending(current)) {
21138 + if (!ret)
21139 + ret = -ERESTARTSYS;
21140 + goto out_nosem;
21141 + }
21142 + down(&dac->sem);
21143 + } while (1);
21144 +
21145 + copied = abdac_dma_translate_from_user(dac, buffer, count);
21146 + if (copied < 0) {
21147 + if (!ret)
21148 + ret = -EFAULT;
21149 + goto out;
21150 + }
21151 +
21152 + abdac_start(dac);
21153 +
21154 + count -= copied;
21155 + ret += copied;
21156 + }
21157 +
21158 +out:
21159 + up(&dac->sem);
21160 +out_nosem:
21161 + remove_wait_queue(&dac->write_wait, &wait);
21162 + set_current_state(TASK_RUNNING);
21163 + return ret;
21164 +}
21165 +
21166 +static int abdac_dsp_ioctl(struct inode *inode, struct file *file,
21167 + unsigned int cmd, unsigned long arg)
21168 +{
21169 + struct at32_dac *dac = file->private_data;
21170 + int __user *up = (int __user *)arg;
21171 + struct audio_buf_info abinfo;
21172 + int val, ret;
21173 +
21174 + switch (cmd) {
21175 + case OSS_GETVERSION:
21176 + return put_user(SOUND_VERSION, up);
21177 +
21178 + case SNDCTL_DSP_SPEED:
21179 + if (get_user(val, up))
21180 + return -EFAULT;
21181 + if (val >= 0) {
21182 + abdac_stop(dac);
21183 + ret = abdac_set_sample_rate(dac, val);
21184 + if (ret)
21185 + return ret;
21186 + }
21187 + return put_user(dac->dsp_settings.sample_rate, up);
21188 +
21189 + case SNDCTL_DSP_STEREO:
21190 + if (get_user(val, up))
21191 + return -EFAULT;
21192 + abdac_stop(dac);
21193 + if (val && dac->dsp_settings.channels == 1)
21194 + dac->dsp_settings.input_order++;
21195 + else if (!val && dac->dsp_settings.channels != 1)
21196 + dac->dsp_settings.input_order--;
21197 + dac->dsp_settings.channels = val ? 2 : 1;
21198 + return 0;
21199 +
21200 + case SNDCTL_DSP_CHANNELS:
21201 + if (get_user(val, up))
21202 + return -EFAULT;
21203 +
21204 + if (val) {
21205 + if (val < 0 || val > 2)
21206 + return -EINVAL;
21207 +
21208 + abdac_stop(dac);
21209 + dac->dsp_settings.input_order
21210 + += val - dac->dsp_settings.channels;
21211 + dac->dsp_settings.channels = val;
21212 + }
21213 + return put_user(val, (int *)arg);
21214 +
21215 + case SNDCTL_DSP_GETFMTS:
21216 + return put_user(AFMT_S16_BE | AFMT_S16_BE, up);
21217 +
21218 + case SNDCTL_DSP_SETFMT:
21219 + if (get_user(val, up))
21220 + return -EFAULT;
21221 +
21222 + if (val == AFMT_QUERY) {
21223 + val = dac->dsp_settings.format;
21224 + } else {
21225 + ret = abdac_set_format(dac, val);
21226 + if (ret)
21227 + return ret;
21228 + }
21229 + return put_user(val, up);
21230 +
21231 + case SNDCTL_DSP_GETOSPACE:
21232 + abdac_update_dma_tail(dac);
21233 + abinfo.fragsize = ((1 << dac->dsp_settings.input_order)
21234 + * (DMA_PERIOD_SIZE / 4));
21235 + abinfo.bytes = (abdac_dma_space(dac)
21236 + << dac->dsp_settings.input_order);
21237 + abinfo.fragstotal = ((DMA_BUFFER_SIZE * 4)
21238 + >> (DMA_PERIOD_SHIFT
21239 + + dac->dsp_settings.input_order));
21240 + abinfo.fragments = ((abinfo.bytes
21241 + >> dac->dsp_settings.input_order)
21242 + / (DMA_PERIOD_SIZE / 4));
21243 + pr_debug("fragments=%d fragstotal=%d fragsize=%d bytes=%d\n",
21244 + abinfo.fragments, abinfo.fragstotal, abinfo.fragsize,
21245 + abinfo.bytes);
21246 + return copy_to_user(up, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
21247 +
21248 + default:
21249 + dev_dbg(&dac->pdev->dev, "Unimplemented ioctl cmd: 0x%x\n", cmd);
21250 + return -EINVAL;
21251 + }
21252 +}
21253 +
21254 +static int abdac_dsp_open(struct inode *inode, struct file *file)
21255 +{
21256 + struct at32_dac *dac = the_dac;
21257 + int ret;
21258 +
21259 + if (file->f_mode & FMODE_READ)
21260 + return -ENXIO;
21261 +
21262 + down(&dac->sem);
21263 + ret = -EBUSY;
21264 + if (dac->busy)
21265 + goto out;
21266 +
21267 + dac->dma.head = dac->dma.tail = 0;
21268 +
21269 + /* FIXME: What are the correct defaults? */
21270 + dac->dsp_settings.channels = 2;
21271 + abdac_set_format(dac, AFMT_S16_BE);
21272 + ret = abdac_set_sample_rate(dac, 8000);
21273 + if (ret)
21274 + goto out;
21275 +
21276 + file->private_data = dac;
21277 + dac->busy = 1;
21278 +
21279 + ret = 0;
21280 +
21281 +out:
21282 + up(&dac->sem);
21283 + return ret;
21284 +}
21285 +
21286 +static int abdac_dsp_release(struct inode *inode, struct file *file)
21287 +{
21288 + struct at32_dac *dac = file->private_data;
21289 +
21290 + down(&dac->sem);
21291 +
21292 + abdac_stop(dac);
21293 + abdac_dma_cleanup(dac);
21294 + dac->busy = 0;
21295 +
21296 + up(&dac->sem);
21297 +
21298 + return 0;
21299 +}
21300 +
21301 +static struct file_operations abdac_dsp_fops = {
21302 + .owner = THIS_MODULE,
21303 + .llseek = no_llseek,
21304 + .write = abdac_dsp_write,
21305 + .ioctl = abdac_dsp_ioctl,
21306 + .open = abdac_dsp_open,
21307 + .release = abdac_dsp_release,
21308 +};
21309 +
21310 +static int __init abdac_probe(struct platform_device *pdev)
21311 +{
21312 + struct at32_dac *dac;
21313 + struct resource *regs;
21314 + struct clk *mck;
21315 + struct clk *sample_clk;
21316 + int irq;
21317 + int ret;
21318 +
21319 + if (the_dac)
21320 + return -EBUSY;
21321 +
21322 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
21323 + if (!regs)
21324 + return -ENXIO;
21325 + irq = platform_get_irq(pdev, 0);
21326 + if (irq < 0)
21327 + return irq;
21328 +
21329 + mck = clk_get(&pdev->dev, "pclk");
21330 + if (IS_ERR(mck))
21331 + return PTR_ERR(mck);
21332 + sample_clk = clk_get(&pdev->dev, "sample_clk");
21333 + if (IS_ERR(sample_clk)) {
21334 + ret = PTR_ERR(sample_clk);
21335 + goto out_put_mck;
21336 + }
21337 + clk_enable(mck);
21338 +
21339 + ret = -ENOMEM;
21340 + dac = kzalloc(sizeof(struct at32_dac), GFP_KERNEL);
21341 + if (!dac)
21342 + goto out_disable_clk;
21343 +
21344 + spin_lock_init(&dac->lock);
21345 + init_MUTEX(&dac->sem);
21346 + init_waitqueue_head(&dac->write_wait);
21347 + dac->pdev = pdev;
21348 + dac->mck = mck;
21349 + dac->sample_clk = sample_clk;
21350 +
21351 + dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
21352 + if (!dac->regs)
21353 + goto out_free_dac;
21354 +
21355 + ret = request_irq(irq, abdac_interrupt, 0, "dac", dac);
21356 + if (ret)
21357 + goto out_unmap_regs;
21358 +
21359 + /* FIXME */
21360 + dac->req.req.dmac = find_dma_controller(0);
21361 + if (!dac->req.req.dmac)
21362 + goto out_free_irq;
21363 +
21364 + ret = dma_alloc_channel(dac->req.req.dmac);
21365 + if (ret < 0)
21366 + goto out_free_irq;
21367 +
21368 + dac->req.req.channel = ret;
21369 + dac->req.req.block_complete = abdac_dma_block_complete;
21370 + dac->req.req.error = abdac_dma_error;
21371 + dac->req.data_reg = regs->start + DAC_DATA;
21372 + dac->req.periph_id = 2; /* FIXME */
21373 + dac->req.direction = DMA_DIR_MEM_TO_PERIPH;
21374 + dac->req.width = DMA_WIDTH_32BIT;
21375 +
21376 + /* Make sure the DAC is silent and disabled */
21377 + dac_writel(dac, DATA, 0);
21378 + dac_writel(dac, CTRL, 0);
21379 +
21380 + ret = register_sound_dsp(&abdac_dsp_fops, -1);
21381 + if (ret < 0)
21382 + goto out_free_dma;
21383 + dac->dev_dsp = ret;
21384 +
21385 + /* TODO: Register mixer */
21386 +
21387 + the_dac = dac;
21388 + platform_set_drvdata(pdev, dac);
21389 +
21390 + return 0;
21391 +
21392 +out_free_dma:
21393 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
21394 +out_free_irq:
21395 + free_irq(irq, dac);
21396 +out_unmap_regs:
21397 + iounmap(dac->regs);
21398 +out_free_dac:
21399 + kfree(dac);
21400 +out_disable_clk:
21401 + clk_disable(mck);
21402 + clk_put(sample_clk);
21403 +out_put_mck:
21404 + clk_put(mck);
21405 + return ret;
21406 +}
21407 +
21408 +static int __exit abdac_remove(struct platform_device *pdev)
21409 +{
21410 + struct at32_dac *dac;
21411 +
21412 + dac = platform_get_drvdata(pdev);
21413 + if (dac) {
21414 + unregister_sound_dsp(dac->dev_dsp);
21415 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
21416 + free_irq(platform_get_irq(pdev, 0), dac);
21417 + iounmap(dac->regs);
21418 + clk_disable(dac->mck);
21419 + clk_put(dac->sample_clk);
21420 + clk_put(dac->mck);
21421 + kfree(dac);
21422 + platform_set_drvdata(pdev, NULL);
21423 + the_dac = NULL;
21424 + }
21425 +
21426 + return 0;
21427 +}
21428 +
21429 +static struct platform_driver abdac_driver = {
21430 + .remove = __exit_p(abdac_remove),
21431 + .driver = {
21432 + .name = "abdac",
21433 + },
21434 +};
21435 +
21436 +static int __init abdac_init(void)
21437 +{
21438 + return platform_driver_probe(&abdac_driver, abdac_probe);
21439 +}
21440 +module_init(abdac_init);
21441 +
21442 +static void __exit abdac_exit(void)
21443 +{
21444 + platform_driver_unregister(&abdac_driver);
21445 +}
21446 +module_exit(abdac_exit);
21447 +
21448 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
21449 +MODULE_DESCRIPTION("Sound Driver for the Atmel AT32 ABDAC");
21450 +MODULE_LICENSE("GPL");
21451 --- /dev/null
21452 +++ b/sound/oss/at32_abdac.h
21453 @@ -0,0 +1,59 @@
21454 +/*
21455 + * Register definitions for the Atmel AT32 on-chip DAC.
21456 + *
21457 + * Copyright (C) 2006 Atmel Corporation
21458 + *
21459 + * This program is free software; you can redistribute it and/or modify
21460 + * it under the terms of the GNU General Public License version 2 as
21461 + * published by the Free Software Foundation.
21462 + */
21463 +#ifndef __SOUND_OSS_AT32_ABDAC_H__
21464 +#define __SOUND_OSS_AT32_ABDAC_H__
21465 +
21466 +/* DAC register offsets */
21467 +#define DAC_DATA 0x0000
21468 +#define DAC_CTRL 0x0008
21469 +#define DAC_INT_MASK 0x000c
21470 +#define DAC_INT_EN 0x0010
21471 +#define DAC_INT_DIS 0x0014
21472 +#define DAC_INT_CLR 0x0018
21473 +#define DAC_INT_STATUS 0x001c
21474 +#define DAC_PDC_DATA 0x0020
21475 +
21476 +/* Bitfields in CTRL */
21477 +#define DAC_SWAP_OFFSET 30
21478 +#define DAC_SWAP_SIZE 1
21479 +#define DAC_EN_OFFSET 31
21480 +#define DAC_EN_SIZE 1
21481 +
21482 +/* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
21483 +#define DAC_UNDERRUN_OFFSET 28
21484 +#define DAC_UNDERRUN_SIZE 1
21485 +#define DAC_TX_READY_OFFSET 29
21486 +#define DAC_TX_READY_SIZE 1
21487 +#define DAC_TX_BUFFER_EMPTY_OFFSET 30
21488 +#define DAC_TX_BUFFER_EMPTY_SIZE 1
21489 +#define DAC_CHANNEL_TX_END_OFFSET 31
21490 +#define DAC_CHANNEL_TX_END_SIZE 1
21491 +
21492 +/* Bit manipulation macros */
21493 +#define DAC_BIT(name) \
21494 + (1 << DAC_##name##_OFFSET)
21495 +#define DAC_BF(name, value) \
21496 + (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
21497 + << DAC_##name##_OFFSET)
21498 +#define DAC_BFEXT(name, value) \
21499 + (((value) >> DAC_##name##_OFFSET) \
21500 + & ((1 << DAC_##name##_SIZE) - 1))
21501 +#define DAC_BFINS(name, value, old) \
21502 + (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
21503 + << DAC_##name##_OFFSET)) \
21504 + | DAC_BF(name,value))
21505 +
21506 +/* Register access macros */
21507 +#define dac_readl(port, reg) \
21508 + __raw_readl((port)->regs + DAC_##reg)
21509 +#define dac_writel(port, reg, value) \
21510 + __raw_writel((value), (port)->regs + DAC_##reg)
21511 +
21512 +#endif /* __SOUND_OSS_AT32_ABDAC_H__ */
21513 --- a/sound/oss/Kconfig
21514 +++ b/sound/oss/Kconfig
21515 @@ -654,3 +654,7 @@
21516 int "DAC channel"
21517 default "1"
21518 depends on SOUND_SH_DAC_AUDIO
21519 +
21520 +config SOUND_AT32_ABDAC
21521 + tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
21522 + depends on SOUND_PRIME && AVR32
21523 --- a/sound/oss/Makefile
21524 +++ b/sound/oss/Makefile
21525 @@ -10,6 +10,7 @@
21526
21527 # Please leave it as is, cause the link order is significant !
21528
21529 +obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
21530 obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
21531 obj-$(CONFIG_SOUND_HAL2) += hal2.o
21532 obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
21533 --- a/sound/spi/at73c213.c
21534 +++ b/sound/spi/at73c213.c
21535 @@ -744,7 +744,7 @@
21536 /*
21537 * Device functions
21538 */
21539 -static int snd_at73c213_ssc_init(struct snd_at73c213 *chip)
21540 +static int __devinit snd_at73c213_ssc_init(struct snd_at73c213 *chip)
21541 {
21542 /*
21543 * Continuous clock output.
21544 @@ -774,7 +774,7 @@
21545 return 0;
21546 }
21547
21548 -static int snd_at73c213_chip_init(struct snd_at73c213 *chip)
21549 +static int __devinit snd_at73c213_chip_init(struct snd_at73c213 *chip)
21550 {
21551 int retval;
21552 unsigned char dac_ctrl = 0;
21553 @@ -939,7 +939,7 @@
21554 return retval;
21555 }
21556
21557 -static int snd_at73c213_probe(struct spi_device *spi)
21558 +static int __devinit snd_at73c213_probe(struct spi_device *spi)
21559 {
21560 struct snd_card *card;
21561 struct snd_at73c213 *chip;
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