package/linux/kernel-source/arch/mips/brcm-boards/bcm947xx/perfcntr.c

   1 /*
   2  * Broadcom BCM47xx Performance Counter /proc/cpuinfo support
   3  *
   4  * Copyright 2004, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #include <asm/mipsregs.h>
  16
  17 /*
  18  * BCM4710 performance counter register select values
  19  * No even-odd control-counter mapping, just counters
  20  */
  21 #define PERF_DCACHE_HIT         0
  22 #define PERF_DCACHE_MISS        1
  23 #define PERF_ICACHE_HIT         2
  24 #define PERF_ICACHE_MISS        3
  25 #define PERF_ICOUNT             4
  26
  27 /*
  28  * Move from Coprocessor 0 Register 25 Select n
  29  * data <- CPR[0,25,n]
  30  * GPR[1] <- data
  31  */
  32 #define read_bcm4710_perf_cntr(n)                               \
  33 ({ int __res;                                                   \
  34         __asm__ __volatile__(                                   \
  35         ".set\tnoreorder\n\t"                                   \
  36         ".set\tnoat\n\t"                                        \
  37         ".word\t"STR(0x4001c800|(n))"\n\t"                      \
  38         "move\t%0,$1\n\t"                                       \
  39         ".set\tat\n\t"                                          \
  40         ".set\treorder"                                         \
  41         :"=r" (__res));                                         \
  42         __res;})
  43
  44 asmlinkage unsigned int read_perf_cntr(unsigned int counter)
  45 {
  46         switch (counter) {
  47         case PERF_DCACHE_HIT:   return read_bcm4710_perf_cntr(PERF_DCACHE_HIT);
  48         case PERF_DCACHE_MISS:  return read_bcm4710_perf_cntr(PERF_DCACHE_MISS);
  49         case PERF_ICACHE_HIT:   return read_bcm4710_perf_cntr(PERF_ICACHE_HIT);
  50         case PERF_ICACHE_MISS:  return read_bcm4710_perf_cntr(PERF_ICACHE_MISS);
  51         case PERF_ICOUNT:       return read_bcm4710_perf_cntr(PERF_ICOUNT);
  52         }
  53         return 0;
  54 }
  55
  56 asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val)
  57 {
  58 }
  59
  60 asmlinkage unsigned int read_perf_cntl(unsigned int counter)
  61 {
  62         return 0;
  63 }
  64
  65 asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val)
  66 {
  67 }