package/uboot-xburst/files/cpu/mips/jz_lcd.h

   1 /*
   2  * JzRISC lcd controller
   3  *
   4  * xiangfu liu <xiangfu.z@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __JZLCD_H__
  23 #define __JZLCD_H__
  24
  25 #include <asm/io.h>
  26 /*
  27  * change u-boot macro to celinux macro
  28  */
  29 /* Chip type */
  30 #if defined(CONFIG_JZ4740)
  31 #define CONFIG_MIPS_JZ4740              1
  32 #endif
  33
  34 /* board type */
  35 #if defined(CONFIG_NANONOTE)
  36 #define CONFIG_MIPS_JZ4740_PI           1
  37 #endif
  38
  39 #define mdelay(n)               udelay((n)*1000)
  40
  41 /*
  42  * change u-boot macro to celinux macro
  43  */
  44
  45 #define NR_PALETTE      256
  46
  47 struct lcd_desc{
  48         unsigned int next_desc; /* LCDDAx */
  49         unsigned int databuf;   /* LCDSAx */
  50         unsigned int frame_id;  /* LCDFIDx */
  51         unsigned int cmd;       /* LCDCMDx */
  52 };
  53
  54 #define MODE_MASK               0x0f
  55 #define MODE_TFT_GEN            0x00
  56 #define MODE_TFT_SHARP          0x01
  57 #define MODE_TFT_CASIO          0x02
  58 #define MODE_TFT_SAMSUNG        0x03
  59 #define MODE_CCIR656_NONINT     0x04
  60 #define MODE_CCIR656_INT        0x05
  61 #define MODE_STN_COLOR_SINGLE   0x08
  62 #define MODE_STN_MONO_SINGLE    0x09
  63 #define MODE_STN_COLOR_DUAL     0x0a
  64 #define MODE_STN_MONO_DUAL      0x0b
  65 #define MODE_8BIT_SERIAL_TFT    0x0c
  66
  67 #define MODE_TFT_18BIT          (1<<7)
  68
  69 #define STN_DAT_PIN1    (0x00 << 4)
  70 #define STN_DAT_PIN2    (0x01 << 4)
  71 #define STN_DAT_PIN4    (0x02 << 4)
  72 #define STN_DAT_PIN8    (0x03 << 4)
  73 #define STN_DAT_PINMASK STN_DAT_PIN8
  74
  75 #define STFT_PSHI       (1 << 15)
  76 #define STFT_CLSHI      (1 << 14)
  77 #define STFT_SPLHI      (1 << 13)
  78 #define STFT_REVHI      (1 << 12)
  79
  80 #define SYNC_MASTER     (0 << 16)
  81 #define SYNC_SLAVE      (1 << 16)
  82
  83 #define DE_P            (0 << 9)
  84 #define DE_N            (1 << 9)
  85
  86 #define PCLK_P          (0 << 10)
  87 #define PCLK_N          (1 << 10)
  88
  89 #define HSYNC_P         (0 << 11)
  90 #define HSYNC_N         (1 << 11)
  91
  92 #define VSYNC_P         (0 << 8)
  93 #define VSYNC_N         (1 << 8)
  94
  95 #define DATA_NORMAL     (0 << 17)
  96 #define DATA_INVERSE    (1 << 17)
  97
  98
  99 /* Jz LCDFB supported I/O controls. */
 100 #define FBIOSETBACKLIGHT        0x4688
 101 #define FBIODISPON              0x4689
 102 #define FBIODISPOFF             0x468a
 103 #define FBIORESET               0x468b
 104 #define FBIOPRINT_REG           0x468c
 105
 106 /*
 107  * LCD panel specific definition
 108  */
 109
 110 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
 111
 112 #if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
 113 #define MODE 0xcd               /* 24bit parellel RGB */
 114 #endif
 115 #if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
 116 #define MODE 0xc9               /* 8bit serial RGB */
 117 #endif
 118
 119 #if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
 120         #define SPEN    (32*2+21)       /*LCD_SPL */
 121         #define SPCK    (32*2+23)       /*LCD_CLS */
 122         #define SPDA    (32*2+22)       /*LCD_D12 */
 123         #define LCD_RET (32*3+27)
 124 #else
 125 #error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
 126 #endif
 127
 128         #define __spi_write_reg1(reg, val) \
 129         do { \
 130                 unsigned char no;\
 131                 unsigned short value;\
 132                 unsigned char a=0;\
 133                 unsigned char b=0;\
 134                 a=reg;\
 135                 b=val;\
 136                 __gpio_set_pin(SPEN);\
 137                 __gpio_set_pin(SPCK);\
 138                 __gpio_clear_pin(SPDA);\
 139                 __gpio_clear_pin(SPEN);\
 140                 udelay(25);\
 141                 value=((a<<8)|(b&0xFF));\
 142                 for(no=0;no<16;no++)\
 143                 {\
 144                         __gpio_clear_pin(SPCK);\
 145                         if((value&0x8000)==0x8000)\
 146                         __gpio_set_pin(SPDA);\
 147                         else\
 148                         __gpio_clear_pin(SPDA);\
 149                         udelay(25);\
 150                         __gpio_set_pin(SPCK);\
 151                         value=(value<<1); \
 152                         udelay(25);\
 153                  }\
 154                 __gpio_set_pin(SPEN);\
 155                 udelay(100);\
 156         } while (0)
 157
 158         #define __spi_write_reg(reg, val) \
 159         do {\
 160                 __spi_write_reg1((reg<<2|2), val);\
 161                 udelay(100); \
 162         }while(0)
 163
 164
 165         #define __lcd_special_pin_init() \
 166         do { \
 167                 __gpio_as_output(SPEN); /* use SPDA */\
 168                 __gpio_as_output(SPCK); /* use SPCK */\
 169                 __gpio_as_output(SPDA); /* use SPDA */\
 170                 __gpio_as_output(LCD_RET);\
 171         } while (0)
 172
 173 #if defined(CONFIG_NANONOTE)
 174         #define __lcd_special_on() \
 175                 do { \
 176                 udelay(50);\
 177                 __spi_write_reg1(0x05, 0x16); \
 178                 __spi_write_reg1(0x04, 0x0b); \
 179                 __spi_write_reg1(0x07, 0x8d); \
 180                 __spi_write_reg1(0x01, 0x95); \
 181                 __spi_write_reg1(0x08, 0xc0); \
 182                 __spi_write_reg1(0x03, 0x40); \
 183                 __spi_write_reg1(0x06, 0x15); \
 184                 __spi_write_reg1(0x05, 0xd7); \
 185                 } while (0)     /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
 186
 187         #define __lcd_special_off()                             \
 188                           do {                                  \
 189                                   __spi_write_reg1(0x05, 0x5e); \
 190                           } while (0)
 191 #endif  /* CONFIG_NANONOTE */
 192 #endif  /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
 193
 194 #ifndef __lcd_special_pin_init
 195 #define __lcd_special_pin_init()
 196 #endif
 197 #ifndef __lcd_special_on
 198 #define __lcd_special_on()
 199 #endif
 200 #ifndef __lcd_special_off
 201 #define __lcd_special_off()
 202 #endif
 203
 204
 205 /*
 206  * Platform specific definition
 207  */
 208
 209 #if defined(CONFIG_MIPS_JZ4740_PI)
 210
 211         /* 100 level: 0,1,...,100 */
 212         #define __lcd_set_backlight_level(n)\
 213         do { \
 214         __gpio_as_output(32*3+27); \
 215         __gpio_set_pin(32*3+27); \
 216         } while (0)
 217
 218         #define __lcd_close_backlight() \
 219         do { \
 220         __gpio_as_output(GPIO_PWM); \
 221         __gpio_clear_pin(GPIO_PWM); \
 222         } while (0)
 223
 224         #define __lcd_display_pin_init() \
 225         do { \
 226                 __gpio_as_output(GPIO_DISP_OFF_N); \
 227                 __cpm_start_tcu(); \
 228                 __lcd_special_pin_init(); \
 229         } while (0)
 230         /*      __lcd_set_backlight_level(100); \*/
 231         #define __lcd_display_on() \
 232         do { \
 233                 __gpio_set_pin(GPIO_DISP_OFF_N); \
 234                 __lcd_special_on(); \
 235         } while (0)
 236
 237         #define __lcd_display_off() \
 238         do { \
 239                 __lcd_special_off(); \
 240                 __gpio_clear_pin(GPIO_DISP_OFF_N); \
 241         } while (0)
 242
 243 #endif /* CONFIG_MIPS_JZ4740_PI) */
 244
 245 /*****************************************************************************
 246  * LCD display pin dummy macros
 247  *****************************************************************************/
 248 #ifndef __lcd_display_pin_init
 249 #define __lcd_display_pin_init()
 250 #endif
 251 #ifndef __lcd_display_on
 252 #define __lcd_display_on()
 253 #endif
 254 #ifndef __lcd_display_off
 255 #define __lcd_display_off()
 256 #endif
 257 #ifndef __lcd_set_backlight_level
 258 #define __lcd_set_backlight_level(n)
 259 #endif
 260