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[generic] ppp: Fix high softirq utilization with pppoa
[openwrt.git] / target / linux / lantiq / patches-3.2 / 0041-MIPS-lantiq-add-xway-nand-driver.patch
1 From 9c7a6f8804aef7559ee8edcb7466676ee7d00c09 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Aug 2011 20:08:14 +0200
4 Subject: [PATCH 41/70] MIPS: lantiq: add xway nand driver
5
6 This patch adds a nand driver for XWAY SoCs. The patch makes use of the
7 plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
8 endianess swap problem on read. To workaround this problem we make the
9 read_byte() callback available via the plat_nand driver causing the nand
10 layer to do byte reads.
11
12 Signed-off-by: John Crispin <blogic@openwrt.org>
13
14 TODO : memory ranges
15 cs lines
16 plat dev
17 ebu2 and not ebu1 ?
18 ---
19 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +
20 arch/mips/lantiq/xway/Makefile | 2 +-
21 arch/mips/lantiq/xway/devices.h | 1 +
22 arch/mips/lantiq/xway/nand.c | 216 ++++++++++++++++++++
23 drivers/mtd/nand/plat_nand.c | 1 +
24 include/linux/mtd/nand.h | 1 +
25 6 files changed, 222 insertions(+), 1 deletions(-)
26 create mode 100644 arch/mips/lantiq/xway/nand.c
27
28 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
29 index 3f22acb..ab2d236 100644
30 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
31 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
32 @@ -145,6 +145,8 @@
33 /* register access macros for EBU and CGU */
34 #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
35 #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
36 +#define ltq_ebu_w32_mask(x, y, z) \
37 + ltq_w32_mask(x, y, ltq_ebu_membase + (z))
38 #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
39 #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
40
41 diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
42 index 9d1a0a2..277aa34 100644
43 --- a/arch/mips/lantiq/xway/Makefile
44 +++ b/arch/mips/lantiq/xway/Makefile
45 @@ -1,4 +1,4 @@
46 -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o
47 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o
48
49 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
50 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
51 diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
52 index e904934..d825cbd 100644
53 --- a/arch/mips/lantiq/xway/devices.h
54 +++ b/arch/mips/lantiq/xway/devices.h
55 @@ -16,5 +16,6 @@ extern void ltq_register_gpio(void);
56 extern void ltq_register_gpio_stp(void);
57 extern void ltq_register_ase_asc(void);
58 extern void ltq_register_etop(struct ltq_eth_data *eth);
59 +extern void xway_register_nand(struct mtd_partition *parts, int count);
60
61 #endif
62 diff --git a/arch/mips/lantiq/xway/nand.c b/arch/mips/lantiq/xway/nand.c
63 new file mode 100644
64 index 0000000..9ab91d8
65 --- /dev/null
66 +++ b/arch/mips/lantiq/xway/nand.c
67 @@ -0,0 +1,216 @@
68 +/*
69 + * This program is free software; you can redistribute it and/or modify it
70 + * under the terms of the GNU General Public License version 2 as published
71 + * by the Free Software Foundation.
72 + *
73 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
74 + */
75 +
76 +#include <linux/mtd/physmap.h>
77 +#include <linux/mtd/nand.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/io.h>
80 +
81 +#include <lantiq_soc.h>
82 +#include <lantiq_irq.h>
83 +#include <lantiq_platform.h>
84 +
85 +#include "devices.h"
86 +
87 +/* nand registers */
88 +#define LTQ_EBU_NAND_WAIT 0xB4
89 +#define LTQ_EBU_NAND_ECC0 0xB8
90 +#define LTQ_EBU_NAND_ECC_AC 0xBC
91 +#define LTQ_EBU_NAND_CON 0xB0
92 +#define LTQ_EBU_ADDSEL1 0x24
93 +
94 +/* gpio definitions */
95 +#define PIN_ALE 13
96 +#define PIN_CLE 24
97 +#define PIN_CS1 23
98 +#define PIN_RDY 48 /* NFLASH_READY */
99 +#define PIN_RD 49 /* NFLASH_READ_N */
100 +
101 +#define NAND_CMD_ALE (1 << 2)
102 +#define NAND_CMD_CLE (1 << 3)
103 +#define NAND_CMD_CS (1 << 4)
104 +#define NAND_WRITE_CMD_RESET 0xff
105 +#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
106 +#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
107 +#define NAND_WRITE_DATA (NAND_CMD_CS)
108 +#define NAND_READ_DATA (NAND_CMD_CS)
109 +#define NAND_WAIT_WR_C (1 << 3)
110 +#define NAND_WAIT_RD (0x1)
111 +
112 +#define ADDSEL1_MASK(x) (x << 4)
113 +#define ADDSEL1_REGEN 1
114 +#define BUSCON1_SETUP (1 << 22)
115 +#define BUSCON1_BCGEN_RES (0x3 << 12)
116 +#define BUSCON1_WAITWRC2 (2 << 8)
117 +#define BUSCON1_WAITRDC2 (2 << 6)
118 +#define BUSCON1_HOLDC1 (1 << 4)
119 +#define BUSCON1_RECOVC1 (1 << 2)
120 +#define BUSCON1_CMULT4 1
121 +#define NAND_CON_NANDM 1
122 +#define NAND_CON_CSMUX (1 << 1)
123 +#define NAND_CON_CS_P (1 << 4)
124 +#define NAND_CON_SE_P (1 << 5)
125 +#define NAND_CON_WP_P (1 << 6)
126 +#define NAND_CON_PRE_P (1 << 7)
127 +#define NAND_CON_IN_CS0 0
128 +#define NAND_CON_OUT_CS0 0
129 +#define NAND_CON_IN_CS1 (1 << 8)
130 +#define NAND_CON_OUT_CS1 (1 << 10)
131 +#define NAND_CON_CE (1 << 20)
132 +
133 +#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
134 +
135 +static const char *part_probes[] = { "cmdlinepart", NULL };
136 +
137 +static void xway_select_chip(struct mtd_info *mtd, int chip)
138 +{
139 + switch (chip) {
140 + case -1:
141 + ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
142 + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
143 + break;
144 + case 0:
145 + ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
146 + ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
147 + /* reset the nand chip */
148 + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
149 + ;
150 + ltq_w32(NAND_WRITE_CMD_RESET,
151 + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
152 + break;
153 + default:
154 + BUG();
155 + }
156 +}
157 +
158 +static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
159 +{
160 + struct nand_chip *this = mtd->priv;
161 +
162 + if (ctrl & NAND_CTRL_CHANGE) {
163 + if (ctrl & NAND_CLE)
164 + this->IO_ADDR_W = (void __iomem *)
165 + (NAND_BASE_ADDRESS | NAND_WRITE_CMD);
166 + else if (ctrl & NAND_ALE)
167 + this->IO_ADDR_W = (void __iomem *)
168 + (NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
169 + }
170 +
171 + if (data != NAND_CMD_NONE) {
172 + *(volatile u8*) ((u32) this->IO_ADDR_W) = data;
173 + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
174 + ;
175 + }
176 +}
177 +
178 +static int xway_dev_ready(struct mtd_info *mtd)
179 +{
180 + return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
181 +}
182 +
183 +void nand_write(unsigned int addr, unsigned int val)
184 +{
185 + ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr)));
186 + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
187 + ;
188 +}
189 +
190 +unsigned char xway_read_byte(struct mtd_info *mtd)
191 +{
192 + return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
193 +}
194 +
195 +static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
196 +{
197 + int i;
198 +
199 + for (i = 0; i < len; i++)
200 + {
201 + unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
202 + buf[i] = res8;
203 + }
204 +}
205 +
206 +static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
207 +{
208 + int i;
209 +
210 + for (i = 0; i < len; i++)
211 + {
212 + ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA))));
213 + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
214 + }
215 +}
216 +
217 +int xway_probe(struct platform_device *pdev)
218 +{
219 + /* might need this later ?
220 + ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1");
221 + */
222 + ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE");
223 + ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE");
224 + if (ltq_is_ar9() || ltq_is_vr9()) {
225 + ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY");
226 + ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD");
227 + }
228 +
229 + ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
230 + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
231 +
232 + ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
233 + | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
234 + | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
235 +
236 + ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
237 + | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
238 + | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
239 +
240 + ltq_w32(NAND_WRITE_CMD_RESET,
241 + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
242 + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
243 + ;
244 +
245 + return 0;
246 +}
247 +
248 +static struct platform_nand_data falcon_flash_nand_data = {
249 + .chip = {
250 + .nr_chips = 1,
251 + .chip_delay = 30,
252 + .part_probe_types = part_probes,
253 + },
254 + .ctrl = {
255 + .probe = xway_probe,
256 + .cmd_ctrl = xway_cmd_ctrl,
257 + .dev_ready = xway_dev_ready,
258 + .select_chip = xway_select_chip,
259 + .read_byte = xway_read_byte,
260 + .read_buf = xway_read_buf,
261 + .write_buf = xway_write_buf,
262 + }
263 +};
264 +
265 +static struct resource ltq_nand_res =
266 + MEM_RES("nand", 0x14000000, 0x7ffffff);
267 +
268 +static struct platform_device ltq_flash_nand = {
269 + .name = "gen_nand",
270 + .id = -1,
271 + .num_resources = 1,
272 + .resource = &ltq_nand_res,
273 + .dev = {
274 + .platform_data = &falcon_flash_nand_data,
275 + },
276 +};
277 +
278 +void __init xway_register_nand(struct mtd_partition *parts, int count)
279 +{
280 + falcon_flash_nand_data.chip.partitions = parts;
281 + falcon_flash_nand_data.chip.nr_partitions = count;
282 + platform_device_register(&ltq_flash_nand);
283 +}
284 diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
285 index ea8e123..9040ba1 100644
286 --- a/drivers/mtd/nand/plat_nand.c
287 +++ b/drivers/mtd/nand/plat_nand.c
288 @@ -75,6 +75,7 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
289 data->chip.select_chip = pdata->ctrl.select_chip;
290 data->chip.write_buf = pdata->ctrl.write_buf;
291 data->chip.read_buf = pdata->ctrl.read_buf;
292 + data->chip.read_byte = pdata->ctrl.read_byte;
293 data->chip.chip_delay = pdata->chip.chip_delay;
294 data->chip.options |= pdata->chip.options;
295 data->chip.bbt_options |= pdata->chip.bbt_options;
296 diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
297 index 904131b..80e11b9 100644
298 --- a/include/linux/mtd/nand.h
299 +++ b/include/linux/mtd/nand.h
300 @@ -650,6 +650,7 @@ struct platform_nand_ctrl {
301 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
302 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
303 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
304 + unsigned char (*read_byte)(struct mtd_info *mtd);
305 void *priv;
306 };
307
308 --
309 1.7.7.1
310
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