target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *               2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/cpu.h>
  13 #include <bcm63xx_cpu.h>
  14 #include <bcm63xx_regs.h>
  15 #include <bcm63xx_io.h>
  16 #include <bcm63xx_irq.h>
  17
  18 const unsigned long *bcm63xx_regs_base;
  19 EXPORT_SYMBOL(bcm63xx_regs_base);
  20
  21 const int *bcm63xx_irqs;
  22 EXPORT_SYMBOL(bcm63xx_irqs);
  23
  24 const unsigned long *bcm63xx_regs_spi;
  25 EXPORT_SYMBOL(bcm63xx_regs_spi);
  26
  27 static u16 bcm63xx_cpu_id;
  28 static u16 bcm63xx_cpu_rev;
  29 static unsigned int bcm63xx_cpu_freq;
  30 static unsigned int bcm63xx_memory_size;
  31
  32 /*
  33  * 6338 register sets and irqs
  34  */
  35
  36 static const unsigned long bcm96338_regs_base[] = {
  37         [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
  38         [RSET_PERF]             = BCM_6338_PERF_BASE,
  39         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
  40         [RSET_WDT]              = BCM_6338_WDT_BASE,
  41         [RSET_UART0]            = BCM_6338_UART0_BASE,
  42         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
  43         [RSET_SPI]              = BCM_6338_SPI_BASE,
  44         [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
  45         [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
  46         [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
  47         [RSET_UDC0]             = BCM_6338_UDC0_BASE,
  48         [RSET_MPI]              = BCM_6338_MPI_BASE,
  49         [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
  50         [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
  51         [RSET_DSL]              = BCM_6338_DSL_BASE,
  52         [RSET_ENET0]            = BCM_6338_ENET0_BASE,
  53         [RSET_ENET1]            = BCM_6338_ENET1_BASE,
  54         [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
  55         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
  56         [RSET_DDR]              = BCM_6338_DDR_BASE,
  57 };
  58
  59 static const int bcm96338_irqs[] = {
  60         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
  61         [IRQ_SPI]               = BCM_6338_SPI_IRQ,
  62         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
  63         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  64         [IRQ_UDC0]              = BCM_6338_UDC0_IRQ,
  65         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  66         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
  67         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
  68         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
  69 };
  70
  71 static const unsigned long bcm96338_regs_spi[] = {
  72         [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
  73         [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
  74         [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
  75         [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
  76         [SPI_ST]                = SPI_BCM_6338_SPI_ST,
  77         [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
  78         [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
  79         [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
  80         [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
  81         [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
  82         [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
  83         [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
  84 };
  85
  86 /*
  87  * 6345 register sets and irqs
  88  */
  89
  90 static const unsigned long bcm96345_regs_base[] = {
  91         [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
  92         [RSET_PERF]             = BCM_6345_PERF_BASE,
  93         [RSET_TIMER]            = BCM_6345_TIMER_BASE,
  94         [RSET_WDT]              = BCM_6345_WDT_BASE,
  95         [RSET_UART0]            = BCM_6345_UART0_BASE,
  96         [RSET_GPIO]             = BCM_6345_GPIO_BASE,
  97         [RSET_SPI]              = BCM_6345_SPI_BASE,
  98         [RSET_UDC0]             = BCM_6345_UDC0_BASE,
  99         [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
 100         [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
 101         [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
 102         [RSET_MPI]              = BCM_6345_MPI_BASE,
 103         [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
 104         [RSET_DSL]              = BCM_6345_DSL_BASE,
 105         [RSET_ENET0]            = BCM_6345_ENET0_BASE,
 106         [RSET_ENET1]            = BCM_6345_ENET1_BASE,
 107         [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
 108         [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
 109         [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
 110         [RSET_MEMC]             = BCM_6345_MEMC_BASE,
 111         [RSET_DDR]              = BCM_6345_DDR_BASE,
 112 };
 113
 114 static const int bcm96345_irqs[] = {
 115         [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
 116         [IRQ_UART0]             = BCM_6345_UART0_IRQ,
 117         [IRQ_DSL]               = BCM_6345_DSL_IRQ,
 118         [IRQ_UDC0]              = BCM_6345_UDC0_IRQ,
 119         [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
 120         [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
 121         [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
 122         [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
 123 };
 124
 125 /*
 126  * 6348 register sets and irqs
 127  */
 128 static const unsigned long bcm96348_regs_base[] = {
 129         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
 130         [RSET_PERF]             = BCM_6348_PERF_BASE,
 131         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
 132         [RSET_WDT]              = BCM_6348_WDT_BASE,
 133         [RSET_UART0]            = BCM_6348_UART0_BASE,
 134         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
 135         [RSET_SPI]              = BCM_6348_SPI_BASE,
 136         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
 137         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
 138         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
 139         [RSET_UDC0]             = BCM_6348_UDC0_BASE,
 140         [RSET_MPI]              = BCM_6348_MPI_BASE,
 141         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
 142         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
 143         [RSET_DSL]              = BCM_6348_DSL_BASE,
 144         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
 145         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
 146         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
 147         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
 148         [RSET_DDR]              = BCM_6348_DDR_BASE,
 149 };
 150
 151 static const int bcm96348_irqs[] = {
 152         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
 153         [IRQ_SPI]               = BCM_6348_SPI_IRQ,
 154         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
 155         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
 156         [IRQ_UDC0]              = BCM_6348_UDC0_IRQ,
 157         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
 158         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
 159         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
 160         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
 161         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
 162         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
 163         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
 164         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
 165         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
 166         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
 167 };
 168
 169 static const unsigned long bcm96348_regs_spi[] = {
 170         [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 171         [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 172         [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 173         [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 174         [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 175         [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 176         [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 177         [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 178         [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 179         [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 180         [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 181         [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 182 };
 183
 184 /*
 185  * 6358 register sets and irqs
 186  */
 187 static const unsigned long bcm96358_regs_base[] = {
 188         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
 189         [RSET_PERF]             = BCM_6358_PERF_BASE,
 190         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 191         [RSET_WDT]              = BCM_6358_WDT_BASE,
 192         [RSET_UART0]            = BCM_6358_UART0_BASE,
 193         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 194         [RSET_SPI]              = BCM_6358_SPI_BASE,
 195         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 196         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 197         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 198         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 199         [RSET_MPI]              = BCM_6358_MPI_BASE,
 200         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 201         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 202         [RSET_DSL]              = BCM_6358_DSL_BASE,
 203         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 204         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 205         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 206         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 207         [RSET_DDR]              = BCM_6358_DDR_BASE,
 208 };
 209
 210 static const int bcm96358_irqs[] = {
 211         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 212         [IRQ_SPI]               = BCM_6358_SPI_IRQ,
 213         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 214         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 215         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 216         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 217         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 218         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 219         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 220         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 221         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 222         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 223         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 224         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 225         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 226 };
 227
 228 static const unsigned long bcm96358_regs_spi[] = {
 229         [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 230         [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 231         [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 232         [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 233         [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 234         [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 235         [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 236         [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 237         [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 238         [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 239         [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 240         [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 241 };
 242
 243 u16 __bcm63xx_get_cpu_id(void)
 244 {
 245         return bcm63xx_cpu_id;
 246 }
 247
 248 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 249
 250 u16 bcm63xx_get_cpu_rev(void)
 251 {
 252         return bcm63xx_cpu_rev;
 253 }
 254
 255 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 256
 257 unsigned int bcm63xx_get_cpu_freq(void)
 258 {
 259         return bcm63xx_cpu_freq;
 260 }
 261
 262 unsigned int bcm63xx_get_memory_size(void)
 263 {
 264         return bcm63xx_memory_size;
 265 }
 266
 267 static unsigned int detect_cpu_clock(void)
 268 {
 269         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 270
 271         if (BCMCPU_IS_6338())
 272                 return 240000000;
 273
 274         if (BCMCPU_IS_6345())
 275                 return 140000000;
 276
 277         /*
 278          * frequency depends on PLL configuration:
 279          */
 280         if (BCMCPU_IS_6348()) {
 281                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 282                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 283                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 284                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 285                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 286                 n1 += 1;
 287                 n2 += 2;
 288                 m1 += 1;
 289         }
 290
 291         if (BCMCPU_IS_6358()) {
 292                 /* 16MHz * N1 * N2 / M1_CPU */
 293                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 294                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 295                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 296                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 297         }
 298
 299         return (16 * 1000000 * n1 * n2) / m1;
 300 }
 301
 302 /*
 303  * attempt to detect the amount of memory installed
 304  */
 305 static unsigned int detect_memory_size(void)
 306 {
 307         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 308         u32 val;
 309
 310         if (BCMCPU_IS_6345())
 311                 return (8 * 1024 * 1024);
 312
 313         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 314                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 315                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 316                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 317                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 318                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 319         }
 320
 321         if (BCMCPU_IS_6358()) {
 322                 val = bcm_memc_readl(MEMC_CFG_REG);
 323                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 324                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 325                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 326                 banks = 2;
 327         }
 328
 329         /* 0 => 11 address bits ... 2 => 13 address bits */
 330         rows += 11;
 331
 332         /* 0 => 8 address bits ... 2 => 10 address bits */
 333         cols += 8;
 334
 335         return 1 << (cols + rows + (is_32bits + 1) + banks);
 336 }
 337
 338 void __init bcm63xx_cpu_init(void)
 339 {
 340         unsigned int tmp, expected_cpu_id;
 341         struct cpuinfo_mips *c = &current_cpu_data;
 342
 343         /* soc registers location depends on cpu type */
 344         expected_cpu_id = 0;
 345
 346         switch (c->cputype) {
 347         case CPU_BCM3302:
 348                 expected_cpu_id = BCM6338_CPU_ID;
 349                 bcm63xx_regs_base = bcm96338_regs_base;
 350                 bcm63xx_irqs = bcm96338_irqs;
 351                 bcm63xx_regs_spi = bcm96338_regs_spi;
 352                 break;
 353         case CPU_BCM6345:
 354                 expected_cpu_id = BCM6345_CPU_ID;
 355                 bcm63xx_regs_base = bcm96345_regs_base;
 356                 bcm63xx_irqs = bcm96345_irqs;
 357                 break;
 358         case CPU_BCM6348:
 359                 expected_cpu_id = BCM6348_CPU_ID;
 360                 bcm63xx_regs_base = bcm96348_regs_base;
 361                 bcm63xx_irqs = bcm96348_irqs;
 362                 bcm63xx_regs_spi = bcm96348_regs_spi;
 363                 break;
 364         case CPU_BCM6358:
 365                 expected_cpu_id = BCM6358_CPU_ID;
 366                 bcm63xx_regs_base = bcm96358_regs_base;
 367                 bcm63xx_irqs = bcm96358_irqs;
 368                 bcm63xx_regs_spi = bcm96358_regs_spi;
 369                 break;
 370         }
 371
 372         /* really early to panic, but delaying panic would not help
 373          * since we will never get any working console */
 374         if (!expected_cpu_id)
 375                 panic("unsupported Broadcom CPU");
 376
 377         /*
 378          * bcm63xx_regs_base is set, we can access soc registers
 379          */
 380
 381         /* double check CPU type */
 382         tmp = bcm_perf_readl(PERF_REV_REG);
 383         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 384         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 385
 386         if (bcm63xx_cpu_id != expected_cpu_id)
 387                 panic("bcm63xx CPU id mismatch");
 388
 389         bcm63xx_cpu_freq = detect_cpu_clock();
 390         bcm63xx_memory_size = detect_memory_size();
 391
 392         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 393                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 394         printk(KERN_INFO "CPU frequency is %u Hz\n",
 395                bcm63xx_cpu_freq);
 396         printk(KERN_INFO "%uMB of RAM installed\n",
 397                bcm63xx_memory_size >> 20);
 398 }