target/linux/ar71xx/patches-3.2/131-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch

   1 From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 11 Dec 2011 18:34:13 +0100
   4 Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
   8 ---
   9  arch/mips/ath79/dev-usb.c                      |   28 +++++++++++++++++++
  10  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   35 ++++++++++++++++++++++++
  11  2 files changed, 63 insertions(+), 0 deletions(-)
  12
  13 --- a/arch/mips/ath79/dev-usb.c
  14 +++ b/arch/mips/ath79/dev-usb.c
  15 @@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void
  16         platform_device_register(&ath79_ehci_device);
  17  }
  18
  19 +static void __init ar934x_usb_setup(void)
  20 +{
  21 +       u32 bootstrap;
  22 +
  23 +       bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  24 +       if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
  25 +               return;
  26 +
  27 +       ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
  28 +       udelay(1000);
  29 +
  30 +       ath79_device_reset_set(AR934X_RESET_USB_PHY);
  31 +       udelay(1000);
  32 +
  33 +       ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
  34 +       udelay(1000);
  35 +
  36 +       ath79_device_reset_set(AR934X_RESET_USB_HOST);
  37 +       udelay(1000);
  38 +
  39 +       ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
  40 +       ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1;
  41 +       ath79_ehci_device.name = "ar934x-ehci";
  42 +       platform_device_register(&ath79_ehci_device);
  43 +}
  44 +
  45  void __init ath79_register_usb(void)
  46  {
  47         if (soc_is_ar71xx())
  48 @@ -192,6 +218,8 @@ void __init ath79_register_usb(void)
  49                 ar913x_usb_setup();
  50         else if (soc_is_ar933x())
  51                 ar933x_usb_setup();
  52 +       else if (soc_is_ar934x())
  53 +               ar934x_usb_setup();
  54         else
  55                 BUG();
  56  }
  57 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  58 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  59 @@ -63,6 +63,8 @@
  60
  61  #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  62  #define AR934X_WMAC_SIZE       0x20000
  63 +#define AR934X_EHCI_BASE       0x1b000000
  64 +#define AR934X_EHCI_SIZE       0x1000
  65
  66  /*
  67   * DDR_CTRL block
  68 @@ -288,6 +290,39 @@
  69  #define AR933X_RESET_USB_PHY           BIT(4)
  70  #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
  71
  72 +#define AR934X_RESET_HOST              BIT(31)
  73 +#define AR934X_RESET_SLIC              BIT(30)
  74 +#define AR934X_RESET_HDMA              BIT(29)
  75 +#define AR934X_RESET_EXTERNAL          BIT(28)
  76 +#define AR934X_RESET_RTC               BIT(27)
  77 +#define AR934X_RESET_PCIE_EP_INT       BIT(26)
  78 +#define AR934X_RESET_CHKSUM_ACC                BIT(25)
  79 +#define AR934X_RESET_FULL_CHIP         BIT(24)
  80 +#define AR934X_RESET_GE1_MDIO          BIT(23)
  81 +#define AR934X_RESET_GE0_MDIO          BIT(22)
  82 +#define AR934X_RESET_CPU_NMI           BIT(21)
  83 +#define AR934X_RESET_CPU_COLD          BIT(20)
  84 +#define AR934X_RESET_HOST_RESET_INT    BIT(19)
  85 +#define AR934X_RESET_PCIE_EP           BIT(18)
  86 +#define AR934X_RESET_UART1             BIT(17)
  87 +#define AR934X_RESET_DDR               BIT(16)
  88 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
  89 +#define AR934X_RESET_NANDF             BIT(14)
  90 +#define AR934X_RESET_GE1_MAC           BIT(13)
  91 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
  92 +#define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
  93 +#define AR934X_RESET_HOST_DMA_INT      BIT(10)
  94 +#define AR934X_RESET_GE0_MAC           BIT(9)
  95 +#define AR934X_RESET_ETH_SIWTCH                BIT(8)
  96 +#define AR934X_RESET_PCIE_PHY          BIT(7)
  97 +#define AR934X_RESET_PCIE              BIT(6)
  98 +#define AR934X_RESET_USB_HOST          BIT(5)
  99 +#define AR934X_RESET_USB_PHY           BIT(4)
 100 +#define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
 101 +#define AR934X_RESET_LUT               BIT(2)
 102 +#define AR934X_RESET_MBOX              BIT(1)
 103 +#define AR934X_RESET_I2S               BIT(0)
 104 +
 105  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
 106
 107  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)