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[openwrt.git] / target / linux / ar71xx / patches-3.3 / 112-MIPS-ath79-fix-a-wrong-IRQ-number.patch
1 From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Tue, 22 Nov 2011 13:59:39 +0100
4 Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number
5
6 The Ubiquiti XM board setup code uses an invalid
7 IRQ number, because it if above of NR_IRQS. This
8 leads to failed 'request_irq' calls:
9
10 ath9k 0000:00:00.0: request_irq failed
11 ath9k: probe of 0000:00:00.0 failed with error -22
12
13 Preserve some IRQ numbers for the built-in IRQ
14 controller of PCI host controllers in the
15 AR71XX/AR724X SoCs, and use the correct IRQ
16 number in the board setup code.
17
18 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
19
20 v2: - no changes
21
22 The IRQ controller code is also missing, that will be
23 added in a separate patch.
24 ---
25 arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
26 arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
27 2 files changed, 8 insertions(+), 3 deletions(-)
28
29 --- a/arch/mips/ath79/mach-ubnt-xm.c
30 +++ b/arch/mips/ath79/mach-ubnt-xm.c
31 @@ -17,6 +17,8 @@
32 #include <linux/ath9k_platform.h>
33 #endif /* CONFIG_PCI */
34
35 +#include <asm/mach-ath79/irq.h>
36 +
37 #include "machtypes.h"
38 #include "dev-gpio-buttons.h"
39 #include "dev-leds-gpio.h"
40 @@ -33,7 +35,6 @@
41 #define UBNT_XM_KEYS_POLL_INTERVAL 20
42 #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
43
44 -#define UBNT_XM_PCI_IRQ 48
45 #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
46
47 static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
48 @@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
49
50 static struct ar724x_pci_data ubnt_xm_pci_data[] = {
51 {
52 - .irq = UBNT_XM_PCI_IRQ,
53 + .irq = ATH79_PCI_IRQ(0),
54 .pdata = &ubnt_xm_eeprom_data,
55 },
56 };
57 --- a/arch/mips/include/asm/mach-ath79/irq.h
58 +++ b/arch/mips/include/asm/mach-ath79/irq.h
59 @@ -10,11 +10,15 @@
60 #define __ASM_MACH_ATH79_IRQ_H
61
62 #define MIPS_CPU_IRQ_BASE 0
63 -#define NR_IRQS 40
64 +#define NR_IRQS 46
65
66 #define ATH79_MISC_IRQ_BASE 8
67 #define ATH79_MISC_IRQ_COUNT 32
68
69 +#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
70 +#define ATH79_PCI_IRQ_COUNT 6
71 +#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
72 +
73 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
74 #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
75 #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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