target/linux/ar71xx/patches-3.3/133-MIPS-ath79-add-PCI-registration-code-for-AR934X.patch

   1 From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sat, 17 Dec 2011 10:13:08 +0100
   4 Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
   8 ---
   9  arch/mips/ath79/Kconfig |    2 ++
  10  arch/mips/ath79/pci.c   |   13 ++++++++++++-
  11  2 files changed, 14 insertions(+), 1 deletions(-)
  12
  13 --- a/arch/mips/ath79/Kconfig
  14 +++ b/arch/mips/ath79/Kconfig
  15 @@ -72,6 +72,8 @@ config SOC_AR933X
  16
  17  config SOC_AR934X
  18         select USB_ARCH_HAS_EHCI
  19 +       select HW_HAS_PCI
  20 +       select PCI_AR724X if PCI
  21         def_bool n
  22
  23  config PCI_AR724X
  24 --- a/arch/mips/ath79/pci.c
  25 +++ b/arch/mips/ath79/pci.c
  26 @@ -14,6 +14,7 @@
  27
  28  #include <linux/init.h>
  29  #include <linux/pci.h>
  30 +#include <asm/mach-ath79/ar71xx_regs.h>
  31  #include <asm/mach-ath79/ath79.h>
  32  #include <asm/mach-ath79/irq.h>
  33  #include <asm/mach-ath79/pci.h>
  34 @@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
  35                 if (soc_is_ar71xx()) {
  36                         ath79_pci_irq_map = ar71xx_pci_irq_map;
  37                         ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
  38 -               } else if (soc_is_ar724x()) {
  39 +               } else if (soc_is_ar724x() ||
  40 +                          soc_is_ar9342() ||
  41 +                          soc_is_ar9344()) {
  42                         ath79_pci_irq_map = ar724x_pci_irq_map;
  43                         ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
  44                 } else {
  45 @@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
  46         if (soc_is_ar724x())
  47                 return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
  48
  49 +       if (soc_is_ar9342() || soc_is_ar9344()) {
  50 +               u32 bootstrap;
  51 +
  52 +               bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  53 +               if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
  54 +                       return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
  55 +       }
  56 +
  57         return -ENODEV;
  58  }