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[openwrt.git] / target / linux / atheros / patches-2.6.38 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -251,6 +251,12 @@ config AX88796_93CX6
4 help
5 Select this if your platform comes with an external 93CX6 eeprom.
6
7 +config AR231X_ETHERNET
8 + tristate "AR231x Ethernet support"
9 + depends on ATHEROS_AR231X
10 + help
11 + Support for the AR231x/531x ethernet controller
12 +
13 config MACE
14 tristate "MACE (Power Mac ethernet) support"
15 depends on PPC_PMAC && PPC32
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -224,6 +224,7 @@ obj-$(CONFIG_EQUALIZER) += eql.o
19 obj-$(CONFIG_KORINA) += korina.o
20 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
21 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
22 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
23 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
24 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
25 obj-$(CONFIG_DECLANCE) += declance.o
26 --- /dev/null
27 +++ b/drivers/net/ar231x.c
28 @@ -0,0 +1,1293 @@
29 +/*
30 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
31 + *
32 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
33 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + *
36 + * Thanks to Atheros for providing hardware and documentation
37 + * enabling me to write this driver.
38 + *
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License as published by
41 + * the Free Software Foundation; either version 2 of the License, or
42 + * (at your option) any later version.
43 + *
44 + * Additional credits:
45 + * This code is taken from John Taylor's Sibyte driver and then
46 + * modified for the AR2313.
47 + */
48 +
49 +#include <linux/module.h>
50 +#include <linux/version.h>
51 +#include <linux/types.h>
52 +#include <linux/errno.h>
53 +#include <linux/ioport.h>
54 +#include <linux/pci.h>
55 +#include <linux/netdevice.h>
56 +#include <linux/etherdevice.h>
57 +#include <linux/skbuff.h>
58 +#include <linux/init.h>
59 +#include <linux/delay.h>
60 +#include <linux/mm.h>
61 +#include <linux/highmem.h>
62 +#include <linux/sockios.h>
63 +#include <linux/pkt_sched.h>
64 +#include <linux/mii.h>
65 +#include <linux/phy.h>
66 +#include <linux/ethtool.h>
67 +#include <linux/ctype.h>
68 +#include <linux/platform_device.h>
69 +
70 +#include <net/sock.h>
71 +#include <net/ip.h>
72 +
73 +#include <asm/system.h>
74 +#include <asm/io.h>
75 +#include <asm/irq.h>
76 +#include <asm/byteorder.h>
77 +#include <asm/uaccess.h>
78 +#include <asm/bootinfo.h>
79 +
80 +#define AR2313_MTU 1692
81 +#define AR2313_PRIOS 1
82 +#define AR2313_QUEUES (2*AR2313_PRIOS)
83 +#define AR2313_DESCR_ENTRIES 64
84 +
85 +
86 +#ifndef min
87 +#define min(a,b) (((a)<(b))?(a):(b))
88 +#endif
89 +
90 +#ifndef SMP_CACHE_BYTES
91 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
92 +#endif
93 +
94 +#define AR2313_MBOX_SET_BIT 0x8
95 +
96 +#include "ar231x.h"
97 +
98 +/*
99 + * New interrupt handler strategy:
100 + *
101 + * An old interrupt handler worked using the traditional method of
102 + * replacing an skbuff with a new one when a packet arrives. However
103 + * the rx rings do not need to contain a static number of buffer
104 + * descriptors, thus it makes sense to move the memory allocation out
105 + * of the main interrupt handler and do it in a bottom half handler
106 + * and only allocate new buffers when the number of buffers in the
107 + * ring is below a certain threshold. In order to avoid starving the
108 + * NIC under heavy load it is however necessary to force allocation
109 + * when hitting a minimum threshold. The strategy for alloction is as
110 + * follows:
111 + *
112 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
113 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
114 + * the buffers in the interrupt handler
115 + * RX_RING_THRES - maximum number of buffers in the rx ring
116 + *
117 + * One advantagous side effect of this allocation approach is that the
118 + * entire rx processing can be done without holding any spin lock
119 + * since the rx rings and registers are totally independent of the tx
120 + * ring and its registers. This of course includes the kmalloc's of
121 + * new skb's. Thus start_xmit can run in parallel with rx processing
122 + * and the memory allocation on SMP systems.
123 + *
124 + * Note that running the skb reallocation in a bottom half opens up
125 + * another can of races which needs to be handled properly. In
126 + * particular it can happen that the interrupt handler tries to run
127 + * the reallocation while the bottom half is either running on another
128 + * CPU or was interrupted on the same CPU. To get around this the
129 + * driver uses bitops to prevent the reallocation routines from being
130 + * reentered.
131 + *
132 + * TX handling can also be done without holding any spin lock, wheee
133 + * this is fun! since tx_csm is only written to by the interrupt
134 + * handler.
135 + */
136 +
137 +/*
138 + * Threshold values for RX buffer allocation - the low water marks for
139 + * when to start refilling the rings are set to 75% of the ring
140 + * sizes. It seems to make sense to refill the rings entirely from the
141 + * intrrupt handler once it gets below the panic threshold, that way
142 + * we don't risk that the refilling is moved to another CPU when the
143 + * one running the interrupt handler just got the slab code hot in its
144 + * cache.
145 + */
146 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
147 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
148 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
149 +#define CRC_LEN 4
150 +#define RX_OFFSET 2
151 +
152 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
153 +#define VLAN_HDR 4
154 +#else
155 +#define VLAN_HDR 0
156 +#endif
157 +
158 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
159 +
160 +#ifdef MODULE
161 +MODULE_LICENSE("GPL");
162 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
163 +MODULE_DESCRIPTION("AR231x Ethernet driver");
164 +#endif
165 +
166 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
167 +
168 +// prototypes
169 +static void ar231x_halt(struct net_device *dev);
170 +static void rx_tasklet_func(unsigned long data);
171 +static void rx_tasklet_cleanup(struct net_device *dev);
172 +static void ar231x_multicast_list(struct net_device *dev);
173 +static void ar231x_tx_timeout(struct net_device *dev);
174 +
175 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
176 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
177 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
178 +static int ar231x_mdiobus_probe (struct net_device *dev);
179 +static void ar231x_adjust_link(struct net_device *dev);
180 +
181 +#ifndef ERR
182 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
183 +#endif
184 +
185 +#ifdef CONFIG_NET_POLL_CONTROLLER
186 +static void
187 +ar231x_netpoll(struct net_device *dev)
188 +{
189 + unsigned long flags;
190 +
191 + local_irq_save(flags);
192 + ar231x_interrupt(dev->irq, dev);
193 + local_irq_restore(flags);
194 +}
195 +#endif
196 +
197 +static const struct net_device_ops ar231x_ops = {
198 + .ndo_open = ar231x_open,
199 + .ndo_stop = ar231x_close,
200 + .ndo_start_xmit = ar231x_start_xmit,
201 + .ndo_set_multicast_list = ar231x_multicast_list,
202 + .ndo_do_ioctl = ar231x_ioctl,
203 + .ndo_change_mtu = eth_change_mtu,
204 + .ndo_validate_addr = eth_validate_addr,
205 + .ndo_set_mac_address = eth_mac_addr,
206 + .ndo_tx_timeout = ar231x_tx_timeout,
207 +#ifdef CONFIG_NET_POLL_CONTROLLER
208 + .ndo_poll_controller = ar231x_netpoll,
209 +#endif
210 +};
211 +
212 +int __init ar231x_probe(struct platform_device *pdev)
213 +{
214 + struct net_device *dev;
215 + struct ar231x_private *sp;
216 + struct resource *res;
217 + unsigned long ar_eth_base;
218 + char buf[64];
219 +
220 + dev = alloc_etherdev(sizeof(struct ar231x_private));
221 +
222 + if (dev == NULL) {
223 + printk(KERN_ERR
224 + "ar231x: Unable to allocate net_device structure!\n");
225 + return -ENOMEM;
226 + }
227 +
228 + platform_set_drvdata(pdev, dev);
229 +
230 + sp = netdev_priv(dev);
231 + sp->dev = dev;
232 + sp->cfg = pdev->dev.platform_data;
233 +
234 + sprintf(buf, "eth%d_membase", pdev->id);
235 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
236 + if (!res)
237 + return -ENODEV;
238 +
239 + sp->link = 0;
240 + ar_eth_base = res->start;
241 +
242 + sprintf(buf, "eth%d_irq", pdev->id);
243 + dev->irq = platform_get_irq_byname(pdev, buf);
244 +
245 + spin_lock_init(&sp->lock);
246 +
247 + dev->features |= NETIF_F_HIGHDMA;
248 + dev->netdev_ops = &ar231x_ops;
249 +
250 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
251 + tasklet_disable(&sp->rx_tasklet);
252 +
253 + sp->eth_regs =
254 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
255 + if (!sp->eth_regs) {
256 + printk("Can't remap eth registers\n");
257 + return (-ENXIO);
258 + }
259 +
260 + /*
261 + * When there's only one MAC, PHY regs are typically on ENET0,
262 + * even though the MAC might be on ENET1.
263 + * Needto remap PHY regs separately in this case
264 + */
265 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
266 + sp->phy_regs = sp->eth_regs;
267 + else {
268 + sp->phy_regs =
269 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
270 + sizeof(*sp->phy_regs));
271 + if (!sp->phy_regs) {
272 + printk("Can't remap phy registers\n");
273 + return (-ENXIO);
274 + }
275 + }
276 +
277 + sp->dma_regs =
278 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
279 + sizeof(*sp->dma_regs));
280 + dev->base_addr = (unsigned int) sp->dma_regs;
281 + if (!sp->dma_regs) {
282 + printk("Can't remap DMA registers\n");
283 + return (-ENXIO);
284 + }
285 +
286 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
287 + if (!sp->int_regs) {
288 + printk("Can't remap INTERRUPT registers\n");
289 + return (-ENXIO);
290 + }
291 +
292 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
293 + sp->name[sizeof(sp->name) - 1] = '\0';
294 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
295 +
296 + if (ar231x_init(dev)) {
297 + /*
298 + * ar231x_init() calls ar231x_init_cleanup() on error.
299 + */
300 + kfree(dev);
301 + return -ENODEV;
302 + }
303 +
304 + if (register_netdev(dev)) {
305 + printk("%s: register_netdev failed\n", __func__);
306 + return -1;
307 + }
308 +
309 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
310 + dev->name, sp->name,
311 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
312 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
313 +
314 + sp->mii_bus = mdiobus_alloc();
315 + if (sp->mii_bus == NULL)
316 + return -1;
317 +
318 + sp->mii_bus->priv = dev;
319 + sp->mii_bus->read = ar231x_mdiobus_read;
320 + sp->mii_bus->write = ar231x_mdiobus_write;
321 + sp->mii_bus->reset = ar231x_mdiobus_reset;
322 + sp->mii_bus->name = "ar231x_eth_mii";
323 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
324 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
325 + *sp->mii_bus->irq = PHY_POLL;
326 +
327 + mdiobus_register(sp->mii_bus);
328 +
329 + if (ar231x_mdiobus_probe(dev) != 0) {
330 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
331 + rx_tasklet_cleanup(dev);
332 + ar231x_init_cleanup(dev);
333 + unregister_netdev(dev);
334 + kfree(dev);
335 + return -ENODEV;
336 + }
337 +
338 + /* start link poll timer */
339 + ar231x_setup_timer(dev);
340 +
341 + return 0;
342 +}
343 +
344 +
345 +static void ar231x_multicast_list(struct net_device *dev)
346 +{
347 + struct ar231x_private *sp = netdev_priv(dev);
348 + unsigned int filter;
349 +
350 + filter = sp->eth_regs->mac_control;
351 +
352 + if (dev->flags & IFF_PROMISC)
353 + filter |= MAC_CONTROL_PR;
354 + else
355 + filter &= ~MAC_CONTROL_PR;
356 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
357 + filter |= MAC_CONTROL_PM;
358 + else
359 + filter &= ~MAC_CONTROL_PM;
360 +
361 + sp->eth_regs->mac_control = filter;
362 +}
363 +
364 +static void rx_tasklet_cleanup(struct net_device *dev)
365 +{
366 + struct ar231x_private *sp = netdev_priv(dev);
367 +
368 + /*
369 + * Tasklet may be scheduled. Need to get it removed from the list
370 + * since we're about to free the struct.
371 + */
372 +
373 + sp->unloading = 1;
374 + tasklet_enable(&sp->rx_tasklet);
375 + tasklet_kill(&sp->rx_tasklet);
376 +}
377 +
378 +static int __devexit ar231x_remove(struct platform_device *pdev)
379 +{
380 + struct net_device *dev = platform_get_drvdata(pdev);
381 + struct ar231x_private *sp = netdev_priv(dev);
382 + rx_tasklet_cleanup(dev);
383 + ar231x_init_cleanup(dev);
384 + unregister_netdev(dev);
385 + mdiobus_unregister(sp->mii_bus);
386 + mdiobus_free(sp->mii_bus);
387 + kfree(dev);
388 + return 0;
389 +}
390 +
391 +
392 +/*
393 + * Restart the AR2313 ethernet controller.
394 + */
395 +static int ar231x_restart(struct net_device *dev)
396 +{
397 + /* disable interrupts */
398 + disable_irq(dev->irq);
399 +
400 + /* stop mac */
401 + ar231x_halt(dev);
402 +
403 + /* initialize */
404 + ar231x_init(dev);
405 +
406 + /* enable interrupts */
407 + enable_irq(dev->irq);
408 +
409 + return 0;
410 +}
411 +
412 +static struct platform_driver ar231x_driver = {
413 + .driver.name = "ar231x-eth",
414 + .probe = ar231x_probe,
415 + .remove = __devexit_p(ar231x_remove),
416 +};
417 +
418 +int __init ar231x_module_init(void)
419 +{
420 + return platform_driver_register(&ar231x_driver);
421 +}
422 +
423 +void __exit ar231x_module_cleanup(void)
424 +{
425 + platform_driver_unregister(&ar231x_driver);
426 +}
427 +
428 +module_init(ar231x_module_init);
429 +module_exit(ar231x_module_cleanup);
430 +
431 +
432 +static void ar231x_free_descriptors(struct net_device *dev)
433 +{
434 + struct ar231x_private *sp = netdev_priv(dev);
435 + if (sp->rx_ring != NULL) {
436 + kfree((void *) KSEG0ADDR(sp->rx_ring));
437 + sp->rx_ring = NULL;
438 + sp->tx_ring = NULL;
439 + }
440 +}
441 +
442 +
443 +static int ar231x_allocate_descriptors(struct net_device *dev)
444 +{
445 + struct ar231x_private *sp = netdev_priv(dev);
446 + int size;
447 + int j;
448 + ar231x_descr_t *space;
449 +
450 + if (sp->rx_ring != NULL) {
451 + printk("%s: already done.\n", __FUNCTION__);
452 + return 0;
453 + }
454 +
455 + size =
456 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
457 + space = kmalloc(size, GFP_KERNEL);
458 + if (space == NULL)
459 + return 1;
460 +
461 + /* invalidate caches */
462 + dma_cache_inv((unsigned int) space, size);
463 +
464 + /* now convert pointer to KSEG1 */
465 + space = (ar231x_descr_t *) KSEG1ADDR(space);
466 +
467 + memset((void *) space, 0, size);
468 +
469 + sp->rx_ring = space;
470 + space += AR2313_DESCR_ENTRIES;
471 +
472 + sp->tx_ring = space;
473 + space += AR2313_DESCR_ENTRIES;
474 +
475 + /* Initialize the transmit Descriptors */
476 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
477 + ar231x_descr_t *td = &sp->tx_ring[j];
478 + td->status = 0;
479 + td->devcs = DMA_TX1_CHAINED;
480 + td->addr = 0;
481 + td->descr =
482 + virt_to_phys(&sp->
483 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
484 + }
485 +
486 + return 0;
487 +}
488 +
489 +
490 +/*
491 + * Generic cleanup handling data allocated during init. Used when the
492 + * module is unloaded or if an error occurs during initialization
493 + */
494 +static void ar231x_init_cleanup(struct net_device *dev)
495 +{
496 + struct ar231x_private *sp = netdev_priv(dev);
497 + struct sk_buff *skb;
498 + int j;
499 +
500 + ar231x_free_descriptors(dev);
501 +
502 + if (sp->eth_regs)
503 + iounmap((void *) sp->eth_regs);
504 + if (sp->dma_regs)
505 + iounmap((void *) sp->dma_regs);
506 +
507 + if (sp->rx_skb) {
508 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
509 + skb = sp->rx_skb[j];
510 + if (skb) {
511 + sp->rx_skb[j] = NULL;
512 + dev_kfree_skb(skb);
513 + }
514 + }
515 + kfree(sp->rx_skb);
516 + sp->rx_skb = NULL;
517 + }
518 +
519 + if (sp->tx_skb) {
520 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
521 + skb = sp->tx_skb[j];
522 + if (skb) {
523 + sp->tx_skb[j] = NULL;
524 + dev_kfree_skb(skb);
525 + }
526 + }
527 + kfree(sp->tx_skb);
528 + sp->tx_skb = NULL;
529 + }
530 +}
531 +
532 +static int ar231x_setup_timer(struct net_device *dev)
533 +{
534 + struct ar231x_private *sp = netdev_priv(dev);
535 +
536 + init_timer(&sp->link_timer);
537 +
538 + sp->link_timer.function = ar231x_link_timer_fn;
539 + sp->link_timer.data = (int) dev;
540 + sp->link_timer.expires = jiffies + HZ;
541 +
542 + add_timer(&sp->link_timer);
543 + return 0;
544 +
545 +}
546 +
547 +static void ar231x_link_timer_fn(unsigned long data)
548 +{
549 + struct net_device *dev = (struct net_device *) data;
550 + struct ar231x_private *sp = netdev_priv(dev);
551 +
552 + // see if the link status changed
553 + // This was needed to make sure we set the PHY to the
554 + // autonegotiated value of half or full duplex.
555 + ar231x_check_link(dev);
556 +
557 + // Loop faster when we don't have link.
558 + // This was needed to speed up the AP bootstrap time.
559 + if (sp->link == 0) {
560 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
561 + } else {
562 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
563 + }
564 +}
565 +
566 +static void ar231x_check_link(struct net_device *dev)
567 +{
568 + struct ar231x_private *sp = netdev_priv(dev);
569 + u16 phyData;
570 +
571 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
572 + if (sp->phyData != phyData) {
573 + if (phyData & BMSR_LSTATUS) {
574 + /* link is present, ready link partner ability to deterine
575 + duplexity */
576 + int duplex = 0;
577 + u16 reg;
578 +
579 + sp->link = 1;
580 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
581 + if (reg & BMCR_ANENABLE) {
582 + /* auto neg enabled */
583 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
584 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
585 + } else {
586 + /* no auto neg, just read duplex config */
587 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
588 + }
589 +
590 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
591 + dev->name, (duplex) ? "full" : "half");
592 +
593 + if (duplex) {
594 + /* full duplex */
595 + sp->eth_regs->mac_control =
596 + ((sp->eth_regs->
597 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
598 + } else {
599 + /* half duplex */
600 + sp->eth_regs->mac_control =
601 + ((sp->eth_regs->
602 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
603 + }
604 + } else {
605 + /* no link */
606 + sp->link = 0;
607 + }
608 + sp->phyData = phyData;
609 + }
610 +}
611 +
612 +static int ar231x_reset_reg(struct net_device *dev)
613 +{
614 + struct ar231x_private *sp = netdev_priv(dev);
615 + unsigned int ethsal, ethsah;
616 + unsigned int flags;
617 +
618 + *sp->int_regs |= sp->cfg->reset_mac;
619 + mdelay(10);
620 + *sp->int_regs &= ~sp->cfg->reset_mac;
621 + mdelay(10);
622 + *sp->int_regs |= sp->cfg->reset_phy;
623 + mdelay(10);
624 + *sp->int_regs &= ~sp->cfg->reset_phy;
625 + mdelay(10);
626 +
627 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
628 + mdelay(10);
629 + sp->dma_regs->bus_mode =
630 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
631 +
632 + /* enable interrupts */
633 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
634 + DMA_STATUS_NIS |
635 + DMA_STATUS_RI |
636 + DMA_STATUS_TI | DMA_STATUS_FBE);
637 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
638 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
639 + sp->dma_regs->control =
640 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
641 +
642 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
643 + sp->eth_regs->vlan_tag = (0x8100);
644 +
645 + /* Enable Ethernet Interface */
646 + flags = (MAC_CONTROL_TE | /* transmit enable */
647 + MAC_CONTROL_PM | /* pass mcast */
648 + MAC_CONTROL_F | /* full duplex */
649 + MAC_CONTROL_HBD); /* heart beat disabled */
650 +
651 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
652 + flags |= MAC_CONTROL_PR;
653 + }
654 + sp->eth_regs->mac_control = flags;
655 +
656 + /* Set all Ethernet station address registers to their initial values */
657 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
658 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
659 +
660 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
661 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
662 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
663 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
664 +
665 + sp->eth_regs->mac_addr[0] = ethsah;
666 + sp->eth_regs->mac_addr[1] = ethsal;
667 +
668 + mdelay(10);
669 +
670 + return (0);
671 +}
672 +
673 +
674 +static int ar231x_init(struct net_device *dev)
675 +{
676 + struct ar231x_private *sp = netdev_priv(dev);
677 + int ecode = 0;
678 +
679 + /*
680 + * Allocate descriptors
681 + */
682 + if (ar231x_allocate_descriptors(dev)) {
683 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
684 + dev->name, __FUNCTION__);
685 + ecode = -EAGAIN;
686 + goto init_error;
687 + }
688 +
689 + /*
690 + * Get the memory for the skb rings.
691 + */
692 + if (sp->rx_skb == NULL) {
693 + sp->rx_skb =
694 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
695 + GFP_KERNEL);
696 + if (!(sp->rx_skb)) {
697 + printk("%s: %s: rx_skb kmalloc failed\n",
698 + dev->name, __FUNCTION__);
699 + ecode = -EAGAIN;
700 + goto init_error;
701 + }
702 + }
703 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
704 +
705 + if (sp->tx_skb == NULL) {
706 + sp->tx_skb =
707 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
708 + GFP_KERNEL);
709 + if (!(sp->tx_skb)) {
710 + printk("%s: %s: tx_skb kmalloc failed\n",
711 + dev->name, __FUNCTION__);
712 + ecode = -EAGAIN;
713 + goto init_error;
714 + }
715 + }
716 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
717 +
718 + /*
719 + * Set tx_csm before we start receiving interrupts, otherwise
720 + * the interrupt handler might think it is supposed to process
721 + * tx ints before we are up and running, which may cause a null
722 + * pointer access in the int handler.
723 + */
724 + sp->rx_skbprd = 0;
725 + sp->cur_rx = 0;
726 + sp->tx_prd = 0;
727 + sp->tx_csm = 0;
728 +
729 + /*
730 + * Zero the stats before starting the interface
731 + */
732 + memset(&dev->stats, 0, sizeof(dev->stats));
733 +
734 + /*
735 + * We load the ring here as there seem to be no way to tell the
736 + * firmware to wipe the ring without re-initializing it.
737 + */
738 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
739 +
740 + /*
741 + * Init hardware
742 + */
743 + ar231x_reset_reg(dev);
744 +
745 + /*
746 + * Get the IRQ
747 + */
748 + ecode =
749 + request_irq(dev->irq, &ar231x_interrupt,
750 + IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
751 + dev->name, dev);
752 + if (ecode) {
753 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
754 + dev->name, __FUNCTION__, dev->irq);
755 + goto init_error;
756 + }
757 +
758 +
759 + tasklet_enable(&sp->rx_tasklet);
760 +
761 + return 0;
762 +
763 + init_error:
764 + ar231x_init_cleanup(dev);
765 + return ecode;
766 +}
767 +
768 +/*
769 + * Load the rx ring.
770 + *
771 + * Loading rings is safe without holding the spin lock since this is
772 + * done only before the device is enabled, thus no interrupts are
773 + * generated and by the interrupt handler/tasklet handler.
774 + */
775 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
776 +{
777 +
778 + struct ar231x_private *sp = netdev_priv(dev);
779 + short i, idx;
780 +
781 + idx = sp->rx_skbprd;
782 +
783 + for (i = 0; i < nr_bufs; i++) {
784 + struct sk_buff *skb;
785 + ar231x_descr_t *rd;
786 +
787 + if (sp->rx_skb[idx])
788 + break;
789 +
790 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
791 + if (!skb) {
792 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
793 + __FUNCTION__);
794 + break;
795 + }
796 +
797 + /*
798 + * Make sure IP header starts on a fresh cache line.
799 + */
800 + skb->dev = dev;
801 + skb_reserve(skb, RX_OFFSET);
802 + sp->rx_skb[idx] = skb;
803 +
804 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
805 +
806 + /* initialize dma descriptor */
807 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
808 + DMA_RX1_CHAINED);
809 + rd->addr = virt_to_phys(skb->data);
810 + rd->descr =
811 + virt_to_phys(&sp->
812 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
813 + rd->status = DMA_RX_OWN;
814 +
815 + idx = DSC_NEXT(idx);
816 + }
817 +
818 + if (i)
819 + sp->rx_skbprd = idx;
820 +
821 + return;
822 +}
823 +
824 +#define AR2313_MAX_PKTS_PER_CALL 64
825 +
826 +static int ar231x_rx_int(struct net_device *dev)
827 +{
828 + struct ar231x_private *sp = netdev_priv(dev);
829 + struct sk_buff *skb, *skb_new;
830 + ar231x_descr_t *rxdesc;
831 + unsigned int status;
832 + u32 idx;
833 + int pkts = 0;
834 + int rval;
835 +
836 + idx = sp->cur_rx;
837 +
838 + /* process at most the entire ring and then wait for another interrupt
839 + */
840 + while (1) {
841 +
842 + rxdesc = &sp->rx_ring[idx];
843 + status = rxdesc->status;
844 + if (status & DMA_RX_OWN) {
845 + /* SiByte owns descriptor or descr not yet filled in */
846 + rval = 0;
847 + break;
848 + }
849 +
850 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
851 + rval = 1;
852 + break;
853 + }
854 +
855 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
856 + dev->stats.rx_errors++;
857 + dev->stats.rx_dropped++;
858 +
859 + /* add statistics counters */
860 + if (status & DMA_RX_ERR_CRC)
861 + dev->stats.rx_crc_errors++;
862 + if (status & DMA_RX_ERR_COL)
863 + dev->stats.rx_over_errors++;
864 + if (status & DMA_RX_ERR_LENGTH)
865 + dev->stats.rx_length_errors++;
866 + if (status & DMA_RX_ERR_RUNT)
867 + dev->stats.rx_over_errors++;
868 + if (status & DMA_RX_ERR_DESC)
869 + dev->stats.rx_over_errors++;
870 +
871 + } else {
872 + /* alloc new buffer. */
873 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
874 + if (skb_new != NULL) {
875 +
876 + skb = sp->rx_skb[idx];
877 + /* set skb */
878 + skb_put(skb,
879 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
880 +
881 + dev->stats.rx_bytes += skb->len;
882 + skb->protocol = eth_type_trans(skb, dev);
883 + /* pass the packet to upper layers */
884 + netif_rx(skb);
885 +
886 + skb_new->dev = dev;
887 + /* 16 bit align */
888 + skb_reserve(skb_new, RX_OFFSET);
889 + /* reset descriptor's curr_addr */
890 + rxdesc->addr = virt_to_phys(skb_new->data);
891 +
892 + dev->stats.rx_packets++;
893 + sp->rx_skb[idx] = skb_new;
894 + } else {
895 + dev->stats.rx_dropped++;
896 + }
897 + }
898 +
899 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
900 + DMA_RX1_CHAINED);
901 + rxdesc->status = DMA_RX_OWN;
902 +
903 + idx = DSC_NEXT(idx);
904 + }
905 +
906 + sp->cur_rx = idx;
907 +
908 + return rval;
909 +}
910 +
911 +
912 +static void ar231x_tx_int(struct net_device *dev)
913 +{
914 + struct ar231x_private *sp = netdev_priv(dev);
915 + u32 idx;
916 + struct sk_buff *skb;
917 + ar231x_descr_t *txdesc;
918 + unsigned int status = 0;
919 +
920 + idx = sp->tx_csm;
921 +
922 + while (idx != sp->tx_prd) {
923 + txdesc = &sp->tx_ring[idx];
924 +
925 + if ((status = txdesc->status) & DMA_TX_OWN) {
926 + /* ar231x dma still owns descr */
927 + break;
928 + }
929 + /* done with this descriptor */
930 + dma_unmap_single(NULL, txdesc->addr,
931 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
932 + DMA_TO_DEVICE);
933 + txdesc->status = 0;
934 +
935 + if (status & DMA_TX_ERROR) {
936 + dev->stats.tx_errors++;
937 + dev->stats.tx_dropped++;
938 + if (status & DMA_TX_ERR_UNDER)
939 + dev->stats.tx_fifo_errors++;
940 + if (status & DMA_TX_ERR_HB)
941 + dev->stats.tx_heartbeat_errors++;
942 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
943 + dev->stats.tx_carrier_errors++;
944 + if (status & (DMA_TX_ERR_LATE |
945 + DMA_TX_ERR_COL |
946 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
947 + dev->stats.tx_aborted_errors++;
948 + } else {
949 + /* transmit OK */
950 + dev->stats.tx_packets++;
951 + }
952 +
953 + skb = sp->tx_skb[idx];
954 + sp->tx_skb[idx] = NULL;
955 + idx = DSC_NEXT(idx);
956 + dev->stats.tx_bytes += skb->len;
957 + dev_kfree_skb_irq(skb);
958 + }
959 +
960 + sp->tx_csm = idx;
961 +
962 + return;
963 +}
964 +
965 +
966 +static void rx_tasklet_func(unsigned long data)
967 +{
968 + struct net_device *dev = (struct net_device *) data;
969 + struct ar231x_private *sp = netdev_priv(dev);
970 +
971 + if (sp->unloading) {
972 + return;
973 + }
974 +
975 + if (ar231x_rx_int(dev)) {
976 + tasklet_hi_schedule(&sp->rx_tasklet);
977 + } else {
978 + unsigned long flags;
979 + spin_lock_irqsave(&sp->lock, flags);
980 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
981 + spin_unlock_irqrestore(&sp->lock, flags);
982 + }
983 +}
984 +
985 +static void rx_schedule(struct net_device *dev)
986 +{
987 + struct ar231x_private *sp = netdev_priv(dev);
988 +
989 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
990 +
991 + tasklet_hi_schedule(&sp->rx_tasklet);
992 +}
993 +
994 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
995 +{
996 + struct net_device *dev = (struct net_device *) dev_id;
997 + struct ar231x_private *sp = netdev_priv(dev);
998 + unsigned int status, enabled;
999 +
1000 + /* clear interrupt */
1001 + /*
1002 + * Don't clear RI bit if currently disabled.
1003 + */
1004 + status = sp->dma_regs->status;
1005 + enabled = sp->dma_regs->intr_ena;
1006 + sp->dma_regs->status = status & enabled;
1007 +
1008 + if (status & DMA_STATUS_NIS) {
1009 + /* normal status */
1010 + /*
1011 + * Don't schedule rx processing if interrupt
1012 + * is already disabled.
1013 + */
1014 + if (status & enabled & DMA_STATUS_RI) {
1015 + /* receive interrupt */
1016 + rx_schedule(dev);
1017 + }
1018 + if (status & DMA_STATUS_TI) {
1019 + /* transmit interrupt */
1020 + ar231x_tx_int(dev);
1021 + }
1022 + }
1023 +
1024 + /* abnormal status */
1025 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1026 + ar231x_restart(dev);
1027 + }
1028 + return IRQ_HANDLED;
1029 +}
1030 +
1031 +
1032 +static int ar231x_open(struct net_device *dev)
1033 +{
1034 + struct ar231x_private *sp = netdev_priv(dev);
1035 + unsigned int ethsal, ethsah;
1036 +
1037 + /* reset the hardware, in case the MAC address changed */
1038 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1039 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1040 +
1041 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1042 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1043 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1044 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1045 +
1046 + sp->eth_regs->mac_addr[0] = ethsah;
1047 + sp->eth_regs->mac_addr[1] = ethsal;
1048 +
1049 + mdelay(10);
1050 +
1051 + dev->mtu = 1500;
1052 + netif_start_queue(dev);
1053 +
1054 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1055 +
1056 + return 0;
1057 +}
1058 +
1059 +static void ar231x_tx_timeout(struct net_device *dev)
1060 +{
1061 + struct ar231x_private *sp = netdev_priv(dev);
1062 + unsigned long flags;
1063 +
1064 + spin_lock_irqsave(&sp->lock, flags);
1065 + ar231x_restart(dev);
1066 + spin_unlock_irqrestore(&sp->lock, flags);
1067 +}
1068 +
1069 +static void ar231x_halt(struct net_device *dev)
1070 +{
1071 + struct ar231x_private *sp = netdev_priv(dev);
1072 + int j;
1073 +
1074 + tasklet_disable(&sp->rx_tasklet);
1075 +
1076 + /* kill the MAC */
1077 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1078 + MAC_CONTROL_TE); /* disable Transmits */
1079 + /* stop dma */
1080 + sp->dma_regs->control = 0;
1081 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1082 +
1083 + /* place phy and MAC in reset */
1084 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1085 +
1086 + /* free buffers on tx ring */
1087 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1088 + struct sk_buff *skb;
1089 + ar231x_descr_t *txdesc;
1090 +
1091 + txdesc = &sp->tx_ring[j];
1092 + txdesc->descr = 0;
1093 +
1094 + skb = sp->tx_skb[j];
1095 + if (skb) {
1096 + dev_kfree_skb(skb);
1097 + sp->tx_skb[j] = NULL;
1098 + }
1099 + }
1100 +}
1101 +
1102 +/*
1103 + * close should do nothing. Here's why. It's called when
1104 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1105 + * the irq is gone forever ! When bond0 is made 'up' again,
1106 + * the ar231x_open () does not call request_irq (). Worse,
1107 + * the call to ar231x_halt() generates a WDOG reset due to
1108 + * the write to 'sp->int_regs' and the box reboots.
1109 + * Commenting this out is good since it allows the
1110 + * system to resume when bond0 is made up again.
1111 + */
1112 +static int ar231x_close(struct net_device *dev)
1113 +{
1114 +#if 0
1115 + /*
1116 + * Disable interrupts
1117 + */
1118 + disable_irq(dev->irq);
1119 +
1120 + /*
1121 + * Without (or before) releasing irq and stopping hardware, this
1122 + * is an absolute non-sense, by the way. It will be reset instantly
1123 + * by the first irq.
1124 + */
1125 + netif_stop_queue(dev);
1126 +
1127 + /* stop the MAC and DMA engines */
1128 + ar231x_halt(dev);
1129 +
1130 + /* release the interrupt */
1131 + free_irq(dev->irq, dev);
1132 +
1133 +#endif
1134 + return 0;
1135 +}
1136 +
1137 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1138 +{
1139 + struct ar231x_private *sp = netdev_priv(dev);
1140 + ar231x_descr_t *td;
1141 + u32 idx;
1142 +
1143 + idx = sp->tx_prd;
1144 + td = &sp->tx_ring[idx];
1145 +
1146 + if (td->status & DMA_TX_OWN) {
1147 + /* free skbuf and lie to the caller that we sent it out */
1148 + dev->stats.tx_dropped++;
1149 + dev_kfree_skb(skb);
1150 +
1151 + /* restart transmitter in case locked */
1152 + sp->dma_regs->xmt_poll = 0;
1153 + return 0;
1154 + }
1155 +
1156 + /* Setup the transmit descriptor. */
1157 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1158 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1159 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1160 + td->status = DMA_TX_OWN;
1161 +
1162 + /* kick transmitter last */
1163 + sp->dma_regs->xmt_poll = 0;
1164 +
1165 + sp->tx_skb[idx] = skb;
1166 + idx = DSC_NEXT(idx);
1167 + sp->tx_prd = idx;
1168 +
1169 + return 0;
1170 +}
1171 +
1172 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1173 +{
1174 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1175 + struct ar231x_private *sp = netdev_priv(dev);
1176 + int ret;
1177 +
1178 + switch (cmd) {
1179 +
1180 + case SIOCETHTOOL:
1181 + spin_lock_irq(&sp->lock);
1182 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1183 + spin_unlock_irq(&sp->lock);
1184 + return ret;
1185 +
1186 + case SIOCSIFHWADDR:
1187 + if (copy_from_user
1188 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1189 + return -EFAULT;
1190 + return 0;
1191 +
1192 + case SIOCGIFHWADDR:
1193 + if (copy_to_user
1194 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1195 + return -EFAULT;
1196 + return 0;
1197 +
1198 + case SIOCGMIIPHY:
1199 + case SIOCGMIIREG:
1200 + case SIOCSMIIREG:
1201 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1202 +
1203 + default:
1204 + break;
1205 + }
1206 +
1207 + return -EOPNOTSUPP;
1208 +}
1209 +
1210 +static void ar231x_adjust_link(struct net_device *dev)
1211 +{
1212 + struct ar231x_private *sp = netdev_priv(dev);
1213 + unsigned int mc;
1214 +
1215 + if (!sp->phy_dev->link)
1216 + return;
1217 +
1218 + if (sp->phy_dev->duplex != sp->oldduplex) {
1219 + mc = readl(&sp->eth_regs->mac_control);
1220 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1221 + if (sp->phy_dev->duplex)
1222 + mc |= MAC_CONTROL_F;
1223 + else
1224 + mc |= MAC_CONTROL_DRO;
1225 + writel(mc, &sp->eth_regs->mac_control);
1226 + sp->oldduplex = sp->phy_dev->duplex;
1227 + }
1228 +}
1229 +
1230 +#define MII_ADDR(phy, reg) \
1231 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1232 +
1233 +static int
1234 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1235 +{
1236 + struct net_device *const dev = bus->priv;
1237 + struct ar231x_private *sp = netdev_priv(dev);
1238 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1239 +
1240 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1241 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1242 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1243 +}
1244 +
1245 +static int
1246 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1247 + u16 value)
1248 +{
1249 + struct net_device *const dev = bus->priv;
1250 + struct ar231x_private *sp = netdev_priv(dev);
1251 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1252 +
1253 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1254 + ethernet->mii_data = value << MII_DATA_SHIFT;
1255 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1256 +
1257 + return 0;
1258 +}
1259 +
1260 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1261 +{
1262 + struct net_device *const dev = bus->priv;
1263 +
1264 + ar231x_reset_reg(dev);
1265 +
1266 + return 0;
1267 +}
1268 +
1269 +static int ar231x_mdiobus_probe (struct net_device *dev)
1270 +{
1271 + struct ar231x_private *const sp = netdev_priv(dev);
1272 + struct phy_device *phydev = NULL;
1273 + int phy_addr;
1274 +
1275 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1276 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1277 + if (sp->mii_bus->phy_map[phy_addr]) {
1278 + phydev = sp->mii_bus->phy_map[phy_addr];
1279 + sp->phy = phy_addr;
1280 + break; /* break out with first one found */
1281 + }
1282 +
1283 + if (!phydev) {
1284 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1285 + return -1;
1286 + }
1287 +
1288 + /* now we are supposed to have a proper phydev, to attach to... */
1289 + BUG_ON(!phydev);
1290 + BUG_ON(phydev->attached_dev);
1291 +
1292 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0,
1293 + PHY_INTERFACE_MODE_MII);
1294 +
1295 + if (IS_ERR(phydev)) {
1296 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1297 + return PTR_ERR(phydev);
1298 + }
1299 +
1300 + /* mask with MAC supported features */
1301 + phydev->supported &= (SUPPORTED_10baseT_Half
1302 + | SUPPORTED_10baseT_Full
1303 + | SUPPORTED_100baseT_Half
1304 + | SUPPORTED_100baseT_Full
1305 + | SUPPORTED_Autoneg
1306 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1307 + | SUPPORTED_MII
1308 + | SUPPORTED_TP);
1309 +
1310 + phydev->advertising = phydev->supported;
1311 +
1312 + sp->oldduplex = -1;
1313 + sp->phy_dev = phydev;
1314 +
1315 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1316 + "(mii_bus:phy_addr=%s)\n",
1317 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1318 +
1319 + return 0;
1320 +}
1321 +
1322 --- /dev/null
1323 +++ b/drivers/net/ar231x.h
1324 @@ -0,0 +1,302 @@
1325 +/*
1326 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1327 + *
1328 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1329 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1330 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1331 + *
1332 + * Thanks to Atheros for providing hardware and documentation
1333 + * enabling me to write this driver.
1334 + *
1335 + * This program is free software; you can redistribute it and/or modify
1336 + * it under the terms of the GNU General Public License as published by
1337 + * the Free Software Foundation; either version 2 of the License, or
1338 + * (at your option) any later version.
1339 + */
1340 +
1341 +#ifndef _AR2313_H_
1342 +#define _AR2313_H_
1343 +
1344 +#include <generated/autoconf.h>
1345 +#include <linux/bitops.h>
1346 +#include <asm/bootinfo.h>
1347 +#include <ar231x_platform.h>
1348 +
1349 +/*
1350 + * probe link timer - 5 secs
1351 + */
1352 +#define LINK_TIMER (5*HZ)
1353 +
1354 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1355 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1356 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1357 +
1358 +#define AR2313_TX_TIMEOUT (HZ/4)
1359 +
1360 +/*
1361 + * Rings
1362 + */
1363 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1364 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1365 +
1366 +#define AR2313_MBGET 2
1367 +#define AR2313_MBSET 3
1368 +#define AR2313_PCI_RECONFIG 4
1369 +#define AR2313_PCI_DUMP 5
1370 +#define AR2313_TEST_PANIC 6
1371 +#define AR2313_TEST_NULLPTR 7
1372 +#define AR2313_READ_DATA 8
1373 +#define AR2313_WRITE_DATA 9
1374 +#define AR2313_GET_VERSION 10
1375 +#define AR2313_TEST_HANG 11
1376 +#define AR2313_SYNC 12
1377 +
1378 +#define DMA_RX_ERR_CRC BIT(1)
1379 +#define DMA_RX_ERR_DRIB BIT(2)
1380 +#define DMA_RX_ERR_MII BIT(3)
1381 +#define DMA_RX_EV2 BIT(5)
1382 +#define DMA_RX_ERR_COL BIT(6)
1383 +#define DMA_RX_LONG BIT(7)
1384 +#define DMA_RX_LS BIT(8) /* last descriptor */
1385 +#define DMA_RX_FS BIT(9) /* first descriptor */
1386 +#define DMA_RX_MF BIT(10) /* multicast frame */
1387 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1388 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1389 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1390 +#define DMA_RX_ERROR BIT(15) /* error summary */
1391 +#define DMA_RX_LEN_MASK 0x3fff0000
1392 +#define DMA_RX_LEN_SHIFT 16
1393 +#define DMA_RX_FILT BIT(30)
1394 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1395 +
1396 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1397 +#define DMA_RX1_BSIZE_SHIFT 0
1398 +#define DMA_RX1_CHAINED BIT(24)
1399 +#define DMA_RX1_RER BIT(25)
1400 +
1401 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1402 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1403 +#define DMA_TX_COL_MASK 0x78
1404 +#define DMA_TX_COL_SHIFT 3
1405 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1406 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1407 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1408 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1409 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1410 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1411 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1412 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1413 +
1414 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1415 +#define DMA_TX1_BSIZE_SHIFT 0
1416 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1417 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1418 +#define DMA_TX1_FS BIT(29) /* first segment */
1419 +#define DMA_TX1_LS BIT(30) /* last segment */
1420 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1421 +
1422 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1423 +
1424 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1425 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1426 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1427 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1428 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1429 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1430 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1431 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1432 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1433 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1434 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1435 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1436 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1437 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1438 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1439 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1440 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1441 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1442 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1443 +
1444 +#define MII_ADDR_BUSY BIT(0)
1445 +#define MII_ADDR_WRITE BIT(1)
1446 +#define MII_ADDR_REG_SHIFT 6
1447 +#define MII_ADDR_PHY_SHIFT 11
1448 +#define MII_DATA_SHIFT 0
1449 +
1450 +#define FLOW_CONTROL_FCE BIT(1)
1451 +
1452 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1453 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1454 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1455 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1456 +
1457 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1458 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1459 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1460 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1461 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1462 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1463 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1464 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1465 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1466 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1467 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1468 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1469 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1470 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1471 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1472 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1473 +
1474 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1475 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1476 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1477 +
1478 +
1479 +typedef struct {
1480 + volatile unsigned int status; // OWN, Device control and status.
1481 + volatile unsigned int devcs; // pkt Control bits + Length
1482 + volatile unsigned int addr; // Current Address.
1483 + volatile unsigned int descr; // Next descriptor in chain.
1484 +} ar231x_descr_t;
1485 +
1486 +
1487 +
1488 +//
1489 +// New Combo structure for Both Eth0 AND eth1
1490 +//
1491 +typedef struct {
1492 + volatile unsigned int mac_control; /* 0x00 */
1493 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1494 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1495 + volatile unsigned int mii_addr; /* 0x14 */
1496 + volatile unsigned int mii_data; /* 0x18 */
1497 + volatile unsigned int flow_control; /* 0x1c */
1498 + volatile unsigned int vlan_tag; /* 0x20 */
1499 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1500 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1501 +
1502 +} ETHERNET_STRUCT;
1503 +
1504 +/********************************************************************
1505 + * Interrupt controller
1506 + ********************************************************************/
1507 +
1508 +typedef struct {
1509 + volatile unsigned int wdog_control; /* 0x08 */
1510 + volatile unsigned int wdog_timer; /* 0x0c */
1511 + volatile unsigned int misc_status; /* 0x10 */
1512 + volatile unsigned int misc_mask; /* 0x14 */
1513 + volatile unsigned int global_status; /* 0x18 */
1514 + volatile unsigned int reserved; /* 0x1c */
1515 + volatile unsigned int reset_control; /* 0x20 */
1516 +} INTERRUPT;
1517 +
1518 +/********************************************************************
1519 + * DMA controller
1520 + ********************************************************************/
1521 +typedef struct {
1522 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1523 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1524 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1525 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1526 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1527 + volatile unsigned int status; /* 0x14 (CSR5) */
1528 + volatile unsigned int control; /* 0x18 (CSR6) */
1529 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1530 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1531 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1532 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1533 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1534 +} DMA;
1535 +
1536 +/*
1537 + * Struct private for the Sibyte.
1538 + *
1539 + * Elements are grouped so variables used by the tx handling goes
1540 + * together, and will go into the same cache lines etc. in order to
1541 + * avoid cache line contention between the rx and tx handling on SMP.
1542 + *
1543 + * Frequently accessed variables are put at the beginning of the
1544 + * struct to help the compiler generate better/shorter code.
1545 + */
1546 +struct ar231x_private {
1547 + struct net_device *dev;
1548 + int version;
1549 + u32 mb[2];
1550 +
1551 + volatile ETHERNET_STRUCT *phy_regs;
1552 + volatile ETHERNET_STRUCT *eth_regs;
1553 + volatile DMA *dma_regs;
1554 + volatile u32 *int_regs;
1555 + struct ar231x_eth *cfg;
1556 +
1557 + spinlock_t lock; /* Serialise access to device */
1558 +
1559 + /*
1560 + * RX and TX descriptors, must be adjacent
1561 + */
1562 + ar231x_descr_t *rx_ring;
1563 + ar231x_descr_t *tx_ring;
1564 +
1565 +
1566 + struct sk_buff **rx_skb;
1567 + struct sk_buff **tx_skb;
1568 +
1569 + /*
1570 + * RX elements
1571 + */
1572 + u32 rx_skbprd;
1573 + u32 cur_rx;
1574 +
1575 + /*
1576 + * TX elements
1577 + */
1578 + u32 tx_prd;
1579 + u32 tx_csm;
1580 +
1581 + /*
1582 + * Misc elements
1583 + */
1584 + char name[48];
1585 + struct {
1586 + u32 address;
1587 + u32 length;
1588 + char *mapping;
1589 + } desc;
1590 +
1591 +
1592 + struct timer_list link_timer;
1593 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1594 + unsigned short mac;
1595 + unsigned short link; /* 0 - link down, 1 - link up */
1596 + u16 phyData;
1597 +
1598 + struct tasklet_struct rx_tasklet;
1599 + int unloading;
1600 +
1601 + struct phy_device *phy_dev;
1602 + struct mii_bus *mii_bus;
1603 + int oldduplex;
1604 +};
1605 +
1606 +
1607 +/*
1608 + * Prototypes
1609 + */
1610 +static int ar231x_init(struct net_device *dev);
1611 +#ifdef TX_TIMEOUT
1612 +static void ar231x_tx_timeout(struct net_device *dev);
1613 +#endif
1614 +static int ar231x_restart(struct net_device *dev);
1615 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1616 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1617 +static int ar231x_open(struct net_device *dev);
1618 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1619 +static int ar231x_close(struct net_device *dev);
1620 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1621 + int cmd);
1622 +static void ar231x_init_cleanup(struct net_device *dev);
1623 +static int ar231x_setup_timer(struct net_device *dev);
1624 +static void ar231x_link_timer_fn(unsigned long data);
1625 +static void ar231x_check_link(struct net_device *dev);
1626 +#endif /* _AR2313_H_ */
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