target/linux/ramips/files/drivers/net/ramips_esw.c

   1 #include <linux/ioport.h>
   2
   3 #include <rt305x_regs.h>
   4 #include <rt305x_esw_platform.h>
   5
   6 #define RT305X_ESW_REG_FCT0             0x08
   7 #define RT305X_ESW_REG_PFC1             0x14
   8 #define RT305X_ESW_REG_PVIDC(_n)        (0x40 + 4 * (_n))
   9 #define RT305X_ESW_REG_VLANI(_n)        (0x50 + 4 * (_n))
  10 #define RT305X_ESW_REG_VMSC(_n)         (0x70 + 4 * (_n))
  11 #define RT305X_ESW_REG_FPA              0x84
  12 #define RT305X_ESW_REG_SOCPC            0x8c
  13 #define RT305X_ESW_REG_POC1             0x90
  14 #define RT305X_ESW_REG_POC2             0x94
  15 #define RT305X_ESW_REG_POC3             0x98
  16 #define RT305X_ESW_REG_SGC              0x9c
  17 #define RT305X_ESW_REG_PCR0             0xc0
  18 #define RT305X_ESW_REG_PCR1             0xc4
  19 #define RT305X_ESW_REG_FPA2             0xc8
  20 #define RT305X_ESW_REG_FCT2             0xcc
  21 #define RT305X_ESW_REG_SGC2             0xe4
  22
  23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S  16
  24 #define RT305X_ESW_PCR0_WT_PHY_CMD      BIT(13)
  25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S   8
  26
  27 #define RT305X_ESW_PCR1_WT_DONE         BIT(0)
  28
  29 #define RT305X_ESW_PHY_TIMEOUT          (5 * HZ)
  30
  31 #define RT305X_ESW_PVIDC_PVID_M         0xfff
  32 #define RT305X_ESW_PVIDC_PVID_S         12
  33
  34 #define RT305X_ESW_VLANI_VID_M          0xfff
  35 #define RT305X_ESW_VLANI_VID_S          12
  36
  37 #define RT305X_ESW_VMSC_MSC_M           0xff
  38 #define RT305X_ESW_VMSC_MSC_S           8
  39
  40 #define RT305X_ESW_SOCPC_DISUN2CPU_S    0
  41 #define RT305X_ESW_SOCPC_DISMC2CPU_S    8
  42 #define RT305X_ESW_SOCPC_DISBC2CPU_S    16
  43 #define RT305X_ESW_SOCPC_CRC_PADDING    BIT(25)
  44
  45 #define RT305X_ESW_POC1_EN_BP_S         0
  46 #define RT305X_ESW_POC1_EN_FC_S         8
  47 #define RT305X_ESW_POC1_DIS_RMC2CPU_S   16
  48 #define RT305X_ESW_POC1_DIS_PORT_S      23
  49
  50 #define RT305X_ESW_POC3_UNTAG_EN_S      0
  51 #define RT305X_ESW_POC3_ENAGING_S       8
  52 #define RT305X_ESW_POC3_DIS_UC_PAUSE_S  16
  53
  54 #define RT305X_ESW_PORT0                0
  55 #define RT305X_ESW_PORT1                1
  56 #define RT305X_ESW_PORT2                2
  57 #define RT305X_ESW_PORT3                3
  58 #define RT305X_ESW_PORT4                4
  59 #define RT305X_ESW_PORT5                5
  60 #define RT305X_ESW_PORT6                6
  61
  62 #define RT305X_ESW_PORTS_INTERNAL                                       \
  63                 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
  64                  BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
  65                  BIT(RT305X_ESW_PORT4))
  66
  67 #define RT305X_ESW_PORTS_NOCPU  \
  68                 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
  69
  70 #define RT305X_ESW_PORTS_CPU    BIT(RT305X_ESW_PORT6)
  71
  72 #define RT305X_ESW_PORTS_ALL    \
  73                 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
  74
  75 #define RT305X_ESW_NUM_VLANS    16
  76 #define RT305X_ESW_NUM_PORTS    7
  77
  78 struct rt305x_esw {
  79         void __iomem *base;
  80         struct rt305x_esw_platform_data *pdata;
  81         spinlock_t reg_rw_lock;
  82 };
  83
  84 static inline void
  85 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
  86 {
  87         __raw_writel(val, esw->base + reg);
  88 }
  89
  90 static inline u32
  91 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
  92 {
  93         return __raw_readl(esw->base + reg);
  94 }
  95
  96 static inline void
  97 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
  98                    unsigned long val)
  99 {
 100         unsigned long t;
 101
 102         t = __raw_readl(esw->base + reg) & ~mask;
 103         __raw_writel(t | val, esw->base + reg);
 104 }
 105
 106 static void
 107 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 108                unsigned long val)
 109 {
 110         unsigned long flags;
 111
 112         spin_lock_irqsave(&esw->reg_rw_lock, flags);
 113         rt305x_esw_rmw_raw(esw, reg, mask, val);
 114         spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 115 }
 116
 117 static u32
 118 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 119                  u32 write_data)
 120 {
 121         unsigned long t_start = jiffies;
 122         int ret = 0;
 123
 124         while (1) {
 125                 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 126                       RT305X_ESW_PCR1_WT_DONE))
 127                         break;
 128                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 129                         ret = 1;
 130                         goto out;
 131                 }
 132         }
 133
 134         write_data &= 0xffff;
 135         rt305x_esw_wr(esw,
 136                       (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 137                       (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 138                       (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 139                       RT305X_ESW_REG_PCR0);
 140
 141         t_start = jiffies;
 142         while (1) {
 143                 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
 144                     RT305X_ESW_PCR1_WT_DONE)
 145                         break;
 146
 147                 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 148                         ret = 1;
 149                         break;
 150                 }
 151         }
 152 out:
 153         if (ret)
 154                 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 155         return ret;
 156 }
 157
 158 static void
 159 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 160 {
 161         unsigned s;
 162
 163         s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 164         rt305x_esw_rmw(esw,
 165                        RT305X_ESW_REG_VLANI(vlan / 2),
 166                        RT305X_ESW_VLANI_VID_M << s,
 167                        (vid & RT305X_ESW_VLANI_VID_M) << s);
 168 }
 169
 170 static void
 171 rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 172 {
 173         unsigned s;
 174
 175         s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 176         rt305x_esw_rmw(esw,
 177                        RT305X_ESW_REG_PVIDC(port / 2),
 178                        RT305X_ESW_PVIDC_PVID_M << s,
 179                        (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 180 }
 181
 182 static void
 183 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 184 {
 185         unsigned s;
 186
 187         s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 188         rt305x_esw_rmw(esw,
 189                        RT305X_ESW_REG_VMSC(vlan / 4),
 190                        RT305X_ESW_VMSC_MSC_M << s,
 191                        (msc & RT305X_ESW_VMSC_MSC_M) << s);
 192 }
 193
 194 static void
 195 rt305x_esw_hw_init(struct rt305x_esw *esw)
 196 {
 197         int i;
 198
 199         /* vodoo from original driver */
 200         rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 201         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 202         rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
 203
 204         /* Enable Back Pressure, and Flow Control */
 205         rt305x_esw_wr(esw,
 206                       ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
 207                        (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
 208                       RT305X_ESW_REG_POC1);
 209
 210         /* Enable Aging, and VLAN TAG removal */
 211         rt305x_esw_wr(esw,
 212                       ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
 213                        (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
 214                       RT305X_ESW_REG_POC3);
 215
 216         rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
 217         rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 218
 219         /* Setup SoC Port control register */
 220         rt305x_esw_wr(esw,
 221                       (RT305X_ESW_SOCPC_CRC_PADDING |
 222                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 223                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 224                        (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 225                       RT305X_ESW_REG_SOCPC);
 226
 227         rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
 228         rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
 229
 230         rt305x_mii_write(esw, 0, 31, 0x8000);
 231         for (i = 0; i < 5; i++) {
 232                 /* TX10 waveform coefficient */
 233                 rt305x_mii_write(esw, i, 0, 0x3100);
 234                 /* TX10 waveform coefficient */
 235                 rt305x_mii_write(esw, i, 26, 0x1601);
 236                 /* TX100/TX10 AD/DA current bias */
 237                 rt305x_mii_write(esw, i, 29, 0x7058);
 238                 /* TX100 slew rate control */
 239                 rt305x_mii_write(esw, i, 30, 0x0018);
 240         }
 241
 242         /* PHY IOT */
 243         /* select global register */
 244         rt305x_mii_write(esw, 0, 31, 0x0);
 245         /* tune TP_IDL tail and head waveform */
 246         rt305x_mii_write(esw, 0, 22, 0x052f);
 247         /* set TX10 signal amplitude threshold to minimum */
 248         rt305x_mii_write(esw, 0, 17, 0x0fe0);
 249         /* set squelch amplitude to higher threshold */
 250         rt305x_mii_write(esw, 0, 18, 0x40ba);
 251         /* longer TP_IDL tail length */
 252         rt305x_mii_write(esw, 0, 14, 0x65);
 253         /* select local register */
 254         rt305x_mii_write(esw, 0, 31, 0x8000);
 255
 256         for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 257                 rt305x_esw_set_vlan_id(esw, i, 0);
 258                 rt305x_esw_set_vmsc(esw, i, 0);
 259         }
 260
 261         for (i = 0; i < RT305X_ESW_NUM_PORTS; i++)
 262                 rt305x_esw_set_pvid(esw, i, 1);
 263
 264         switch (esw->pdata->vlan_config) {
 265         case RT305X_ESW_VLAN_CONFIG_NONE:
 266                 break;
 267
 268         case RT305X_ESW_VLAN_CONFIG_LLLLW:
 269                 rt305x_esw_set_vlan_id(esw, 0, 1);
 270                 rt305x_esw_set_vlan_id(esw, 1, 2);
 271                 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
 272
 273                 rt305x_esw_set_vmsc(esw, 0,
 274                                 BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
 275                                 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
 276                                 BIT(RT305X_ESW_PORT6));
 277                 rt305x_esw_set_vmsc(esw, 1,
 278                                 BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6));
 279                 break;
 280
 281         case RT305X_ESW_VLAN_CONFIG_WLLLL:
 282                 rt305x_esw_set_vlan_id(esw, 0, 1);
 283                 rt305x_esw_set_vlan_id(esw, 1, 2);
 284                 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT0, 2);
 285
 286                 rt305x_esw_set_vmsc(esw, 0,
 287                                 BIT(RT305X_ESW_PORT1) | BIT(RT305X_ESW_PORT2) |
 288                                 BIT(RT305X_ESW_PORT3) | BIT(RT305X_ESW_PORT4) |
 289                                 BIT(RT305X_ESW_PORT6));
 290                 rt305x_esw_set_vmsc(esw, 1,
 291                                 BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT6));
 292                 break;
 293
 294         default:
 295                 BUG();
 296         }
 297 }
 298
 299 static int
 300 rt305x_esw_probe(struct platform_device *pdev)
 301 {
 302         struct rt305x_esw_platform_data *pdata;
 303         struct rt305x_esw *esw;
 304         struct resource *res;
 305         int err;
 306
 307         pdata = pdev->dev.platform_data;
 308         if (!pdata)
 309                 return -EINVAL;
 310
 311         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 312         if (!res) {
 313                 dev_err(&pdev->dev, "no memory resource found\n");
 314                 return -ENOMEM;
 315         }
 316
 317         esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
 318         if (!esw) {
 319                 dev_err(&pdev->dev, "no memory for private data\n");
 320                 return -ENOMEM;
 321         }
 322
 323         esw->base = ioremap(res->start, resource_size(res));
 324         if (!esw->base) {
 325                 dev_err(&pdev->dev, "ioremap failed\n");
 326                 err = -ENOMEM;
 327                 goto free_esw;
 328         }
 329
 330         platform_set_drvdata(pdev, esw);
 331
 332         esw->pdata = pdata;
 333         spin_lock_init(&esw->reg_rw_lock);
 334         rt305x_esw_hw_init(esw);
 335
 336         return 0;
 337
 338 free_esw:
 339         kfree(esw);
 340         return err;
 341 }
 342
 343 static int
 344 rt305x_esw_remove(struct platform_device *pdev)
 345 {
 346         struct rt305x_esw *esw;
 347
 348         esw = platform_get_drvdata(pdev);
 349         if (esw) {
 350                 platform_set_drvdata(pdev, NULL);
 351                 iounmap(esw->base);
 352                 kfree(esw);
 353         }
 354
 355         return 0;
 356 }
 357
 358 static struct platform_driver rt305x_esw_driver = {
 359         .probe = rt305x_esw_probe,
 360         .remove = rt305x_esw_remove,
 361         .driver = {
 362                 .name = "rt305x-esw",
 363                 .owner = THIS_MODULE,
 364         },
 365 };
 366
 367 static int __init
 368 rt305x_esw_init(void)
 369 {
 370         return platform_driver_register(&rt305x_esw_driver);
 371 }
 372
 373 static void
 374 rt305x_esw_exit(void)
 375 {
 376         platform_driver_unregister(&rt305x_esw_driver);
 377 }