2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71 #define AR7240_REG_TAG_PRIORITY 0x70
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
200 #define AR7240_MAX_VLANS 16
202 #define AR934X_REG_OPER_MODE0 0x04
203 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
204 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206 #define AR934X_REG_OPER_MODE1 0x08
207 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
209 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
211 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
212 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
213 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
214 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
215 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
216 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
217 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
218 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
219 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
221 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
222 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
223 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
224 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
225 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
226 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
227 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
229 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
232 struct mii_bus
*mii_bus
;
233 struct ag71xx_switch_platform_data
*swdata
;
234 struct switch_dev swdev
;
238 u16 vlan_id
[AR7240_MAX_VLANS
];
239 u8 vlan_table
[AR7240_MAX_VLANS
];
241 u16 pvid
[AR7240_NUM_PORTS
];
245 struct ar7240sw_hw_stat
{
246 char string
[ETH_GSTRING_LEN
];
251 static DEFINE_MUTEX(reg_mutex
);
253 static inline int sw_is_ar7240(struct ar7240sw
*as
)
255 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR7240
;
258 static inline int sw_is_ar934x(struct ar7240sw
*as
)
260 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR934X
;
263 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
268 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
270 return BIT(as
->swdev
.ports
) - 1;
273 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
275 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
278 static inline u16
mk_phy_addr(u32 reg
)
280 return 0x17 & ((reg
>> 4) | 0x10);
283 static inline u16
mk_phy_reg(u32 reg
)
285 return (reg
<< 1) & 0x1e;
288 static inline u16
mk_high_addr(u32 reg
)
290 return (reg
>> 7) & 0x1ff;
293 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
300 reg
= (reg
& 0xfffffffc) >> 2;
301 phy_addr
= mk_phy_addr(reg
);
302 phy_reg
= mk_phy_reg(reg
);
304 local_irq_save(flags
);
305 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
306 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
307 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
308 local_irq_restore(flags
);
310 return (hi
<< 16) | lo
;
313 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
319 reg
= (reg
& 0xfffffffc) >> 2;
320 phy_addr
= mk_phy_addr(reg
);
321 phy_reg
= mk_phy_reg(reg
);
323 local_irq_save(flags
);
324 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
325 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
326 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
327 local_irq_restore(flags
);
330 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
334 mutex_lock(®_mutex
);
335 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
336 mutex_unlock(®_mutex
);
341 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
343 mutex_lock(®_mutex
);
344 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
345 mutex_unlock(®_mutex
);
348 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
352 mutex_lock(®_mutex
);
353 t
= __ar7240sw_reg_read(mii
, reg
);
356 __ar7240sw_reg_write(mii
, reg
, t
);
357 mutex_unlock(®_mutex
);
362 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
366 mutex_lock(®_mutex
);
367 t
= __ar7240sw_reg_read(mii
, reg
);
369 __ar7240sw_reg_write(mii
, reg
, t
);
370 mutex_unlock(®_mutex
);
373 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
378 for (i
= 0; i
< timeout
; i
++) {
381 t
= __ar7240sw_reg_read(mii
, reg
);
382 if ((t
& mask
) == val
)
391 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
396 mutex_lock(®_mutex
);
397 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
398 mutex_unlock(®_mutex
);
402 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
408 if (phy_addr
>= AR7240_NUM_PHYS
)
411 mutex_lock(®_mutex
);
412 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
413 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
414 AR7240_MDIO_CTRL_MASTER_EN
|
415 AR7240_MDIO_CTRL_BUSY
|
416 AR7240_MDIO_CTRL_CMD_READ
;
418 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
419 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
420 AR7240_MDIO_CTRL_BUSY
, 0, 5);
422 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
423 mutex_unlock(®_mutex
);
425 return val
& AR7240_MDIO_CTRL_DATA_M
;
428 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
429 unsigned reg_addr
, u16 reg_val
)
434 if (phy_addr
>= AR7240_NUM_PHYS
)
437 mutex_lock(®_mutex
);
438 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
439 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
440 AR7240_MDIO_CTRL_MASTER_EN
|
441 AR7240_MDIO_CTRL_BUSY
|
442 AR7240_MDIO_CTRL_CMD_WRITE
|
445 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
446 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
447 AR7240_MDIO_CTRL_BUSY
, 0, 5);
448 mutex_unlock(®_mutex
);
453 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
455 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
456 AR7240_PORT_CTRL_STATE_DISABLED
);
459 static void ar7240sw_setup(struct ar7240sw
*as
)
461 struct mii_bus
*mii
= as
->mii_bus
;
463 /* Enable CPU port, and disable mirror port */
464 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
466 (15 << AR7240_MIRROR_PORT_S
));
468 /* Setup TAG priority mapping */
469 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
471 /* Enable ARP frame acknowledge, aging, MAC replacing */
472 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
473 0x2b /* 5 min age time */ |
474 AR7240_AT_CTRL_AGE_EN
|
475 AR7240_AT_CTRL_ARP_EN
|
476 AR7240_AT_CTRL_LEARN_CHANGE
);
478 /* Enable Broadcast frames transmitted to the CPU */
479 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
480 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
483 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
, AR7240_GLOBAL_CTRL_MTU_M
,
486 /* setup Service TAG */
487 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
490 static int ar7240sw_reset(struct ar7240sw
*as
)
492 struct mii_bus
*mii
= as
->mii_bus
;
496 /* Set all ports to disabled state. */
497 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
498 ar7240sw_disable_port(as
, i
);
500 /* Wait for transmit queues to drain. */
503 /* Reset the switch. */
504 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
505 AR7240_MASK_CTRL_SOFT_RESET
);
507 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
508 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
514 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
516 struct mii_bus
*mii
= as
->mii_bus
;
520 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
521 AR7240_PORT_CTRL_SINGLE_VLAN
;
523 if (port
== AR7240_PORT_CPU
) {
524 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
525 AR7240_PORT_STATUS_SPEED_1000
|
526 AR7240_PORT_STATUS_TXFLOW
|
527 AR7240_PORT_STATUS_RXFLOW
|
528 AR7240_PORT_STATUS_TXMAC
|
529 AR7240_PORT_STATUS_RXMAC
|
530 AR7240_PORT_STATUS_DUPLEX
);
532 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
533 AR7240_PORT_STATUS_LINK_AUTO
);
536 /* Set the default VID for this port */
538 vid
= as
->vlan_id
[as
->pvid
[port
]];
539 mode
= AR7240_PORT_VLAN_MODE_SECURE
;
542 mode
= AR7240_PORT_VLAN_MODE_PORT_ONLY
;
545 if (as
->vlan
&& (as
->vlan_tagged
& BIT(port
))) {
546 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
547 AR7240_PORT_CTRL_VLAN_MODE_S
;
549 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
550 AR7240_PORT_CTRL_VLAN_MODE_S
;
554 if (port
== AR7240_PORT_CPU
)
555 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
557 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
560 /* allow the port to talk to all other ports, but exclude its
561 * own ID to prevent frames from being reflected back to the
562 * port that they came from */
563 portmask
&= ar7240sw_port_mask_but(as
, port
);
565 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
566 if (sw_is_ar934x(as
)) {
569 vlan1
= (vid
<< AR934X_PORT_VLAN1_DEFAULT_CVID_S
);
570 vlan2
= (portmask
<< AR934X_PORT_VLAN2_PORT_VID_MEM_S
) |
571 (mode
<< AR934X_PORT_VLAN2_8021Q_MODE_S
);
572 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN1(port
), vlan1
);
573 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN2(port
), vlan2
);
577 vlan
= vid
| (mode
<< AR7240_PORT_VLAN_MODE_S
) |
578 (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
580 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
584 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
586 struct mii_bus
*mii
= as
->mii_bus
;
589 t
= (addr
[4] << 8) | addr
[5];
590 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
592 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
593 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
599 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
600 struct switch_val
*val
)
602 struct ar7240sw
*as
= sw_to_ar7240(dev
);
603 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
608 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
609 struct switch_val
*val
)
611 struct ar7240sw
*as
= sw_to_ar7240(dev
);
612 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
617 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
619 struct ar7240sw
*as
= sw_to_ar7240(dev
);
621 /* make sure no invalid PVIDs get set */
623 if (vlan
>= dev
->vlans
)
626 as
->pvid
[port
] = vlan
;
631 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
633 struct ar7240sw
*as
= sw_to_ar7240(dev
);
634 *vlan
= as
->pvid
[port
];
639 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
641 struct ar7240sw
*as
= sw_to_ar7240(dev
);
642 u8 ports
= as
->vlan_table
[val
->port_vlan
];
646 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
647 struct switch_port
*p
;
649 if (!(ports
& (1 << i
)))
652 p
= &val
->value
.ports
[val
->len
++];
654 if (as
->vlan_tagged
& (1 << i
))
655 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
663 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
665 struct ar7240sw
*as
= sw_to_ar7240(dev
);
666 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
670 for (i
= 0; i
< val
->len
; i
++) {
671 struct switch_port
*p
= &val
->value
.ports
[i
];
673 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
674 as
->vlan_tagged
|= (1 << p
->id
);
676 as
->vlan_tagged
&= ~(1 << p
->id
);
677 as
->pvid
[p
->id
] = val
->port_vlan
;
679 /* make sure that an untagged port does not
680 * appear in other vlans */
681 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
682 if (j
== val
->port_vlan
)
684 as
->vlan_table
[j
] &= ~(1 << p
->id
);
694 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
695 struct switch_val
*val
)
697 struct ar7240sw
*as
= sw_to_ar7240(dev
);
698 as
->vlan
= !!val
->value
.i
;
703 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
704 struct switch_val
*val
)
706 struct ar7240sw
*as
= sw_to_ar7240(dev
);
707 val
->value
.i
= as
->vlan
;
712 ar7240_speed_str(u32 status
)
716 speed
= (status
>> AR7240_PORT_STATUS_SPEED_S
) &
717 AR7240_PORT_STATUS_SPEED_M
;
719 case AR7240_PORT_STATUS_SPEED_10
:
721 case AR7240_PORT_STATUS_SPEED_100
:
723 case AR7240_PORT_STATUS_SPEED_1000
:
731 ar7240_port_get_link(struct switch_dev
*dev
, const struct switch_attr
*attr
,
732 struct switch_val
*val
)
734 struct ar7240sw
*as
= sw_to_ar7240(dev
);
735 struct mii_bus
*mii
= as
->mii_bus
;
740 port
= val
->port_vlan
;
742 memset(as
->buf
, '\0', sizeof(as
->buf
));
743 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
745 if (status
& AR7240_PORT_STATUS_LINK_UP
) {
746 len
= snprintf(as
->buf
, sizeof(as
->buf
),
747 "port:%d link:up speed:%s %s-duplex %s%s%s",
749 ar7240_speed_str(status
),
750 (status
& AR7240_PORT_STATUS_DUPLEX
) ?
752 (status
& AR7240_PORT_STATUS_TXFLOW
) ?
754 (status
& AR7240_PORT_STATUS_RXFLOW
) ?
756 (status
& AR7240_PORT_STATUS_LINK_AUTO
) ?
759 len
= snprintf(as
->buf
, sizeof(as
->buf
),
760 "port:%d link:down", port
);
763 val
->value
.s
= as
->buf
;
770 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
772 struct mii_bus
*mii
= as
->mii_bus
;
774 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
777 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
778 val
&= AR7240_VTUDATA_MEMBER
;
779 val
|= AR7240_VTUDATA_VALID
;
780 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
782 op
|= AR7240_VTU_ACTIVE
;
783 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
787 ar7240_hw_apply(struct switch_dev
*dev
)
789 struct ar7240sw
*as
= sw_to_ar7240(dev
);
790 u8 portmask
[AR7240_NUM_PORTS
];
793 /* flush all vlan translation unit entries */
794 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
796 memset(portmask
, 0, sizeof(portmask
));
798 /* calculate the port destination masks and load vlans
799 * into the vlan translation unit */
800 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
801 u8 vp
= as
->vlan_table
[j
];
806 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
809 portmask
[i
] |= vp
& ~mask
;
814 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
819 * isolate all ports, but connect them to the cpu port */
820 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
821 if (i
== AR7240_PORT_CPU
)
824 portmask
[i
] = 1 << AR7240_PORT_CPU
;
825 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
829 /* update the port destination mask registers and tag settings */
830 for (i
= 0; i
< as
->swdev
.ports
; i
++)
831 ar7240sw_setup_port(as
, i
, portmask
[i
]);
837 ar7240_reset_switch(struct switch_dev
*dev
)
839 struct ar7240sw
*as
= sw_to_ar7240(dev
);
844 static struct switch_attr ar7240_globals
[] = {
846 .type
= SWITCH_TYPE_INT
,
847 .name
= "enable_vlan",
848 .description
= "Enable VLAN mode",
849 .set
= ar7240_set_vlan
,
850 .get
= ar7240_get_vlan
,
855 static struct switch_attr ar7240_port
[] = {
857 .type
= SWITCH_TYPE_STRING
,
859 .description
= "Get port link information",
862 .get
= ar7240_port_get_link
,
866 static struct switch_attr ar7240_vlan
[] = {
868 .type
= SWITCH_TYPE_INT
,
870 .description
= "VLAN ID",
871 .set
= ar7240_set_vid
,
872 .get
= ar7240_get_vid
,
877 static const struct switch_dev_ops ar7240_ops
= {
879 .attr
= ar7240_globals
,
880 .n_attr
= ARRAY_SIZE(ar7240_globals
),
884 .n_attr
= ARRAY_SIZE(ar7240_port
),
888 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
890 .get_port_pvid
= ar7240_get_pvid
,
891 .set_port_pvid
= ar7240_set_pvid
,
892 .get_vlan_ports
= ar7240_get_ports
,
893 .set_vlan_ports
= ar7240_set_ports
,
894 .apply_config
= ar7240_hw_apply
,
895 .reset_switch
= ar7240_reset_switch
,
898 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
900 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
901 struct mii_bus
*mii
= ag
->mii_bus
;
903 struct switch_dev
*swdev
;
909 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
910 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
911 if ((phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) &&
912 (phy_id1
!= AR934X_PHY_ID1
|| phy_id2
!= AR934X_PHY_ID2
)) {
913 pr_err("%s: unknown phy id '%04x:%04x'\n",
914 ag
->dev
->name
, phy_id1
, phy_id2
);
918 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
923 as
->swdata
= pdata
->switch_data
;
927 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
928 as
->ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) &
929 AR7240_MASK_CTRL_VERSION_M
;
931 if (sw_is_ar7240(as
)) {
932 swdev
->name
= "AR7240/AR9330 built-in switch";
933 } else if (sw_is_ar934x(as
)) {
934 swdev
->name
= "AR934X built-in switch";
936 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
937 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
938 AR934X_OPER_MODE0_MAC_GMII_EN
);
939 } else if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
940 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
941 AR934X_OPER_MODE0_PHY_MII_EN
);
943 pr_err("%s: invalid PHY interface mode\n",
948 if (as
->swdata
->phy4_mii_en
)
949 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE1
,
950 AR934X_REG_OPER_MODE1_PHY4_MII_EN
);
952 pr_err("%s: unsupported chip, ctrl=%08x\n",
953 ag
->dev
->name
, ctrl
);
957 swdev
->ports
= AR7240_NUM_PORTS
- 1;
958 swdev
->cpu_port
= AR7240_PORT_CPU
;
959 swdev
->vlans
= AR7240_MAX_VLANS
;
960 swdev
->ops
= &ar7240_ops
;
962 if (register_switch(&as
->swdev
, ag
->dev
) < 0)
965 pr_info("%s: Found an %s\n", ag
->dev
->name
, swdev
->name
);
967 /* initialize defaults */
968 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
971 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
980 static void link_function(struct work_struct
*work
) {
981 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
986 for (i
= 0; i
< 4; i
++) {
987 int link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
988 if(link
& BMSR_LSTATUS
) {
994 spin_lock_irqsave(&ag
->lock
, flags
);
995 if(status
!= ag
->link
) {
997 ag71xx_link_adjust(ag
);
999 spin_unlock_irqrestore(&ag
->lock
, flags
);
1001 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
1004 void ag71xx_ar7240_start(struct ag71xx
*ag
)
1006 struct ar7240sw
*as
= ag
->phy_priv
;
1010 ag
->speed
= SPEED_1000
;
1013 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
1014 ar7240_hw_apply(&as
->swdev
);
1016 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
1019 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
1021 cancel_delayed_work_sync(&ag
->link_work
);
1024 int __devinit
ag71xx_ar7240_init(struct ag71xx
*ag
)
1026 struct ar7240sw
*as
;
1028 as
= ar7240_probe(ag
);
1035 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
1040 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
1042 struct ar7240sw
*as
= ag
->phy_priv
;
1047 unregister_switch(&as
->swdev
);
1049 ag
->phy_priv
= NULL
;