projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Update brcm63xx to 2.6.17, restore the use of "generic patches" since there is no...
[openwrt.git] / target / linux / brcm63xx-2.6 / patches / 020-bcmdrivers.patch
1 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/Makefile linux-2.6.16.7-patched/bcmdrivers/opensource/Makefile
2 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/Makefile 2006-07-05 15:21:58.000000000 +0200
4 @@ -0,0 +1,20 @@
5 +# File: modules/drivers/Makefile
6 +#
7 +# Makefile for the GPLed Linux kernel modules.
8 +#
9 +
10 +LN_NAME=bcm9$(BRCM_CHIP)
11 +LN_DRIVER_DIRS =
12 +
13 +-include $(KERNEL_DIR)/.config
14 +
15 +ifneq ($(CONFIG_BCM_SERIAL),)
16 + LN_DRIVER_DIRS +=ln -sn impl$(CONFIG_BCM_SERIAL_IMPL) char/serial/$(LN_NAME);
17 +endif
18 +
19 +obj-$(CONFIG_BCM_SERIAL) += char/serial/impl$(CONFIG_BCM_SERIAL_IMPL)/
20 +
21 +
22 +symlinks:
23 + find . -lname "*" -name "$(LN_NAME)" -print -exec rm -f "{}" ";"
24 + $(CONFIG_SHELL) -c "$(LN_DRIVER_DIRS)"
25 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/char/serial/impl1/Makefile linux-2.6.16.7-patched/bcmdrivers/opensource/char/serial/impl1/Makefile
26 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/char/serial/impl1/Makefile 1970-01-01 01:00:00.000000000 +0100
27 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/char/serial/impl1/Makefile 2006-07-05 15:21:58.000000000 +0200
28 @@ -0,0 +1,13 @@
29 +# File: bcmdrivers/opensource/char/serial
30 +#
31 +# Makefile for the BCM63xx serial/console driver
32 +
33 +obj-$(CONFIG_BCM_SERIAL) += bcm63xx_cons.o
34 +
35 +EXTRA_CFLAGS += -I$(INC_BRCMDRIVER_PUB_PATH)/$(BRCM_BOARD)
36 +
37 +-include $(TOPDIR)/Rules.make
38 +
39 +clean:
40 + rm -f core *.o *.a *.s
41 +
42 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c linux-2.6.16.7-patched/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c
43 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c 1970-01-01 01:00:00.000000000 +0100
44 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c 2006-07-05 15:21:58.000000000 +0200
45 @@ -0,0 +1,1038 @@
46 +/*
47 +<:copyright-gpl
48 + Copyright 2002 Broadcom Corp. All Rights Reserved.
49 +
50 + This program is free software; you can distribute it and/or modify it
51 + under the terms of the GNU General Public License (Version 2) as
52 + published by the Free Software Foundation.
53 +
54 + This program is distributed in the hope it will be useful, but WITHOUT
55 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
56 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
57 + for more details.
58 +
59 + You should have received a copy of the GNU General Public License along
60 + with this program; if not, write to the Free Software Foundation, Inc.,
61 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
62 +:>
63 +*/
64 +
65 +/* Description: Serial port driver for the BCM963XX. */
66 +
67 +#define CARDNAME "bcm963xx_serial driver"
68 +#define VERSION "2.0"
69 +#define VER_STR CARDNAME " v" VERSION "\n"
70 +
71 +
72 +#include <linux/kernel.h>
73 +#include <linux/module.h>
74 +#include <linux/version.h>
75 +#include <linux/init.h>
76 +#include <linux/slab.h>
77 +#include <linux/interrupt.h>
78 +
79 +/* for definition of struct console */
80 +#include <linux/console.h>
81 +#include <linux/tty.h>
82 +#include <linux/tty_flip.h>
83 +#include <linux/serial.h>
84 +#include <asm/uaccess.h>
85 +
86 +#include <bcmtypes.h>
87 +#include <board.h>
88 +#include <bcm_map_part.h>
89 +#include <bcm_intr.h>
90 +
91 +extern void _putc(char);
92 +extern void _puts(const char *);
93 +
94 +typedef struct bcm_serial {
95 + volatile Uart * port;
96 + int type;
97 + int flags;
98 + int irq;
99 + int baud_base;
100 + int blocked_open;
101 + unsigned short close_delay;
102 + unsigned short closing_wait;
103 + unsigned short line; /* port/line number */
104 + unsigned short cflags; /* line configuration flag */
105 + unsigned short x_char; /* xon/xoff character */
106 + unsigned short read_status_mask; /* mask for read condition */
107 + unsigned short ignore_status_mask; /* mask for ignore condition */
108 + unsigned long event; /* mask used in BH */
109 + int xmit_head; /* Position of the head */
110 + int xmit_tail; /* Position of the tail */
111 + int xmit_cnt; /* Count of the chars in the buffer */
112 + int count; /* indicates how many times it has been opened */
113 + int magic;
114 +
115 + struct async_icount icount; /* keep track of things ... */
116 + struct tty_struct *tty; /* tty associated */
117 + struct termios normal_termios;
118 +
119 + wait_queue_head_t open_wait;
120 + wait_queue_head_t close_wait;
121 +
122 + long session; /* Session of opening process */
123 + long pgrp; /* pgrp of opening process */
124 +
125 + unsigned char is_initialized;
126 +} Context;
127 +
128 +
129 +/*---------------------------------------------------------------------*/
130 +/* Define bits in the Interrupt Enable register */
131 +/*---------------------------------------------------------------------*/
132 +/* Enable receive interrupt */
133 +#define RXINT (RXFIFONE|RXOVFERR)
134 +
135 +/* Enable transmit interrupt */
136 +#define TXINT (TXFIFOEMT|TXUNDERR|TXOVFERR)
137 +
138 +/* Enable receiver line status interrupt */
139 +#define LSINT (RXBRK|RXPARERR|RXFRAMERR)
140 +
141 +#define BCM_NUM_UARTS 1
142 +
143 +#define BD_BCM63XX_TIMER_CLOCK_INPUT (FPERIPH)
144 +
145 +
146 +static struct bcm_serial multi[BCM_NUM_UARTS];
147 +static struct bcm_serial *lines[BCM_NUM_UARTS];
148 +static struct tty_driver serial_driver;
149 +static struct tty_struct *serial_table[BCM_NUM_UARTS];
150 +static struct termios *serial_termios[BCM_NUM_UARTS];
151 +static struct termios *serial_termios_locked[BCM_NUM_UARTS];
152 +static int serial_refcount;
153 +
154 +
155 +static void bcm_stop (struct tty_struct *tty);
156 +static void bcm_start (struct tty_struct *tty);
157 +static inline void receive_chars (struct bcm_serial * info);
158 +static int startup (struct bcm_serial *info);
159 +static void shutdown (struct bcm_serial * info);
160 +static void change_speed( volatile Uart *pUart, tcflag_t cFlag );
161 +static void bcm63xx_cons_flush_chars (struct tty_struct *tty);
162 +static int bcm63xx_cons_write (struct tty_struct *tty, int from_user,
163 + const unsigned char *buf, int count);
164 +static int bcm63xx_cons_write_room (struct tty_struct *tty);
165 +static int bcm_chars_in_buffer (struct tty_struct *tty);
166 +static void bcm_flush_buffer (struct tty_struct *tty);
167 +static void bcm_throttle (struct tty_struct *tty);
168 +static void bcm_unthrottle (struct tty_struct *tty);
169 +static void bcm_send_xchar (struct tty_struct *tty, char ch);
170 +static int get_serial_info(struct bcm_serial *info, struct serial_struct *retinfo);
171 +static int set_serial_info (struct bcm_serial *info, struct serial_struct *new_info);
172 +static int get_lsr_info (struct bcm_serial *info, unsigned int *value);
173 +static void send_break (struct bcm_serial *info, int duration);
174 +static int bcm_ioctl (struct tty_struct * tty, struct file * file,
175 + unsigned int cmd, unsigned long arg);
176 +static void bcm_set_termios (struct tty_struct *tty, struct termios *old_termios);
177 +static void bcm63xx_cons_close (struct tty_struct *tty, struct file *filp);
178 +static void bcm_hangup (struct tty_struct *tty);
179 +static int block_til_ready (struct tty_struct *tty, struct file *filp, struct bcm_serial *info);
180 +static int bcm63xx_cons_open (struct tty_struct * tty, struct file * filp);
181 +static int __init bcm63xx_serialinit(void);
182 +
183 +
184 +/*
185 + * ------------------------------------------------------------
186 + * rs_stop () and rs_start ()
187 + *
188 + * These routines are called before setting or resetting
189 + * tty->stopped. They enable or disable transmitter interrupts,
190 + * as necessary.
191 + * ------------------------------------------------------------
192 + */
193 +static void bcm_stop (struct tty_struct *tty)
194 +{
195 +}
196 +
197 +static void bcm_start (struct tty_struct *tty)
198 +{
199 + _puts(CARDNAME " Start\n");
200 +}
201 +
202 +/*
203 + * ------------------------------------------------------------
204 + * receive_char ()
205 + *
206 + * This routine deals with inputs from any lines.
207 + * ------------------------------------------------------------
208 + */
209 +static inline void receive_chars (struct bcm_serial * info)
210 +{
211 + struct tty_struct *tty = 0;
212 + struct async_icount * icount;
213 + int ignore = 0;
214 + unsigned short status, tmp;
215 + UCHAR ch = 0;
216 + while ((status = info->port->intStatus) & RXINT)
217 + {
218 + char flag_char = 0;
219 +
220 + if (status & RXFIFONE)
221 + ch = info->port->Data; // Read the character
222 + tty = info->tty; /* now tty points to the proper dev */
223 + icount = &info->icount;
224 + if (! tty)
225 + break;
226 + if (!tty_buffer_request_room(tty, 1))
227 + break;
228 + icount->rx++;
229 + if (status & RXBRK)
230 + {
231 + flag_char = TTY_BREAK;
232 + icount->brk++;
233 + }
234 + // keep track of the statistics
235 + if (status & (RXFRAMERR | RXPARERR | RXOVFERR))
236 + {
237 + if (status & RXPARERR) /* parity error */
238 + icount->parity++;
239 + else
240 + if (status & RXFRAMERR) /* frame error */
241 + icount->frame++;
242 + if (status & RXOVFERR)
243 + {
244 + // Overflow. Reset the RX FIFO
245 + info->port->fifoctl |= RSTRXFIFOS;
246 + icount->overrun++;
247 + }
248 + // check to see if we should ignore the character
249 + // and mask off conditions that should be ignored
250 + if (status & info->ignore_status_mask)
251 + {
252 + if (++ignore > 100 )
253 + break;
254 + goto ignore_char;
255 + }
256 + // Mask off the error conditions we want to ignore
257 + tmp = status & info->read_status_mask;
258 + if (tmp & RXPARERR)
259 + {
260 + flag_char = TTY_PARITY;
261 + }
262 + else
263 + if (tmp & RXFRAMERR)
264 + {
265 + flag_char = TTY_FRAME;
266 + }
267 + if (tmp & RXOVFERR)
268 + {
269 + tty_insert_flip_char(tty, ch, flag_char);
270 + ch = 0;
271 + flag_char = TTY_OVERRUN;
272 + if (!tty_buffer_request_room(tty, 1))
273 + break;
274 + }
275 + }
276 + tty_insert_flip_char(tty, ch, flag_char);
277 + }
278 +ignore_char:
279 + if (tty)
280 + tty_flip_buffer_push(tty);
281 +}
282 +
283 +
284 +/*
285 + * ------------------------------------------------------------
286 + * bcm_interrupt ()
287 + *
288 + * this is the main interrupt routine for the chip.
289 + * It deals with the multiple ports.
290 + * ------------------------------------------------------------
291 + */
292 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
293 +static irqreturn_t bcm_interrupt (int irq, void * dev, struct pt_regs * regs)
294 +#else
295 +static void bcm_interrupt (int irq, void * dev, struct pt_regs * regs)
296 +#endif
297 +{
298 + struct bcm_serial * info = lines[0];
299 + UINT16 intStat;
300 +
301 + /* get pending interrupt flags from UART */
302 +
303 + /* Mask with only the serial interrupts that are enabled */
304 + intStat = info->port->intStatus & info->port->intMask;
305 + while (intStat)
306 + {
307 + if (intStat & RXINT)
308 + receive_chars (info);
309 + else
310 + if (intStat & TXINT)
311 + info->port->intStatus = TXINT;
312 + else /* don't know what it was, so let's mask it */
313 + info->port->intMask &= ~intStat;
314 +
315 + intStat = info->port->intStatus & info->port->intMask;
316 + }
317 +
318 + // Clear the interrupt
319 + BcmHalInterruptEnable (INTERRUPT_ID_UART);
320 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
321 + return IRQ_HANDLED;
322 +#endif
323 +}
324 +
325 +/*
326 + * -------------------------------------------------------------------
327 + * startup ()
328 + *
329 + * various initialization tasks
330 + * -------------------------------------------------------------------
331 + */
332 +static int startup (struct bcm_serial *info)
333 +{
334 + // Port is already started...
335 + return 0;
336 +}
337 +
338 +/*
339 + * -------------------------------------------------------------------
340 + * shutdown ()
341 + *
342 + * This routine will shutdown a serial port; interrupts are disabled, and
343 + * DTR is dropped if the hangup on close termio flag is on.
344 + * -------------------------------------------------------------------
345 + */
346 +static void shutdown (struct bcm_serial * info)
347 +{
348 + unsigned long flags;
349 + if (!info->is_initialized)
350 + return;
351 +
352 + save_flags (flags);
353 + cli ();
354 +
355 + info->port->control &= ~(BRGEN|TXEN|RXEN);
356 + if (info->tty)
357 + set_bit (TTY_IO_ERROR, &info->tty->flags);
358 + info->is_initialized = 0;
359 +
360 + restore_flags (flags);
361 +}
362 +/*
363 + * -------------------------------------------------------------------
364 + * change_speed ()
365 + *
366 + * Set the baud rate, character size, parity and stop bits.
367 + * -------------------------------------------------------------------
368 + */
369 +static void change_speed( volatile Uart *pUart, tcflag_t cFlag )
370 +{
371 + unsigned long ulFlags, ulBaud, ulClockFreqHz, ulTmp;
372 + save_flags(ulFlags);
373 + cli();
374 + switch( cFlag & (CBAUD | CBAUDEX) )
375 + {
376 + case B115200:
377 + ulBaud = 115200;
378 + break;
379 + case B57600:
380 + ulBaud = 57600;
381 + break;
382 + case B38400:
383 + ulBaud = 38400;
384 + break;
385 + case B19200:
386 + ulBaud = 19200;
387 + break;
388 + case B9600:
389 + ulBaud = 9600;
390 + break;
391 + case B4800:
392 + ulBaud = 4800;
393 + break;
394 + case B2400:
395 + ulBaud = 2400;
396 + break;
397 + case B1800:
398 + ulBaud = 1800;
399 + break;
400 + case B1200:
401 + ulBaud = 1200;
402 + break;
403 + case B600:
404 + ulBaud = 600;
405 + break;
406 + case B300:
407 + ulBaud = 300;
408 + break;
409 + case B200:
410 + ulBaud = 200;
411 + break;
412 + case B150:
413 + ulBaud = 150;
414 + break;
415 + case B134:
416 + ulBaud = 134;
417 + break;
418 + case B110:
419 + ulBaud = 110;
420 + break;
421 + case B75:
422 + ulBaud = 75;
423 + break;
424 + case B50:
425 + ulBaud = 50;
426 + break;
427 + default:
428 + ulBaud = 115200;
429 + break;
430 + }
431 +
432 + /* Calculate buad rate. */
433 + ulClockFreqHz = BD_BCM63XX_TIMER_CLOCK_INPUT;
434 + ulTmp = (ulClockFreqHz / ulBaud) / 16;
435 + if( ulTmp & 0x01 )
436 + ulTmp /= 2; /* Rounding up, so sub is already accounted for */
437 + else
438 + ulTmp = (ulTmp / 2) - 1; /* Rounding down so we must sub 1 */
439 + pUart->baudword = ulTmp;
440 +
441 + /* Set character size, stop bits and parity. */
442 + switch( cFlag & CSIZE )
443 + {
444 + case CS5:
445 + ulTmp = BITS5SYM; /* select transmit 5 bit data size */
446 + break;
447 + case CS6:
448 + ulTmp = BITS6SYM; /* select transmit 6 bit data size */
449 + break;
450 + case CS7:
451 + ulTmp = BITS7SYM; /* select transmit 7 bit data size */
452 + break;
453 + /*case CS8:*/
454 + default:
455 + ulTmp = BITS8SYM; /* select transmit 8 bit data size */
456 + break;
457 + }
458 + if( cFlag & CSTOPB )
459 + ulTmp |= TWOSTOP; /* select 2 stop bits */
460 + else
461 + ulTmp |= ONESTOP; /* select one stop bit */
462 +
463 + /* Write these values into the config reg. */
464 + pUart->config = ulTmp;
465 + pUart->control &= ~(RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN);
466 + switch( cFlag & (PARENB | PARODD) )
467 + {
468 + case PARENB|PARODD:
469 + pUart->control |= RXPARITYEN | TXPARITYEN;
470 + break;
471 + case PARENB:
472 + pUart->control |= RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN;
473 + break;
474 + default:
475 + pUart->control |= 0;
476 + break;
477 + }
478 +
479 + /* Reset and flush uart */
480 + pUart->fifoctl = RSTTXFIFOS | RSTRXFIFOS;
481 + restore_flags( ulFlags );
482 +}
483 +
484 +
485 +/*
486 + * -------------------------------------------------------------------
487 + * bcm_flush_char ()
488 + *
489 + * Nothing to flush. Polled I/O is used.
490 + * -------------------------------------------------------------------
491 + */
492 +static void bcm63xx_cons_flush_chars (struct tty_struct *tty)
493 +{
494 +}
495 +
496 +
497 +/*
498 + * -------------------------------------------------------------------
499 + * bcm63xx_cons_write ()
500 + *
501 + * Main output routine using polled I/O.
502 + * -------------------------------------------------------------------
503 + */
504 +static int bcm63xx_cons_write (struct tty_struct *tty, int from_user,
505 + const unsigned char *buf, int count)
506 +{
507 + int c;
508 +
509 + for (c = 0; c < count; c++)
510 + _putc(buf[c]);
511 + return count;
512 +}
513 +
514 +/*
515 + * -------------------------------------------------------------------
516 + * bcm63xx_cons_write_room ()
517 + *
518 + * Compute the amount of space available for writing.
519 + * -------------------------------------------------------------------
520 + */
521 +static int bcm63xx_cons_write_room (struct tty_struct *tty)
522 +{
523 + /* Pick a number. Any number. Polled I/O is used. */
524 + return 1024;
525 +}
526 +
527 +/*
528 + * -------------------------------------------------------------------
529 + * bcm_chars_in_buffer ()
530 + *
531 + * compute the amount of char left to be transmitted
532 + * -------------------------------------------------------------------
533 + */
534 +static int bcm_chars_in_buffer (struct tty_struct *tty)
535 +{
536 + return 0;
537 +}
538 +
539 +/*
540 + * -------------------------------------------------------------------
541 + * bcm_flush_buffer ()
542 + *
543 + * Empty the output buffer
544 + * -------------------------------------------------------------------
545 + */
546 +static void bcm_flush_buffer (struct tty_struct *tty)
547 +{
548 +}
549 +
550 +/*
551 + * ------------------------------------------------------------
552 + * bcm_throttle () and bcm_unthrottle ()
553 + *
554 + * This routine is called by the upper-layer tty layer to signal that
555 + * incoming characters should be throttled (or not).
556 + * ------------------------------------------------------------
557 + */
558 +static void bcm_throttle (struct tty_struct *tty)
559 +{
560 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
561 + if (I_IXOFF(tty))
562 + info->x_char = STOP_CHAR(tty);
563 +}
564 +
565 +static void bcm_unthrottle (struct tty_struct *tty)
566 +{
567 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
568 + if (I_IXOFF(tty))
569 + {
570 + if (info->x_char)
571 + info->x_char = 0;
572 + else
573 + info->x_char = START_CHAR(tty);
574 + }
575 +}
576 +
577 +static void bcm_send_xchar (struct tty_struct *tty, char ch)
578 +{
579 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
580 + info->x_char = ch;
581 + if (ch)
582 + bcm_start (info->tty);
583 +}
584 +
585 +/*
586 + * ------------------------------------------------------------
587 + * rs_ioctl () and friends
588 + * ------------------------------------------------------------
589 + */
590 +static int get_serial_info(struct bcm_serial *info, struct serial_struct *retinfo)
591 +{
592 + struct serial_struct tmp;
593 +
594 + if (!retinfo)
595 + return -EFAULT;
596 +
597 + memset (&tmp, 0, sizeof(tmp));
598 + tmp.type = info->type;
599 + tmp.line = info->line;
600 + tmp.port = (int) info->port;
601 + tmp.irq = info->irq;
602 + tmp.flags = 0;
603 + tmp.baud_base = info->baud_base;
604 + tmp.close_delay = info->close_delay;
605 + tmp.closing_wait = info->closing_wait;
606 +
607 + return copy_to_user (retinfo, &tmp, sizeof(*retinfo));
608 +}
609 +
610 +static int set_serial_info (struct bcm_serial *info, struct serial_struct *new_info)
611 +{
612 + struct serial_struct new_serial;
613 + struct bcm_serial old_info;
614 + int retval = 0;
615 +
616 + if (!new_info)
617 + return -EFAULT;
618 +
619 + copy_from_user (&new_serial, new_info, sizeof(new_serial));
620 + old_info = *info;
621 +
622 + if (!capable(CAP_SYS_ADMIN))
623 + return -EPERM;
624 +
625 +
626 + if (info->count > 1)
627 + return -EBUSY;
628 +
629 + /* OK, past this point, all the error checking has been done.
630 + * At this point, we start making changes.....
631 + */
632 + info->baud_base = new_serial.baud_base;
633 + info->type = new_serial.type;
634 + info->close_delay = new_serial.close_delay;
635 + info->closing_wait = new_serial.closing_wait;
636 + retval = startup (info);
637 + return retval;
638 +}
639 +
640 +/*
641 + * get_lsr_info - get line status register info
642 + *
643 + * Purpose: Let user call ioctl() to get info when the UART physically
644 + * is emptied. On bus types like RS485, the transmitter must
645 + * release the bus after transmitting. This must be done when
646 + * the transmit shift register is empty, not be done when the
647 + * transmit holding register is empty. This functionality
648 + * allows an RS485 driver to be written in user space.
649 + */
650 +static int get_lsr_info (struct bcm_serial *info, unsigned int *value)
651 +{
652 + return( 0 );
653 +}
654 +
655 +/*
656 + * This routine sends a break character out the serial port.
657 + */
658 +static void send_break (struct bcm_serial *info, int duration)
659 +{
660 + unsigned long flags;
661 +
662 + if (!info->port)
663 + return;
664 +
665 + current->state = TASK_INTERRUPTIBLE;
666 +
667 + save_flags (flags);
668 + cli();
669 +
670 + info->port->control |= XMITBREAK;
671 + schedule_timeout(duration);
672 + info->port->control &= ~XMITBREAK;
673 +
674 + restore_flags (flags);
675 +}
676 +
677 +static int bcm_ioctl (struct tty_struct * tty, struct file * file,
678 + unsigned int cmd, unsigned long arg)
679 +{
680 + int error;
681 + struct bcm_serial * info = (struct bcm_serial *)tty->driver_data;
682 + int retval;
683 +
684 + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
685 + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
686 + (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT))
687 + {
688 + if (tty->flags & (1 << TTY_IO_ERROR))
689 + return -EIO;
690 + }
691 + switch (cmd)
692 + {
693 +
694 + case TCSBRK: /* SVID version: non-zero arg --> no break */
695 + retval = tty_check_change (tty);
696 + if (retval)
697 + return retval;
698 + tty_wait_until_sent (tty, 0);
699 + if (!arg)
700 + send_break (info, HZ/4); /* 1/4 second */
701 + return 0;
702 +
703 + case TCSBRKP: /* support for POSIX tcsendbreak() */
704 + retval = tty_check_change (tty);
705 + if (retval)
706 + return retval;
707 + tty_wait_until_sent (tty, 0);
708 + send_break (info, arg ? arg*(HZ/10) : HZ/4);
709 + return 0;
710 +
711 + case TIOCGSOFTCAR:
712 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(long));
713 + if (!error)
714 + return -EFAULT;
715 + else
716 + {
717 + put_user (C_CLOCAL(tty) ? 1 : 0, (unsigned long *)arg);
718 + return 0;
719 + }
720 +
721 + case TIOCSSOFTCAR:
722 + error = get_user (arg, (unsigned long *)arg);
723 + if (error)
724 + return error;
725 + tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
726 + return 0;
727 +
728 + case TIOCGSERIAL:
729 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(struct serial_struct));
730 + if (!error)
731 + return -EFAULT;
732 + else
733 + return get_serial_info (info, (struct serial_struct *)arg);
734 +
735 + case TIOCSSERIAL:
736 + return set_serial_info (info, (struct serial_struct *) arg);
737 +
738 + case TIOCSERGETLSR: /* Get line status register */
739 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(unsigned int));
740 + if (!error)
741 + return -EFAULT;
742 + else
743 + return get_lsr_info (info, (unsigned int *)arg);
744 +
745 + case TIOCSERGSTRUCT:
746 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(struct bcm_serial));
747 + if (!error)
748 + return -EFAULT;
749 + else
750 + {
751 + copy_to_user((struct bcm_serial *)arg, info, sizeof(struct bcm_serial));
752 + return 0;
753 + }
754 +
755 + default:
756 + return -ENOIOCTLCMD;
757 + }
758 + return 0;
759 +}
760 +
761 +static void bcm_set_termios (struct tty_struct *tty, struct termios *old_termios)
762 +{
763 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
764 +
765 + if( tty->termios->c_cflag != old_termios->c_cflag )
766 + change_speed (info->port, tty->termios->c_cflag);
767 +}
768 +
769 +/*
770 + * ------------------------------------------------------------
771 + * bcm63xx_cons_close()
772 + *
773 + * This routine is called when the serial port gets closed. First, we
774 + * wait for the last remaining data to be sent. Then, we turn off
775 + * the transmit enable and receive enable flags.
776 + * ------------------------------------------------------------
777 + */
778 +static void bcm63xx_cons_close (struct tty_struct *tty, struct file *filp)
779 +{
780 + struct bcm_serial * info = (struct bcm_serial *)tty->driver_data;
781 + unsigned long flags;
782 +
783 + if (!info)
784 + return;
785 +
786 + save_flags (flags);
787 + cli();
788 +
789 + if (tty_hung_up_p (filp))
790 + {
791 + restore_flags (flags);
792 + return;
793 + }
794 +
795 + if ((tty->count == 1) && (info->count != 1))
796 + {
797 +
798 + /* Uh, oh. tty->count is 1, which means that the tty
799 + * structure will be freed. Info->count should always
800 + * be one in these conditions. If it's greater than
801 + * one, we've got real problems, since it means the
802 + * serial port won't be shutdown.
803 + */
804 + printk("bcm63xx_cons_close: bad serial port count; tty->count is 1, "
805 + "info->count is %d\n", info->count);
806 + info->count = 1;
807 + }
808 +
809 + if (--info->count < 0)
810 + {
811 + printk("ds_close: bad serial port count for ttys%d: %d\n",
812 + info->line, info->count);
813 + info->count = 0;
814 + }
815 +
816 + if (info->count)
817 + {
818 + restore_flags (flags);
819 + return;
820 + }
821 +
822 + /* Now we wait for the transmit buffer to clear; and we notify
823 + * the line discipline to only process XON/XOFF characters.
824 + */
825 + tty->closing = 1;
826 +
827 + /* At this point we stop accepting input. To do this, we
828 + * disable the receive line status interrupts.
829 + */
830 + shutdown (info);
831 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
832 + if (tty->driver->flush_buffer)
833 + tty->driver->flush_buffer (tty);
834 +#else
835 + if (tty->driver.flush_buffer)
836 + tty->driver.flush_buffer (tty);
837 +#endif
838 + if (tty->ldisc.flush_buffer)
839 + tty->ldisc.flush_buffer (tty);
840 +
841 + tty->closing = 0;
842 + info->event = 0;
843 + info->tty = 0;
844 + if (tty->ldisc.num != tty_ldisc_get(N_TTY)->num)
845 + {
846 + if (tty->ldisc.close)
847 + (tty->ldisc.close)(tty);
848 + tty->ldisc = *tty_ldisc_get(N_TTY);
849 + tty->termios->c_line = N_TTY;
850 + if (tty->ldisc.open)
851 + (tty->ldisc.open)(tty);
852 + }
853 + if (info->blocked_open)
854 + {
855 + if (info->close_delay)
856 + {
857 + current->state = TASK_INTERRUPTIBLE;
858 + schedule_timeout(info->close_delay);
859 + }
860 + wake_up_interruptible (&info->open_wait);
861 + }
862 + wake_up_interruptible (&info->close_wait);
863 +
864 + restore_flags (flags);
865 +}
866 +
867 +/*
868 + * bcm_hangup () --- called by tty_hangup() when a hangup is signaled.
869 + */
870 +static void bcm_hangup (struct tty_struct *tty)
871 +{
872 +
873 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
874 +
875 + shutdown (info);
876 + info->event = 0;
877 + info->count = 0;
878 + info->tty = 0;
879 + wake_up_interruptible (&info->open_wait);
880 +}
881 +
882 +/*
883 + * ------------------------------------------------------------
884 + * rs_open() and friends
885 + * ------------------------------------------------------------
886 + */
887 +static int block_til_ready (struct tty_struct *tty, struct file *filp,
888 + struct bcm_serial *info)
889 +{
890 + return 0;
891 +}
892 +
893 +/*
894 + * This routine is called whenever a serial port is opened. It
895 + * enables interrupts for a serial port. It also performs the
896 + * serial-specific initialization for the tty structure.
897 + */
898 +static int bcm63xx_cons_open (struct tty_struct * tty, struct file * filp)
899 +{
900 + struct bcm_serial *info;
901 + int retval, line;
902 +
903 + // Make sure we're only opening on of the ports we support
904 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
905 + line = MINOR(tty->driver->cdev.dev) - tty->driver->minor_start;
906 +#else
907 + line = MINOR(tty->device) - tty->driver.minor_start;
908 +#endif
909 +
910 + if ((line < 0) || (line >= BCM_NUM_UARTS))
911 + return -ENODEV;
912 +
913 + info = lines[line];
914 +
915 + info->port->intMask = 0; /* Clear any pending interrupts */
916 + info->port->intMask = RXINT; /* Enable RX */
917 +
918 + info->count++;
919 + tty->driver_data = info;
920 + info->tty = tty;
921 + BcmHalInterruptEnable (INTERRUPT_ID_UART);
922 +
923 + // Start up serial port
924 + retval = startup (info);
925 + if (retval)
926 + return retval;
927 +
928 + retval = block_til_ready (tty, filp, info);
929 + if (retval)
930 + return retval;
931 +
932 +
933 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
934 + info->pgrp = process_group(current);
935 + info->session = current->signal->session;
936 +#else
937 + info->session = current->session;
938 + info->pgrp = current->pgrp;
939 +#endif
940 +
941 + return 0;
942 +}
943 +
944 +/* --------------------------------------------------------------------------
945 + Name: bcm63xx_serialinit
946 + Purpose: Initialize our BCM63xx serial driver
947 +-------------------------------------------------------------------------- */
948 +static int __init bcm63xx_serialinit(void)
949 +{
950 + int i, flags;
951 + struct bcm_serial * info;
952 +
953 + // Print the driver version information
954 + printk(VER_STR);
955 +
956 + memset(&serial_driver, 0, sizeof(struct tty_driver));
957 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
958 + serial_driver.owner = THIS_MODULE;
959 + serial_driver.devfs_name = "tts/";
960 +#endif
961 + serial_driver.magic = TTY_DRIVER_MAGIC;
962 + serial_driver.name = "ttyS";
963 + serial_driver.major = TTY_MAJOR;
964 + serial_driver.minor_start = 64;
965 + serial_driver.num = BCM_NUM_UARTS;
966 + serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
967 + serial_driver.subtype = SERIAL_TYPE_NORMAL;
968 + serial_driver.init_termios = tty_std_termios;
969 + serial_driver.init_termios.c_cflag = B115200 | CS8 | CREAD | CLOCAL;
970 + serial_driver.flags = TTY_DRIVER_REAL_RAW;
971 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
972 + serial_driver.refcount = serial_refcount;
973 + serial_driver.ttys = serial_table;
974 +#else
975 + serial_driver.refcount = &serial_refcount;
976 + serial_driver.table = serial_table;
977 +#endif
978 +
979 + serial_driver.termios = serial_termios;
980 + serial_driver.termios_locked = serial_termios_locked;
981 + serial_driver.open = bcm63xx_cons_open;
982 + serial_driver.close = bcm63xx_cons_close;
983 + serial_driver.write = bcm63xx_cons_write;
984 + serial_driver.flush_chars = bcm63xx_cons_flush_chars;
985 + serial_driver.write_room = bcm63xx_cons_write_room;
986 + serial_driver.chars_in_buffer = bcm_chars_in_buffer;
987 + serial_driver.flush_buffer = bcm_flush_buffer;
988 + serial_driver.ioctl = bcm_ioctl;
989 + serial_driver.throttle = bcm_throttle;
990 + serial_driver.unthrottle = bcm_unthrottle;
991 + serial_driver.send_xchar = bcm_send_xchar;
992 + serial_driver.set_termios = bcm_set_termios;
993 + serial_driver.stop = bcm_stop;
994 + serial_driver.start = bcm_start;
995 + serial_driver.hangup = bcm_hangup;
996 +
997 + if (tty_register_driver (&serial_driver))
998 + panic("Couldn't register serial driver\n");
999 +
1000 + save_flags(flags); cli();
1001 + for (i = 0; i < BCM_NUM_UARTS; i++)
1002 + {
1003 + info = &multi[i];
1004 + lines[i] = info;
1005 + info->port = (Uart *) ((char *)UART_BASE + (i * 0x20));
1006 + info->irq = (2 - i) + 8;
1007 + info->line = i;
1008 + info->tty = 0;
1009 + info->close_delay = 50;
1010 + info->closing_wait = 3000;
1011 + info->x_char = 0;
1012 + info->event = 0;
1013 + info->count = 0;
1014 + info->blocked_open = 0;
1015 + info->normal_termios = serial_driver.init_termios;
1016 + init_waitqueue_head(&info->open_wait);
1017 + init_waitqueue_head(&info->close_wait);
1018 +
1019 + /* If we are pointing to address zero then punt - not correctly
1020 + * set up in setup.c to handle this.
1021 + */
1022 + if (! info->port)
1023 + return 0;
1024 + BcmHalMapInterrupt(bcm_interrupt, 0, INTERRUPT_ID_UART);
1025 + }
1026 +
1027 + /* order matters here... the trick is that flags
1028 + * is updated... in request_irq - to immediatedly obliterate
1029 + * it is unwise.
1030 + */
1031 + restore_flags(flags);
1032 + return 0;
1033 +}
1034 +
1035 +module_init(bcm63xx_serialinit);
1036 +
1037 +/* --------------------------------------------------------------------------
1038 + Name: bcm_console_print
1039 + Purpose: bcm_console_print is registered for printk.
1040 + The console_lock must be held when we get here.
1041 +-------------------------------------------------------------------------- */
1042 +static void bcm_console_print (struct console * cons, const char * str,
1043 + unsigned int count)
1044 +{
1045 + unsigned int i;
1046 + //_puts(str);
1047 + for(i=0; i<count; i++, str++)
1048 + {
1049 + _putc(*str);
1050 + if (*str == 10)
1051 + {
1052 + _putc(13);
1053 + }
1054 + }
1055 +}
1056 +
1057 +static struct tty_driver * bcm_console_device(struct console * c, int *index)
1058 +{
1059 + *index = c->index;
1060 + return &serial_driver;
1061 +}
1062 +
1063 +static int __init bcm_console_setup(struct console * co, char * options)
1064 +{
1065 + return 0;
1066 +}
1067 +
1068 +static struct console bcm_sercons = {
1069 + .name = "ttyS",
1070 + .write = bcm_console_print,
1071 + .device = bcm_console_device,
1072 + .setup = bcm_console_setup,
1073 + .flags = CON_PRINTBUFFER, // CON_CONSDEV, CONSOLE_LINE,
1074 + .index = -1,
1075 +};
1076 +
1077 +static int __init bcm63xx_console_init(void)
1078 +{
1079 + register_console(&bcm_sercons);
1080 + return 0;
1081 +}
1082 +
1083 +console_initcall(bcm63xx_console_init);
1084 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6338_intr.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6338_intr.h
1085 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6338_intr.h 1970-01-01 01:00:00.000000000 +0100
1086 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6338_intr.h 2006-07-05 15:21:58.000000000 +0200
1087 @@ -0,0 +1,72 @@
1088 +/*
1089 +<:copyright-gpl
1090 + Copyright 2003 Broadcom Corp. All Rights Reserved.
1091 +
1092 + This program is free software; you can distribute it and/or modify it
1093 + under the terms of the GNU General Public License (Version 2) as
1094 + published by the Free Software Foundation.
1095 +
1096 + This program is distributed in the hope it will be useful, but WITHOUT
1097 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1098 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1099 + for more details.
1100 +
1101 + You should have received a copy of the GNU General Public License along
1102 + with this program; if not, write to the Free Software Foundation, Inc.,
1103 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1104 +:>
1105 +*/
1106 +
1107 +#ifndef __6338_INTR_H
1108 +#define __6338_INTR_H
1109 +
1110 +#ifdef __cplusplus
1111 + extern "C" {
1112 +#endif
1113 +
1114 +/*=====================================================================*/
1115 +/* BCM6338 External Interrupt Level Assignments */
1116 +/*=====================================================================*/
1117 +#define INTERRUPT_ID_EXTERNAL_0 3
1118 +#define INTERRUPT_ID_EXTERNAL_1 4
1119 +#define INTERRUPT_ID_EXTERNAL_2 5
1120 +#define INTERRUPT_ID_EXTERNAL_3 6
1121 +
1122 +/*=====================================================================*/
1123 +/* BCM6338 Timer Interrupt Level Assignments */
1124 +/*=====================================================================*/
1125 +#define MIPS_TIMER_INT 7
1126 +
1127 +/*=====================================================================*/
1128 +/* Peripheral ISR Table Offset */
1129 +/*=====================================================================*/
1130 +#define INTERNAL_ISR_TABLE_OFFSET 8
1131 +
1132 +/*=====================================================================*/
1133 +/* Logical Peripheral Interrupt IDs */
1134 +/*=====================================================================*/
1135 +
1136 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1137 +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
1138 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1139 +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 4)
1140 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 5)
1141 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 6)
1142 +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 7)
1143 +#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
1144 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
1145 +#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 10)
1146 +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 11)
1147 +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 12)
1148 +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 13)
1149 +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
1150 +#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
1151 +#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
1152 +#define INTERRUPT_ID_SDIO (INTERNAL_ISR_TABLE_OFFSET + 17)
1153 +
1154 +#ifdef __cplusplus
1155 + }
1156 +#endif
1157 +
1158 +#endif /* __BCM6338_H */
1159 +
1160 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h
1161 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h 1970-01-01 01:00:00.000000000 +0100
1162 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h 2006-07-05 15:21:58.000000000 +0200
1163 @@ -0,0 +1,341 @@
1164 +/*
1165 +<:copyright-gpl
1166 + Copyright 2004 Broadcom Corp. All Rights Reserved.
1167 +
1168 + This program is free software; you can distribute it and/or modify it
1169 + under the terms of the GNU General Public License (Version 2) as
1170 + published by the Free Software Foundation.
1171 +
1172 + This program is distributed in the hope it will be useful, but WITHOUT
1173 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1174 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1175 + for more details.
1176 +
1177 + You should have received a copy of the GNU General Public License along
1178 + with this program; if not, write to the Free Software Foundation, Inc.,
1179 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1180 +:>
1181 +*/
1182 +
1183 +#ifndef __BCM6338_MAP_H
1184 +#define __BCM6338_MAP_H
1185 +
1186 +#if __cplusplus
1187 +extern "C" {
1188 +#endif
1189 +
1190 +#include "bcmtypes.h"
1191 +
1192 +#define PERF_BASE 0xfffe0000
1193 +#define TIMR_BASE 0xfffe0200
1194 +#define UART_BASE 0xfffe0300
1195 +#define GPIO_BASE 0xfffe0400
1196 +#define SPI_BASE 0xfffe0c00
1197 +
1198 +typedef struct PerfControl {
1199 + uint32 RevID;
1200 + uint16 testControl;
1201 + uint16 blkEnables;
1202 +#define EMAC_CLK_EN 0x0010
1203 +#define USBS_CLK_EN 0x0010
1204 +#define SAR_CLK_EN 0x0020
1205 +
1206 +#define SPI_CLK_EN 0x0200
1207 +
1208 + uint32 pll_control;
1209 +#define SOFT_RESET 0x00000001
1210 +
1211 + uint32 IrqMask;
1212 + uint32 IrqStatus;
1213 +
1214 + uint32 ExtIrqCfg;
1215 +#define EI_SENSE_SHFT 0
1216 +#define EI_STATUS_SHFT 5
1217 +#define EI_CLEAR_SHFT 10
1218 +#define EI_MASK_SHFT 15
1219 +#define EI_INSENS_SHFT 20
1220 +#define EI_LEVEL_SHFT 25
1221 +
1222 + uint32 unused[4]; /* (18) */
1223 + uint32 BlockSoftReset; /* (28) */
1224 +#define BSR_SPI 0x00000001
1225 +#define BSR_EMAC 0x00000004
1226 +#define BSR_USBH 0x00000008
1227 +#define BSR_USBS 0x00000010
1228 +#define BSR_ADSL 0x00000020
1229 +#define BSR_DMAMEM 0x00000040
1230 +#define BSR_SAR 0x00000080
1231 +#define BSR_ACLC 0x00000100
1232 +#define BSR_ADSL_MIPS_PLL 0x00000400
1233 +#define BSR_ALL_BLOCKS \
1234 + (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
1235 + BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
1236 +} PerfControl;
1237 +
1238 +#define PERF ((volatile PerfControl * const) PERF_BASE)
1239 +
1240 +
1241 +typedef struct Timer {
1242 + uint16 unused0;
1243 + byte TimerMask;
1244 +#define TIMER0EN 0x01
1245 +#define TIMER1EN 0x02
1246 +#define TIMER2EN 0x04
1247 + byte TimerInts;
1248 +#define TIMER0 0x01
1249 +#define TIMER1 0x02
1250 +#define TIMER2 0x04
1251 +#define WATCHDOG 0x08
1252 + uint32 TimerCtl0;
1253 + uint32 TimerCtl1;
1254 + uint32 TimerCtl2;
1255 +#define TIMERENABLE 0x80000000
1256 +#define RSTCNTCLR 0x40000000
1257 + uint32 TimerCnt0;
1258 + uint32 TimerCnt1;
1259 + uint32 TimerCnt2;
1260 + uint32 WatchDogDefCount;
1261 +
1262 + /* Write 0xff00 0x00ff to Start timer
1263 + * Write 0xee00 0x00ee to Stop and re-load default count
1264 + * Read from this register returns current watch dog count
1265 + */
1266 + uint32 WatchDogCtl;
1267 +
1268 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1269 + uint32 WDResetCount;
1270 +} Timer;
1271 +
1272 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1273 +typedef struct UartChannel {
1274 + byte unused0;
1275 + byte control;
1276 +#define BRGEN 0x80 /* Control register bit defs */
1277 +#define TXEN 0x40
1278 +#define RXEN 0x20
1279 +#define LOOPBK 0x10
1280 +#define TXPARITYEN 0x08
1281 +#define TXPARITYEVEN 0x04
1282 +#define RXPARITYEN 0x02
1283 +#define RXPARITYEVEN 0x01
1284 +
1285 + byte config;
1286 +#define XMITBREAK 0x40
1287 +#define BITS5SYM 0x00
1288 +#define BITS6SYM 0x10
1289 +#define BITS7SYM 0x20
1290 +#define BITS8SYM 0x30
1291 +#define ONESTOP 0x07
1292 +#define TWOSTOP 0x0f
1293 + /* 4-LSBS represent STOP bits/char
1294 + * in 1/8 bit-time intervals. Zero
1295 + * represents 1/8 stop bit interval.
1296 + * Fifteen represents 2 stop bits.
1297 + */
1298 + byte fifoctl;
1299 +#define RSTTXFIFOS 0x80
1300 +#define RSTRXFIFOS 0x40
1301 + /* 5-bit TimeoutCnt is in low bits of this register.
1302 + * This count represents the number of characters
1303 + * idle times before setting receive Irq when below threshold
1304 + */
1305 + uint32 baudword;
1306 + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
1307 + */
1308 +
1309 + byte txf_levl; /* Read-only fifo depth */
1310 + byte rxf_levl; /* Read-only fifo depth */
1311 + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
1312 + * RxThreshold. Irq can be asserted
1313 + * when rx fifo> thresh, txfifo<thresh
1314 + */
1315 + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
1316 + * if these bits are also enabled to GPIO_o
1317 + */
1318 +#define DTREN 0x01
1319 +#define RTSEN 0x02
1320 +
1321 + byte unused1;
1322 + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
1323 + * detect irq on rising AND falling
1324 + * edges for corresponding GPIO_i
1325 + * if enabled (edge insensitive)
1326 + */
1327 + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
1328 + * 0 for negedge sense if
1329 + * not configured for edge
1330 + * insensitive (see above)
1331 + * Lower 4 bits: Mask to enable change
1332 + * detection IRQ for corresponding
1333 + * GPIO_i
1334 + */
1335 + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
1336 + * have changed (may set IRQ).
1337 + * read automatically clears bit
1338 + * Lower 4 bits are actual status
1339 + */
1340 +
1341 + uint16 intMask; /* Same Bit defs for Mask and status */
1342 + uint16 intStatus;
1343 +#define DELTAIP 0x0001
1344 +#define TXUNDERR 0x0002
1345 +#define TXOVFERR 0x0004
1346 +#define TXFIFOTHOLD 0x0008
1347 +#define TXREADLATCH 0x0010
1348 +#define TXFIFOEMT 0x0020
1349 +#define RXUNDERR 0x0040
1350 +#define RXOVFERR 0x0080
1351 +#define RXTIMEOUT 0x0100
1352 +#define RXFIFOFULL 0x0200
1353 +#define RXFIFOTHOLD 0x0400
1354 +#define RXFIFONE 0x0800
1355 +#define RXFRAMERR 0x1000
1356 +#define RXPARERR 0x2000
1357 +#define RXBRK 0x4000
1358 +
1359 + uint16 unused2;
1360 + uint16 Data; /* Write to TX, Read from RX */
1361 + /* bits 11:8 are BRK,PAR,FRM errors */
1362 +
1363 + uint32 unused3;
1364 + uint32 unused4;
1365 +} Uart;
1366 +
1367 +#define UART ((volatile Uart * const) UART_BASE)
1368 +
1369 +typedef struct GpioControl {
1370 + uint32 unused0;
1371 + uint32 GPIODir; /* bits 7:0 */
1372 + uint32 unused1;
1373 + uint32 GPIOio; /* bits 7:0 */
1374 + uint32 LEDCtrl;
1375 +#define LED3_STROBE 0x08000000
1376 +#define LED2_STROBE 0x04000000
1377 +#define LED1_STROBE 0x02000000
1378 +#define LED0_STROBE 0x01000000
1379 +#define LED_TEST 0x00010000
1380 +#define LED3_DISABLE_LINK_ACT 0x00008000
1381 +#define LED2_DISABLE_LINK_ACT 0x00004000
1382 +#define LED1_DISABLE_LINK_ACT 0x00002000
1383 +#define LED0_DISABLE_LINK_ACT 0x00001000
1384 +#define LED_INTERVAL_SET_MASK 0x00000f00
1385 +#define LED_INTERVAL_SET_320MS 0x00000500
1386 +#define LED_INTERVAL_SET_160MS 0x00000400
1387 +#define LED_INTERVAL_SET_80MS 0x00000300
1388 +#define LED_INTERVAL_SET_40MS 0x00000200
1389 +#define LED_INTERVAL_SET_20MS 0x00000100
1390 +#define LED3_ON 0x00000080
1391 +#define LED2_ON 0x00000040
1392 +#define LED1_ON 0x00000020
1393 +#define LED0_ON 0x00000010
1394 +#define LED3_ENABLE 0x00000008
1395 +#define LED2_ENABLE 0x00000004
1396 +#define LED1_ENABLE 0x00000002
1397 +#define LED0_ENABLE 0x00000001
1398 + uint32 SpiSlaveCfg;
1399 +#define SPI_SLAVE_RESET 0x00010000
1400 +#define SPI_RESTRICT 0x00000400
1401 +#define SPI_DELAY_DISABLE 0x00000200
1402 +#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
1403 +#define SPI_SER_ADDR_CFG_MASK 0x0000000c
1404 +#define SPI_MODE 0x00000001
1405 + uint32 vRegConfig;
1406 +} GpioControl;
1407 +
1408 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
1409 +
1410 +/* Number to mask conversion macro used for GPIODir and GPIOio */
1411 +#define GPIO_NUM_MAX_BITS_MASK 0x0f
1412 +#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
1413 +
1414 +/*
1415 +** Spi Controller
1416 +*/
1417 +
1418 +typedef struct SpiControl {
1419 + uint16 spiCmd; /* (0x0): SPI command */
1420 +#define SPI_CMD_START_IMMEDIATE 3
1421 +
1422 +#define SPI_CMD_COMMAND_SHIFT 0
1423 +#define SPI_CMD_DEVICE_ID_SHIFT 4
1424 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1425 +
1426 + byte spiIntStatus; /* (0x2): SPI interrupt status */
1427 + byte spiMaskIntStatus; /* (0x3): SPI masked interrupt status */
1428 +
1429 + byte spiIntMask; /* (0x4): SPI interrupt mask */
1430 +#define SPI_INTR_CMD_DONE 0x01
1431 +#define SPI_INTR_CLEAR_ALL 0x1f
1432 +
1433 + byte spiStatus; /* (0x5): SPI status */
1434 +
1435 + byte spiClkCfg; /* (0x6): SPI clock configuration */
1436 +
1437 + byte spiFillByte; /* (0x7): SPI fill byte */
1438 +
1439 + byte unused0;
1440 + byte spiMsgTail; /* (0x9): msgtail */
1441 + byte unused1;
1442 + byte spiRxTail; /* (0xB): rxtail */
1443 +
1444 + uint32 unused2[13]; /* (0x0c - 0x3c) reserved */
1445 +
1446 + byte spiMsgCtl; /* (0x40) control byte */
1447 +#define HALF_DUPLEX_W 1
1448 +#define HALF_DUPLEX_R 2
1449 +#define SPI_MSG_TYPE_SHIFT 6
1450 +#define SPI_BYTE_CNT_SHIFT 0
1451 + byte spiMsgData[63]; /* (0x41 - 0x7f) msg data */
1452 + byte spiRxDataFifo[64]; /* (0x80 - 0xbf) rx data */
1453 + byte unused3[64]; /* (0xc0 - 0xff) reserved */
1454 +} SpiControl;
1455 +
1456 +#define SPI ((volatile SpiControl * const) SPI_BASE)
1457 +
1458 +/*
1459 +** External Bus Interface
1460 +*/
1461 +typedef struct EbiChipSelect {
1462 + uint32 base; /* base address in upper 24 bits */
1463 +#define EBI_SIZE_8K 0
1464 +#define EBI_SIZE_16K 1
1465 +#define EBI_SIZE_32K 2
1466 +#define EBI_SIZE_64K 3
1467 +#define EBI_SIZE_128K 4
1468 +#define EBI_SIZE_256K 5
1469 +#define EBI_SIZE_512K 6
1470 +#define EBI_SIZE_1M 7
1471 +#define EBI_SIZE_2M 8
1472 +#define EBI_SIZE_4M 9
1473 +#define EBI_SIZE_8M 10
1474 +#define EBI_SIZE_16M 11
1475 +#define EBI_SIZE_32M 12
1476 +#define EBI_SIZE_64M 13
1477 +#define EBI_SIZE_128M 14
1478 +#define EBI_SIZE_256M 15
1479 + uint32 config;
1480 +#define EBI_ENABLE 0x00000001 /* .. enable this range */
1481 +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
1482 +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
1483 +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
1484 +#define EBI_WREN 0x00000020 /* enable posted writes */
1485 +#define EBI_POLARITY 0x00000040 /* .. set to invert something,
1486 + ** don't know what yet */
1487 +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
1488 +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
1489 +#define EBI_FIFO 0x00000200 /* .. use fifo */
1490 +#define EBI_RE 0x00000400 /* .. Reverse Endian */
1491 +} EbiChipSelect;
1492 +
1493 +typedef struct MpiRegisters {
1494 + EbiChipSelect cs[1]; /* size chip select configuration */
1495 +} MpiRegisters;
1496 +
1497 +#define MPI ((volatile MpiRegisters * const) MPI_BASE)
1498 +
1499 +#if __cplusplus
1500 +}
1501 +#endif
1502 +
1503 +#endif
1504 +
1505 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6345_intr.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6345_intr.h
1506 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6345_intr.h 1970-01-01 01:00:00.000000000 +0100
1507 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6345_intr.h 2006-07-05 15:21:58.000000000 +0200
1508 @@ -0,0 +1,78 @@
1509 +/*
1510 +<:copyright-gpl
1511 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1512 +
1513 + This program is free software; you can distribute it and/or modify it
1514 + under the terms of the GNU General Public License (Version 2) as
1515 + published by the Free Software Foundation.
1516 +
1517 + This program is distributed in the hope it will be useful, but WITHOUT
1518 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1519 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1520 + for more details.
1521 +
1522 + You should have received a copy of the GNU General Public License along
1523 + with this program; if not, write to the Free Software Foundation, Inc.,
1524 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1525 +:>
1526 +*/
1527 +
1528 +#ifndef __6345_INTR_H
1529 +#define __6345_INTR_H
1530 +
1531 +#ifdef __cplusplus
1532 + extern "C" {
1533 +#endif
1534 +
1535 +/*=====================================================================*/
1536 +/* BCM6345 External Interrupt Level Assignments */
1537 +/*=====================================================================*/
1538 +#define INTERRUPT_ID_EXTERNAL_0 3
1539 +#define INTERRUPT_ID_EXTERNAL_1 4
1540 +#define INTERRUPT_ID_EXTERNAL_2 5
1541 +#define INTERRUPT_ID_EXTERNAL_3 6
1542 +
1543 +/*=====================================================================*/
1544 +/* BCM6345 Timer Interrupt Level Assignments */
1545 +/*=====================================================================*/
1546 +#define MIPS_TIMER_INT 7
1547 +
1548 +/*=====================================================================*/
1549 +/* Peripheral ISR Table Offset */
1550 +/*=====================================================================*/
1551 +#define INTERNAL_ISR_TABLE_OFFSET 8
1552 +#define DMA_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 13)
1553 +
1554 +/*=====================================================================*/
1555 +/* Logical Peripheral Interrupt IDs */
1556 +/*=====================================================================*/
1557 +
1558 +/* Internal peripheral interrupt IDs */
1559 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1560 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1561 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 3)
1562 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 4)
1563 +#define INTERRUPT_ID_USB (INTERNAL_ISR_TABLE_OFFSET + 5)
1564 +#define INTERRUPT_ID_EMAC (INTERNAL_ISR_TABLE_OFFSET + 8)
1565 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12)
1566 +
1567 +/* DMA channel interrupt IDs */
1568 +#define INTERRUPT_ID_EMAC_RX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_RX_CHAN)
1569 +#define INTERRUPT_ID_EMAC_TX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_TX_CHAN)
1570 +#define INTERRUPT_ID_EBI_RX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_RX_CHAN)
1571 +#define INTERRUPT_ID_EBI_TX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_TX_CHAN)
1572 +#define INTERRUPT_ID_RESERVED_RX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_RX_CHAN)
1573 +#define INTERRUPT_ID_RESERVED_TX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_TX_CHAN)
1574 +#define INTERRUPT_ID_USB_BULK_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_RX_CHAN)
1575 +#define INTERRUPT_ID_USB_BULK_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_TX_CHAN)
1576 +#define INTERRUPT_ID_USB_CNTL_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_RX_CHAN)
1577 +#define INTERRUPT_ID_USB_CNTL_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_TX_CHAN)
1578 +#define INTERRUPT_ID_USB_ISO_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_RX_CHAN)
1579 +#define INTERRUPT_ID_USB_ISO_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_TX_CHAN)
1580 +
1581 +#ifdef __cplusplus
1582 + }
1583 +#endif
1584 +
1585 +#endif /* __BCM6345_H */
1586 +
1587 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h
1588 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h 1970-01-01 01:00:00.000000000 +0100
1589 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h 2006-07-05 15:21:58.000000000 +0200
1590 @@ -0,0 +1,169 @@
1591 +/*
1592 +<:copyright-gpl
1593 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1594 +
1595 + This program is free software; you can distribute it and/or modify it
1596 + under the terms of the GNU General Public License (Version 2) as
1597 + published by the Free Software Foundation.
1598 +
1599 + This program is distributed in the hope it will be useful, but WITHOUT
1600 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1601 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1602 + for more details.
1603 +
1604 + You should have received a copy of the GNU General Public License along
1605 + with this program; if not, write to the Free Software Foundation, Inc.,
1606 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1607 +:>
1608 +*/
1609 +
1610 +#ifndef __BCM6345_MAP_H
1611 +#define __BCM6345_MAP_H
1612 +
1613 +#if __cplusplus
1614 +extern "C" {
1615 +#endif
1616 +
1617 +#include "bcmtypes.h"
1618 +#include "6345_intr.h"
1619 +
1620 +typedef struct IntControl {
1621 + uint32 RevID;
1622 + uint16 testControl;
1623 + uint16 blkEnables;
1624 +#define USB_CLK_EN 0x0100
1625 +#define EMAC_CLK_EN 0x0080
1626 +#define UART_CLK_EN 0x0008
1627 +#define CPU_CLK_EN 0x0001
1628 +
1629 + uint32 pll_control;
1630 +#define SOFT_RESET 0x00000001
1631 +
1632 + uint32 IrqMask;
1633 + uint32 IrqStatus;
1634 +
1635 + uint32 ExtIrqCfg;
1636 +#define EI_SENSE_SHFT 0
1637 +#define EI_STATUS_SHFT 4
1638 +#define EI_CLEAR_SHFT 8
1639 +#define EI_MASK_SHFT 12
1640 +#define EI_INSENS_SHFT 16
1641 +#define EI_LEVEL_SHFT 20
1642 +} IntControl;
1643 +
1644 +#define INTC_BASE 0xfffe0000
1645 +#define PERF ((volatile IntControl * const) INTC_BASE)
1646 +
1647 +#define TIMR_BASE 0xfffe0200
1648 +typedef struct Timer {
1649 + uint16 unused0;
1650 + byte TimerMask;
1651 +#define TIMER0EN 0x01
1652 +#define TIMER1EN 0x02
1653 +#define TIMER2EN 0x04
1654 + byte TimerInts;
1655 +#define TIMER0 0x01
1656 +#define TIMER1 0x02
1657 +#define TIMER2 0x04
1658 +#define WATCHDOG 0x08
1659 + uint32 TimerCtl0;
1660 + uint32 TimerCtl1;
1661 + uint32 TimerCtl2;
1662 +#define TIMERENABLE 0x80000000
1663 +#define RSTCNTCLR 0x40000000
1664 + uint32 TimerCnt0;
1665 + uint32 TimerCnt1;
1666 + uint32 TimerCnt2;
1667 + uint32 WatchDogDefCount;
1668 +
1669 + /* Write 0xff00 0x00ff to Start timer
1670 + * Write 0xee00 0x00ee to Stop and re-load default count
1671 + * Read from this register returns current watch dog count
1672 + */
1673 + uint32 WatchDogCtl;
1674 +
1675 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1676 + uint32 WDResetCount;
1677 +} Timer;
1678 +
1679 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1680 +
1681 +typedef struct UartChannel {
1682 + byte unused0;
1683 + byte control;
1684 +#define BRGEN 0x80 /* Control register bit defs */
1685 +#define TXEN 0x40
1686 +#define RXEN 0x20
1687 +#define TXPARITYEN 0x08
1688 +#define TXPARITYEVEN 0x04
1689 +#define RXPARITYEN 0x02
1690 +#define RXPARITYEVEN 0x01
1691 + byte config;
1692 +#define BITS5SYM 0x00
1693 +#define BITS6SYM 0x10
1694 +#define BITS7SYM 0x20
1695 +#define BITS8SYM 0x30
1696 +#define XMITBREAK 0x40
1697 +#define ONESTOP 0x07
1698 +#define TWOSTOP 0x0f
1699 +
1700 + byte fifoctl;
1701 +#define RSTTXFIFOS 0x80
1702 +#define RSTRXFIFOS 0x40
1703 + uint32 baudword;
1704 +
1705 + byte txf_levl;
1706 + byte rxf_levl;
1707 + byte fifocfg;
1708 + byte prog_out;
1709 +
1710 + byte unused1;
1711 + byte DeltaIPEdgeNoSense;
1712 + byte DeltaIPConfig_Mask;
1713 + byte DeltaIP_SyncIP;
1714 + uint16 intMask;
1715 + uint16 intStatus;
1716 +#define TXUNDERR 0x0002
1717 +#define TXOVFERR 0x0004
1718 +#define TXFIFOEMT 0x0020
1719 +#define RXOVFERR 0x0080
1720 +#define RXFIFONE 0x0800
1721 +#define RXFRAMERR 0x1000
1722 +#define RXPARERR 0x2000
1723 +#define RXBRK 0x4000
1724 +
1725 + uint16 unused2;
1726 + uint16 Data;
1727 + uint32 unused3;
1728 + uint32 unused4;
1729 +} Uart;
1730 +
1731 +#define UART_BASE 0xfffe0300
1732 +#define UART ((volatile Uart * const) UART_BASE)
1733 +
1734 +typedef struct GpioControl {
1735 + uint16 unused0;
1736 + byte unused1;
1737 + byte TBusSel;
1738 +
1739 + uint16 unused2;
1740 + uint16 GPIODir;
1741 + byte unused3;
1742 + byte Leds;
1743 + uint16 GPIOio;
1744 +
1745 + uint32 UartCtl;
1746 +} GpioControl;
1747 +
1748 +#define GPIO_BASE 0xfffe0400
1749 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
1750 +
1751 +#define GPIO_NUM_MAX_BITS_MASK 0x0f
1752 +#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
1753 +
1754 +#if __cplusplus
1755 +}
1756 +#endif
1757 +
1758 +#endif
1759 +
1760 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6348_intr.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6348_intr.h
1761 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6348_intr.h 1970-01-01 01:00:00.000000000 +0100
1762 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6348_intr.h 2006-07-05 15:21:58.000000000 +0200
1763 @@ -0,0 +1,80 @@
1764 +/*
1765 +<:copyright-gpl
1766 + Copyright 2003 Broadcom Corp. All Rights Reserved.
1767 +
1768 + This program is free software; you can distribute it and/or modify it
1769 + under the terms of the GNU General Public License (Version 2) as
1770 + published by the Free Software Foundation.
1771 +
1772 + This program is distributed in the hope it will be useful, but WITHOUT
1773 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1774 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1775 + for more details.
1776 +
1777 + You should have received a copy of the GNU General Public License along
1778 + with this program; if not, write to the Free Software Foundation, Inc.,
1779 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1780 +:>
1781 +*/
1782 +
1783 +#ifndef __6348_INTR_H
1784 +#define __6348_INTR_H
1785 +
1786 +#ifdef __cplusplus
1787 + extern "C" {
1788 +#endif
1789 +
1790 +/*=====================================================================*/
1791 +/* BCM6348 External Interrupt Level Assignments */
1792 +/*=====================================================================*/
1793 +#define INTERRUPT_ID_EXTERNAL_0 3
1794 +#define INTERRUPT_ID_EXTERNAL_1 4
1795 +#define INTERRUPT_ID_EXTERNAL_2 5
1796 +#define INTERRUPT_ID_EXTERNAL_3 6
1797 +
1798 +/*=====================================================================*/
1799 +/* BCM6348 Timer Interrupt Level Assignments */
1800 +/*=====================================================================*/
1801 +#define MIPS_TIMER_INT 7
1802 +
1803 +/*=====================================================================*/
1804 +/* Peripheral ISR Table Offset */
1805 +/*=====================================================================*/
1806 +#define INTERNAL_ISR_TABLE_OFFSET 8
1807 +
1808 +/*=====================================================================*/
1809 +/* Logical Peripheral Interrupt IDs */
1810 +/*=====================================================================*/
1811 +
1812 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1813 +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
1814 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1815 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 4)
1816 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 5)
1817 +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 6)
1818 +#define INTERRUPT_ID_EMAC2 (INTERNAL_ISR_TABLE_OFFSET + 7)
1819 +#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
1820 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
1821 +#define INTERRUPT_ID_M2M (INTERNAL_ISR_TABLE_OFFSET + 10)
1822 +#define INTERRUPT_ID_ACLC (INTERNAL_ISR_TABLE_OFFSET + 11)
1823 +#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 12)
1824 +#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 13)
1825 +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
1826 +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
1827 +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
1828 +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 17)
1829 +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 18)
1830 +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 19)
1831 +#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 20)
1832 +#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 21)
1833 +#define INTERRUPT_ID_EMAC2_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 22)
1834 +#define INTERRUPT_ID_EMAC2_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 23)
1835 +#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 24)
1836 +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 25)
1837 +
1838 +#ifdef __cplusplus
1839 + }
1840 +#endif
1841 +
1842 +#endif /* __BCM6348_H */
1843 +
1844 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h
1845 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h 1970-01-01 01:00:00.000000000 +0100
1846 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h 2006-07-05 15:21:58.000000000 +0200
1847 @@ -0,0 +1,508 @@
1848 +/*
1849 +<:copyright-gpl
1850 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1851 +
1852 + This program is free software; you can distribute it and/or modify it
1853 + under the terms of the GNU General Public License (Version 2) as
1854 + published by the Free Software Foundation.
1855 +
1856 + This program is distributed in the hope it will be useful, but WITHOUT
1857 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1858 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1859 + for more details.
1860 +
1861 + You should have received a copy of the GNU General Public License along
1862 + with this program; if not, write to the Free Software Foundation, Inc.,
1863 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1864 +:>
1865 +*/
1866 +
1867 +#ifndef __BCM6348_MAP_H
1868 +#define __BCM6348_MAP_H
1869 +
1870 +#if __cplusplus
1871 +extern "C" {
1872 +#endif
1873 +
1874 +#include "bcmtypes.h"
1875 +
1876 +#define PERF_BASE 0xfffe0000
1877 +#define TIMR_BASE 0xfffe0200
1878 +#define UART_BASE 0xfffe0300
1879 +#define GPIO_BASE 0xfffe0400
1880 +#define MPI_BASE 0xfffe2000 /* MPI control registers */
1881 +#define USB_HOST_BASE 0xfffe1b00 /* USB host registers */
1882 +#define USB_HOST_NON_OHCI 0xfffe1c00 /* USB host non-OHCI registers */
1883 +
1884 +typedef struct PerfControl {
1885 + uint32 RevID;
1886 + uint16 testControl;
1887 + uint16 blkEnables;
1888 +#define EMAC_CLK_EN 0x0010
1889 +#define SAR_CLK_EN 0x0020
1890 +#define USBS_CLK_EN 0x0040
1891 +#define USBH_CLK_EN 0x0100
1892 +
1893 + uint32 pll_control;
1894 +#define SOFT_RESET 0x00000001
1895 +
1896 + uint32 IrqMask;
1897 + uint32 IrqStatus;
1898 +
1899 + uint32 ExtIrqCfg;
1900 +#define EI_SENSE_SHFT 0
1901 +#define EI_STATUS_SHFT 5
1902 +#define EI_CLEAR_SHFT 10
1903 +#define EI_MASK_SHFT 15
1904 +#define EI_INSENS_SHFT 20
1905 +#define EI_LEVEL_SHFT 25
1906 +
1907 + uint32 unused[4]; /* (18) */
1908 + uint32 BlockSoftReset; /* (28) */
1909 +#define BSR_SPI 0x00000001
1910 +#define BSR_EMAC 0x00000004
1911 +#define BSR_USBH 0x00000008
1912 +#define BSR_USBS 0x00000010
1913 +#define BSR_ADSL 0x00000020
1914 +#define BSR_DMAMEM 0x00000040
1915 +#define BSR_SAR 0x00000080
1916 +#define BSR_ACLC 0x00000100
1917 +#define BSR_ADSL_MIPS_PLL 0x00000400
1918 +#define BSR_ALL_BLOCKS \
1919 + (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
1920 + BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
1921 + uint32 unused2[2]; /* (2c) */
1922 + uint32 PllStrap; /* (34) */
1923 +#define PLL_N1_SHFT 20
1924 +#define PLL_N1_MASK (7<<PLL_N1_SHFT)
1925 +#define PLL_N2_SHFT 15
1926 +#define PLL_N2_MASK (0x1f<<PLL_N2_SHFT)
1927 +#define PLL_M1_REF_SHFT 12
1928 +#define PLL_M1_REF_MASK (7<<PLL_M1_REF_SHFT)
1929 +#define PLL_M2_REF_SHFT 9
1930 +#define PLL_M2_REF_MASK (7<<PLL_M2_REF_SHFT)
1931 +#define PLL_M1_CPU_SHFT 6
1932 +#define PLL_M1_CPU_MASK (7<<PLL_M1_CPU_SHFT)
1933 +#define PLL_M1_BUS_SHFT 3
1934 +#define PLL_M1_BUS_MASK (7<<PLL_M1_BUS_SHFT)
1935 +#define PLL_M2_BUS_SHFT 0
1936 +#define PLL_M2_BUS_MASK (7<<PLL_M2_BUS_SHFT)
1937 +} PerfControl;
1938 +
1939 +#define PERF ((volatile PerfControl * const) PERF_BASE)
1940 +
1941 +typedef struct Timer {
1942 + uint16 unused0;
1943 + byte TimerMask;
1944 +#define TIMER0EN 0x01
1945 +#define TIMER1EN 0x02
1946 +#define TIMER2EN 0x04
1947 + byte TimerInts;
1948 +#define TIMER0 0x01
1949 +#define TIMER1 0x02
1950 +#define TIMER2 0x04
1951 +#define WATCHDOG 0x08
1952 + uint32 TimerCtl0;
1953 + uint32 TimerCtl1;
1954 + uint32 TimerCtl2;
1955 +#define TIMERENABLE 0x80000000
1956 +#define RSTCNTCLR 0x40000000
1957 + uint32 TimerCnt0;
1958 + uint32 TimerCnt1;
1959 + uint32 TimerCnt2;
1960 + uint32 WatchDogDefCount;
1961 +
1962 + /* Write 0xff00 0x00ff to Start timer
1963 + * Write 0xee00 0x00ee to Stop and re-load default count
1964 + * Read from this register returns current watch dog count
1965 + */
1966 + uint32 WatchDogCtl;
1967 +
1968 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1969 + uint32 WDResetCount;
1970 +} Timer;
1971 +
1972 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1973 +
1974 +typedef struct UartChannel {
1975 + byte unused0;
1976 + byte control;
1977 +#define BRGEN 0x80 /* Control register bit defs */
1978 +#define TXEN 0x40
1979 +#define RXEN 0x20
1980 +#define LOOPBK 0x10
1981 +#define TXPARITYEN 0x08
1982 +#define TXPARITYEVEN 0x04
1983 +#define RXPARITYEN 0x02
1984 +#define RXPARITYEVEN 0x01
1985 +
1986 + byte config;
1987 +#define XMITBREAK 0x40
1988 +#define BITS5SYM 0x00
1989 +#define BITS6SYM 0x10
1990 +#define BITS7SYM 0x20
1991 +#define BITS8SYM 0x30
1992 +#define ONESTOP 0x07
1993 +#define TWOSTOP 0x0f
1994 + /* 4-LSBS represent STOP bits/char
1995 + * in 1/8 bit-time intervals. Zero
1996 + * represents 1/8 stop bit interval.
1997 + * Fifteen represents 2 stop bits.
1998 + */
1999 + byte fifoctl;
2000 +#define RSTTXFIFOS 0x80
2001 +#define RSTRXFIFOS 0x40
2002 + /* 5-bit TimeoutCnt is in low bits of this register.
2003 + * This count represents the number of characters
2004 + * idle times before setting receive Irq when below threshold
2005 + */
2006 + uint32 baudword;
2007 + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
2008 + */
2009 +
2010 + byte txf_levl; /* Read-only fifo depth */
2011 + byte rxf_levl; /* Read-only fifo depth */
2012 + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
2013 + * RxThreshold. Irq can be asserted
2014 + * when rx fifo> thresh, txfifo<thresh
2015 + */
2016 + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
2017 + * if these bits are also enabled to GPIO_o
2018 + */
2019 +#define DTREN 0x01
2020 +#define RTSEN 0x02
2021 +
2022 + byte unused1;
2023 + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
2024 + * detect irq on rising AND falling
2025 + * edges for corresponding GPIO_i
2026 + * if enabled (edge insensitive)
2027 + */
2028 + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
2029 + * 0 for negedge sense if
2030 + * not configured for edge
2031 + * insensitive (see above)
2032 + * Lower 4 bits: Mask to enable change
2033 + * detection IRQ for corresponding
2034 + * GPIO_i
2035 + */
2036 + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
2037 + * have changed (may set IRQ).
2038 + * read automatically clears bit
2039 + * Lower 4 bits are actual status
2040 + */
2041 +
2042 + uint16 intMask; /* Same Bit defs for Mask and status */
2043 + uint16 intStatus;
2044 +#define DELTAIP 0x0001
2045 +#define TXUNDERR 0x0002
2046 +#define TXOVFERR 0x0004
2047 +#define TXFIFOTHOLD 0x0008
2048 +#define TXREADLATCH 0x0010
2049 +#define TXFIFOEMT 0x0020
2050 +#define RXUNDERR 0x0040
2051 +#define RXOVFERR 0x0080
2052 +#define RXTIMEOUT 0x0100
2053 +#define RXFIFOFULL 0x0200
2054 +#define RXFIFOTHOLD 0x0400
2055 +#define RXFIFONE 0x0800
2056 +#define RXFRAMERR 0x1000
2057 +#define RXPARERR 0x2000
2058 +#define RXBRK 0x4000
2059 +
2060 + uint16 unused2;
2061 + uint16 Data; /* Write to TX, Read from RX */
2062 + /* bits 11:8 are BRK,PAR,FRM errors */
2063 +
2064 + uint32 unused3;
2065 + uint32 unused4;
2066 +} Uart;
2067 +
2068 +#define UART ((volatile Uart * const) UART_BASE)
2069 +
2070 +typedef struct GpioControl {
2071 + uint32 GPIODir_high; /* bits 36:32 */
2072 + uint32 GPIODir; /* bits 31:00 */
2073 + uint32 GPIOio_high; /* bits 36:32 */
2074 + uint32 GPIOio; /* bits 31:00 */
2075 + uint32 LEDCtrl;
2076 +#define LED3_STROBE 0x08000000
2077 +#define LED2_STROBE 0x04000000
2078 +#define LED1_STROBE 0x02000000
2079 +#define LED0_STROBE 0x01000000
2080 +#define LED_TEST 0x00010000
2081 +#define LED3_DISABLE_LINK_ACT 0x00008000
2082 +#define LED2_DISABLE_LINK_ACT 0x00004000
2083 +#define LED1_DISABLE_LINK_ACT 0x00002000
2084 +#define LED0_DISABLE_LINK_ACT 0x00001000
2085 +#define LED_INTERVAL_SET_MASK 0x00000f00
2086 +#define LED_INTERVAL_SET_320MS 0x00000500
2087 +#define LED_INTERVAL_SET_160MS 0x00000400
2088 +#define LED_INTERVAL_SET_80MS 0x00000300
2089 +#define LED_INTERVAL_SET_40MS 0x00000200
2090 +#define LED_INTERVAL_SET_20MS 0x00000100
2091 +#define LED3_ON 0x00000080
2092 +#define LED2_ON 0x00000040
2093 +#define LED1_ON 0x00000020
2094 +#define LED0_ON 0x00000010
2095 +#define LED3_ENABLE 0x00000008
2096 +#define LED2_ENABLE 0x00000004
2097 +#define LED1_ENABLE 0x00000002
2098 +#define LED0_ENABLE 0x00000001
2099 + uint32 SpiSlaveCfg;
2100 +#define SPI_SLAVE_RESET 0x00010000
2101 +#define SPI_RESTRICT 0x00000400
2102 +#define SPI_DELAY_DISABLE 0x00000200
2103 +#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
2104 +#define SPI_SER_ADDR_CFG_MASK 0x0000000c
2105 +#define SPI_MODE 0x00000001
2106 + uint32 GPIOMode;
2107 +#define GROUP4_DIAG 0x00090000
2108 +#define GROUP4_UTOPIA 0x00080000
2109 +#define GROUP4_LEGACY_LED 0x00030000
2110 +#define GROUP4_MII_SNOOP 0x00020000
2111 +#define GROUP4_EXT_EPHY 0x00010000
2112 +#define GROUP3_DIAG 0x00009000
2113 +#define GROUP3_UTOPIA 0x00008000
2114 +#define GROUP3_EXT_MII 0x00007000
2115 +#define GROUP2_DIAG 0x00000900
2116 +#define GROUP2_PCI 0x00000500
2117 +#define GROUP1_DIAG 0x00000090
2118 +#define GROUP1_UTOPIA 0x00000080
2119 +#define GROUP1_SPI_UART 0x00000060
2120 +#define GROUP1_SPI_MASTER 0x00000060
2121 +#define GROUP1_MII_PCCARD 0x00000040
2122 +#define GROUP1_MII_SNOOP 0x00000020
2123 +#define GROUP1_EXT_EPHY 0x00000010
2124 +#define GROUP0_DIAG 0x00000009
2125 +#define GROUP0_EXT_MII 0x00000007
2126 +
2127 +} GpioControl;
2128 +
2129 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
2130 +
2131 +/* Number to mask conversion macro used for GPIODir and GPIOio */
2132 +#define GPIO_NUM_TOTAL_BITS_MASK 0x3f
2133 +#define GPIO_NUM_MAX_BITS_MASK 0x1f
2134 +#define GPIO_NUM_TO_MASK(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) < 32) ? (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) : (0) )
2135 +
2136 +/* Number to mask conversion macro used for GPIODir_high and GPIOio_high */
2137 +#define GPIO_NUM_MAX_BITS_MASK_HIGH 0x07
2138 +#define GPIO_NUM_TO_MASK_HIGH(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) >= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) )
2139 +
2140 +
2141 +/*
2142 +** External Bus Interface
2143 +*/
2144 +typedef struct EbiChipSelect {
2145 + uint32 base; /* base address in upper 24 bits */
2146 +#define EBI_SIZE_8K 0
2147 +#define EBI_SIZE_16K 1
2148 +#define EBI_SIZE_32K 2
2149 +#define EBI_SIZE_64K 3
2150 +#define EBI_SIZE_128K 4
2151 +#define EBI_SIZE_256K 5
2152 +#define EBI_SIZE_512K 6
2153 +#define EBI_SIZE_1M 7
2154 +#define EBI_SIZE_2M 8
2155 +#define EBI_SIZE_4M 9
2156 +#define EBI_SIZE_8M 10
2157 +#define EBI_SIZE_16M 11
2158 +#define EBI_SIZE_32M 12
2159 +#define EBI_SIZE_64M 13
2160 +#define EBI_SIZE_128M 14
2161 +#define EBI_SIZE_256M 15
2162 + uint32 config;
2163 +#define EBI_ENABLE 0x00000001 /* .. enable this range */
2164 +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
2165 +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
2166 +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
2167 +#define EBI_WREN 0x00000020 /* enable posted writes */
2168 +#define EBI_POLARITY 0x00000040 /* .. set to invert something,
2169 + ** don't know what yet */
2170 +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
2171 +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
2172 +#define EBI_FIFO 0x00000200 /* .. use fifo */
2173 +#define EBI_RE 0x00000400 /* .. Reverse Endian */
2174 +} EbiChipSelect;
2175 +
2176 +typedef struct MpiRegisters {
2177 + EbiChipSelect cs[7]; /* size chip select configuration */
2178 +#define EBI_CS0_BASE 0
2179 +#define EBI_CS1_BASE 1
2180 +#define EBI_CS2_BASE 2
2181 +#define EBI_CS3_BASE 3
2182 +#define PCMCIA_COMMON_BASE 4
2183 +#define PCMCIA_ATTRIBUTE_BASE 5
2184 +#define PCMCIA_IO_BASE 6
2185 + uint32 unused0[2]; /* reserved */
2186 + uint32 ebi_control; /* ebi control */
2187 + uint32 unused1[4]; /* reserved */
2188 +#define EBI_ACCESS_TIMEOUT 0x000007FF
2189 + uint32 pcmcia_cntl1; /* pcmcia control 1 */
2190 +#define PCCARD_CARD_RESET 0x00040000
2191 +#define CARDBUS_ENABLE 0x00008000
2192 +#define PCMCIA_ENABLE 0x00004000
2193 +#define PCMCIA_GPIO_ENABLE 0x00002000
2194 +#define CARDBUS_IDSEL 0x00001F00
2195 +#define VS2_OEN 0x00000080
2196 +#define VS1_OEN 0x00000040
2197 +#define VS2_OUT 0x00000020
2198 +#define VS1_OUT 0x00000010
2199 +#define VS2_IN 0x00000008
2200 +#define VS1_IN 0x00000004
2201 +#define CD2_IN 0x00000002
2202 +#define CD1_IN 0x00000001
2203 +#define VS_MASK 0x0000000C
2204 +#define CD_MASK 0x00000003
2205 + uint32 unused2; /* reserved */
2206 + uint32 pcmcia_cntl2; /* pcmcia control 2 */
2207 +#define PCMCIA_BYTESWAP_DIS 0x00000002
2208 +#define PCMCIA_HALFWORD_EN 0x00000001
2209 +#define RW_ACTIVE_CNT_BIT 2
2210 +#define INACTIVE_CNT_BIT 8
2211 +#define CE_SETUP_CNT_BIT 16
2212 +#define CE_HOLD_CNT_BIT 24
2213 + uint32 unused3[40]; /* reserved */
2214 +
2215 + uint32 sp0range; /* PCI to internal system bus address space */
2216 + uint32 sp0remap;
2217 + uint32 sp0cfg;
2218 + uint32 sp1range;
2219 + uint32 sp1remap;
2220 + uint32 sp1cfg;
2221 +
2222 + uint32 EndianCfg;
2223 +
2224 + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */
2225 +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */
2226 +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */
2227 +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */
2228 +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */
2229 +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */
2230 +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */
2231 +
2232 + uint32 l2pmrange1; /* internal system bus to PCI memory space */
2233 +#define PCI_SIZE_64K 0xFFFF0000
2234 +#define PCI_SIZE_128K 0xFFFE0000
2235 +#define PCI_SIZE_256K 0xFFFC0000
2236 +#define PCI_SIZE_512K 0xFFF80000
2237 +#define PCI_SIZE_1M 0xFFF00000
2238 +#define PCI_SIZE_2M 0xFFE00000
2239 +#define PCI_SIZE_4M 0xFFC00000
2240 +#define PCI_SIZE_8M 0xFF800000
2241 +#define PCI_SIZE_16M 0xFF000000
2242 +#define PCI_SIZE_32M 0xFE000000
2243 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */
2244 + uint32 l2pmremap1;
2245 +#define CARDBUS_MEM 0x00000004
2246 +#define MEM_WINDOW_EN 0x00000001
2247 + uint32 l2pmrange2;
2248 + uint32 l2pmbase2;
2249 + uint32 l2pmremap2;
2250 + uint32 l2piorange; /* internal system bus to PCI I/O space */
2251 + uint32 l2piobase;
2252 + uint32 l2pioremap;
2253 +
2254 + uint32 pcimodesel;
2255 +#define PCI2_INT_BUS_RD_PREFECH 0x000000F0
2256 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */
2257 +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */
2258 +
2259 + uint32 pciintstat; /* PCI interrupt mask/status */
2260 +#define MAILBOX1_SENT 0x08
2261 +#define MAILBOX0_SENT 0x04
2262 +#define MAILBOX1_MSG_RCV 0x02
2263 +#define MAILBOX0_MSG_RCV 0x01
2264 + uint32 locbuscntrl; /* internal system bus control */
2265 +#define DIR_U2P_NOSWAP 0x00000002
2266 +#define EN_PCI_GPIO 0x00000001
2267 + uint32 locintstat; /* internal system bus interrupt mask/status */
2268 +#define CSERR 0x0200
2269 +#define SERR 0x0100
2270 +#define EXT_PCI_INT 0x0080
2271 +#define DIR_FAILED 0x0040
2272 +#define DIR_COMPLETE 0x0020
2273 +#define PCI_CFG 0x0010
2274 + uint32 unused5[7];
2275 +
2276 + uint32 mailbox0;
2277 + uint32 mailbox1;
2278 +
2279 + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */
2280 +#define PCI_CFG_REG_WRITE_EN 0x00000080
2281 +#define PCI_CFG_ADDR 0x0000003C
2282 + uint32 pcicfgdata; /* internal system bus PCI configuration data */
2283 +
2284 + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */
2285 +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */
2286 +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */
2287 +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */
2288 +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */
2289 + uint32 locch2intStat;
2290 +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */
2291 +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */
2292 +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */
2293 + uint32 locch2intMask;
2294 + uint32 unused6;
2295 + uint32 locch2descaddr;
2296 + uint32 locch2status1;
2297 +#define LOCAL_DESC_STATE 0xE0000000
2298 +#define PCI_DESC_STATE 0x1C000000
2299 +#define BYTE_DONE 0x03FFC000
2300 +#define RING_ADDR 0x00003FFF
2301 + uint32 locch2status2;
2302 +#define BUFPTR_OFFSET 0x1FFF0000
2303 +#define PCI_MASTER_STATE 0x000000C0
2304 +#define LOC_MASTER_STATE 0x00000038
2305 +#define CONTROL_STATE 0x00000007
2306 + uint32 unused7;
2307 +
2308 + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */
2309 +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */
2310 +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */
2311 + uint32 locch1intstat;
2312 + uint32 locch1intmask;
2313 + uint32 unused8;
2314 + uint32 locch1descaddr;
2315 + uint32 locch1status1;
2316 + uint32 locch1status2;
2317 + uint32 unused9;
2318 +
2319 + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */
2320 + uint32 pcich1intstat;
2321 + uint32 pcich1intmask;
2322 + uint32 pcich1descaddr;
2323 + uint32 pcich1status1;
2324 + uint32 pcich1status2;
2325 +
2326 + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */
2327 + uint32 pcich2intstat;
2328 + uint32 pcich2intmask;
2329 + uint32 pcich2descaddr;
2330 + uint32 pcich2status1;
2331 + uint32 pcich2status2;
2332 +
2333 + uint32 perm_id; /* permanent device and vendor id */
2334 + uint32 perm_rev; /* permanent revision id */
2335 +} MpiRegisters;
2336 +
2337 +#define MPI ((volatile MpiRegisters * const) MPI_BASE)
2338 +
2339 +/* PCI configuration address space start offset 0x40 */
2340 +#define BRCM_PCI_CONFIG_TIMER 0x40
2341 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00
2342 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF
2343 +
2344 +/* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */
2345 +#define NON_OHCI_ENABLE_PORT1 0x00000001 /* Use USB port 1 for host, not dev */
2346 +#define NON_OHCI_BYTE_SWAP 0x00000008 /* Swap USB host registers */
2347 +
2348 +#define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI)
2349 +
2350 +#if __cplusplus
2351 +}
2352 +#endif
2353 +
2354 +#endif
2355 +
2356 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmTag.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmTag.h
2357 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmTag.h 1970-01-01 01:00:00.000000000 +0100
2358 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmTag.h 2006-07-05 15:21:58.000000000 +0200
2359 @@ -0,0 +1,153 @@
2360 +/*
2361 +<:copyright-gpl
2362 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2363 +
2364 + This program is free software; you can distribute it and/or modify it
2365 + under the terms of the GNU General Public License (Version 2) as
2366 + published by the Free Software Foundation.
2367 +
2368 + This program is distributed in the hope it will be useful, but WITHOUT
2369 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2370 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2371 + for more details.
2372 +
2373 + You should have received a copy of the GNU General Public License along
2374 + with this program; if not, write to the Free Software Foundation, Inc.,
2375 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2376 +:>
2377 +*/
2378 +//**************************************************************************************
2379 +// File Name : bcmTag.h
2380 +//
2381 +// Description: add tag with validation system to the firmware image file to be uploaded
2382 +// via http
2383 +//
2384 +// Created : 02/28/2002 seanl
2385 +//**************************************************************************************
2386 +
2387 +#ifndef _BCMTAG_H_
2388 +#define _BCMTAG_H_
2389 +
2390 +
2391 +#define BCM_SIG_1 "Broadcom Corporation"
2392 +#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id.
2393 +
2394 +#define BCM_TAG_VER "6"
2395 +#define BCM_TAG_VER_LAST "26"
2396 +
2397 +// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars
2398 +#define TAG_LEN 256
2399 +#define TAG_VER_LEN 4
2400 +#define SIG_LEN 20
2401 +#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID
2402 +#define CHIP_ID_LEN 6
2403 +#define IMAGE_LEN 10
2404 +#define ADDRESS_LEN 12
2405 +#define FLAG_LEN 2
2406 +#define TOKEN_LEN 20
2407 +#define BOARD_ID_LEN 16
2408 +#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \
2409 + (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN))
2410 +
2411 +
2412 +// TAG for downloadable image (kernel plus file system)
2413 +typedef struct _FILE_TAG
2414 +{
2415 + unsigned char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here.
2416 + unsigned char signiture_1[SIG_LEN]; // text line for company info
2417 + unsigned char signiture_2[SIG_LEN_2]; // additional info (can be version number)
2418 + unsigned char chipId[CHIP_ID_LEN]; // chip id
2419 + unsigned char boardId[BOARD_ID_LEN]; // board id
2420 + unsigned char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host
2421 + unsigned char totalImageLen[IMAGE_LEN]; // the sum of all the following length
2422 + unsigned char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address
2423 + unsigned char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text.
2424 + unsigned char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address
2425 + unsigned char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text.
2426 + unsigned char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address
2427 + unsigned char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text.
2428 + unsigned char dualImage[FLAG_LEN]; // if 1, dual image
2429 + unsigned char inactiveLen[FLAG_LEN]; // if 1, the image is INACTIVE; if 0, active
2430 + unsigned char reserved[RESERVED_LEN]; // reserved for later use
2431 + unsigned char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for
2432 + // now will be 4 unsigned char crc
2433 + unsigned char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken)
2434 +} FILE_TAG, *PFILE_TAG;
2435 +
2436 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
2437 +#define CRC_LEN 4
2438 +
2439 +// only included if for bcmTag.exe program
2440 +#ifdef BCMTAG_EXE_USE
2441 +
2442 +static unsigned long Crc32_table[256] = {
2443 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
2444 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
2445 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
2446 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
2447 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
2448 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
2449 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
2450 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
2451 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
2452 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
2453 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
2454 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
2455 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
2456 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
2457 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
2458 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
2459 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
2460 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
2461 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
2462 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
2463 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
2464 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
2465 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
2466 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
2467 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
2468 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
2469 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
2470 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
2471 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
2472 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
2473 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
2474 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
2475 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
2476 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
2477 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
2478 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
2479 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
2480 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
2481 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
2482 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
2483 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
2484 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
2485 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
2486 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
2487 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
2488 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
2489 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
2490 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
2491 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
2492 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
2493 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
2494 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
2495 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
2496 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
2497 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
2498 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
2499 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
2500 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
2501 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
2502 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
2503 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
2504 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
2505 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
2506 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
2507 +};
2508 +#endif // BCMTAG_USE
2509 +
2510 +
2511 +#endif // _BCMTAG_H_
2512 +
2513 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h
2514 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h 1970-01-01 01:00:00.000000000 +0100
2515 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h 2006-07-05 15:21:58.000000000 +0200
2516 @@ -0,0 +1,59 @@
2517 +/*
2518 +<:copyright-gpl
2519 + Copyright 2003 Broadcom Corp. All Rights Reserved.
2520 +
2521 + This program is free software; you can distribute it and/or modify it
2522 + under the terms of the GNU General Public License (Version 2) as
2523 + published by the Free Software Foundation.
2524 +
2525 + This program is distributed in the hope it will be useful, but WITHOUT
2526 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2527 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2528 + for more details.
2529 +
2530 + You should have received a copy of the GNU General Public License along
2531 + with this program; if not, write to the Free Software Foundation, Inc.,
2532 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2533 +:>
2534 +*/
2535 +
2536 +#ifndef __BCM_INTR_H
2537 +#define __BCM_INTR_H
2538 +
2539 +#ifdef __cplusplus
2540 + extern "C" {
2541 +#endif
2542 +
2543 +#if defined(CONFIG_BCM96338)
2544 +#include <6338_intr.h>
2545 +#endif
2546 +#if defined(CONFIG_BCM96345)
2547 +#include <6345_intr.h>
2548 +#endif
2549 +#if defined(CONFIG_BCM96348)
2550 +#include <6348_intr.h>
2551 +#endif
2552 +
2553 +/* defines */
2554 +struct pt_regs;
2555 +typedef int (*FN_HANDLER) (int, void *, struct pt_regs *);
2556 +
2557 +/* prototypes */
2558 +extern void enable_brcm_irq(unsigned int irq);
2559 +extern void disable_brcm_irq(unsigned int irq);
2560 +extern int request_external_irq(unsigned int irq,
2561 + FN_HANDLER handler, unsigned long irqflags,
2562 + const char * devname, void *dev_id);
2563 +extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param,
2564 + unsigned int interruptId);
2565 +extern void dump_intr_regs(void);
2566 +
2567 +/* compatibility definitions */
2568 +#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq )
2569 +#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq )
2570 +
2571 +#ifdef __cplusplus
2572 + }
2573 +#endif
2574 +
2575 +#endif
2576 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h
2577 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h 1970-01-01 01:00:00.000000000 +0100
2578 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h 2006-07-05 15:21:58.000000000 +0200
2579 @@ -0,0 +1,34 @@
2580 +/*
2581 +<:copyright-gpl
2582 + Copyright 2004 Broadcom Corp. All Rights Reserved.
2583 +
2584 + This program is free software; you can distribute it and/or modify it
2585 + under the terms of the GNU General Public License (Version 2) as
2586 + published by the Free Software Foundation.
2587 +
2588 + This program is distributed in the hope it will be useful, but WITHOUT
2589 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2590 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2591 + for more details.
2592 +
2593 + You should have received a copy of the GNU General Public License along
2594 + with this program; if not, write to the Free Software Foundation, Inc.,
2595 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2596 +:>
2597 +*/
2598 +
2599 +#ifndef __BCM_MAP_PART_H
2600 +#define __BCM_MAP_PART_H
2601 +
2602 +#if defined(CONFIG_BCM96338)
2603 +#include <6338_map_part.h>
2604 +#endif
2605 +#if defined(CONFIG_BCM96345)
2606 +#include <6345_map_part.h>
2607 +#endif
2608 +#if defined(CONFIG_BCM96348)
2609 +#include <6348_map_part.h>
2610 +#endif
2611 +
2612 +#endif
2613 +
2614 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmpci.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmpci.h
2615 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmpci.h 1970-01-01 01:00:00.000000000 +0100
2616 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmpci.h 2006-07-05 15:21:58.000000000 +0200
2617 @@ -0,0 +1,87 @@
2618 +/*
2619 +<:copyright-gpl
2620 + Copyright 2004 Broadcom Corp. All Rights Reserved.
2621 +
2622 + This program is free software; you can distribute it and/or modify it
2623 + under the terms of the GNU General Public License (Version 2) as
2624 + published by the Free Software Foundation.
2625 +
2626 + This program is distributed in the hope it will be useful, but WITHOUT
2627 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2628 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2629 + for more details.
2630 +
2631 + You should have received a copy of the GNU General Public License along
2632 + with this program; if not, write to the Free Software Foundation, Inc.,
2633 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2634 +:>
2635 +*/
2636 +
2637 +//
2638 +// bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
2639 +//
2640 +#ifndef BCMPCI_H
2641 +#define BCMPCI_H
2642 +
2643 +/* Memory window in internal system bus address space */
2644 +#define BCM_PCI_MEM_BASE 0x08000000
2645 +/* IO window in internal system bus address space */
2646 +#define BCM_PCI_IO_BASE 0x0C000000
2647 +
2648 +#define BCM_PCI_ADDR_MASK 0x1fffffff
2649 +
2650 +/* Memory window size (range) */
2651 +#define BCM_PCI_MEM_SIZE_16MB 0x01000000
2652 +/* IO window size (range) */
2653 +#define BCM_PCI_IO_SIZE_64KB 0x00010000
2654 +
2655 +/* PCI Configuration and I/O space acesss */
2656 +#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
2657 +
2658 +/* fake USB PCI slot */
2659 +#define USB_HOST_SLOT 9
2660 +#define USB_BAR0_MEM_SIZE 0x0800
2661 +
2662 +#define BCM_HOST_MEM_SPACE1 0x10000000
2663 +#define BCM_HOST_MEM_SPACE2 0x00000000
2664 +
2665 +/*
2666 + * EBI bus clock is 33MHz and share with PCI bus
2667 + * each clock cycle is 30ns.
2668 + */
2669 +/* attribute memory access wait cnt for 4306 */
2670 +#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
2671 +#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
2672 +#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
2673 +#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
2674 +
2675 +/* common memory access wait cnt for 4306 */
2676 +#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
2677 +#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
2678 +#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
2679 +#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
2680 +
2681 +#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
2682 +#define PCCARD_VCC_33V 0x00010000
2683 +#define PCCARD_VCC_50V 0x00020000
2684 +
2685 +typedef enum {
2686 + MPI_CARDTYPE_NONE, // No Card in slot
2687 + MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
2688 + MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
2689 +} CardType;
2690 +
2691 +#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
2692 +
2693 +#define pcmciaAttrOffset 0x00200000
2694 +#define pcmciaMemOffset 0x00000000
2695 +// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
2696 +#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
2697 +// Base Address is that mapped into the MPI ChipSelect registers.
2698 +// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
2699 +#define pcmciaBase 0xbf000000
2700 +#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
2701 +#define pcmciaMem (pcmciaMemOffset | pcmciaBase)
2702 +#define pcmciaIo (pcmciaIoOffset | pcmciaBase)
2703 +
2704 +#endif
2705 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h
2706 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h 1970-01-01 01:00:00.000000000 +0100
2707 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h 2006-07-05 15:21:58.000000000 +0200
2708 @@ -0,0 +1,163 @@
2709 +/*
2710 +<:copyright-gpl
2711 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2712 +
2713 + This program is free software; you can distribute it and/or modify it
2714 + under the terms of the GNU General Public License (Version 2) as
2715 + published by the Free Software Foundation.
2716 +
2717 + This program is distributed in the hope it will be useful, but WITHOUT
2718 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2719 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2720 + for more details.
2721 +
2722 + You should have received a copy of the GNU General Public License along
2723 + with this program; if not, write to the Free Software Foundation, Inc.,
2724 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2725 +:>
2726 +*/
2727 +
2728 +//
2729 +// bcmtypes.h - misc useful typedefs
2730 +//
2731 +#ifndef BCMTYPES_H
2732 +#define BCMTYPES_H
2733 +
2734 +// These are also defined in typedefs.h in the application area, so I need to
2735 +// protect against re-definition.
2736 +
2737 +#ifndef _TYPEDEFS_H_
2738 +typedef unsigned char uint8;
2739 +typedef unsigned short uint16;
2740 +typedef unsigned long uint32;
2741 +typedef signed char int8;
2742 +typedef signed short int16;
2743 +typedef signed long int32;
2744 +#if !defined(__cplusplus)
2745 +typedef int bool;
2746 +#endif
2747 +#endif
2748 +
2749 +typedef unsigned char byte;
2750 +// typedef unsigned long sem_t;
2751 +
2752 +typedef unsigned long HANDLE,*PULONG,DWORD,*PDWORD;
2753 +typedef signed long LONG,*PLONG;
2754 +
2755 +typedef unsigned int *PUINT;
2756 +typedef signed int INT;
2757 +
2758 +typedef unsigned short *PUSHORT;
2759 +typedef signed short SHORT,*PSHORT;
2760 +typedef unsigned short WORD,*PWORD;
2761 +
2762 +typedef unsigned char *PUCHAR;
2763 +typedef signed char *PCHAR;
2764 +
2765 +typedef void *PVOID;
2766 +
2767 +typedef unsigned char BOOLEAN, *PBOOL, *PBOOLEAN;
2768 +
2769 +typedef unsigned char BYTE,*PBYTE;
2770 +
2771 +//#ifndef __GNUC__
2772 +//The following has been defined in Vxworks internally: vxTypesOld.h
2773 +//redefine under vxworks will cause error
2774 +typedef signed int *PINT;
2775 +
2776 +typedef signed char INT8;
2777 +typedef signed short INT16;
2778 +typedef signed long INT32;
2779 +
2780 +typedef unsigned char UINT8;
2781 +typedef unsigned short UINT16;
2782 +typedef unsigned long UINT32;
2783 +
2784 +typedef unsigned char UCHAR;
2785 +typedef unsigned short USHORT;
2786 +typedef unsigned int UINT;
2787 +typedef unsigned long ULONG;
2788 +
2789 +typedef void VOID;
2790 +typedef unsigned char BOOL;
2791 +
2792 +//#endif /* __GNUC__ */
2793 +
2794 +
2795 +// These are also defined in typedefs.h in the application area, so I need to
2796 +// protect against re-definition.
2797 +#ifndef TYPEDEFS_H
2798 +
2799 +// Maximum and minimum values for a signed 16 bit integer.
2800 +#define MAX_INT16 32767
2801 +#define MIN_INT16 -32768
2802 +
2803 +// Useful for true/false return values. This uses the
2804 +// Taligent notation (k for constant).
2805 +typedef enum
2806 +{
2807 + kFalse = 0,
2808 + kTrue = 1
2809 +} Bool;
2810 +
2811 +#endif
2812 +
2813 +/* macros to protect against unaligned accesses */
2814 +
2815 +#if 0
2816 +/* first arg is an address, second is a value */
2817 +#define PUT16( a, d ) { \
2818 + *((byte *)a) = (byte)((d)>>8); \
2819 + *(((byte *)a)+1) = (byte)(d); \
2820 +}
2821 +
2822 +#define PUT32( a, d ) { \
2823 + *((byte *)a) = (byte)((d)>>24); \
2824 + *(((byte *)a)+1) = (byte)((d)>>16); \
2825 + *(((byte *)a)+2) = (byte)((d)>>8); \
2826 + *(((byte *)a)+3) = (byte)(d); \
2827 +}
2828 +
2829 +/* first arg is an address, returns a value */
2830 +#define GET16( a ) ( \
2831 + (*((byte *)a) << 8) | \
2832 + (*(((byte *)a)+1)) \
2833 +)
2834 +
2835 +#define GET32( a ) ( \
2836 + (*((byte *)a) << 24) | \
2837 + (*(((byte *)a)+1) << 16) | \
2838 + (*(((byte *)a)+2) << 8) | \
2839 + (*(((byte *)a)+3)) \
2840 +)
2841 +#endif
2842 +
2843 +#ifndef YES
2844 +#define YES 1
2845 +#endif
2846 +
2847 +#ifndef NO
2848 +#define NO 0
2849 +#endif
2850 +
2851 +#ifndef IN
2852 +#define IN
2853 +#endif
2854 +
2855 +#ifndef OUT
2856 +#define OUT
2857 +#endif
2858 +
2859 +#ifndef TRUE
2860 +#define TRUE 1
2861 +#endif
2862 +
2863 +#ifndef FALSE
2864 +#define FALSE 0
2865 +#endif
2866 +
2867 +#define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr))
2868 +#define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr))
2869 +#define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr))
2870 +
2871 +#endif
2872 diff -Naurp linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/board.h linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/board.h
2873 --- linux-2.6.16.7-generic-patched/bcmdrivers/opensource/include/bcm963xx/board.h 1970-01-01 01:00:00.000000000 +0100
2874 +++ linux-2.6.16.7-patched/bcmdrivers/opensource/include/bcm963xx/board.h 2006-07-05 15:21:58.000000000 +0200
2875 @@ -0,0 +1,374 @@
2876 +/*
2877 +<:copyright-gpl
2878 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2879 +
2880 + This program is free software; you can distribute it and/or modify it
2881 + under the terms of the GNU General Public License (Version 2) as
2882 + published by the Free Software Foundation.
2883 +
2884 + This program is distributed in the hope it will be useful, but WITHOUT
2885 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2886 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2887 + for more details.
2888 +
2889 + You should have received a copy of the GNU General Public License along
2890 + with this program; if not, write to the Free Software Foundation, Inc.,
2891 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2892 +:>
2893 +*/
2894 +/***********************************************************************/
2895 +/* */
2896 +/* MODULE: board.h */
2897 +/* DATE: 97/02/18 */
2898 +/* PURPOSE: Board specific information. This module should include */
2899 +/* all base device addresses and board specific macros. */
2900 +/* */
2901 +/***********************************************************************/
2902 +#ifndef _BOARD_H
2903 +#define _BOARD_H
2904 +
2905 +#if __cplusplus
2906 +extern "C" {
2907 +#endif
2908 +/*****************************************************************************/
2909 +/* Misc board definitions */
2910 +/*****************************************************************************/
2911 +
2912 +#define DYING_GASP_API
2913 +
2914 +/*****************************************************************************/
2915 +/* Physical Memory Map */
2916 +/*****************************************************************************/
2917 +
2918 +#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */
2919 +#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */
2920 +
2921 +/*****************************************************************************/
2922 +/* Note that the addresses above are physical addresses and that programs */
2923 +/* have to use converted addresses defined below: */
2924 +/*****************************************************************************/
2925 +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
2926 +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
2927 +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
2928 +
2929 +/*****************************************************************************/
2930 +/* Select the PLL value to get the desired CPU clock frequency. */
2931 +/* */
2932 +/* */
2933 +/*****************************************************************************/
2934 +#define FPERIPH 50000000
2935 +
2936 +#define ONEK 1024
2937 +#define BLK64K (64*ONEK)
2938 +#define FLASH45_BLKS_BOOT_ROM 1
2939 +#define FLASH45_LENGTH_BOOT_ROM (FLASH45_BLKS_BOOT_ROM * BLK64K)
2940 +#define FLASH_RESERVED_AT_END (64*ONEK) /*reserved for PSI, scratch pad*/
2941 +
2942 +/*****************************************************************************/
2943 +/* Note that the addresses above are physical addresses and that programs */
2944 +/* have to use converted addresses defined below: */
2945 +/*****************************************************************************/
2946 +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
2947 +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
2948 +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
2949 +
2950 +/*****************************************************************************/
2951 +/* Select the PLL value to get the desired CPU clock frequency. */
2952 +/* */
2953 +/* */
2954 +/*****************************************************************************/
2955 +#define FPERIPH 50000000
2956 +
2957 +#define SDRAM_TYPE_ADDRESS_OFFSET 16
2958 +#define NVRAM_DATA_OFFSET 0x0580
2959 +#define NVRAM_DATA_ID 0x0f1e2d3c
2960 +#define BOARD_SDRAM_TYPE *(unsigned long *) \
2961 + (FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET)
2962 +
2963 +#define ONEK 1024
2964 +#define BLK64K (64*ONEK)
2965 +
2966 +// nvram and psi flash definitions for 45
2967 +#define FLASH45_LENGTH_NVRAM ONEK // 1k nvram
2968 +#define NVRAM_PSI_DEFAULT 24 // default psi in K byes
2969 +
2970 +/*****************************************************************************/
2971 +/* NVRAM Offset and definition */
2972 +/*****************************************************************************/
2973 +
2974 +#define NVRAM_VERSION_NUMBER 2
2975 +#define NVRAM_VERSION_NUMBER_ADDRESS 0
2976 +
2977 +#define NVRAM_BOOTLINE_LEN 256
2978 +#define NVRAM_BOARD_ID_STRING_LEN 16
2979 +#define NVRAM_MAC_ADDRESS_LEN 6
2980 +#define NVRAM_MAC_COUNT_MAX 32
2981 +
2982 +/*****************************************************************************/
2983 +/* Misc Offsets */
2984 +/*****************************************************************************/
2985 +
2986 +#define CFE_VERSION_OFFSET 0x0570
2987 +#define CFE_VERSION_MARK_SIZE 5
2988 +#define CFE_VERSION_SIZE 5
2989 +
2990 +typedef struct
2991 +{
2992 + unsigned long ulVersion;
2993 + char szBootline[NVRAM_BOOTLINE_LEN];
2994 + char szBoardId[NVRAM_BOARD_ID_STRING_LEN];
2995 + unsigned long ulReserved1[2];
2996 + unsigned long ulNumMacAddrs;
2997 + unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN];
2998 + char chReserved[2];
2999 + unsigned long ulCheckSum;
3000 +} NVRAM_DATA, *PNVRAM_DATA;
3001 +
3002 +
3003 +/*****************************************************************************/
3004 +/* board ioctl calls for flash, led and some other utilities */
3005 +/*****************************************************************************/
3006 +
3007 +
3008 +/* Defines. for board driver */
3009 +#define BOARD_IOCTL_MAGIC 'B'
3010 +#define BOARD_DRV_MAJOR 206
3011 +
3012 +#define MAC_ADDRESS_ANY (unsigned long) -1
3013 +
3014 +#define BOARD_IOCTL_FLASH_INIT \
3015 + _IOWR(BOARD_IOCTL_MAGIC, 0, BOARD_IOCTL_PARMS)
3016 +
3017 +#define BOARD_IOCTL_FLASH_WRITE \
3018 + _IOWR(BOARD_IOCTL_MAGIC, 1, BOARD_IOCTL_PARMS)
3019 +
3020 +#define BOARD_IOCTL_FLASH_READ \
3021 + _IOWR(BOARD_IOCTL_MAGIC, 2, BOARD_IOCTL_PARMS)
3022 +
3023 +#define BOARD_IOCTL_GET_NR_PAGES \
3024 + _IOWR(BOARD_IOCTL_MAGIC, 3, BOARD_IOCTL_PARMS)
3025 +
3026 +#define BOARD_IOCTL_DUMP_ADDR \
3027 + _IOWR(BOARD_IOCTL_MAGIC, 4, BOARD_IOCTL_PARMS)
3028 +
3029 +#define BOARD_IOCTL_SET_MEMORY \
3030 + _IOWR(BOARD_IOCTL_MAGIC, 5, BOARD_IOCTL_PARMS)
3031 +
3032 +#define BOARD_IOCTL_MIPS_SOFT_RESET \
3033 + _IOWR(BOARD_IOCTL_MAGIC, 6, BOARD_IOCTL_PARMS)
3034 +
3035 +#define BOARD_IOCTL_LED_CTRL \
3036 + _IOWR(BOARD_IOCTL_MAGIC, 7, BOARD_IOCTL_PARMS)
3037 +
3038 +#define BOARD_IOCTL_GET_ID \
3039 + _IOWR(BOARD_IOCTL_MAGIC, 8, BOARD_IOCTL_PARMS)
3040 +
3041 +#define BOARD_IOCTL_GET_MAC_ADDRESS \
3042 + _IOWR(BOARD_IOCTL_MAGIC, 9, BOARD_IOCTL_PARMS)
3043 +
3044 +#define BOARD_IOCTL_RELEASE_MAC_ADDRESS \
3045 + _IOWR(BOARD_IOCTL_MAGIC, 10, BOARD_IOCTL_PARMS)
3046 +
3047 +#define BOARD_IOCTL_GET_PSI_SIZE \
3048 + _IOWR(BOARD_IOCTL_MAGIC, 11, BOARD_IOCTL_PARMS)
3049 +
3050 +#define BOARD_IOCTL_GET_SDRAM_SIZE \
3051 + _IOWR(BOARD_IOCTL_MAGIC, 12, BOARD_IOCTL_PARMS)
3052 +
3053 +#define BOARD_IOCTL_SET_MONITOR_FD \
3054 + _IOWR(BOARD_IOCTL_MAGIC, 13, BOARD_IOCTL_PARMS)
3055 +
3056 +#define BOARD_IOCTL_WAKEUP_MONITOR_TASK \
3057 + _IOWR(BOARD_IOCTL_MAGIC, 14, BOARD_IOCTL_PARMS)
3058 +
3059 +#define BOARD_IOCTL_GET_BOOTLINE \
3060 + _IOWR(BOARD_IOCTL_MAGIC, 15, BOARD_IOCTL_PARMS)
3061 +
3062 +#define BOARD_IOCTL_SET_BOOTLINE \
3063 + _IOWR(BOARD_IOCTL_MAGIC, 16, BOARD_IOCTL_PARMS)
3064 +
3065 +#define BOARD_IOCTL_GET_BASE_MAC_ADDRESS \
3066 + _IOWR(BOARD_IOCTL_MAGIC, 17, BOARD_IOCTL_PARMS)
3067 +
3068 +#define BOARD_IOCTL_GET_CHIP_ID \
3069 + _IOWR(BOARD_IOCTL_MAGIC, 18, BOARD_IOCTL_PARMS)
3070 +
3071 +#define BOARD_IOCTL_GET_NUM_ENET \
3072 + _IOWR(BOARD_IOCTL_MAGIC, 19, BOARD_IOCTL_PARMS)
3073 +
3074 +#define BOARD_IOCTL_GET_CFE_VER \
3075 + _IOWR(BOARD_IOCTL_MAGIC, 20, BOARD_IOCTL_PARMS)
3076 +
3077 +#define BOARD_IOCTL_GET_ENET_CFG \
3078 + _IOWR(BOARD_IOCTL_MAGIC, 21, BOARD_IOCTL_PARMS)
3079 +
3080 +#define BOARD_IOCTL_GET_WLAN_ANT_INUSE \
3081 + _IOWR(BOARD_IOCTL_MAGIC, 22, BOARD_IOCTL_PARMS)
3082 +
3083 +#define BOARD_IOCTL_SET_TRIGGER_EVENT \
3084 + _IOWR(BOARD_IOCTL_MAGIC, 23, BOARD_IOCTL_PARMS)
3085 +
3086 +#define BOARD_IOCTL_GET_TRIGGER_EVENT \
3087 + _IOWR(BOARD_IOCTL_MAGIC, 24, BOARD_IOCTL_PARMS)
3088 +
3089 +#define BOARD_IOCTL_UNSET_TRIGGER_EVENT \
3090 + _IOWR(BOARD_IOCTL_MAGIC, 25, BOARD_IOCTL_PARMS)
3091 +
3092 +#define BOARD_IOCTL_SET_SES_LED \
3093 + _IOWR(BOARD_IOCTL_MAGIC, 26, BOARD_IOCTL_PARMS)
3094 +
3095 +//<<JUNHON, 2004/09/15, get reset button status , tim hou , 05/04/12
3096 +#define RESET_BUTTON_UP 1
3097 +#define RESET_BUTTON_PRESSDOWN 0
3098 +#define BOARD_IOCTL_GET_RESETHOLD \
3099 + _IOWR(BOARD_IOCTL_MAGIC, 27, BOARD_IOCTL_PARMS)
3100 +//>>JUNHON, 2004/09/15
3101 +
3102 +// for the action in BOARD_IOCTL_PARMS for flash operation
3103 +typedef enum
3104 +{
3105 + PERSISTENT,
3106 + NVRAM,
3107 + BCM_IMAGE_CFE,
3108 + BCM_IMAGE_FS,
3109 + BCM_IMAGE_KERNEL,
3110 + BCM_IMAGE_WHOLE,
3111 + SCRATCH_PAD,
3112 + FLASH_SIZE,
3113 +} BOARD_IOCTL_ACTION;
3114 +
3115 +
3116 +typedef struct boardIoctParms
3117 +{
3118 + char *string;
3119 + char *buf;
3120 + int strLen;
3121 + int offset;
3122 + BOARD_IOCTL_ACTION action; /* flash read/write: nvram, persistent, bcm image */
3123 + int result;
3124 +} BOARD_IOCTL_PARMS;
3125 +
3126 +
3127 +// LED defines
3128 +typedef enum
3129 +{
3130 + kLedAdsl,
3131 + kLedWireless,
3132 + kLedUsb,
3133 + kLedHpna,
3134 + kLedWanData,
3135 + kLedPPP,
3136 + kLedVoip,
3137 + kLedSes,
3138 + kLedEnd, // NOTE: Insert the new led name before this one. Alway stay at the end.
3139 +} BOARD_LED_NAME;
3140 +
3141 +typedef enum
3142 +{
3143 + kLedStateOff, /* turn led off */
3144 + kLedStateOn, /* turn led on */
3145 + kLedStateFail, /* turn led on red */
3146 + kLedStateBlinkOnce, /* blink once, ~100ms and ignore the same call during the 100ms period */
3147 + kLedStateSlowBlinkContinues, /* slow blink continues at ~600ms interval */
3148 + kLedStateFastBlinkContinues, /* fast blink continues at ~200ms interval */
3149 +} BOARD_LED_STATE;
3150 +
3151 +
3152 +// virtual and physical map pair defined in board.c
3153 +typedef struct ledmappair
3154 +{
3155 + BOARD_LED_NAME ledName; // virtual led name
3156 + BOARD_LED_STATE ledInitState; // initial led state when the board boots.
3157 + unsigned short ledMask; // physical GPIO pin mask
3158 + unsigned short ledActiveLow; // reset bit to turn on LED
3159 + unsigned short ledMaskFail; // physical GPIO pin mask for state failure
3160 + unsigned short ledActiveLowFail;// reset bit to turn on LED
3161 +} LED_MAP_PAIR, *PLED_MAP_PAIR;
3162 +
3163 +typedef void (*HANDLE_LED_FUNC)(BOARD_LED_NAME ledName, BOARD_LED_STATE ledState);
3164 +
3165 +/* Flash storage address information that is determined by the flash driver. */
3166 +typedef struct flashaddrinfo
3167 +{
3168 + int flash_persistent_start_blk;
3169 + int flash_persistent_number_blk;
3170 + int flash_persistent_length;
3171 + unsigned long flash_persistent_blk_offset;
3172 + int flash_scratch_pad_start_blk; // start before psi (SP_BUF_LEN)
3173 + int flash_scratch_pad_number_blk;
3174 + int flash_scratch_pad_length;
3175 + unsigned long flash_scratch_pad_blk_offset;
3176 + int flash_nvram_start_blk;
3177 + int flash_nvram_number_blk;
3178 + int flash_nvram_length;
3179 + unsigned long flash_nvram_blk_offset;
3180 +} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO;
3181 +
3182 +// scratch pad defines
3183 +/* SP - Persisten Scratch Pad format:
3184 + sp header : 32 bytes
3185 + tokenId-1 : 8 bytes
3186 + tokenId-1 len : 4 bytes
3187 + tokenId-1 data
3188 + ....
3189 + tokenId-n : 8 bytes
3190 + tokenId-n len : 4 bytes
3191 + tokenId-n data
3192 +*/
3193 +
3194 +#define MAGIC_NUM_LEN 8
3195 +#define MAGIC_NUMBER "gOGoBrCm"
3196 +#define TOKEN_NAME_LEN 16
3197 +#define SP_VERSION 1
3198 +#define SP_MAX_LEN 8 * 1024 // 8k buf before psi
3199 +#define SP_RESERVERD 16
3200 +
3201 +typedef struct _SP_HEADER
3202 +{
3203 + char SPMagicNum[MAGIC_NUM_LEN]; // 8 bytes of magic number
3204 + int SPVersion; // version number
3205 + int SPUsedLen; // used sp len
3206 + char SPReserved[SP_RESERVERD]; // reservied, total 32 bytes
3207 +} SP_HEADER, *PSP_HEADER;
3208 +
3209 +typedef struct _TOKEN_DEF
3210 +{
3211 + char tokenName[TOKEN_NAME_LEN];
3212 + int tokenLen;
3213 +} SP_TOKEN, *PSP_TOKEN;
3214 +
3215 +
3216 +/*****************************************************************************/
3217 +/* Function Prototypes */
3218 +/*****************************************************************************/
3219 +#if !defined(__ASM_ASM_H)
3220 +void dumpaddr( unsigned char *pAddr, int nLen );
3221 +
3222 +void kerSysFlashAddrInfoGet(PFLASH_ADDR_INFO pflash_addr_info);
3223 +int kerSysNvRamGet(char *string, int strLen, int offset);
3224 +int kerSysNvRamSet(char *string, int strLen, int offset);
3225 +int kerSysPersistentGet(char *string, int strLen, int offset);
3226 +int kerSysPersistentSet(char *string, int strLen, int offset);
3227 +int kerSysScratchPadGet(char *tokName, char *tokBuf, int tokLen);
3228 +int kerSysScratchPadSet(char *tokName, char *tokBuf, int tokLen);
3229 +int kerSysBcmImageSet( int flash_start_addr, char *string, int size);
3230 +int kerSysGetMacAddress( unsigned char *pucaAddr, unsigned long ulId );
3231 +int kerSysReleaseMacAddress( unsigned char *pucaAddr );
3232 +int kerSysGetSdramSize( void );
3233 +void kerSysGetBootline(char *string, int strLen);
3234 +void kerSysSetBootline(char *string, int strLen);
3235 +void kerSysMipsSoftReset(void);
3236 +void kerSysLedCtrl(BOARD_LED_NAME, BOARD_LED_STATE);
3237 +void kerSysLedRegisterHwHandler( BOARD_LED_NAME, HANDLE_LED_FUNC, int );
3238 +int kerSysFlashSizeGet(void);
3239 +void kerSysRegisterDyingGaspHandler(char *devname, void *cbfn, void *context);
3240 +void kerSysDeregisterDyingGaspHandler(char *devname);
3241 +void kerSysWakeupMonitorTask( void );
3242 +#endif
3243 +
3244 +#if __cplusplus
3245 +}
3246 +#endif
3247 +
3248 +#endif /* _BOARD_H */
3249 +
Personal OpenWRT clone
This page took 0.200844 seconds and 5 git commands to generate.