update brcm-2.4 to 2.4.35.4, integrate new broadcom system code, update broadcom...
[openwrt.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / include / sbextif.h
1 /*
2 * Hardware-specific External Interface I/O core definitions
3 * for the BCM47xx family of SiliconBackplane-based chips.
4 *
5 * The External Interface core supports a total of three external chip selects
6 * supporting external interfaces. One of the external chip selects is
7 * used for Flash, one is used for PCMCIA, and the other may be
8 * programmed to support either a synchronous interface or an
9 * asynchronous interface. The asynchronous interface can be used to
10 * support external devices such as UARTs and the BCM2019 Bluetooth
11 * baseband processor.
12 * The external interface core also contains 2 on-chip 16550 UARTs, clock
13 * frequency control, a watchdog interrupt timer, and a GPIO interface.
14 *
15 * Copyright 2006, Broadcom Corporation
16 * All Rights Reserved.
17 *
18 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
20 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
21 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22 *
23 * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
24 */
25
26 #ifndef _SBEXTIF_H
27 #define _SBEXTIF_H
28
29 /* external interface address space */
30 #define EXTIF_PCMCIA_MEMBASE(x) (x)
31 #define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
32 #define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
33 #define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
34 #define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
35
36 /* cpp contortions to concatenate w/arg prescan */
37 #ifndef PAD
38 #define _PADLINE(line) pad ## line
39 #define _XSTR(line) _PADLINE(line)
40 #define PAD _XSTR(__LINE__)
41 #endif /* PAD */
42
43 /*
44 * The multiple instances of output and output enable registers
45 * are present to allow driver software for multiple cores to control
46 * gpio outputs without needing to share a single register pair.
47 */
48 struct gpiouser {
49 uint32 out;
50 uint32 outen;
51 };
52 #define NGPIOUSER 5
53
54 typedef volatile struct {
55 uint32 corecontrol;
56 uint32 extstatus;
57 uint32 PAD[2];
58
59 /* pcmcia control registers */
60 uint32 pcmcia_config;
61 uint32 pcmcia_memwait;
62 uint32 pcmcia_attrwait;
63 uint32 pcmcia_iowait;
64
65 /* programmable interface control registers */
66 uint32 prog_config;
67 uint32 prog_waitcount;
68
69 /* flash control registers */
70 uint32 flash_config;
71 uint32 flash_waitcount;
72 uint32 PAD[4];
73
74 uint32 watchdog;
75
76 /* clock control */
77 uint32 clockcontrol_n;
78 uint32 clockcontrol_sb;
79 uint32 clockcontrol_pci;
80 uint32 clockcontrol_mii;
81 uint32 PAD[3];
82
83 /* gpio */
84 uint32 gpioin;
85 struct gpiouser gpio[NGPIOUSER];
86 uint32 PAD;
87 uint32 ejtagouten;
88 uint32 gpiointpolarity;
89 uint32 gpiointmask;
90 uint32 PAD[153];
91
92 uint8 uartdata;
93 uint8 PAD[3];
94 uint8 uartimer;
95 uint8 PAD[3];
96 uint8 uartfcr;
97 uint8 PAD[3];
98 uint8 uartlcr;
99 uint8 PAD[3];
100 uint8 uartmcr;
101 uint8 PAD[3];
102 uint8 uartlsr;
103 uint8 PAD[3];
104 uint8 uartmsr;
105 uint8 PAD[3];
106 uint8 uartscratch;
107 uint8 PAD[3];
108 } extifregs_t;
109
110 /* corecontrol */
111 #define CC_UE (1 << 0) /* uart enable */
112
113 /* extstatus */
114 #define ES_EM (1 << 0) /* endian mode (ro) */
115 #define ES_EI (1 << 1) /* external interrupt pin (ro) */
116 #define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
117
118 /* gpio bit mask */
119 #define GPIO_BIT0 (1 << 0)
120 #define GPIO_BIT1 (1 << 1)
121 #define GPIO_BIT2 (1 << 2)
122 #define GPIO_BIT3 (1 << 3)
123 #define GPIO_BIT4 (1 << 4)
124 #define GPIO_BIT5 (1 << 5)
125 #define GPIO_BIT6 (1 << 6)
126 #define GPIO_BIT7 (1 << 7)
127
128
129 /* pcmcia/prog/flash_config */
130 #define CF_EN (1 << 0) /* enable */
131 #define CF_EM_MASK 0xe /* mode */
132 #define CF_EM_SHIFT 1
133 #define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
134 #define CF_EM_SYNC 0x2 /* synchronous mode */
135 #define CF_EM_PCMCIA 0x4 /* pcmcia mode */
136 #define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
137 #define CF_BS (1 << 5) /* byteswap */
138 #define CF_CD_MASK 0xc0 /* clock divider */
139 #define CF_CD_SHIFT 6
140 #define CF_CD_DIV2 0x0 /* backplane/2 */
141 #define CF_CD_DIV3 0x40 /* backplane/3 */
142 #define CF_CD_DIV4 0x80 /* backplane/4 */
143 #define CF_CE (1 << 8) /* clock enable */
144 #define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
145
146 /* pcmcia_memwait */
147 #define PM_W0_MASK 0x3f /* waitcount0 */
148 #define PM_W1_MASK 0x1f00 /* waitcount1 */
149 #define PM_W1_SHIFT 8
150 #define PM_W2_MASK 0x1f0000 /* waitcount2 */
151 #define PM_W2_SHIFT 16
152 #define PM_W3_MASK 0x1f000000 /* waitcount3 */
153 #define PM_W3_SHIFT 24
154
155 /* pcmcia_attrwait */
156 #define PA_W0_MASK 0x3f /* waitcount0 */
157 #define PA_W1_MASK 0x1f00 /* waitcount1 */
158 #define PA_W1_SHIFT 8
159 #define PA_W2_MASK 0x1f0000 /* waitcount2 */
160 #define PA_W2_SHIFT 16
161 #define PA_W3_MASK 0x1f000000 /* waitcount3 */
162 #define PA_W3_SHIFT 24
163
164 /* prog_waitcount */
165 #define PW_W0_MASK 0x0000001f /* waitcount0 */
166 #define PW_W1_MASK 0x00001f00 /* waitcount1 */
167 #define PW_W1_SHIFT 8
168 #define PW_W2_MASK 0x001f0000 /* waitcount2 */
169 #define PW_W2_SHIFT 16
170 #define PW_W3_MASK 0x1f000000 /* waitcount3 */
171 #define PW_W3_SHIFT 24
172
173 #define PW_W0 0x0000000c
174 #define PW_W1 0x00000a00
175 #define PW_W2 0x00020000
176 #define PW_W3 0x01000000
177
178 /* flash_waitcount */
179 #define FW_W0_MASK 0x1f /* waitcount0 */
180 #define FW_W1_MASK 0x1f00 /* waitcount1 */
181 #define FW_W1_SHIFT 8
182 #define FW_W2_MASK 0x1f0000 /* waitcount2 */
183 #define FW_W2_SHIFT 16
184 #define FW_W3_MASK 0x1f000000 /* waitcount3 */
185 #define FW_W3_SHIFT 24
186
187 /* watchdog */
188 #define WATCHDOG_CLOCK 48000000 /* Hz */
189
190 /* clockcontrol_n */
191 #define CN_N1_MASK 0x3f /* n1 control */
192 #define CN_N2_MASK 0x3f00 /* n2 control */
193 #define CN_N2_SHIFT 8
194
195 /* clockcontrol_sb/pci/mii */
196 #define CC_M1_MASK 0x3f /* m1 control */
197 #define CC_M2_MASK 0x3f00 /* m2 control */
198 #define CC_M2_SHIFT 8
199 #define CC_M3_MASK 0x3f0000 /* m3 control */
200 #define CC_M3_SHIFT 16
201 #define CC_MC_MASK 0x1f000000 /* mux control */
202 #define CC_MC_SHIFT 24
203
204 /* Clock control default values */
205 #define CC_DEF_N 0x0009 /* Default values for bcm4710 */
206 #define CC_DEF_100 0x04020011
207 #define CC_DEF_33 0x11030011
208 #define CC_DEF_25 0x11050011
209
210 /* Clock control values for 125Mhz */
211 #define CC_125_N 0x0802
212 #define CC_125_M 0x04020009
213 #define CC_125_M25 0x11090009
214 #define CC_125_M33 0x11090005
215
216 /* Clock control magic field values */
217 #define CC_F6_2 0x02 /* A factor of 2 in */
218 #define CC_F6_3 0x03 /* 6-bit fields like */
219 #define CC_F6_4 0x05 /* N1, M1 or M3 */
220 #define CC_F6_5 0x09
221 #define CC_F6_6 0x11
222 #define CC_F6_7 0x21
223
224 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
225
226 #define CC_MC_BYPASS 0x08
227 #define CC_MC_M1 0x04
228 #define CC_MC_M1M2 0x02
229 #define CC_MC_M1M2M3 0x01
230 #define CC_MC_M1M3 0x11
231
232 #define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
233
234 #endif /* _SBEXTIF_H */
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