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Simplify configure and add target optimizations,
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN kernel-base/arch/mips/ar7/ar7/jump.S kernel-current/arch/mips/ar7/ar7/jump.S
2 --- kernel-base/arch/mips/ar7/ar7/jump.S 1970-01-01 01:00:00.000000000 +0100
3 +++ kernel-current/arch/mips/ar7/ar7/jump.S 2005-07-10 06:40:39.582267000 +0200
4 @@ -0,0 +1,89 @@
5 +/*
6 + * $Id$
7 + * Copyright (C) $Date$ $Author$
8 + *
9 + * This program is free software; you can redistribute it and/or modify
10 + * it under the terms of the GNU General Public License as published by
11 + * the Free Software Foundation; either version 2 of the License, or
12 + * (at your option) any later version.
13 + *
14 + * This program is distributed in the hope that it will be useful,
15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 + * GNU General Public License for more details.
18 + *
19 + * You should have received a copy of the GNU General Public License
20 + * along with this program; if not, write to the Free Software
21 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 + *
23 + */
24 +
25 +#include <linux/config.h>
26 +#include <linux/threads.h>
27 +
28 +#include <asm/asm.h>
29 +#include <asm/cacheops.h>
30 +#include <asm/current.h>
31 +#include <asm/offset.h>
32 +#include <asm/processor.h>
33 +#include <asm/regdef.h>
34 +#include <asm/cachectl.h>
35 +#include <asm/mipsregs.h>
36 +#include <asm/stackframe.h>
37 +
38 +.text
39 +
40 +.set noreorder
41 +.set noat
42 +
43 +/* TLB Miss Vector */
44 +
45 +LEAF(jump_tlb_miss)
46 + .set mips2
47 + lui k0,0x9400
48 + ori k0,0
49 + jr k0
50 + nop
51 +END(jump_tlb_miss)
52 +
53 + /* Unused TLB Miss Vector */
54 +
55 +LEAF(jump_tlb_miss_unused)
56 + .set mips2
57 + lui k0,0x9400
58 + ori k0,0x80
59 + jr k0
60 + nop
61 +END(jump_tlb_miss_unused)
62 +
63 + /* Cache Error Vector */
64 +
65 +LEAF(jump_cache_error)
66 + .set mips2
67 + lui k0,0x9400
68 + ori k0,0x100
69 + jr k0
70 + nop
71 +END(jump_cache_error)
72 +
73 + /* General Exception */
74 +
75 +LEAF(jump_general_exception)
76 + .set mips2
77 + lui k0,0x9400
78 + ori k0,0x180
79 + jr k0
80 + nop
81 +END(jump_general_exception)
82 +
83 + /* Dedicated Interrupt */
84 +
85 +LEAF(jump_dedicated_interrupt)
86 + .set mips2
87 + lui k0,0x9400
88 + ori k0,0x200
89 + jr k0
90 + nop
91 +END(jump_dedicated_interrupt)
92 +
93 + .set at
94 diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile
95 --- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
96 +++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 17:46:24.037377984 +0200
97 @@ -0,0 +1,31 @@
98 +# $Id$
99 +# Copyright (C) $Date$ $Author$
100 +#
101 +# This program is free software; you can redistribute it and/or modify
102 +# it under the terms of the GNU General Public License as published by
103 +# the Free Software Foundation; either version 2 of the License, or
104 +# (at your option) any later version.
105 +#
106 +# This program is distributed in the hope that it will be useful,
107 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
108 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
109 +# GNU General Public License for more details.
110 +#
111 +# You should have received a copy of the GNU General Public License
112 +# along with this program; if not, write to the Free Software
113 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
114 +
115 +.S.s:
116 + $(CPP) $(AFLAGS) $< -o $*.s
117 +
118 +.S.o:
119 + $(CC) $(AFLAGS) -c $< -o $*.o
120 +
121 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
122 +
123 +O_TARGET := ar7.o
124 +
125 +export-objs := misc.o
126 +obj-y += paging.o jump.o misc.o
127 +
128 +include $(TOPDIR)/Rules.make
129 diff -urN kernel-base/arch/mips/ar7/ar7/misc.c kernel-current/arch/mips/ar7/ar7/misc.c
130 --- kernel-base/arch/mips/ar7/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
131 +++ kernel-current/arch/mips/ar7/ar7/misc.c 2005-07-10 19:02:11.699779472 +0200
132 @@ -0,0 +1,319 @@
133 +#include <asm/ar7/sangam.h>
134 +#include <asm/ar7/avalanche_misc.h>
135 +#include <linux/module.h>
136 +#include <linux/spinlock.h>
137 +
138 +#define TRUE 1
139 +
140 +static unsigned int avalanche_vbus_freq;
141 +
142 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
143 +
144 +/*****************************************************************************
145 + * Reset Control Module.
146 + *****************************************************************************/
147 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
148 + AVALANCHE_RESET_CTRL_T reset_ctrl)
149 +{
150 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
151 +
152 + if(module_reset_bit >= 32 && module_reset_bit < 64)
153 + return;
154 +
155 + if(module_reset_bit >= 64)
156 + {
157 + if(p_remote_vlynq_dev_reset_ctrl)
158 + return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
159 + else
160 + return;
161 + }
162 +
163 + if(reset_ctrl == OUT_OF_RESET)
164 + *reset_reg |= 1 << module_reset_bit;
165 + else
166 + *reset_reg &= ~(1 << module_reset_bit);
167 +}
168 +
169 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
170 +{
171 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
172 +
173 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
174 +}
175 +
176 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
177 +{
178 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
179 + *sw_reset_reg = mode;
180 +}
181 +
182 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
183 +
184 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
185 +{
186 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
187 +
188 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
189 +}
190 +
191 +
192 +/*****************************************************************************
193 + * Power Control Module
194 + *****************************************************************************/
195 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
196 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
197 +
198 +
199 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
200 +{
201 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
202 +
203 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
204 + /* power down the module */
205 + *power_reg |= (1 << module_power_bit);
206 + else
207 + /* power on the module */
208 + *power_reg &= (~(1 << module_power_bit));
209 +}
210 +
211 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
212 +{
213 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
214 +
215 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
216 +}
217 +
218 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
219 +{
220 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
221 +
222 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
223 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
224 +}
225 +
226 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
227 +{
228 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
229 +
230 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
231 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
232 +}
233 +
234 +/*****************************************************************************
235 + * GPIO Control
236 + *****************************************************************************/
237 +
238 +/****************************************************************************
239 + * FUNCTION: avalanche_gpio_init
240 + ***************************************************************************/
241 +void avalanche_gpio_init(void)
242 +{
243 + spinlock_t closeLock;
244 + unsigned int closeFlag;
245 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
246 + spin_lock_irqsave(&closeLock, closeFlag);
247 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
248 + spin_unlock_irqrestore(&closeLock, closeFlag);
249 +}
250 +
251 +/****************************************************************************
252 + * FUNCTION: avalanche_gpio_ctrl
253 + ***************************************************************************/
254 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
255 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
256 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
257 +{
258 + spinlock_t closeLock;
259 + unsigned int closeFlag;
260 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
261 +
262 + if(gpio_pin >= 32)
263 + return(-1);
264 +
265 + spin_lock_irqsave(&closeLock, closeFlag);
266 +
267 + if(pin_mode == GPIO_PIN)
268 + {
269 + *gpio_ctrl |= (1 << gpio_pin);
270 +
271 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
272 +
273 + if(pin_direction == GPIO_INPUT_PIN)
274 + *gpio_ctrl |= (1 << gpio_pin);
275 + else
276 + *gpio_ctrl &= ~(1 << gpio_pin);
277 + }
278 + else /* FUNCTIONAL PIN */
279 + {
280 + *gpio_ctrl &= ~(1 << gpio_pin);
281 + }
282 +
283 + spin_unlock_irqrestore(&closeLock, closeFlag);
284 +
285 + return (0);
286 +}
287 +
288 +/****************************************************************************
289 + * FUNCTION: avalanche_gpio_out
290 + ***************************************************************************/
291 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
292 +{
293 + spinlock_t closeLock;
294 + unsigned int closeFlag;
295 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
296 +
297 + if(gpio_pin >= 32)
298 + return(-1);
299 +
300 + spin_lock_irqsave(&closeLock, closeFlag);
301 + if(value == TRUE)
302 + *gpio_out |= 1 << gpio_pin;
303 + else
304 + *gpio_out &= ~(1 << gpio_pin);
305 + spin_unlock_irqrestore(&closeLock, closeFlag);
306 +
307 + return(0);
308 +}
309 +
310 +/****************************************************************************
311 + * FUNCTION: avalanche_gpio_in
312 + ***************************************************************************/
313 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
314 +{
315 + spinlock_t closeLock;
316 + unsigned int closeFlag;
317 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
318 + int ret_val = 0;
319 +
320 + if(gpio_pin >= 32)
321 + return(-1);
322 +
323 + spin_lock_irqsave(&closeLock, closeFlag);
324 + ret_val = ((*gpio_in) & (1 << gpio_pin));
325 + spin_unlock_irqrestore(&closeLock, closeFlag);
326 +
327 + return (ret_val);
328 +}
329 +
330 +/****************************************************************************
331 + * FUNCTION: avalanche_gpio_out_val
332 + ***************************************************************************/
333 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
334 + unsigned int reg_index)
335 +{
336 + spinlock_t closeLock;
337 + unsigned int closeFlag;
338 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
339 +
340 + if(reg_index > 0)
341 + return(-1);
342 +
343 + spin_lock_irqsave(&closeLock, closeFlag);
344 + *gpio_out &= ~out_mask;
345 + *gpio_out |= out_val;
346 + spin_unlock_irqrestore(&closeLock, closeFlag);
347 +
348 + return(0);
349 +}
350 +
351 +/****************************************************************************
352 + * FUNCTION: avalanche_gpio_in_value
353 + ***************************************************************************/
354 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
355 +{
356 + spinlock_t closeLock;
357 + unsigned int closeFlag;
358 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
359 +
360 + if(reg_index > 0)
361 + return(-1);
362 +
363 + spin_lock_irqsave(&closeLock, closeFlag);
364 + *in_val = *gpio_in;
365 + spin_unlock_irqrestore(&closeLock, closeFlag);
366 +
367 + return (0);
368 +}
369 +
370 +/***********************************************************************
371 + *
372 + * Wakeup Control Module for TNETV1050 Communication Processor
373 + *
374 + ***********************************************************************/
375 +
376 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
377 +
378 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
379 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
380 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
381 +{
382 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
383 +
384 + /* enable/disable */
385 + if (wakeup_ctrl == WAKEUP_ENABLED)
386 + /* enable wakeup */
387 + *wakeup_status_reg |= wakeup_int;
388 + else
389 + /* disable wakeup */
390 + *wakeup_status_reg &= (~wakeup_int);
391 +
392 + /* set polarity */
393 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
394 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
395 + else
396 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
397 +}
398 +
399 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
400 +{
401 + avalanche_vbus_freq = new_vbus_freq;
402 +}
403 +
404 +unsigned int avalanche_get_vbus_freq()
405 +{
406 + return(avalanche_vbus_freq);
407 +}
408 +
409 +unsigned int avalanche_get_chip_version_info()
410 +{
411 + return(*(volatile unsigned int*)AVALANCHE_CVR);
412 +}
413 +
414 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
415 +
416 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
417 +{
418 + if(p_set_mdix_on_chip_fn)
419 + return (p_set_mdix_on_chip_fn(base_addr, operation));
420 + else
421 + return(-1);
422 +}
423 +
424 +unsigned int avalanche_is_mdix_on_chip(void)
425 +{
426 + return(p_set_mdix_on_chip_fn ? 1:0);
427 +}
428 +
429 +EXPORT_SYMBOL(avalanche_reset_ctrl);
430 +EXPORT_SYMBOL(avalanche_get_reset_status);
431 +EXPORT_SYMBOL(avalanche_sys_reset);
432 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
433 +EXPORT_SYMBOL(avalanche_power_ctrl);
434 +EXPORT_SYMBOL(avalanche_get_power_status);
435 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
436 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
437 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
438 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
439 +
440 +EXPORT_SYMBOL(avalanche_gpio_init);
441 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
442 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
443 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
444 +EXPORT_SYMBOL(avalanche_gpio_out_value);
445 +EXPORT_SYMBOL(avalanche_gpio_in_value);
446 +
447 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
448 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
449 +
450 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
451 +
452 diff -urN kernel-base/arch/mips/ar7/ar7/paging.c kernel-current/arch/mips/ar7/ar7/paging.c
453 --- kernel-base/arch/mips/ar7/ar7/paging.c 1970-01-01 01:00:00.000000000 +0100
454 +++ kernel-current/arch/mips/ar7/ar7/paging.c 2005-07-10 07:08:33.725758000 +0200
455 @@ -0,0 +1,314 @@
456 +/*
457 + * -*- linux-c -*-
458 + * This file is subject to the terms and conditions of the GNU General Public
459 + * License. See the file "COPYING" in the main directory of this archive
460 + * for more details.
461 + *
462 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
463 + * Copyright (C) 2002 Texas Instruments, Inc.
464 + *
465 + */
466 +
467 +/*
468 + * This file takes care of the "memory hole" issue that exists with the standard
469 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
470 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
471 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
472 + *
473 + * -JAH
474 + */
475 +#include <linux/config.h>
476 +#include <linux/signal.h>
477 +#include <linux/sched.h>
478 +#include <linux/kernel.h>
479 +#include <linux/errno.h>
480 +#include <linux/string.h>
481 +#include <linux/types.h>
482 +#include <linux/ptrace.h>
483 +#include <linux/mman.h>
484 +#include <linux/mm.h>
485 +#include <linux/swap.h>
486 +#include <linux/smp.h>
487 +#include <linux/init.h>
488 +#ifdef CONFIG_BLK_DEV_INITRD
489 +#include <linux/blk.h>
490 +#endif /* CONFIG_BLK_DEV_INITRD */
491 +#include <linux/highmem.h>
492 +#include <linux/bootmem.h>
493 +
494 +#include <asm/processor.h>
495 +#include <asm/system.h>
496 +#include <asm/uaccess.h>
497 +#include <asm/pgtable.h>
498 +#include <asm/pgalloc.h>
499 +#include <asm/mmu_context.h>
500 +#include <asm/io.h>
501 +#include <asm/tlb.h>
502 +#include <asm/cpu.h>
503 +
504 +#define __MEMORY_START CONFIG_AR7_MEMORY
505 +
506 +#ifdef CONFIG_DISCONTIGMEM
507 +pg_data_t discontig_page_data[NR_NODES];
508 +bootmem_data_t discontig_node_bdata[NR_NODES];
509 +#endif
510 +
511 +static unsigned long totalram_pages;
512 +/* static unsigned long totalhigh_pages; */
513 +
514 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
515 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
516 +
517 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
518 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
519 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
520 +
521 +unsigned long bootmap_size;
522 +
523 +extern char *prom_getenv(char *envname);
524 +
525 +/*
526 + * We have upto 8 empty zeroed pages so we can map one of the right colour
527 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
528 + * where we have to avoid VCED / VECI exceptions for good performance at
529 + * any price. Since page is never written to after the initialization we
530 + * don't have to care about aliases on other CPUs.
531 + */
532 +
533 +static inline unsigned long setup_zero_pages(void)
534 +{
535 + unsigned long order, size;
536 + struct page *page;
537 + if(current_cpu_data.options & MIPS_CPU_VCE)
538 + order = 3;
539 + else
540 + order = 0;
541 +
542 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
543 +
544 + if (!empty_zero_page)
545 + panic("Oh boy, that early out of memory?");
546 +
547 + page = virt_to_page(empty_zero_page);
548 +
549 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
550 + set_bit(PG_reserved, &page->flags);
551 + set_page_count(page, 0);
552 + page++;
553 + }
554 +
555 + size = PAGE_SIZE << order;
556 + zero_page_mask = (size - 1) & PAGE_MASK;
557 + memset((void *)empty_zero_page, 0, size);
558 +
559 + return 1UL << order;
560 +}
561 +
562 +/*
563 + * paging_init() sets up the page tables
564 + *
565 + * This routines also unmaps the page at virtual kernel address 0, so
566 + * that we can trap those pesky NULL-reference errors in the kernel.
567 + */
568 +void __init paging_init(void)
569 +{
570 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
571 + unsigned long low, start_pfn;
572 +
573 + /* Initialize the entire pgd. */
574 + pgd_init((unsigned long)swapper_pg_dir);
575 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
576 +
577 +
578 + start_pfn = START_PFN;
579 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
580 + low = MAX_LOW_PFN;
581 +
582 + /* Avalanche DMA-able memory 0x14000000+memsize */
583 +
584 + zones_size[ZONE_DMA] = low - start_pfn;
585 +
586 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
587 +
588 +#ifdef CONFIG_DISCONTIGMEM
589 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
590 + zones_size[ZONE_NORMAL] = 0;
591 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
592 +#endif /* CONFIG_DISCONTIGMEM */
593 +
594 +}
595 +
596 +extern char _ftext, _etext, _fdata, _edata, _end;
597 +extern char __init_begin, __init_end;
598 +
599 +void __init mem_init(void)
600 +{
601 + int codesize, reservedpages, datasize, initsize;
602 + int tmp;
603 +
604 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
605 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
606 +
607 + /* free up the memory associated with Adam2 -
608 + * that is the, after the first page that is
609 + * reserved all the way up to the start of the kernel
610 + */
611 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
612 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
613 +
614 + /* this will put all low memory onto the freelists */
615 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
616 +
617 + /* Setup zeroed pages */
618 + totalram_pages -= setup_zero_pages();
619 +
620 +
621 +#ifdef CONFIG_DISCONTIGMEM
622 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
623 +#endif
624 + reservedpages = 0;
625 + for (tmp = 0; tmp < num_physpages; tmp++)
626 + /*
627 + * Only count reserved RAM pages
628 + */
629 + if (PageReserved(mem_map+tmp))
630 + reservedpages++;
631 +
632 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
633 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
634 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
635 +
636 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
637 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
638 + max_mapnr << (PAGE_SHIFT-10),
639 + codesize >> 10,
640 + reservedpages << (PAGE_SHIFT-10),
641 + datasize >> 10,
642 + initsize >> 10);
643 +
644 +}
645 +
646 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
647 +
648 +void avalanche_bootmem_init(void)
649 +{
650 + unsigned long start_pfn, max_pfn;
651 + unsigned long max_low_pfn;
652 + unsigned int memsize,memory_end,memory_start;
653 + char *memsize_str;
654 +
655 + memsize_str = prom_getenv("memsize");
656 + if (!memsize_str) {
657 + memsize = 0x02000000;
658 + } else {
659 + memsize = simple_strtol(memsize_str, NULL, 0);
660 + }
661 +
662 +
663 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
664 + memory_end = memory_start + memsize;
665 +
666 + /*
667 + * Find the highest memory page fram number we have available
668 + */
669 +
670 + max_pfn = PFN_DOWN(__pa(memory_end));
671 +
672 + /*
673 + * Determine the low and high memory ranges
674 + */
675 +
676 + max_low_pfn = max_pfn;
677 +
678 + /*
679 + * Partially used pages are not usable - thus we are
680 + * rounding upwards:
681 + */
682 +
683 + start_pfn = PFN_UP(__pa(&_end));
684 +
685 + /*
686 + * Find a proper area for the bootmem bitmap. After this
687 + * bootstrap step all allocations (until the page allocator is
688 + * intact) must be done via bootmem_alloc().
689 + */
690 +
691 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
692 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
693 +
694 +
695 + /*
696 + * Register fully available low RAM pages with the bootmem allocator.
697 + */
698 +
699 + {
700 + unsigned long curr_pfn, last_pfn, pages;
701 +
702 + /*
703 + * We are rounding up the start address of usable memory:
704 + */
705 + curr_pfn = PFN_UP(__MEMORY_START);
706 +
707 + /*
708 + * ... and at the end of the usable range downwards:
709 + */
710 + last_pfn = PFN_DOWN(__pa(memory_end));
711 +
712 + if (last_pfn > max_low_pfn)
713 + last_pfn = max_low_pfn;
714 +
715 + pages = last_pfn - curr_pfn;
716 +
717 +
718 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
719 + PFN_PHYS(pages));
720 + }
721 +
722 + /*
723 + * Reserve the kernel text and
724 + * Reserve the bootmem bitmap. We do this in two steps (first step
725 + * was init_bootmem()), because this catches the (definitely buggy)
726 + * case of us accidentally initializing the bootmem allocator with
727 + * an invalid RAM area.
728 + */
729 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
730 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
731 +
732 + /*
733 + * reserve physical page 0 - it's a special BIOS page on many boxes,
734 + * enabling clean reboots, SMP operation, laptop functions.
735 + */
736 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
737 +}
738 +
739 +extern char __init_begin, __init_end;
740 +
741 +void free_initmem(void)
742 +{
743 + unsigned long addr;
744 + // prom_free_prom_memory ();
745 +
746 + addr = (unsigned long) &__init_begin;
747 + while (addr < (unsigned long) &__init_end) {
748 + ClearPageReserved(virt_to_page(addr));
749 + set_page_count(virt_to_page(addr), 1);
750 + free_page(addr);
751 + totalram_pages++;
752 + addr += PAGE_SIZE;
753 + }
754 + printk("Freeing unused kernel memory: %dk freed\n",
755 + (&__init_end - &__init_begin) >> 10);
756 +}
757 +
758 +void si_meminfo(struct sysinfo *val)
759 +{
760 + val->totalram = totalram_pages;
761 + val->sharedram = 0;
762 + val->freeram = nr_free_pages();
763 + val->bufferram = atomic_read(&buffermem_pages);
764 + val->totalhigh = 0;
765 + val->freehigh = nr_free_highpages();
766 + val->mem_unit = PAGE_SIZE;
767 +
768 + return;
769 +}
770 diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-current/arch/mips/ar7/cmdline.c
771 --- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
772 +++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266000 +0200
773 @@ -0,0 +1,64 @@
774 +/*
775 + * Carsten Langgaard, carstenl@mips.com
776 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
777 + *
778 + * This program is free software; you can distribute it and/or modify it
779 + * under the terms of the GNU General Public License (Version 2) as
780 + * published by the Free Software Foundation.
781 + *
782 + * This program is distributed in the hope it will be useful, but WITHOUT
783 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
784 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
785 + * for more details.
786 + *
787 + * You should have received a copy of the GNU General Public License along
788 + * with this program; if not, write to the Free Software Foundation, Inc.,
789 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
790 + *
791 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
792 + */
793 +#include <linux/init.h>
794 +#include <linux/string.h>
795 +
796 +#include <asm/bootinfo.h>
797 +
798 +extern int prom_argc;
799 +extern int *_prom_argv;
800 +
801 +/*
802 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
803 + * This macro take care of sign extension.
804 + */
805 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
806 +
807 +char arcs_cmdline[CL_SIZE];
808 +
809 +char * __init prom_getcmdline(void)
810 +{
811 + return &(arcs_cmdline[0]);
812 +}
813 +
814 +
815 +void __init prom_init_cmdline(void)
816 +{
817 + char *cp;
818 + int actr;
819 +
820 + actr = 1; /* Always ignore argv[0] */
821 +
822 + cp = &(arcs_cmdline[0]);
823 +#ifdef CONFIG_CMDLINE_BOOL
824 + strcpy(cp, CONFIG_CMDLINE);
825 + cp += strlen(CONFIG_CMDLINE);
826 + *cp++ = ' ';
827 +#endif
828 + while(actr < prom_argc) {
829 + strcpy(cp, prom_argv(actr));
830 + cp += strlen(prom_argv(actr));
831 + *cp++ = ' ';
832 + actr++;
833 + }
834 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
835 + --cp;
836 + *cp = '\0';
837 +}
838 diff -urN kernel-base/arch/mips/ar7/init.c kernel-current/arch/mips/ar7/init.c
839 --- kernel-base/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
840 +++ kernel-current/arch/mips/ar7/init.c 2005-07-10 17:53:38.565319696 +0200
841 @@ -0,0 +1,144 @@
842 +/*
843 + * Carsten Langgaard, carstenl@mips.com
844 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
845 + *
846 + * This program is free software; you can distribute it and/or modify it
847 + * under the terms of the GNU General Public License (Version 2) as
848 + * published by the Free Software Foundation.
849 + *
850 + * This program is distributed in the hope it will be useful, but WITHOUT
851 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
852 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
853 + * for more details.
854 + *
855 + * You should have received a copy of the GNU General Public License along
856 + * with this program; if not, write to the Free Software Foundation, Inc.,
857 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
858 + *
859 + * PROM library initialisation code.
860 + */
861 +#include <linux/config.h>
862 +#include <linux/init.h>
863 +#include <linux/string.h>
864 +#include <linux/kernel.h>
865 +#include <linux/module.h>
866 +
867 +#include <asm/io.h>
868 +#include <asm/mips-boards/prom.h>
869 +#include <asm/mips-boards/generic.h>
870 +
871 +/* Environment variable */
872 +typedef struct {
873 + char *name;
874 + char *val;
875 +} t_env_var;
876 +
877 +int prom_argc;
878 +int *_prom_argv, *_prom_envp;
879 +
880 +/* max # of Adam2 environment variables */
881 +#define MAX_ENV_ENTRY 80
882 +
883 +static t_env_var local_envp[MAX_ENV_ENTRY];
884 +int init_debug = 0;
885 +
886 +char *prom_getenv(char *envname)
887 +{
888 + /*
889 + * Return a pointer to the given environment variable.
890 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
891 + * in the PROM structures are only 32-bit, so we need some
892 + * workarounds, if we are running in 64-bit mode.
893 + */
894 + int i, index=0;
895 + t_env_var *env = (t_env_var *) local_envp;
896 +
897 + i = strlen(envname);
898 + while (env->name) {
899 + if(strncmp(envname, env->name, i) == 0) {
900 + return(env->val);
901 + }
902 + env++;
903 + }
904 +
905 + return NULL;
906 +}
907 +
908 +static inline unsigned char str2hexnum(unsigned char c)
909 +{
910 + if (c >= '0' && c <= '9')
911 + return c - '0';
912 + if (c >= 'a' && c <= 'f')
913 + return c - 'a' + 10;
914 + return 0; /* foo */
915 +}
916 +
917 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
918 +{
919 + int i;
920 +
921 + for (i = 0; i < 6; i++) {
922 + unsigned char num;
923 +
924 + if((*str == '.') || (*str == ':'))
925 + str++;
926 + num = str2hexnum(*str++) << 4;
927 + num |= (str2hexnum(*str++));
928 + ea[i] = num;
929 + }
930 +}
931 +
932 +int get_ethernet_addr(char *ethernet_addr)
933 +{
934 + char *ethaddr_str;
935 +
936 + ethaddr_str = prom_getenv("ethaddr");
937 + if (!ethaddr_str) {
938 + printk("ethaddr not set in boot prom\n");
939 + return -1;
940 + }
941 + str2eaddr(ethernet_addr, ethaddr_str);
942 +
943 + if (init_debug > 1) {
944 + int i;
945 + printk("get_ethernet_addr: ");
946 + for (i=0; i<5; i++)
947 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
948 + printk("%02x\n", *(ethernet_addr+i));
949 + }
950 +
951 + return 0;
952 +}
953 +
954 +int __init prom_init(int argc, char **argv, char **envp)
955 +{
956 + int i;
957 + t_env_var *env = (t_env_var *) envp;
958 +
959 + prom_argc = argc;
960 + _prom_argv = (int *)argv;
961 + _prom_envp = (int *)envp;
962 +
963 + /* Copy what we need locally so we are not dependent on
964 + * bootloader RAM. In Adam2, the environment parameters
965 + * are in flash but the table that references them is in
966 + * RAM
967 + */
968 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
969 + if (env->name) {
970 + local_envp[i].name = env->name;
971 + local_envp[i].val = env->val;
972 + } else {
973 + local_envp[i].name = NULL;
974 + local_envp[i].val = NULL;
975 + }
976 + }
977 +
978 + set_io_port_base(0);
979 +
980 + prom_printf("\nLINUX started...\n");
981 + prom_init_cmdline();
982 + prom_meminit();
983 +
984 + return 0;
985 +}
986 diff -urN kernel-base/arch/mips/ar7/irq.c kernel-current/arch/mips/ar7/irq.c
987 --- kernel-base/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
988 +++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 17:53:17.841470200 +0200
989 @@ -0,0 +1,705 @@
990 +/*
991 + * Nitin Dhingra, iamnd@ti.com
992 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
993 + *
994 + * ########################################################################
995 + *
996 + * This program is free software; you can distribute it and/or modify it
997 + * under the terms of the GNU General Public License (Version 2) as
998 + * published by the Free Software Foundation.
999 + *
1000 + * This program is distributed in the hope it will be useful, but WITHOUT
1001 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1002 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1003 + * for more details.
1004 + *
1005 + * You should have received a copy of the GNU General Public License along
1006 + * with this program; if not, write to the Free Software Foundation, Inc.,
1007 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1008 + *
1009 + * ########################################################################
1010 + *
1011 + * Routines for generic manipulation of the interrupts found on the Texas
1012 + * Instruments avalanche board
1013 + *
1014 + */
1015 +
1016 +#include <linux/config.h>
1017 +#include <linux/init.h>
1018 +#include <linux/sched.h>
1019 +#include <linux/slab.h>
1020 +#include <linux/interrupt.h>
1021 +#include <linux/kernel_stat.h>
1022 +#include <linux/proc_fs.h>
1023 +#include <asm/irq.h>
1024 +#include <asm/mips-boards/prom.h>
1025 +#include <asm/ar7/ar7.h>
1026 +#include <asm/ar7/avalanche_intc.h>
1027 +#include <asm/gdb-stub.h>
1028 +
1029 +
1030 +#define shutdown_avalanche_irq disable_avalanche_irq
1031 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
1032 +
1033 +static unsigned int startup_avalanche_irq(unsigned int irq);
1034 +static void end_avalanche_irq(unsigned int irq);
1035 +void enable_avalanche_irq(unsigned int irq_nr);
1036 +void disable_avalanche_irq(unsigned int irq_nr);
1037 +
1038 +static struct hw_interrupt_type avalanche_irq_type = {
1039 + "TI AVALANCHE",
1040 + startup_avalanche_irq,
1041 + shutdown_avalanche_irq,
1042 + enable_avalanche_irq,
1043 + disable_avalanche_irq,
1044 + mask_and_ack_avalanche_irq,
1045 + end_avalanche_irq,
1046 + NULL
1047 +};
1048 +
1049 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
1050 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
1051 +
1052 +
1053 +unsigned long spurious_count = 0;
1054 +
1055 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
1056 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
1057 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
1058 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
1059 +
1060 +extern asmlinkage void mipsIRQ(void);
1061 +
1062 +
1063 +/*
1064 + * The avalanche/MIPS interrupt line numbers are used to represent the
1065 + * interrupts within the irqaction arrays. The index notation is
1066 + * is as follows:
1067 + *
1068 + * 0-7 MIPS CPU Exceptions (HW/SW)
1069 + * 8-47 Primary Interrupts (Avalanche)
1070 + * 48-79 Secondary Interrupts (Avalanche)
1071 + *
1072 + */
1073 +
1074 +
1075 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
1076 +{
1077 + NULL, NULL, NULL, NULL,
1078 + NULL, NULL, NULL, NULL,
1079 + NULL, NULL, NULL, NULL,
1080 + NULL, NULL, NULL, NULL,
1081 + NULL, NULL, NULL, NULL,
1082 + NULL, NULL, NULL, NULL,
1083 + NULL, NULL, NULL, NULL,
1084 + NULL, NULL, NULL, NULL,
1085 + NULL, NULL, NULL, NULL,
1086 + NULL, NULL, NULL, NULL
1087 +};
1088 +
1089 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
1090 +{
1091 + NULL, NULL, NULL, NULL,
1092 + NULL, NULL, NULL, NULL,
1093 + NULL, NULL, NULL, NULL,
1094 + NULL, NULL, NULL, NULL,
1095 + NULL, NULL, NULL, NULL,
1096 + NULL, NULL, NULL, NULL,
1097 + NULL, NULL, NULL, NULL,
1098 + NULL, NULL, NULL, NULL
1099 +};
1100 +
1101 +/*
1102 + This remaps interrupts to exist on other channels than the default
1103 + channels. essentially we can use the line # as the index for this
1104 + array
1105 + */
1106 +
1107 +
1108 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1109 +unsigned long uni_secondary_interrupt = 0;
1110 +
1111 +static struct irqaction r4ktimer_action = {
1112 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
1113 +};
1114 +
1115 +static struct irqaction *irq_action[8] = {
1116 + NULL, /* SW int 0 */
1117 + NULL, /* SW int 1 */
1118 + NULL, /* HW int 0 */
1119 + NULL,
1120 + NULL,
1121 + NULL, /* HW int 3 */
1122 + NULL, /* HW int 4 */
1123 + &r4ktimer_action /* HW int 5 */
1124 +};
1125 +
1126 +static void end_avalanche_irq(unsigned int irq)
1127 +{
1128 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1129 + enable_avalanche_irq(irq);
1130 +}
1131 +
1132 +void disable_avalanche_irq(unsigned int irq_nr)
1133 +{
1134 + unsigned long flags;
1135 + unsigned long chan_nr=0;
1136 + unsigned long int_bit=0;
1137 +
1138 + if(irq_nr >= AVALANCHE_INT_END)
1139 + {
1140 + printk("whee, invalid irq_nr %d\n", irq_nr);
1141 + panic("IRQ, you lose...");
1142 + }
1143 +
1144 + save_and_cli(flags);
1145 +
1146 +
1147 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1148 + {
1149 + /* disable mips exception */
1150 +
1151 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
1152 + change_c0_status(ST0_IM,int_bit);
1153 + restore_flags(flags);
1154 + return;
1155 + }
1156 +
1157 + /* irq_nr represents the line number for the interrupt. We must
1158 + * disable the channel number associated with that line number.
1159 + */
1160 +
1161 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1162 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
1163 + else
1164 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
1165 +
1166 + /* disable the interrupt channel bit */
1167 +
1168 + /* primary interrupt #'s 0-31 */
1169 +
1170 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1171 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
1172 +
1173 + /* primary interrupt #'s 32-39 */
1174 +
1175 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1176 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1177 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1178 +
1179 + else /* secondary interrupt #'s 0-31 */
1180 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1181 +
1182 + restore_flags(flags);
1183 +}
1184 +
1185 +void enable_avalanche_irq(unsigned int irq_nr)
1186 +{
1187 + unsigned long flags;
1188 + unsigned long chan_nr=0;
1189 + unsigned long int_bit=0;
1190 +
1191 + if(irq_nr > AVALANCHE_INT_END) {
1192 + printk("whee, invalid irq_nr %d\n", irq_nr);
1193 + panic("IRQ, you lose...");
1194 + }
1195 +
1196 + save_and_cli(flags);
1197 +
1198 +
1199 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1200 + {
1201 + /* Enable MIPS exceptions */
1202 + int_bit = read_c0_status();
1203 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
1204 + restore_flags(flags);
1205 + return;
1206 + }
1207 +
1208 + /* irq_nr represents the line number for the interrupt. We must
1209 + * disable the channel number associated with that line number.
1210 + */
1211 +
1212 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1213 + chan_nr = AVINTNUM(irq_nr);
1214 + else
1215 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
1216 +
1217 + /* enable the interrupt channel bit */
1218 +
1219 + /* primary interrupt #'s 0-31 */
1220 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1221 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
1222 +
1223 + /* primary interrupt #'s 32 throuth 39 */
1224 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1225 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1226 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1227 +
1228 + else /* secondary interrupt #'s 0-31 */
1229 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1230 +
1231 + restore_flags(flags);
1232 +}
1233 +
1234 +static unsigned int startup_avalanche_irq(unsigned int irq)
1235 +{
1236 + enable_avalanche_irq(irq);
1237 + return 0; /* never anything pending */
1238 +}
1239 +
1240 +
1241 +int get_irq_list(char *buf)
1242 +{
1243 + int i, len = 0;
1244 + int num = 0;
1245 + struct irqaction *action;
1246 +
1247 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
1248 + {
1249 + action = irq_action[i];
1250 + if (!action)
1251 + continue;
1252 + len += sprintf(buf+len, "%2d: %8d %c %s",
1253 + num, kstat.irqs[0][num],
1254 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1255 + action->name);
1256 + for (action=action->next; action; action = action->next) {
1257 + len += sprintf(buf+len, ",%s %s",
1258 + (action->flags & SA_INTERRUPT) ? " +" : "",
1259 + action->name);
1260 + }
1261 + len += sprintf(buf+len, " [MIPS interrupt]\n");
1262 + }
1263 +
1264 +
1265 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
1266 + {
1267 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1268 + action = hw0_irq_action_primary[i];
1269 + else
1270 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1271 + if (!action)
1272 + continue;
1273 + len += sprintf(buf+len, "%2d: %8d %c %s",
1274 + num, kstat.irqs[0][ LNXINTNUM(i) ],
1275 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1276 + action->name);
1277 +
1278 + for (action=action->next; action; action = action->next)
1279 + {
1280 + len += sprintf(buf+len, ",%s %s",
1281 + (action->flags & SA_INTERRUPT) ? " +" : "",
1282 + action->name);
1283 + }
1284 +
1285 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1286 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
1287 + else
1288 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
1289 +
1290 + }
1291 +
1292 + return len;
1293 +}
1294 +
1295 +int request_irq(unsigned int irq,
1296 + void (*handler)(int, void *, struct pt_regs *),
1297 + unsigned long irqflags,
1298 + const char * devname,
1299 + void *dev_id)
1300 +{
1301 + struct irqaction *action;
1302 +
1303 + if (irq > AVALANCHE_INT_END)
1304 + return -EINVAL;
1305 + if (!handler)
1306 + return -EINVAL;
1307 +
1308 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
1309 + if(!action)
1310 + return -ENOMEM;
1311 +
1312 + action->handler = handler;
1313 + action->flags = irqflags;
1314 + action->mask = 0;
1315 + action->name = devname;
1316 + irq_desc_ti[irq].action = action;
1317 + action->dev_id = dev_id;
1318 +
1319 + action->next = 0;
1320 +
1321 + if(irq < MIPS_EXCEPTION_OFFSET)
1322 + {
1323 + irq_action[irq] = action;
1324 + enable_avalanche_irq(irq);
1325 + return 0;
1326 + }
1327 +
1328 + if(irq < AVALANCHE_INT_END_PRIMARY)
1329 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1330 + else
1331 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1332 +
1333 + enable_avalanche_irq(irq);
1334 +
1335 + return 0;
1336 +}
1337 +
1338 +void free_irq(unsigned int irq, void *dev_id)
1339 +{
1340 + struct irqaction *action;
1341 +
1342 + if (irq > AVALANCHE_INT_END) {
1343 + printk("Trying to free IRQ%d\n",irq);
1344 + return;
1345 + }
1346 +
1347 + if(irq < MIPS_EXCEPTION_OFFSET)
1348 + {
1349 + action = irq_action[irq];
1350 + irq_action[irq] = NULL;
1351 + irq_desc_ti[irq].action = NULL;
1352 + disable_avalanche_irq(irq);
1353 + kfree(action);
1354 + return;
1355 + }
1356 +
1357 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1358 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1359 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1360 + irq_desc_ti[irq].action = NULL;
1361 + }
1362 + else {
1363 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1364 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1365 + irq_desc_ti[irq].action = NULL;
1366 + }
1367 +
1368 + disable_avalanche_irq(irq);
1369 + kfree(action);
1370 +}
1371 +
1372 +#ifdef CONFIG_KGDB
1373 +extern void breakpoint(void);
1374 +extern int remote_debug;
1375 +#endif
1376 +
1377 +//void init_IRQ(void) __init;
1378 +void __init init_IRQ(void)
1379 +{
1380 + int i;
1381 +
1382 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1383 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1384 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1385 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1386 +
1387 + /* Disable interrupts and clear pending
1388 + */
1389 +
1390 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1391 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1392 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1393 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1394 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1395 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1396 +
1397 +
1398 + /* Channel to line mapping, Line to Channel mapping */
1399 +
1400 + for(i = 0; i < 40; i++)
1401 + avalanche_int_set(i,i);
1402 +
1403 + /* Now safe to set the exception vector. */
1404 + set_except_vector(0, mipsIRQ);
1405 +
1406 + /* Setup the IRQ description array. These will be mapped
1407 + * as flat interrupts numbers. The mapping is as follows
1408 + *
1409 + * 0-7 MIPS CPU Exceptions (HW/SW)
1410 + * 8-46 Primary Interrupts (Avalanche)
1411 + * 47-78 Secondary Interrupts (Avalanche)
1412 + */
1413 +
1414 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1415 + {
1416 + irq_desc_ti[i].status = IRQ_DISABLED;
1417 + irq_desc_ti[i].action = 0;
1418 + irq_desc_ti[i].depth = 1;
1419 + irq_desc_ti[i].handler = &avalanche_irq_type;
1420 + }
1421 +
1422 +#ifdef CONFIG_KGDB
1423 + if (remote_debug)
1424 + {
1425 + set_debug_traps();
1426 + breakpoint();
1427 + }
1428 +#endif
1429 +}
1430 +
1431 +
1432 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1433 +{
1434 + struct irqaction *action;
1435 + int irq, cpu = smp_processor_id();
1436 + unsigned long int_line_number,status;
1437 + int i,secondary = 0;
1438 + int chan_nr=0;
1439 +
1440 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1441 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1442 +
1443 +
1444 + if(chan_nr < 32)
1445 + {
1446 + if( chan_nr != uni_secondary_interrupt)
1447 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1448 +
1449 + }
1450 +
1451 + if((chan_nr < 40) && (chan_nr > 31))
1452 + {
1453 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1454 + }
1455 +
1456 +
1457 + /* If the Priority Interrupt Index Register returns 40 then no
1458 + * interrupts are pending
1459 + */
1460 +
1461 + if(chan_nr == 40)
1462 + return;
1463 +
1464 + if(chan_nr == uni_secondary_interrupt)
1465 + {
1466 + status = avalanche_hw0_ecregs->exsr;
1467 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1468 + {
1469 + if (status & 1<<i)
1470 + {
1471 + /* clear secondary interrupt */
1472 + avalanche_hw0_ecregs->excr = 1 << i;
1473 + break;
1474 + }
1475 + }
1476 + irq = i;
1477 + secondary = 1;
1478 +
1479 + /* clear the universal secondary interrupt */
1480 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1481 +
1482 + }
1483 + else
1484 + irq = chan_nr;
1485 +
1486 + /* Suraj Add code to clear secondary interrupt */
1487 +
1488 + if(secondary)
1489 + action = hw0_irq_action_secondary[irq];
1490 + else
1491 + action = hw0_irq_action_primary[irq];
1492 +
1493 + /* if action == NULL, then we don't have a handler for the irq */
1494 +
1495 + if ( action == NULL ) {
1496 + printk("No handler for hw0 irq: %i\n", irq);
1497 + return;
1498 + }
1499 +
1500 + irq_enter(cpu,irq);
1501 + if(secondary)
1502 + {
1503 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1504 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1505 + }
1506 + else
1507 + {
1508 + kstat.irqs[0][irq + 8]++;
1509 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1510 + }
1511 +
1512 + irq_exit(cpu,irq);
1513 +
1514 + if(softirq_pending(cpu))
1515 + do_softirq();
1516 +
1517 + return;
1518 +}
1519 +
1520 +void avalanche_int_set(int channel, int line)
1521 +{
1522 + switch(channel)
1523 + {
1524 + case(0):
1525 + avalanche_hw0_chregs->cintnr0 = line;
1526 + break;
1527 + case(1):
1528 + avalanche_hw0_chregs->cintnr1 = line;
1529 + break;
1530 + case(2):
1531 + avalanche_hw0_chregs->cintnr2 = line;
1532 + break;
1533 + case(3):
1534 + avalanche_hw0_chregs->cintnr3 = line;
1535 + break;
1536 + case(4):
1537 + avalanche_hw0_chregs->cintnr4 = line;
1538 + break;
1539 + case(5):
1540 + avalanche_hw0_chregs->cintnr5 = line;
1541 + break;
1542 + case(6):
1543 + avalanche_hw0_chregs->cintnr6 = line;
1544 + break;
1545 + case(7):
1546 + avalanche_hw0_chregs->cintnr7 = line;
1547 + break;
1548 + case(8):
1549 + avalanche_hw0_chregs->cintnr8 = line;
1550 + break;
1551 + case(9):
1552 + avalanche_hw0_chregs->cintnr9 = line;
1553 + break;
1554 + case(10):
1555 + avalanche_hw0_chregs->cintnr10 = line;
1556 + break;
1557 + case(11):
1558 + avalanche_hw0_chregs->cintnr11 = line;
1559 + break;
1560 + case(12):
1561 + avalanche_hw0_chregs->cintnr12 = line;
1562 + break;
1563 + case(13):
1564 + avalanche_hw0_chregs->cintnr13 = line;
1565 + break;
1566 + case(14):
1567 + avalanche_hw0_chregs->cintnr14 = line;
1568 + break;
1569 + case(15):
1570 + avalanche_hw0_chregs->cintnr15 = line;
1571 + break;
1572 + case(16):
1573 + avalanche_hw0_chregs->cintnr16 = line;
1574 + break;
1575 + case(17):
1576 + avalanche_hw0_chregs->cintnr17 = line;
1577 + break;
1578 + case(18):
1579 + avalanche_hw0_chregs->cintnr18 = line;
1580 + break;
1581 + case(19):
1582 + avalanche_hw0_chregs->cintnr19 = line;
1583 + break;
1584 + case(20):
1585 + avalanche_hw0_chregs->cintnr20 = line;
1586 + break;
1587 + case(21):
1588 + avalanche_hw0_chregs->cintnr21 = line;
1589 + break;
1590 + case(22):
1591 + avalanche_hw0_chregs->cintnr22 = line;
1592 + break;
1593 + case(23):
1594 + avalanche_hw0_chregs->cintnr23 = line;
1595 + break;
1596 + case(24):
1597 + avalanche_hw0_chregs->cintnr24 = line;
1598 + break;
1599 + case(25):
1600 + avalanche_hw0_chregs->cintnr25 = line;
1601 + break;
1602 + case(26):
1603 + avalanche_hw0_chregs->cintnr26 = line;
1604 + break;
1605 + case(27):
1606 + avalanche_hw0_chregs->cintnr27 = line;
1607 + break;
1608 + case(28):
1609 + avalanche_hw0_chregs->cintnr28 = line;
1610 + break;
1611 + case(29):
1612 + avalanche_hw0_chregs->cintnr29 = line;
1613 + break;
1614 + case(30):
1615 + avalanche_hw0_chregs->cintnr30 = line;
1616 + break;
1617 + case(31):
1618 + avalanche_hw0_chregs->cintnr31 = line;
1619 + break;
1620 + case(32):
1621 + avalanche_hw0_chregs->cintnr32 = line;
1622 + break;
1623 + case(33):
1624 + avalanche_hw0_chregs->cintnr33 = line;
1625 + break;
1626 + case(34):
1627 + avalanche_hw0_chregs->cintnr34 = line;
1628 + break;
1629 + case(35):
1630 + avalanche_hw0_chregs->cintnr35 = line;
1631 + break;
1632 + case(36):
1633 + avalanche_hw0_chregs->cintnr36 = line;
1634 + break;
1635 + case(37):
1636 + avalanche_hw0_chregs->cintnr37 = line;
1637 + break;
1638 + case(38):
1639 + avalanche_hw0_chregs->cintnr38 = line;
1640 + break;
1641 + case(39):
1642 + avalanche_hw0_chregs->cintnr39 = line;
1643 + break;
1644 + default:
1645 + printk("Error: Unknown Avalanche interrupt channel\n");
1646 + }
1647 +
1648 + line_to_channel[line] = channel; /* Suraj check */
1649 +
1650 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1651 + uni_secondary_interrupt = line;
1652 +
1653 +}
1654 +
1655 +
1656 +#define AVALANCHE_MAX_PACING_BLK 3
1657 +#define AVALANCHE_PACING_LOW_VAL 2
1658 +#define AVALANCHE_PACING_HIGH_VAL 63
1659 +
1660 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
1661 + unsigned int pace_value)
1662 +{
1663 + unsigned int blk_offset;
1664 + unsigned long flags;
1665 +
1666 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
1667 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
1668 + return (0);
1669 +
1670 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
1671 + return(-1);
1672 +
1673 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
1674 + pace_value < AVALANCHE_PACING_LOW_VAL)
1675 + return(-1);
1676 +
1677 + blk_offset = blk_num*8;
1678 +
1679 + save_and_cli(flags);
1680 +
1681 + /* disable the interrupt pacing, if enabled previously */
1682 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
1683 +
1684 + /* clear the pacing map */
1685 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
1686 +
1687 + /* setup the new values */
1688 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
1689 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
1690 +
1691 + restore_flags(flags);
1692 +
1693 + return(0);
1694 +}
1695 diff -urN kernel-base/arch/mips/ar7/Makefile kernel-current/arch/mips/ar7/Makefile
1696 --- kernel-base/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
1697 +++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 17:53:46.635092904 +0200
1698 @@ -0,0 +1,28 @@
1699 +# $Id$
1700 +# Copyright (C) $Date$ $Author$
1701 +#
1702 +# This program is free software; you can redistribute it and/or modify
1703 +# it under the terms of the GNU General Public License as published by
1704 +# the Free Software Foundation; either version 2 of the License, or
1705 +# (at your option) any later version.
1706 +#
1707 +# This program is distributed in the hope that it will be useful,
1708 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
1709 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1710 +# GNU General Public License for more details.
1711 +#
1712 +# You should have received a copy of the GNU General Public License
1713 +# along with this program; if not, write to the Free Software
1714 +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
1715 +
1716 +.S.s:
1717 + $(CPP) $(AFLAGS) $< -o $*.s
1718 +
1719 +.S.o:
1720 + $(CC) $(AFLAGS) -c $< -o $*.o
1721 +
1722 +O_TARGET := ar7.o
1723 +
1724 +obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
1725 +
1726 +include $(TOPDIR)/Rules.make
1727 diff -urN kernel-base/arch/mips/ar7/memory.c kernel-current/arch/mips/ar7/memory.c
1728 --- kernel-base/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1729 +++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266000 +0200
1730 @@ -0,0 +1,130 @@
1731 +/*
1732 + * Carsten Langgaard, carstenl@mips.com
1733 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1734 + *
1735 + * ########################################################################
1736 + *
1737 + * This program is free software; you can distribute it and/or modify it
1738 + * under the terms of the GNU General Public License (Version 2) as
1739 + * published by the Free Software Foundation.
1740 + *
1741 + * This program is distributed in the hope it will be useful, but WITHOUT
1742 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1743 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1744 + * for more details.
1745 + *
1746 + * You should have received a copy of the GNU General Public License along
1747 + * with this program; if not, write to the Free Software Foundation, Inc.,
1748 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1749 + *
1750 + * ########################################################################
1751 + *
1752 + * PROM library functions for acquiring/using memory descriptors given to
1753 + * us from the YAMON.
1754 + *
1755 + */
1756 +#include <linux/config.h>
1757 +#include <linux/init.h>
1758 +#include <linux/mm.h>
1759 +#include <linux/bootmem.h>
1760 +
1761 +#include <asm/bootinfo.h>
1762 +#include <asm/page.h>
1763 +#include <asm/mips-boards/prom.h>
1764 +#include <asm/ar7/ar7.h>
1765 +
1766 +enum yamon_memtypes {
1767 + yamon_dontuse,
1768 + yamon_prom,
1769 + yamon_free,
1770 +};
1771 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1772 +
1773 +/* References to section boundaries */
1774 +extern char _end;
1775 +
1776 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1777 +
1778 +
1779 +struct prom_pmemblock * __init prom_getmdesc(void)
1780 +{
1781 + char *memsize_str;
1782 + unsigned int memsize;
1783 +
1784 + memsize_str = prom_getenv("memsize");
1785 + if (!memsize_str) {
1786 + memsize = 0x02000000;
1787 + } else {
1788 + memsize = simple_strtol(memsize_str, NULL, 0);
1789 + }
1790 +
1791 + memset(mdesc, 0, sizeof(mdesc));
1792 +
1793 + mdesc[0].type = yamon_dontuse;
1794 + mdesc[0].base = 0x00000000;
1795 + mdesc[0].size = CONFIG_AR7_MEMORY;
1796 +
1797 + mdesc[1].type = yamon_prom;
1798 + mdesc[1].base = CONFIG_AR7_MEMORY;
1799 + mdesc[1].size = 0x00020000;
1800 +
1801 + mdesc[2].type = yamon_free;
1802 + mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1803 + mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1804 +
1805 + return &mdesc[0];
1806 +}
1807 +
1808 +static int __init prom_memtype_classify (unsigned int type)
1809 +{
1810 + switch (type) {
1811 + case yamon_free:
1812 + return BOOT_MEM_RAM;
1813 + case yamon_prom:
1814 + return BOOT_MEM_ROM_DATA;
1815 + default:
1816 + return BOOT_MEM_RESERVED;
1817 + }
1818 +}
1819 +
1820 +void __init prom_meminit(void)
1821 +{
1822 + struct prom_pmemblock *p;
1823 +
1824 + p = prom_getmdesc();
1825 +
1826 + while (p->size) {
1827 + long type;
1828 + unsigned long base, size;
1829 +
1830 + type = prom_memtype_classify (p->type);
1831 + base = p->base;
1832 + size = p->size;
1833 +
1834 + add_memory_region(base, size, type);
1835 + p++;
1836 + }
1837 +}
1838 +
1839 +void __init prom_free_prom_memory (void)
1840 +{
1841 + int i;
1842 + unsigned long freed = 0;
1843 + unsigned long addr;
1844 +
1845 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1846 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1847 + continue;
1848 +
1849 + addr = boot_mem_map.map[i].addr;
1850 + while (addr < boot_mem_map.map[i].addr
1851 + + boot_mem_map.map[i].size) {
1852 + ClearPageReserved(virt_to_page(__va(addr)));
1853 + set_page_count(virt_to_page(__va(addr)), 1);
1854 + free_page((unsigned long)__va(addr));
1855 + addr += PAGE_SIZE;
1856 + freed += PAGE_SIZE;
1857 + }
1858 + }
1859 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1860 +}
1861 diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-current/arch/mips/ar7/mipsIRQ.S
1862 --- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1863 +++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266000 +0200
1864 @@ -0,0 +1,120 @@
1865 +/*
1866 + * Carsten Langgaard, carstenl@mips.com
1867 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1868 + *
1869 + * ########################################################################
1870 + *
1871 + * This program is free software; you can distribute it and/or modify it
1872 + * under the terms of the GNU General Public License (Version 2) as
1873 + * published by the Free Software Foundation.
1874 + *
1875 + * This program is distributed in the hope it will be useful, but WITHOUT
1876 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1877 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1878 + * for more details.
1879 + *
1880 + * You should have received a copy of the GNU General Public License along
1881 + * with this program; if not, write to the Free Software Foundation, Inc.,
1882 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1883 + *
1884 + * ########################################################################
1885 + *
1886 + * Interrupt exception dispatch code.
1887 + *
1888 + */
1889 +#include <linux/config.h>
1890 +
1891 +#include <asm/asm.h>
1892 +#include <asm/mipsregs.h>
1893 +#include <asm/regdef.h>
1894 +#include <asm/stackframe.h>
1895 +
1896 +/* A lot of complication here is taken away because:
1897 + *
1898 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1899 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1900 + * common case is one pending IRQ so optimize in that direction.
1901 + *
1902 + * 2) We need not check against bits in the status register IRQ mask, that
1903 + * would make this routine slow as hell.
1904 + *
1905 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1906 + * between like BSD spl() brain-damage.
1907 + *
1908 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1909 + * IRQs which we don't use at all and all external interrupt sources are
1910 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1911 + *
1912 + * MIPS IRQ Source
1913 + * -------- ------
1914 + * 0 Software (ignored)
1915 + * 1 Software (ignored)
1916 + * 2 Combined hardware interrupt (hw0)
1917 + * 3 Hardware (ignored)
1918 + * 4 Hardware (ignored)
1919 + * 5 Hardware (ignored)
1920 + * 6 Hardware (ignored)
1921 + * 7 R4k timer (what we use)
1922 + *
1923 + * Note: On the SEAD board thing are a little bit different.
1924 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1925 + * wired to UART1.
1926 + *
1927 + * We handle the IRQ according to _our_ priority which is:
1928 + *
1929 + * Highest ---- R4k Timer
1930 + * Lowest ---- Combined hardware interrupt
1931 + *
1932 + * then we just return, if multiple IRQs are pending then we will just take
1933 + * another exception, big deal.
1934 + */
1935 +
1936 +.text
1937 +.set noreorder
1938 +.set noat
1939 + .align 5
1940 +NESTED(mipsIRQ, PT_SIZE, sp)
1941 + SAVE_ALL
1942 + CLI
1943 + .set at
1944 +
1945 + mfc0 s0, CP0_CAUSE # get irq bits
1946 +
1947 + /* First we check for r4k counter/timer IRQ. */
1948 + andi a0, s0, CAUSEF_IP7
1949 + beq a0, zero, 1f
1950 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1951 +
1952 + /* Wheee, a timer interrupt. */
1953 + move a0, sp
1954 + jal ar7_timer_interrupt
1955 + nop
1956 +
1957 + j ret_from_irq
1958 + nop
1959 +
1960 + 1:
1961 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1962 + nop
1963 +
1964 + /* Wheee, combined hardware level zero interrupt. */
1965 + jal avalanche_hw0_irqdispatch
1966 + move a0, sp # delay slot
1967 +
1968 + j ret_from_irq
1969 + nop # delay slot
1970 +
1971 + 1:
1972 + /*
1973 + * Here by mistake? This is possible, what can happen is that by the
1974 + * time we take the exception the IRQ pin goes low, so just leave if
1975 + * this is the case.
1976 + */
1977 + move a1,s0
1978 + PRINT("Got interrupt: c0_cause = %08x\n")
1979 + mfc0 a1, CP0_EPC
1980 + PRINT("c0_epc = %08x\n")
1981 +
1982 + j ret_from_irq
1983 + nop
1984 +END(mipsIRQ)
1985 diff -urN kernel-base/arch/mips/ar7/printf.c kernel-current/arch/mips/ar7/printf.c
1986 --- kernel-base/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1987 +++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266000 +0200
1988 @@ -0,0 +1,54 @@
1989 +/*
1990 + * Carsten Langgaard, carstenl@mips.com
1991 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1992 + *
1993 + * This program is free software; you can distribute it and/or modify it
1994 + * under the terms of the GNU General Public License (Version 2) as
1995 + * published by the Free Software Foundation.
1996 + *
1997 + * This program is distributed in the hope it will be useful, but WITHOUT
1998 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1999 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2000 + * for more details.
2001 + *
2002 + * You should have received a copy of the GNU General Public License along
2003 + * with this program; if not, write to the Free Software Foundation, Inc.,
2004 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2005 + *
2006 + * Putting things on the screen/serial line using Adam2 facilities.
2007 + */
2008 +
2009 +#include <linux/config.h>
2010 +#include <linux/init.h>
2011 +#include <linux/kernel.h>
2012 +#include <linux/serial_reg.h>
2013 +#include <linux/spinlock.h>
2014 +#include <asm/io.h>
2015 +#include <asm/serial.h>
2016 +#include <asm/addrspace.h>
2017 +#include <asm/ar7/ar7.h>
2018 +
2019 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
2020 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
2021 +
2022 +static char ppbuf[1024];
2023 +
2024 +void (*prom_print_str)(unsigned int out, char *s, int len);
2025 +
2026 +void prom_printf(char *fmt, ...) __init;
2027 +void prom_printf(char *fmt, ...)
2028 +{
2029 + va_list args;
2030 + int len;
2031 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
2032 +
2033 + va_start(args, fmt);
2034 + vsprintf(ppbuf, fmt, args);
2035 + len = strlen(ppbuf);
2036 +
2037 + prom_print_str(1, ppbuf, len);
2038 +
2039 + va_end(args);
2040 + return;
2041 +
2042 +}
2043 diff -urN kernel-base/arch/mips/ar7/reset.c kernel-current/arch/mips/ar7/reset.c
2044 --- kernel-base/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
2045 +++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266000 +0200
2046 @@ -0,0 +1,54 @@
2047 +/*
2048 + * Carsten Langgaard, carstenl@mips.com
2049 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2050 + *
2051 + * ########################################################################
2052 + *
2053 + * This program is free software; you can distribute it and/or modify it
2054 + * under the terms of the GNU General Public License (Version 2) as
2055 + * published by the Free Software Foundation.
2056 + *
2057 + * This program is distributed in the hope it will be useful, but WITHOUT
2058 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2059 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2060 + * for more details.
2061 + *
2062 + * You should have received a copy of the GNU General Public License along
2063 + * with this program; if not, write to the Free Software Foundation, Inc.,
2064 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2065 + *
2066 + * ########################################################################
2067 + *
2068 + * Reset the MIPS boards.
2069 + *
2070 + */
2071 +#include <linux/config.h>
2072 +
2073 +#include <asm/reboot.h>
2074 +#include <asm/mips-boards/generic.h>
2075 +
2076 +static void ar7_machine_restart(char *command);
2077 +static void ar7_machine_halt(void);
2078 +static void ar7_machine_power_off(void);
2079 +
2080 +static void ar7_machine_restart(char *command)
2081 +{
2082 +
2083 +}
2084 +
2085 +static void ar7_machine_halt(void)
2086 +{
2087 +
2088 +}
2089 +
2090 +static void ar7_machine_power_off(void)
2091 +{
2092 +
2093 +}
2094 +
2095 +void ar7_reboot_setup(void)
2096 +{
2097 + _machine_restart = ar7_machine_restart;
2098 + _machine_halt = ar7_machine_halt;
2099 + _machine_power_off = ar7_machine_power_off;
2100 +}
2101 diff -urN kernel-base/arch/mips/ar7/setup.c kernel-current/arch/mips/ar7/setup.c
2102 --- kernel-base/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
2103 +++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266000 +0200
2104 @@ -0,0 +1,120 @@
2105 +/*
2106 + * Carsten Langgaard, carstenl@mips.com
2107 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
2108 + *
2109 + * This program is free software; you can distribute it and/or modify it
2110 + * under the terms of the GNU General Public License (Version 2) as
2111 + * published by the Free Software Foundation.
2112 + *
2113 + * This program is distributed in the hope it will be useful, but WITHOUT
2114 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2115 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2116 + * for more details.
2117 + *
2118 + * You should have received a copy of the GNU General Public License along
2119 + * with this program; if not, write to the Free Software Foundation, Inc.,
2120 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2121 + */
2122 +#include <linux/config.h>
2123 +#include <linux/init.h>
2124 +#include <linux/sched.h>
2125 +#include <linux/mc146818rtc.h>
2126 +#include <linux/ioport.h>
2127 +
2128 +#include <asm/cpu.h>
2129 +#include <asm/bootinfo.h>
2130 +#include <asm/irq.h>
2131 +#include <asm/mips-boards/generic.h>
2132 +#include <asm/mips-boards/prom.h>
2133 +
2134 +#include <asm/dma.h>
2135 +#include <asm/time.h>
2136 +#include <asm/traps.h>
2137 +
2138 +#ifdef CONFIG_KGDB
2139 +extern void rs_kgdb_hook(int);
2140 +int remote_debug = 0;
2141 +#endif
2142 +
2143 +extern struct rtc_ops no_rtc_ops;
2144 +
2145 +extern void ar7_reboot_setup(void);
2146 +
2147 +extern void ar7_time_init(void);
2148 +extern void ar7_timer_setup(struct irqaction *irq);
2149 +
2150 +const char *get_system_type(void)
2151 +{
2152 + return "Texas Instruments AR7";
2153 +}
2154 +
2155 +void __init ar7_setup(void)
2156 +{
2157 +#ifdef CONFIG_KGDB
2158 + int rs_putDebugChar(char);
2159 + char rs_getDebugChar(void);
2160 + extern int (*generic_putDebugChar)(char);
2161 + extern char (*generic_getDebugChar)(void);
2162 +#endif
2163 + char *argptr;
2164 +#ifdef CONFIG_SERIAL_CONSOLE
2165 + argptr = prom_getcmdline();
2166 + if ((argptr = strstr(argptr, "console=")) == NULL) {
2167 + char console[20];
2168 + char *s;
2169 + int i = 0;
2170 +
2171 + s = prom_getenv("modetty0");
2172 + strcpy(console, "38400");
2173 +
2174 + if (s != NULL) {
2175 + while (s[i] >= '0' && s[i] <= '9')
2176 + i++;
2177 +
2178 + if (i > 0) {
2179 + strncpy(console, s, i);
2180 + console[i] = 0;
2181 + }
2182 + }
2183 +
2184 + argptr = prom_getcmdline();
2185 + strcat(argptr, " console=ttyS0,");
2186 + strcat(argptr, console);
2187 + }
2188 +#endif
2189 +
2190 +#ifdef CONFIG_KGDB
2191 + argptr = prom_getcmdline();
2192 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2193 + int line;
2194 + argptr += strlen("kgdb=ttyS");
2195 + if (*argptr != '0' && *argptr != '1')
2196 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
2197 + "falling back to /dev/ttyS1\n", *argptr);
2198 + line = *argptr == '0' ? 0 : 1;
2199 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2200 + line ? 1 : 0);
2201 +
2202 + rs_kgdb_hook(line);
2203 + generic_putDebugChar = rs_putDebugChar;
2204 + generic_getDebugChar = rs_getDebugChar;
2205 +
2206 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2207 + "please connect your debugger\n", line ? 1 : 0);
2208 +
2209 + remote_debug = 1;
2210 + /* Breakpoints are in init_IRQ() */
2211 + }
2212 +#endif
2213 +
2214 + argptr = prom_getcmdline();
2215 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
2216 + cpu_data[0].options &= ~MIPS_CPU_FPU;
2217 +
2218 + rtc_ops = &no_rtc_ops;
2219 +
2220 + ar7_reboot_setup();
2221 +
2222 + board_time_init = ar7_time_init;
2223 + board_timer_setup = ar7_timer_setup;
2224 +}
2225 diff -urN kernel-base/arch/mips/ar7/time.c kernel-current/arch/mips/ar7/time.c
2226 --- kernel-base/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
2227 +++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266000 +0200
2228 @@ -0,0 +1,125 @@
2229 +/*
2230 + * Carsten Langgaard, carstenl@mips.com
2231 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2232 + *
2233 + * ########################################################################
2234 + *
2235 + * This program is free software; you can distribute it and/or modify it
2236 + * under the terms of the GNU General Public License (Version 2) as
2237 + * published by the Free Software Foundation.
2238 + *
2239 + * This program is distributed in the hope it will be useful, but WITHOUT
2240 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2241 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2242 + * for more details.
2243 + *
2244 + * You should have received a copy of the GNU General Public License along
2245 + * with this program; if not, write to the Free Software Foundation, Inc.,
2246 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2247 + *
2248 + * ########################################################################
2249 + *
2250 + * Setting up the clock on the MIPS boards.
2251 + *
2252 + */
2253 +
2254 +#include <linux/types.h>
2255 +#include <linux/config.h>
2256 +#include <linux/init.h>
2257 +#include <linux/kernel_stat.h>
2258 +#include <linux/sched.h>
2259 +#include <linux/spinlock.h>
2260 +
2261 +#include <asm/mipsregs.h>
2262 +#include <asm/ptrace.h>
2263 +#include <asm/hardirq.h>
2264 +#include <asm/div64.h>
2265 +
2266 +#include <linux/interrupt.h>
2267 +#include <linux/mc146818rtc.h>
2268 +#include <linux/timex.h>
2269 +
2270 +#include <asm/mips-boards/generic.h>
2271 +#include <asm/mips-boards/prom.h>
2272 +#include <asm/ar7/ar7.h>
2273 +
2274 +extern asmlinkage void mipsIRQ(void);
2275 +
2276 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2277 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
2278 +
2279 +#define MIPS_CPU_TIMER_IRQ 7
2280 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2281 +
2282 +static inline void ack_r4ktimer(unsigned long newval)
2283 +{
2284 + write_c0_compare(newval);
2285 +}
2286 +
2287 +void ar7_timer_interrupt(struct pt_regs *regs)
2288 +{
2289 + int cpu = smp_processor_id();
2290 +
2291 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2292 +
2293 + if (r4k_offset == 0)
2294 + goto null;
2295 +
2296 + do {
2297 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2298 + do_timer(regs);
2299 + r4k_cur += r4k_offset;
2300 + ack_r4ktimer(r4k_cur);
2301 +
2302 + } while (((unsigned long)read_c0_count()
2303 + - r4k_cur) < 0x7fffffff);
2304 +
2305 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2306 +
2307 + if (softirq_pending(cpu))
2308 + do_softirq();
2309 +
2310 + return;
2311 +
2312 +null:
2313 + ack_r4ktimer(0);
2314 +}
2315 +
2316 +/*
2317 + * Figure out the r4k offset, the amount to increment the compare
2318 + * register for each time tick.
2319 + */
2320 +static unsigned long __init cal_r4koff(void)
2321 +{
2322 + return ((CONFIG_AR7_CPU_FREQUENCY*500000)/HZ);
2323 +}
2324 +
2325 +void __init ar7_time_init(void)
2326 +{
2327 + unsigned long flags;
2328 + unsigned int est_freq;
2329 +
2330 + set_except_vector(0, mipsIRQ);
2331 + write_c0_count(0);
2332 +
2333 + printk("calculating r4koff... ");
2334 + r4k_offset = cal_r4koff();
2335 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2336 +
2337 + est_freq = 2*r4k_offset*HZ;
2338 + est_freq += 5000; /* round */
2339 + est_freq -= est_freq%10000;
2340 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2341 + (est_freq%1000000)*100/1000000);
2342 +}
2343 +
2344 +void __init ar7_timer_setup(struct irqaction *irq)
2345 +{
2346 + /* we are using the cpu counter for timer interrupts */
2347 + irq->handler = no_action; /* we use our own handler */
2348 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2349 +
2350 + r4k_cur = (read_c0_count() + r4k_offset);
2351 + write_c0_compare(r4k_cur);
2352 + set_c0_status(ALLINTS);
2353 +}
2354 diff -urN kernel-base/arch/mips/config-shared.in kernel-current/arch/mips/config-shared.in
2355 --- kernel-base/arch/mips/config-shared.in 2005-07-10 03:00:44.784181376 +0200
2356 +++ kernel-current/arch/mips/config-shared.in 2005-07-10 06:40:39.589266000 +0200
2357 @@ -20,6 +20,16 @@
2358 mainmenu_option next_comment
2359 comment 'Machine selection'
2360 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2361 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2362 +if [ "$CONFIG_AR7" = "y" ]; then
2363 + choice 'Texas Instruments Reference Platform' \
2364 + "AR7DB CONFIG_AR7DB \
2365 + AR7RD CONFIG_AR7RD \
2366 + AR7WRD CONFIG_AR7WRD" AR7DB
2367 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU_FREQUENCY 150
2368 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS_FREQUENCY 125
2369 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2370 +fi
2371 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2372 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2373 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2374 @@ -239,6 +249,11 @@
2375 define_bool CONFIG_NONCOHERENT_IO y
2376 define_bool CONFIG_PC_KEYB y
2377 fi
2378 +if [ "$CONFIG_AR7" = "y" ]; then
2379 + define_bool CONFIG_NONCOHERENT_IO y
2380 + define_bool CONFIG_SWAP_IO_SPACE y
2381 + define_bool CONFIG_AR7_PAGING y
2382 +fi
2383 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2384 define_bool CONFIG_IRQ_CPU y
2385 define_bool CONFIG_NONCOHERENT_IO y
2386 @@ -736,6 +751,7 @@
2387 mainmenu_option next_comment
2388 comment 'General setup'
2389 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2390 + "$CONFIG_AR7" = "y" -o \
2391 "$CONFIG_CASIO_E55" = "y" -o \
2392 "$CONFIG_DDB5074" = "y" -o \
2393 "$CONFIG_DDB5476" = "y" -o \
2394 @@ -797,6 +813,7 @@
2395 bool 'Networking support' CONFIG_NET
2396
2397 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2398 + "$CONFIG_AR7" = "y" -o \
2399 "$CONFIG_CASIO_E55" = "y" -o \
2400 "$CONFIG_DECSTATION" = "y" -o \
2401 "$CONFIG_IBM_WORKPAD" = "y" -o \
2402 diff -urN kernel-base/arch/mips/kernel/irq.c kernel-current/arch/mips/kernel/irq.c
2403 --- kernel-base/arch/mips/kernel/irq.c 2005-07-10 03:00:44.784181376 +0200
2404 +++ kernel-current/arch/mips/kernel/irq.c 2005-07-10 06:40:39.589266000 +0200
2405 @@ -76,6 +76,7 @@
2406 * Generic, controller-independent functions:
2407 */
2408
2409 +#ifndef CONFIG_AR7
2410 int get_irq_list(char *buf)
2411 {
2412 int i, j;
2413 @@ -110,6 +111,7 @@
2414 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2415 return p - buf;
2416 }
2417 +#endif
2418
2419 #ifdef CONFIG_SMP
2420 int global_irq_holder = NO_PROC_ID;
2421 @@ -525,6 +527,7 @@
2422 *
2423 */
2424
2425 +#ifndef CONFIG_AR7
2426 int request_irq(unsigned int irq,
2427 void (*handler)(int, void *, struct pt_regs *),
2428 unsigned long irqflags,
2429 @@ -569,6 +572,7 @@
2430 kfree(action);
2431 return retval;
2432 }
2433 +#endif
2434
2435 /**
2436 * free_irq - free an interrupt
2437 @@ -588,6 +592,7 @@
2438 * the machine.
2439 */
2440
2441 +#ifndef CONFIG_AR7
2442 void free_irq(unsigned int irq, void *dev_id)
2443 {
2444 irq_desc_t *desc;
2445 @@ -629,6 +634,7 @@
2446 return;
2447 }
2448 }
2449 +#endif
2450
2451 /*
2452 * IRQ autodetection code..
2453 diff -urN kernel-base/arch/mips/kernel/mips_ksyms.c kernel-current/arch/mips/kernel/mips_ksyms.c
2454 --- kernel-base/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
2455 +++ kernel-current/arch/mips/kernel/mips_ksyms.c 2005-07-10 17:55:55.738466208 +0200
2456 @@ -40,6 +40,12 @@
2457 extern long __strnlen_user_nocheck_asm(const char *s);
2458 extern long __strnlen_user_asm(const char *s);
2459
2460 +#ifdef CONFIG_AR7
2461 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
2462 +char *prom_getenv(char *envname);
2463 +#endif
2464 +
2465 +
2466 EXPORT_SYMBOL(mips_machtype);
2467 #ifdef CONFIG_EISA
2468 EXPORT_SYMBOL(EISA_bus);
2469 @@ -103,3 +109,9 @@
2470 #endif
2471
2472 EXPORT_SYMBOL(get_wchan);
2473 +
2474 +#ifdef CONFIG_AR7
2475 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
2476 +EXPORT_SYMBOL_NOVERS(prom_getenv);
2477 +#endif
2478 +
2479 diff -urN kernel-base/arch/mips/kernel/setup.c kernel-current/arch/mips/kernel/setup.c
2480 --- kernel-base/arch/mips/kernel/setup.c 2005-07-10 03:00:44.785181224 +0200
2481 +++ kernel-current/arch/mips/kernel/setup.c 2005-07-10 06:40:39.590265000 +0200
2482 @@ -109,6 +109,7 @@
2483 unsigned long isa_slot_offset;
2484 EXPORT_SYMBOL(isa_slot_offset);
2485
2486 +extern void avalanche_bootmem_init(void);
2487 extern void SetUpBootInfo(void);
2488 extern void load_mmu(void);
2489 extern asmlinkage void start_kernel(void);
2490 @@ -267,6 +268,9 @@
2491 #endif /* CONFIG_BLK_DEV_INITRD */
2492
2493 /* Find the highest page frame number we have available. */
2494 +#ifdef CONFIG_AR7_PAGING
2495 + avalanche_bootmem_init();
2496 +#else
2497 max_pfn = 0;
2498 first_usable_pfn = -1UL;
2499 for (i = 0; i < boot_mem_map.nr_map; i++) {
2500 @@ -377,6 +381,7 @@
2501 /* Reserve the bootmap memory. */
2502 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
2503
2504 +#endif
2505 #ifdef CONFIG_BLK_DEV_INITRD
2506 /* Board specific code should have set up initrd_start and initrd_end */
2507 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
2508 @@ -494,6 +499,7 @@
2509 void hp_setup(void);
2510 void au1x00_setup(void);
2511 void frame_info_init(void);
2512 + void ar7_setup(void);
2513
2514 frame_info_init();
2515 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
2516 @@ -691,6 +697,11 @@
2517 pmc_yosemite_setup();
2518 break;
2519 #endif
2520 +#ifdef CONFIG_AR7
2521 + case MACH_GROUP_UNKNOWN:
2522 + ar7_setup();
2523 + break;
2524 +#endif
2525 default:
2526 panic("Unsupported architecture");
2527 }
2528 diff -urN kernel-base/arch/mips/kernel/traps.c kernel-current/arch/mips/kernel/traps.c
2529 --- kernel-base/arch/mips/kernel/traps.c 2005-07-10 03:00:44.786181072 +0200
2530 +++ kernel-current/arch/mips/kernel/traps.c 2005-07-10 06:40:39.591265000 +0200
2531 @@ -40,6 +40,10 @@
2532 #include <asm/uaccess.h>
2533 #include <asm/mmu_context.h>
2534
2535 +#ifdef CONFIG_AR7
2536 +#include <asm/ar7/ar7.h>
2537 +#endif
2538 +
2539 extern asmlinkage void handle_mod(void);
2540 extern asmlinkage void handle_tlbl(void);
2541 extern asmlinkage void handle_tlbs(void);
2542 @@ -869,9 +873,15 @@
2543
2544 exception_handlers[n] = handler;
2545 if (n == 0 && cpu_has_divec) {
2546 +#ifdef CONFIG_AR7
2547 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
2548 + (0x03ffffff & (handler >> 2));
2549 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
2550 +#else
2551 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
2552 (0x03ffffff & (handler >> 2));
2553 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
2554 +#endif
2555 }
2556 return (void *)old_handler;
2557 }
2558 @@ -920,14 +930,46 @@
2559 void __init trap_init(void)
2560 {
2561 extern char except_vec1_generic;
2562 + extern char except_vec2_generic;
2563 extern char except_vec3_generic, except_vec3_r4000;
2564 extern char except_vec_ejtag_debug;
2565 extern char except_vec4;
2566 unsigned long i;
2567
2568 +#ifdef CONFIG_AR7
2569 + extern char jump_tlb_miss, jump_tlb_miss_unused;
2570 + extern char jump_cache_error,jump_general_exception;
2571 + extern char jump_dedicated_interrupt;
2572 + clear_c0_status(ST0_BEV);
2573 +#endif
2574 +
2575 /* Copy the generic exception handler code to it's final destination. */
2576 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
2577 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
2578 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2579
2580 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
2581 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
2582 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
2583 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
2584 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
2585 +
2586 +#ifdef CONFIG_AR7
2587 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
2588 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
2589 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
2590 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
2591 +
2592 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
2593 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
2594 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
2595 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
2596 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
2597 +#else
2598 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
2599 +#endif
2600 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
2601 +
2602 /*
2603 * Setup default vectors
2604 */
2605 @@ -951,8 +993,12 @@
2606 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
2607 * interrupt processing overhead. Use it where available.
2608 */
2609 +#ifdef CONFIG_AR7
2610 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
2611 +#else
2612 if (cpu_has_divec)
2613 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
2614 +#endif
2615
2616 /*
2617 * Some CPUs can enable/disable for cache parity detection, but does
2618 @@ -991,12 +1037,17 @@
2619 if (cpu_has_mcheck)
2620 set_except_vector(24, handle_mcheck);
2621
2622 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2623 +#ifdef CONFIG_AR7
2624 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
2625 +#else
2626 if (cpu_has_vce)
2627 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
2628 else if (cpu_has_4kex)
2629 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
2630 else
2631 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
2632 +#endif
2633
2634 if (current_cpu_data.cputype == CPU_R6000 ||
2635 current_cpu_data.cputype == CPU_R6000A) {
2636 @@ -1023,7 +1074,11 @@
2637 if (board_nmi_handler_setup)
2638 board_nmi_handler_setup();
2639
2640 +#ifdef CONFIG_AR7
2641 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
2642 +#else
2643 flush_icache_range(KSEG0, KSEG0 + 0x400);
2644 +#endif
2645
2646 per_cpu_trap_init();
2647 }
2648 diff -urN kernel-base/arch/mips/lib/promlib.c kernel-current/arch/mips/lib/promlib.c
2649 --- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
2650 +++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265000 +0200
2651 @@ -1,3 +1,4 @@
2652 +#ifndef CONFIG_AR7
2653 #include <stdarg.h>
2654 #include <linux/kernel.h>
2655
2656 @@ -22,3 +23,4 @@
2657 }
2658 va_end(args);
2659 }
2660 +#endif
2661 diff -urN kernel-base/arch/mips/Makefile kernel-current/arch/mips/Makefile
2662 --- kernel-base/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200
2663 +++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265000 +0200
2664 @@ -369,6 +369,16 @@
2665 endif
2666
2667 #
2668 +# Texas Instruments AR7
2669 +#
2670 +
2671 +ifdef CONFIG_AR7
2672 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/ar7/ar7.o
2673 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/ar7
2674 +LOADADDR += 0x94020000
2675 +endif
2676 +
2677 +#
2678 # DECstation family
2679 #
2680 ifdef CONFIG_DECSTATION
2681 diff -urN kernel-base/arch/mips/mm/init.c kernel-current/arch/mips/mm/init.c
2682 --- kernel-base/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200
2683 +++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216000 +0200
2684 @@ -40,8 +40,10 @@
2685
2686 mmu_gather_t mmu_gathers[NR_CPUS];
2687 unsigned long highstart_pfn, highend_pfn;
2688 +#ifndef CONFIG_AR7_PAGING
2689 static unsigned long totalram_pages;
2690 static unsigned long totalhigh_pages;
2691 +#endif
2692
2693 void pgd_init(unsigned long page)
2694 {
2695 @@ -235,6 +237,7 @@
2696 #endif
2697 }
2698
2699 +#ifndef CONFIG_AR7_PAGING
2700 void __init paging_init(void)
2701 {
2702 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
2703 @@ -272,6 +275,7 @@
2704
2705 free_area_init(zones_size);
2706 }
2707 +#endif
2708
2709 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
2710 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
2711 @@ -298,6 +302,7 @@
2712 return 0;
2713 }
2714
2715 +#ifndef CONFIG_AR7_PAGING
2716 void __init mem_init(void)
2717 {
2718 unsigned long codesize, reservedpages, datasize, initsize;
2719 @@ -359,6 +364,7 @@
2720 initsize >> 10,
2721 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
2722 }
2723 +#endif
2724
2725 #ifdef CONFIG_BLK_DEV_INITRD
2726 void free_initrd_mem(unsigned long start, unsigned long end)
2727 @@ -376,6 +382,7 @@
2728 }
2729 #endif
2730
2731 +#ifndef CONFIG_AR7_PAGING
2732 extern char __init_begin, __init_end;
2733 extern void prom_free_prom_memory(void) __init;
2734
2735 @@ -383,7 +390,9 @@
2736 {
2737 unsigned long addr;
2738
2739 +#ifndef CONFIG_AR7
2740 prom_free_prom_memory ();
2741 +#endif
2742
2743 addr = (unsigned long) &__init_begin;
2744 while (addr < (unsigned long) &__init_end) {
2745 @@ -409,3 +418,4 @@
2746
2747 return;
2748 }
2749 +#endif
2750 diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-current/arch/mips/mm/tlb-r4k.c
2751 --- kernel-base/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200
2752 +++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265000 +0200
2753 @@ -20,6 +20,10 @@
2754 #include <asm/pgtable.h>
2755 #include <asm/system.h>
2756
2757 +#ifdef CONFIG_AR7
2758 +#include <asm/ar7/ar7.h>
2759 +#endif
2760 +
2761 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
2762
2763 /* CP0 hazard avoidance. */
2764 @@ -375,7 +379,12 @@
2765 else if (current_cpu_data.cputype == CPU_R4600)
2766 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
2767 else
2768 +#ifdef CONFIG_AR7
2769 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
2770 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
2771 +#else
2772 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
2773 flush_icache_range(KSEG0, KSEG0 + 0x80);
2774 +#endif
2775 }
2776 }
2777 diff -urN kernel-base/drivers/char/serial.c kernel-current/drivers/char/serial.c
2778 --- kernel-base/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200
2779 +++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600000 +0200
2780 @@ -419,7 +419,40 @@
2781 return 0;
2782 }
2783
2784 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
2785 +#if defined(CONFIG_AR7)
2786 +
2787 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
2788 +{
2789 + return (inb(info->port + (offset * 4)) & 0xff);
2790 +}
2791 +
2792 +
2793 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
2794 +{
2795 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
2796 + return (inb(info->port + (offset * 4)) & 0xff);
2797 +#else
2798 + return (inb_p(info->port + (offset * 4)) & 0xff);
2799 +#endif
2800 +}
2801 +
2802 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
2803 +{
2804 + outb(value, info->port + (offset * 4));
2805 +}
2806 +
2807 +
2808 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
2809 + int value)
2810 +{
2811 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
2812 + outb(value, info->port + (offset * 4));
2813 +#else
2814 + outb_p(value, info->port + (offset * 4));
2815 +#endif
2816 +}
2817 +
2818 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
2819
2820 #include <asm/mips-boards/atlas.h>
2821
2822 @@ -478,8 +511,10 @@
2823 * needed for certain old 386 machines, I've left these #define's
2824 * in....
2825 */
2826 +#ifndef CONFIG_AR7
2827 #define serial_inp(info, offset) serial_in(info, offset)
2828 #define serial_outp(info, offset, value) serial_out(info, offset, value)
2829 +#endif
2830
2831
2832 /*
2833 @@ -1728,7 +1763,16 @@
2834 /* Special case since 134 is really 134.5 */
2835 quot = (2*baud_base / 269);
2836 else if (baud)
2837 +#ifdef CONFIG_AR7
2838 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
2839 + //quot = get_avalanche_vbus_freq() / baud;
2840 +
2841 + if ((quot%16)>7)
2842 + quot += 8;
2843 + quot /=16;
2844 +#else
2845 quot = baud_base / baud;
2846 +#endif
2847 }
2848 /* If the quotient is zero refuse the change */
2849 if (!quot && old_termios) {
2850 @@ -5552,8 +5596,10 @@
2851 state->irq = irq_cannonicalize(state->irq);
2852 if (state->hub6)
2853 state->io_type = SERIAL_IO_HUB6;
2854 +#ifndef CONFIG_AR7
2855 if (state->port && check_region(state->port,8))
2856 continue;
2857 +#endif
2858 #ifdef CONFIG_MCA
2859 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
2860 continue;
2861 @@ -6009,7 +6055,16 @@
2862 info->io_type = state->io_type;
2863 info->iomem_base = state->iomem_base;
2864 info->iomem_reg_shift = state->iomem_reg_shift;
2865 +#ifdef CONFIG_AR7
2866 + //quot = get_avalanche_vbus_freq() / baud;
2867 + quot = (CONFIG_AR7_SYS_FREQUENCY*500000) / baud;
2868 +
2869 + if ((quot%16)>7)
2870 + quot += 8;
2871 + quot /=16;
2872 +#else
2873 quot = state->baud_base / baud;
2874 +#endif
2875 cval = cflag & (CSIZE | CSTOPB);
2876 #if defined(__powerpc__) || defined(__alpha__)
2877 cval >>= 8;
2878 diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-current/include/asm-mips/ar7/ar7.h
2879 --- kernel-base/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
2880 +++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261000 +0200
2881 @@ -0,0 +1,33 @@
2882 +/*
2883 + * $Id$
2884 + * Copyright (C) $Date$ $Author$
2885 + *
2886 + * This program is free software; you can redistribute it and/or modify
2887 + * it under the terms of the GNU General Public License as published by
2888 + * the Free Software Foundation; either version 2 of the License, or
2889 + * (at your option) any later version.
2890 + *
2891 + * This program is distributed in the hope that it will be useful,
2892 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2893 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2894 + * GNU General Public License for more details.
2895 + *
2896 + * You should have received a copy of the GNU General Public License
2897 + * along with this program; if not, write to the Free Software
2898 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
2899 + *
2900 + */
2901 +
2902 +#ifndef _AR7_H
2903 +#define _AR7_H
2904 +
2905 +#include <asm/addrspace.h>
2906 +#include <linux/config.h>
2907 +
2908 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
2909 +
2910 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
2911 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610E00))
2912 +#define AR7_BASE_BAUD ( 3686400 / 16 )
2913 +
2914 +#endif
2915 diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-current/include/asm-mips/ar7/avalanche_intc.h
2916 --- kernel-base/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
2917 +++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261000 +0200
2918 @@ -0,0 +1,278 @@
2919 + /*
2920 + * Nitin Dhingra, iamnd@ti.com
2921 + * Copyright (C) 2000 Texas Instruments Inc.
2922 + *
2923 + *
2924 + * ########################################################################
2925 + *
2926 + * This program is free software; you can distribute it and/or modify it
2927 + * under the terms of the GNU General Public License (Version 2) as
2928 + * published by the Free Software Foundation.
2929 + *
2930 + * This program is distributed in the hope it will be useful, but WITHOUT
2931 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2932 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2933 + * for more details.
2934 + *
2935 + * You should have received a copy of the GNU General Public License along
2936 + * with this program; if not, write to the Free Software Foundation, Inc.,
2937 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2938 + *
2939 + * ########################################################################
2940 + *
2941 + * Defines of the Sead board specific address-MAP, registers, etc.
2942 + *
2943 + */
2944 +#ifndef _AVALANCHE_INTC_H
2945 +#define _AVALANCHE_INTC_H
2946 +
2947 +#define MIPS_EXCEPTION_OFFSET 8
2948 +
2949 +/******************************************************************************
2950 + Avalanche Interrupt number
2951 +******************************************************************************/
2952 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
2953 +
2954 +/*******************************************************************************
2955 +*Linux Interrupt number
2956 +*******************************************************************************/
2957 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
2958 +
2959 +
2960 +
2961 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
2962 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
2963 +
2964 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
2965 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
2966 +
2967 +
2968 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
2969 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
2970 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
2971 +
2972 +
2973 +/*
2974 + * Avalanche interrupt controller register base (primary)
2975 + */
2976 +#define KSEG1_BASE 0xA0000000
2977 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
2978 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
2979 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
2980 +
2981 +#define AVALANCHE_ICTRL_REGS_BASE KSEG1ADDR(0x08612400)// AVALANCHE_INTC_BASE
2982 +
2983 +/******************************************************************************
2984 + * Avalanche exception controller register base (secondary)
2985 + ******************************************************************************/
2986 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
2987 +
2988 +
2989 +/******************************************************************************
2990 + * Avalanche Interrupt pacing register base (secondary)
2991 + ******************************************************************************/
2992 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
2993 +
2994 +
2995 +
2996 +/******************************************************************************
2997 + * Avalanche Interrupt Channel Control register base
2998 + *****************************************************************************/
2999 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3000 +
3001 +
3002 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3003 +{
3004 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
3005 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
3006 + volatile unsigned long unused1; /*0x08 */
3007 + volatile unsigned long unused2; /*0x0C */
3008 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
3009 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
3010 + volatile unsigned long unused3; /*0x18 */
3011 + volatile unsigned long unused4; /*0x1C */
3012 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
3013 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
3014 + volatile unsigned long unused5; /*0x28 */
3015 + volatile unsigned long unused6; /*0x2C */
3016 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
3017 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
3018 + volatile unsigned long unused7; /* 0x38 */
3019 + volatile unsigned long unused8; /* 0x3c */
3020 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
3021 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
3022 + volatile unsigned long unused9; /* 0x48 */
3023 + volatile unsigned long unused10; /* 0x4C */
3024 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
3025 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
3026 + volatile unsigned long unused11; /* 0x58 */
3027 + volatile unsigned long unused12; /*0x5C */
3028 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
3029 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
3030 +};
3031 +
3032 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3033 +{
3034 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
3035 + volatile unsigned long reserved; /*0x84 */
3036 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
3037 + volatile unsigned long reserved1; /*0x8c */
3038 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
3039 + volatile unsigned long reserved2; /*0x94 */
3040 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
3041 +};
3042 +struct avalanche_ipace_regs
3043 +{
3044 +
3045 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
3046 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
3047 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
3048 +};
3049 +struct avalanche_channel_int_number
3050 +{
3051 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
3052 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
3053 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
3054 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
3055 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
3056 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
3057 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
3058 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
3059 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
3060 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
3061 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
3062 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
3063 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
3064 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
3065 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
3066 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
3067 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
3068 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
3069 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
3070 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
3071 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
3072 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
3073 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
3074 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
3075 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
3076 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
3077 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
3078 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
3079 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
3080 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
3081 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
3082 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
3083 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
3084 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
3085 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
3086 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
3087 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
3088 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
3089 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
3090 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
3091 +};
3092 +
3093 +struct avalanche_interrupt_line_to_channel
3094 +{
3095 + unsigned long int_line0; /* Start of primary interrupts */
3096 + unsigned long int_line1;
3097 + unsigned long int_line2;
3098 + unsigned long int_line3;
3099 + unsigned long int_line4;
3100 + unsigned long int_line5;
3101 + unsigned long int_line6;
3102 + unsigned long int_line7;
3103 + unsigned long int_line8;
3104 + unsigned long int_line9;
3105 + unsigned long int_line10;
3106 + unsigned long int_line11;
3107 + unsigned long int_line12;
3108 + unsigned long int_line13;
3109 + unsigned long int_line14;
3110 + unsigned long int_line15;
3111 + unsigned long int_line16;
3112 + unsigned long int_line17;
3113 + unsigned long int_line18;
3114 + unsigned long int_line19;
3115 + unsigned long int_line20;
3116 + unsigned long int_line21;
3117 + unsigned long int_line22;
3118 + unsigned long int_line23;
3119 + unsigned long int_line24;
3120 + unsigned long int_line25;
3121 + unsigned long int_line26;
3122 + unsigned long int_line27;
3123 + unsigned long int_line28;
3124 + unsigned long int_line29;
3125 + unsigned long int_line30;
3126 + unsigned long int_line31;
3127 + unsigned long int_line32;
3128 + unsigned long int_line33;
3129 + unsigned long int_line34;
3130 + unsigned long int_line35;
3131 + unsigned long int_line36;
3132 + unsigned long int_line37;
3133 + unsigned long int_line38;
3134 + unsigned long int_line39;
3135 +};
3136 +
3137 +
3138 +/* Interrupt Line #'s (Sangam peripherals) */
3139 +
3140 +/*------------------------------*/
3141 +/* Sangam primary interrupts */
3142 +/*------------------------------*/
3143 +
3144 +#define UNIFIED_SECONDARY_INTERRUPT 0
3145 +#define AVALANCHE_EXT_INT_0 1
3146 +#define AVALANCHE_EXT_INT_1 2
3147 +/* Line #3 Reserved */
3148 +/* Line #4 Reserved */
3149 +#define AVALANCHE_TIMER_0_INT 5
3150 +#define AVALANCHE_TIMER_1_INT 6
3151 +#define AVALANCHE_UART0_INT 7
3152 +#define AVALANCHE_UART1_INT 8
3153 +#define AVALANCHE_PDMA_INT0 9
3154 +#define AVALANCHE_PDMA_INT1 10
3155 +/* Line #11 Reserved */
3156 +/* Line #12 Reserved */
3157 +/* Line #13 Reserved */
3158 +/* Line #14 Reserved */
3159 +#define AVALANCHE_ATM_SAR_INT 15
3160 +/* Line #16 Reserved */
3161 +/* Line #17 Reserved */
3162 +/* Line #18 Reserved */
3163 +#define AVALANCHE_MAC0_INT 19
3164 +/* Line #20 Reserved */
3165 +#define AVALANCHE_VLYNQ0_INT 21
3166 +#define AVALANCHE_CODEC_WAKE_INT 22
3167 +/* Line #23 Reserved */
3168 +#define AVALANCHE_USB_INT 24
3169 +#define AVALANCHE_VLYNQ1_INT 25
3170 +/* Line #26 Reserved */
3171 +/* Line #27 Reserved */
3172 +#define AVALANCHE_MAC1_INT 28
3173 +#define AVALANCHE_I2CM_INT 29
3174 +#define AVALANCHE_PDMA_INT2 30
3175 +#define AVALANCHE_PDMA_INT3 31
3176 +/* Line #32 Reserved */
3177 +/* Line #33 Reserved */
3178 +/* Line #34 Reserved */
3179 +/* Line #35 Reserved */
3180 +/* Line #36 Reserved */
3181 +#define AVALANCHE_VDMA_VT_RX_INT 37
3182 +#define AVALANCHE_VDMA_VT_TX_INT 38
3183 +#define AVALANCHE_ADSLSS_INT 39
3184 +
3185 +/*-----------------------------------*/
3186 +/* Sangam Secondary Interrupts */
3187 +/*-----------------------------------*/
3188 +#define PRIMARY_INTS 40
3189 +
3190 +#define EMIF_INT (7 + PRIMARY_INTS)
3191 +
3192 +
3193 +extern void avalanche_int_set(int channel, int line);
3194 +
3195 +
3196 +#endif /* _AVALANCHE_INTC_H */
3197 diff -urN kernel-base/include/asm-mips/ar7/avalanche_misc.h kernel-current/include/asm-mips/ar7/avalanche_misc.h
3198 --- kernel-base/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
3199 +++ kernel-current/include/asm-mips/ar7/avalanche_misc.h 2005-07-10 18:45:35.089287296 +0200
3200 @@ -0,0 +1,174 @@
3201 +#ifndef _AVALANCHE_MISC_H_
3202 +#define _AVALANCHE_MISC_H_
3203 +
3204 +typedef enum AVALANCHE_ERR_t
3205 +{
3206 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
3207 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
3208 +
3209 + /* Pointers and args */
3210 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
3211 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
3212 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
3213 +
3214 + /* Memory issues */
3215 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
3216 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
3217 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
3218 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
3219 +
3220 + /* Device issues */
3221 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
3222 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
3223 +
3224 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
3225 +
3226 +} AVALANCHE_ERR;
3227 +
3228 +/*****************************************************************************
3229 + * Reset Control Module
3230 + *****************************************************************************/
3231 +
3232 +typedef enum AVALANCHE_RESET_MODULE_tag
3233 +{
3234 + RESET_MODULE_UART0 = 0,
3235 + RESET_MODULE_UART1 = 1,
3236 + RESET_MODULE_I2C = 2,
3237 + RESET_MODULE_TIMER0 = 3,
3238 + RESET_MODULE_TIMER1 = 4,
3239 + RESET_MODULE_GPIO = 6,
3240 + RESET_MODULE_ADSLSS = 7,
3241 + RESET_MODULE_USBS = 8,
3242 + RESET_MODULE_SAR = 9,
3243 + RESET_MODULE_VDMA_VT = 11,
3244 + RESET_MODULE_FSER = 12,
3245 + RESET_MODULE_VLYNQ1 = 16,
3246 + RESET_MODULE_EMAC0 = 17,
3247 + RESET_MODULE_DMA = 18,
3248 + RESET_MODULE_BIST = 19,
3249 + RESET_MODULE_VLYNQ0 = 20,
3250 + RESET_MODULE_EMAC1 = 21,
3251 + RESET_MODULE_MDIO = 22,
3252 + RESET_MODULE_ADSLSS_DSP = 23,
3253 + RESET_MODULE_EPHY = 26
3254 +} AVALANCHE_RESET_MODULE_T;
3255 +
3256 +typedef enum AVALANCHE_RESET_CTRL_tag
3257 +{
3258 + IN_RESET = 0,
3259 + OUT_OF_RESET
3260 +} AVALANCHE_RESET_CTRL_T;
3261 +
3262 +typedef enum AVALANCHE_SYS_RST_MODE_tag
3263 +{
3264 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
3265 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
3266 +} AVALANCHE_SYS_RST_MODE_T;
3267 +
3268 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
3269 +{
3270 + HARDWARE_RESET = 0,
3271 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
3272 + WATCHDOG_RESET,
3273 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
3274 +} AVALANCHE_SYS_RESET_STATUS_T;
3275 +
3276 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
3277 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
3278 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
3279 +
3280 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
3281 +
3282 +/*****************************************************************************
3283 + * Power Control Module
3284 + *****************************************************************************/
3285 +
3286 +typedef enum AVALANCHE_POWER_CTRL_tag
3287 +{
3288 + POWER_CTRL_POWER_UP = 0,
3289 + POWER_CTRL_POWER_DOWN
3290 +} AVALANCHE_POWER_CTRL_T;
3291 +
3292 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
3293 +{
3294 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
3295 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
3296 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
3297 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
3298 +} AVALANCHE_SYS_POWER_MODE_T;
3299 +
3300 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
3301 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
3302 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
3303 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
3304 +
3305 +/*****************************************************************************
3306 + * Wakeup Control
3307 + *****************************************************************************/
3308 +
3309 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
3310 +{
3311 + WAKEUP_INT0 = 1,
3312 + WAKEUP_INT1 = 2,
3313 + WAKEUP_INT2 = 4,
3314 + WAKEUP_INT3 = 8
3315 +} AVALANCHE_WAKEUP_INTERRUPT_T;
3316 +
3317 +typedef enum TNETV1050_WAKEUP_CTRL_tag
3318 +{
3319 + WAKEUP_DISABLED = 0,
3320 + WAKEUP_ENABLED
3321 +} AVALANCHE_WAKEUP_CTRL_T;
3322 +
3323 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
3324 +{
3325 + WAKEUP_ACTIVE_HIGH = 0,
3326 + WAKEUP_ACTIVE_LOW
3327 +} AVALANCHE_WAKEUP_POLARITY_T;
3328 +
3329 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
3330 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
3331 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
3332 +
3333 +/*****************************************************************************
3334 + * GPIO Control
3335 + *****************************************************************************/
3336 +
3337 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
3338 +{
3339 + FUNCTIONAL_PIN = 0,
3340 + GPIO_PIN = 1
3341 +} AVALANCHE_GPIO_PIN_MODE_T;
3342 +
3343 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
3344 +{
3345 + GPIO_OUTPUT_PIN = 0,
3346 + GPIO_INPUT_PIN = 1
3347 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
3348 +
3349 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
3350 +
3351 +void avalanche_gpio_init(void);
3352 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
3353 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
3354 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
3355 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
3356 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
3357 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
3358 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
3359 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
3360 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
3361 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
3362 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
3363 +
3364 +unsigned int avalanche_get_chip_version_info(void);
3365 +
3366 +unsigned int avalanche_get_vbus_freq(void);
3367 +void avalanche_set_vbus_freq(unsigned int);
3368 +
3369 +
3370 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
3371 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
3372 +unsigned int avalanche_is_mdix_on_chip(void);
3373 +
3374 +#endif
3375 diff -urN kernel-base/include/asm-mips/ar7/avalanche_regs.h kernel-current/include/asm-mips/ar7/avalanche_regs.h
3376 --- kernel-base/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
3377 +++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 18:48:26.333254256 +0200
3378 @@ -0,0 +1,567 @@
3379 +/*
3380 + * $Id$
3381 + * Avalanche Register Descriptions
3382 + *
3383 + * Jeff Harrell, jharrell@ti.com
3384 + * 2000 (c) Texas Instruments Inc.
3385 + */
3386 +
3387 +#ifndef __AVALANCHE_REGS_H
3388 +#define __AVALANCHE_REGS_H
3389 +
3390 +#include <asm/addrspace.h>
3391 +#include <linux/config.h>
3392 +
3393 +/*----------------------------------------*/
3394 +/* Base offsets within the Avalanche ASIC */
3395 +/*----------------------------------------*/
3396 +
3397 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
3398 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
3399 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
3400 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
3401 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
3402 +#define DES_BASE (KSEG1ADDR(0x08600000))
3403 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
3404 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
3405 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
3406 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
3407 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
3408 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
3409 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
3410 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
3411 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
3412 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
3413 +#define I2C_BASE (KSEG1ADDR(0x08611000))
3414 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
3415 +#define USB_BASE (KSEG1ADDR(0x08611200))
3416 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
3417 +#define DMA_BASE (KSEG1ADDR(0x08611400))
3418 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
3419 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
3420 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
3421 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
3422 +
3423 +/*---------------------------------*/
3424 +/* Device ID, chip version number */
3425 +/*---------------------------------*/
3426 +
3427 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
3428 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
3429 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
3430 +
3431 +/*----------------------------------*/
3432 +/* Reset Control VW changed to ptrs */
3433 +/*----------------------------------*/
3434 +
3435 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
3436 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
3437 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
3438 +
3439 +/* reset control bits */
3440 +
3441 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
3442 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
3443 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
3444 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
3445 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
3446 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
3447 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
3448 +/*
3449 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
3450 + If you reset the GPIO interface all of the directions (i/o) of the UART B
3451 + interface pins are inputs and must be reconfigured so as not to lose the
3452 + serial console interface
3453 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
3454 +*/
3455 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
3456 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
3457 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
3458 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
3459 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
3460 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
3461 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
3462 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
3463 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
3464 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
3465 +
3466 +/*----------------------*/
3467 +/* Physical interfaces */
3468 +/*----------------------*/
3469 +
3470 +/* Phy loopback */
3471 +#define PHY_LOOPBACK 1
3472 +
3473 +
3474 +/* Phy 0 */
3475 +#define PHY0BASE (PHY_BASE)
3476 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
3477 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
3478 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
3479 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
3480 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
3481 +
3482 +
3483 +/* Phy 1 */
3484 +
3485 +#define PHY1BASE (PHY_BASE + 0x100000)
3486 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
3487 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
3488 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
3489 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
3490 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
3491 +
3492 +/* Phy 2 */
3493 +
3494 +#define PHY2BASE (PHY_BASE + 0x200000)
3495 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
3496 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
3497 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
3498 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
3499 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
3500 +
3501 +/*-------------------*/
3502 +/* Avalanche ATM SAR */
3503 +/*-------------------*/
3504 +
3505 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
3506 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
3507 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
3508 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
3509 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
3510 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
3511 +
3512 +/* Transmit completion ring registers */
3513 +
3514 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
3515 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
3516 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
3517 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
3518 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
3519 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
3520 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
3521 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
3522 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
3523 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
3524 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
3525 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
3526 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
3527 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
3528 +
3529 +/* Transmit Queue Packet registers */
3530 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
3531 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
3532 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
3533 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
3534 +/* Receive completion ring registers */
3535 +
3536 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
3537 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
3538 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
3539 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
3540 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
3541 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
3542 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
3543 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
3544 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
3545 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
3546 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
3547 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
3548 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
3549 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
3550 +
3551 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
3552 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
3553 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
3554 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
3555 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
3556 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
3557 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
3558 +
3559 +
3560 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
3561 +
3562 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
3563 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
3564 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
3565 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
3566 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
3567 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
3568 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
3569 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
3570 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
3571 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
3572 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
3573 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
3574 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
3575 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
3576 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
3577 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
3578 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
3579 +
3580 +
3581 +/*
3582 +
3583 +#define OAM_CPID_ADD 0xa30104e0
3584 +
3585 +#define OAM_LLID_ADD 0xa30104f0
3586 +
3587 +#define OAM_LLID_VAL 0xffffffff
3588 +
3589 +#define OAM_CORR_TAG 0xa3010500
3590 +
3591 +#define OAM_FAR_COUNT_ADD 0xa3010520
3592 +
3593 +#define OAM_NEAR_COUNT_ADD 0xa3010540
3594 +
3595 +#define OAM_CONFIG_REG_ADD 0xa3000018
3596 +*/
3597 +
3598 +
3599 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
3600 +
3601 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
3602 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
3603 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
3604 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
3605 +
3606 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
3607 +
3608 +
3609 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
3610 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
3611 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
3612 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
3613 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
3614 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
3615 +
3616 +/*------------------------------------------*/
3617 +/* DSL Interface */
3618 +/*------------------------------------------*/
3619 +
3620 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
3621 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
3622 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
3623 +
3624 +/* Fast */
3625 +
3626 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
3627 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
3628 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
3629 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
3630 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
3631 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
3632 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
3633 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
3634 +
3635 +/* Interleaved */
3636 +
3637 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
3638 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
3639 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
3640 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
3641 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
3642 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
3643 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
3644 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
3645 +
3646 +/*------------------------------------------*/
3647 +/* Broadband I/F */
3648 +/*------------------------------------------*/
3649 +
3650 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
3651 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
3652 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
3653 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
3654 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
3655 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
3656 +
3657 +#define AVBBIF_DISABLED 0x0
3658 +#define AVBBIF_LBT4040_INT 0x1
3659 +#define AVBBIF_XBUS 0x2
3660 +#define AVBBIF_LBT4040_EXT 0x4
3661 +
3662 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
3663 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
3664 +#define AVBBIF_TRANS_MASK 0xff000000
3665 +/*------------------------------------------*/
3666 +/* GPIO I/F */
3667 +/*------------------------------------------*/
3668 +
3669 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
3670 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
3671 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
3672 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
3673 +
3674 +#define GPIO_0 (1<<21)
3675 +#define GPIO_1 (1<<22)
3676 +#define GPIO_2 (1<<23)
3677 +#define GPIO_3 (1<<24)
3678 +#define EINT_1 (1<<18)
3679 +
3680 +/*
3681 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
3682 + If you reset the GPIO interface all of the directions (i/o) of the UART B
3683 + interface pins are inputs and must be reconfigured so as not to lose the
3684 + serial console interface
3685 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
3686 +*/
3687 +
3688 +/*------------------------------------------*/
3689 +/* CLK_CTRL */
3690 +/*------------------------------------------*/
3691 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
3692 +
3693 +#define PCLK_0_HALF_VBUS (0<<16)
3694 +#define PCLK_EQ_INPUT (1<<16)
3695 +#define BBIF_CLK_HALF_VBUS (0<<17)
3696 +#define BBIF_CLK_EQ_VBUS (1<<17)
3697 +#define BBIF_CLK_EQ_BBCLK (3<<17)
3698 +#define DSP_MODCLK_DSPCLKI (0<<20)
3699 +#define DSP_MODCLK_REFCLKI (1<<20)
3700 +#define USB_CLK_EQ_USBCLKI (0<<21)
3701 +#define USB_CLK_EQ_REFCLKI (1<<21)
3702 +
3703 +/*------------------------------------------*/
3704 +/* PCI Control Registers */
3705 +/*------------------------------------------*/
3706 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
3707 +#define PCIC_CONTROL_CFG_DONE (1<<0)
3708 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
3709 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
3710 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
3711 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
3712 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
3713 +#define PCIC_CONTROL_MEM_MASK (1<<6)
3714 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
3715 +#define PCIC_CONTROL_IO_MASK (1<<8)
3716 +/* PCIC_CONTROL_RESERVED (1<<9) */
3717 +#define PCIC_CONTROL_BASE0_EN (1<<10)
3718 +#define PCIC_CONTROL_BASE1_EN (1<<11)
3719 +#define PCIC_CONTROL_BASE2_EN (1<<12)
3720 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
3721 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
3722 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
3723 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
3724 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
3725 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
3726 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
3727 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
3728 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
3729 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
3730 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
3731 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
3732 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
3733 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
3734 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
3735 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
3736 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
3737 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
3738 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
3739 +#define PCIC_INT_CLEAR_PM (1<<0)
3740 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
3741 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
3742 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
3743 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
3744 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
3745 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
3746 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
3747 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
3748 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
3749 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
3750 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
3751 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
3752 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
3753 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
3754 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
3755 +#define PCIC_INT_EN_AVAL_PM (1<<0)
3756 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
3757 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
3758 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
3759 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
3760 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
3761 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
3762 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
3763 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
3764 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
3765 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
3766 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
3767 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
3768 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
3769 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
3770 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
3771 +#define PCIC_INT_EN_PCI_PM (1<<0)
3772 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
3773 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
3774 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
3775 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
3776 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
3777 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
3778 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
3779 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
3780 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
3781 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
3782 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
3783 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
3784 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
3785 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
3786 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
3787 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
3788 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
3789 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
3790 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
3791 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
3792 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
3793 +/* PCIC_PM_CTL_RESERVED (1<<2) */
3794 +/* PCIC_PM_CTL_RESERVED (1<<3) */
3795 +/* PCIC_PM_CTL_RESERVED (1<<4) */
3796 +/* PCIC_PM_CTL_RESERVED (1<<5) */
3797 +/* PCIC_PM_CTL_RESERVED (1<<6) */
3798 +/* PCIC_PM_CTL_RESERVED (1<<7) */
3799 +/* PCIC_PM_CTL_RESERVED (1<<8) */
3800 +/* PCIC_PM_CTL_RESERVED (1<<9) */
3801 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
3802 +#define PCIC_PM_CTL_PMEIN (1<<11)
3803 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
3804 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
3805 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
3806 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
3807 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
3808 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
3809 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
3810 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
3811 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
3812 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
3813 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
3814 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
3815 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
3816 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
3817 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
3818 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
3819 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
3820 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
3821 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
3822 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
3823 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
3824 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
3825 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
3826 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
3827 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
3828 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
3829 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
3830 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
3831 +
3832 +/*------------------------------------------*/
3833 +/* IIC_INTERFACE */
3834 +/*------------------------------------------*/
3835 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
3836 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
3837 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
3838 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
3839 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
3840 +
3841 +#define I2CWRITE 0x200
3842 +#define I2CREAD 0x300
3843 +#define I2C_END_BURST 0x400
3844 +
3845 +/* read bits */
3846 +#define I2C_READ_ERROR 0x8000
3847 +#define I2C_READ_COMPLETE 0x4000
3848 +#define I2C_READ_BUSY 0x2000
3849 +
3850 +/* device types */
3851 +#define I2C_IO_EXPANDER 0x2
3852 +#define I2C_RTC 0xd
3853 +
3854 +/* device Addresses on I2C bus (EVM3) */
3855 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
3856 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
3857 +#define EVM3_RTC_I2C_ADDR 0x0
3858 +
3859 +/*------------------------------------------*/
3860 +/* Ethernet MAC register offset definitions */
3861 +/*------------------------------------------*/
3862 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
3863 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
3864 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
3865 +
3866 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
3867 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
3868 +
3869 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
3870 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
3871 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
3872 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
3873 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
3874 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
3875 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
3876 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
3877 +
3878 +
3879 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
3880 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
3881 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
3882 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
3883 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
3884 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
3885 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
3886 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
3887 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
3888 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
3889 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
3890 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
3891 +
3892 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
3893 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
3894 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
3895 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
3896 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
3897 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
3898 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
3899 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
3900 +
3901 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
3902 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
3903 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
3904 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
3905 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
3906 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
3907 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
3908 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
3909 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
3910 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
3911 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
3912 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
3913 +
3914 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
3915 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
3916 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
3917 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
3918 +
3919 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
3920 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
3921 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
3922 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
3923 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
3924 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
3925 +
3926 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
3927 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
3928 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
3929 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
3930 +
3931 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
3932 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
3933 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
3934 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
3935 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
3936 +
3937 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
3938 +
3939 +#endif __AVALANCHE_REGS_H
3940 +
3941 +
3942 +
3943 +
3944 +
3945 +
3946 diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-current/include/asm-mips/ar7/if_port.h
3947 --- kernel-base/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
3948 +++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260000 +0200
3949 @@ -0,0 +1,26 @@
3950 +/*******************************************************************************
3951 + * FILE PURPOSE: Interface port id Header file
3952 + *******************************************************************************
3953 + * FILE NAME: if_port.h
3954 + *
3955 + * DESCRIPTION: Header file carrying information about port ids of interfaces
3956 + *
3957 + *
3958 + * (C) Copyright 2003, Texas Instruments, Inc
3959 + ******************************************************************************/
3960 +#ifndef _IF_PORT_H_
3961 +#define _IF_PORT_H_
3962 +
3963 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
3964 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
3965 +#define AVALANCHE_USB_PORT_ID 2
3966 +#define AVALANCHE_WLAN_PORT_ID 3
3967 +
3968 +
3969 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
3970 +
3971 +/* The marvell ports occupy port ids from 4 to 8 */
3972 +/* so the next port id number should start at 9 */
3973 +
3974 +
3975 +#endif /* _IF_PORT_H_ */
3976 diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-current/include/asm-mips/ar7/sangam_boards.h
3977 --- kernel-base/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
3978 +++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260000 +0200
3979 @@ -0,0 +1,77 @@
3980 +#ifndef _SANGAM_BOARDS_H
3981 +#define _SANGAM_BOARDS_H
3982 +
3983 +// Let us define board specific information here.
3984 +
3985 +
3986 +#if defined(CONFIG_AR7DB)
3987 +
3988 +#define AFECLK_FREQ 35328000
3989 +#define REFCLK_FREQ 25000000
3990 +#define OSC3_FREQ 24000000
3991 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
3992 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
3993 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
3994 +
3995 +#endif
3996 +
3997 +
3998 +#if defined(CONFIG_AR7RD)
3999 +#define AFECLK_FREQ 35328000
4000 +#define REFCLK_FREQ 25000000
4001 +#define OSC3_FREQ 24000000
4002 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4003 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4004 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4005 +#endif
4006 +
4007 +
4008 +#if defined(CONFIG_AR7WI)
4009 +#define AFECLK_FREQ 35328000
4010 +#define REFCLK_FREQ 25000000
4011 +#define OSC3_FREQ 24000000
4012 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4013 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4014 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4015 +#endif
4016 +
4017 +
4018 +#if defined(CONFIG_AR7V)
4019 +#define AFECLK_FREQ 35328000
4020 +#define REFCLK_FREQ 25000000
4021 +#define OSC3_FREQ 24000000
4022 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4023 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4024 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4025 +#endif
4026 +
4027 +
4028 +#if defined(CONFIG_AR7WRD)
4029 +#define AFECLK_FREQ 35328000
4030 +#define REFCLK_FREQ 25000000
4031 +#define OSC3_FREQ 24000000
4032 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4033 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4034 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4035 +#endif
4036 +
4037 +
4038 +#if defined(CONFIG_AR7VWI)
4039 +#define AFECLK_FREQ 35328000
4040 +#define REFCLK_FREQ 25000000
4041 +#define OSC3_FREQ 24000000
4042 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4043 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4044 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4045 +#endif
4046 +
4047 +
4048 +#if defined CONFIG_SEAD2
4049 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
4050 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
4051 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
4052 +#include <asm/mips-boards/sead.h>
4053 +#endif
4054 +
4055 +
4056 +#endif
4057 diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-current/include/asm-mips/ar7/sangam.h
4058 --- kernel-base/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
4059 +++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260000 +0200
4060 @@ -0,0 +1,180 @@
4061 +#ifndef _SANGAM_H_
4062 +#define _SANGAM_H_
4063 +
4064 +#include <linux/config.h>
4065 +#include <asm/addrspace.h>
4066 +
4067 +/*----------------------------------------------------
4068 + * Sangam's Module Base Addresses
4069 + *--------------------------------------------------*/
4070 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
4071 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
4072 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
4073 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
4074 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
4075 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
4076 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
4077 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
4078 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
4079 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
4080 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
4081 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
4082 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
4083 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
4084 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
4085 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
4086 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
4087 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
4088 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
4089 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
4090 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
4091 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
4092 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
4093 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
4094 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
4095 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
4096 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
4097 +
4098 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
4099 +
4100 +
4101 +/*----------------------------------------------------
4102 + * Sangam Interrupt Map (Primary Interrupts)
4103 + *--------------------------------------------------*/
4104 +
4105 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
4106 +#define AVALANCHE_EXT_INT_0 1
4107 +#define AVALANCHE_EXT_INT_1 2
4108 +/* Line# 3 to 4 are reserved */
4109 +#define AVALANCHE_TIMER_0_INT 5
4110 +#define AVALANCHE_TIMER_1_INT 6
4111 +#define AVALANCHE_UART0_INT 7
4112 +#define AVALANCHE_UART1_INT 8
4113 +#define AVALANCHE_DMA_INT0 9
4114 +#define AVALANCHE_DMA_INT1 10
4115 +/* Line# 11 to 14 are reserved */
4116 +#define AVALANCHE_ATM_SAR_INT 15
4117 +/* Line# 16 to 18 are reserved */
4118 +#define AVALANCHE_LOW_CPMAC_INT 19
4119 +/* Line# 20 is reserved */
4120 +#define AVALANCHE_LOW_VLYNQ_INT 21
4121 +#define AVALANCHE_CODEC_WAKEUP_INT 22
4122 +/* Line# 23 is reserved */
4123 +#define AVALANCHE_USB_SLAVE_INT 24
4124 +#define AVALANCHE_HIGH_VLYNQ_INT 25
4125 +/* Line# 26 to 27 are reserved */
4126 +#define AVALANCHE_UNIFIED_PHY_INT 28
4127 +#define AVALANCHE_I2C_INT 29
4128 +#define AVALANCHE_DMA_INT2 30
4129 +#define AVALANCHE_DMA_INT3 31
4130 +/* Line# 32 is reserved */
4131 +#define AVALANCHE_HIGH_CPMAC_INT 33
4132 +/* Line# 34 to 36 is reserved */
4133 +#define AVALANCHE_VDMA_VT_RX_INT 37
4134 +#define AVALANCHE_VDMA_VT_TX_INT 38
4135 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
4136 +
4137 +
4138 +#define AVALANCHE_EMIF_INT 47
4139 +
4140 +
4141 +
4142 +/*-----------------------------------------------------------
4143 + * Sangam's Reset Bits
4144 + *---------------------------------------------------------*/
4145 +
4146 +#define AVALANCHE_UART0_RESET_BIT 0
4147 +#define AVALANCHE_UART1_RESET_BIT 1
4148 +#define AVALANCHE_I2C_RESET_BIT 2
4149 +#define AVALANCHE_TIMER0_RESET_BIT 3
4150 +#define AVALANCHE_TIMER1_RESET_BIT 4
4151 +/* Reset bit 5 is reserved. */
4152 +#define AVALANCHE_GPIO_RESET_BIT 6
4153 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
4154 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
4155 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
4156 +/* Reset bit 10 is reserved. */
4157 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
4158 +#define AVALANCHE_FSER_RESET_BIT 12
4159 +/* Reset bit 13 to 15 are reserved */
4160 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
4161 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
4162 +#define AVALANCHE_MCDMA_RESET_BIT 18
4163 +#define AVALANCHE_BIST_RESET_BIT 19
4164 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
4165 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
4166 +#define AVALANCHE_MDIO_RESET_BIT 22
4167 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
4168 +/* Reset bit 24 to 25 are reserved */
4169 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
4170 +/* Reset bit 27 to 31 are reserved */
4171 +
4172 +
4173 +#define AVALANCHE_POWER_MODULE_USBSP 0
4174 +#define AVALANCHE_POWER_MODULE_WDTP 1
4175 +#define AVALANCHE_POWER_MODULE_UT0P 2
4176 +#define AVALANCHE_POWER_MODULE_UT1P 3
4177 +#define AVALANCHE_POWER_MODULE_IICP 4
4178 +#define AVALANCHE_POWER_MODULE_VDMAP 5
4179 +#define AVALANCHE_POWER_MODULE_GPIOP 6
4180 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
4181 +#define AVALANCHE_POWER_MODULE_SARP 8
4182 +#define AVALANCHE_POWER_MODULE_ADSLP 9
4183 +#define AVALANCHE_POWER_MODULE_EMIFP 10
4184 +#define AVALANCHE_POWER_MODULE_ADSPP 12
4185 +#define AVALANCHE_POWER_MODULE_RAMP 13
4186 +#define AVALANCHE_POWER_MODULE_ROMP 14
4187 +#define AVALANCHE_POWER_MODULE_DMAP 15
4188 +#define AVALANCHE_POWER_MODULE_BISTP 16
4189 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
4190 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
4191 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
4192 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
4193 +#define AVALANCHE_POWER_MODULE_EPHYP 24
4194 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
4195 +
4196 +
4197 +
4198 +
4199 +
4200 +/*
4201 + * Sangam board vectors
4202 + */
4203 +
4204 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
4205 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
4206 +
4207 +/*-----------------------------------------------------------------------------
4208 + * Sangam's system register.
4209 + *
4210 + *---------------------------------------------------------------------------*/
4211 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
4212 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
4213 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
4214 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
4215 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
4216 +
4217 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
4218 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
4219 +
4220 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
4221 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
4222 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
4223 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
4224 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
4225 +
4226 +/*
4227 + * Yamon Prom print address.
4228 + */
4229 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
4230 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
4231 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
4232 +
4233 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
4234 +
4235 +#define AVALANCHE_GPIO_PIN_COUNT 32
4236 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
4237 +
4238 +#include "sangam_boards.h"
4239 +
4240 +#endif /*_SANGAM_H_ */
4241 diff -urN kernel-base/include/asm-mips/io.h kernel-current/include/asm-mips/io.h
4242 --- kernel-base/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200
4243 +++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260000 +0200
4244 @@ -63,8 +63,12 @@
4245 #ifdef CONFIG_64BIT_PHYS_ADDR
4246 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
4247 #else
4248 +#ifdef CONFIG_AR7_PAGING
4249 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
4250 +#else
4251 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
4252 #endif
4253 +#endif
4254
4255 #define IO_SPACE_LIMIT 0xffff
4256
4257 diff -urN kernel-base/include/asm-mips/irq.h kernel-current/include/asm-mips/irq.h
4258 --- kernel-base/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200
4259 +++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260000 +0200
4260 @@ -14,7 +14,12 @@
4261 #include <linux/config.h>
4262 #include <linux/linkage.h>
4263
4264 +#ifdef CONFIG_AR7
4265 +#include <asm/ar7/avalanche_intc.h>
4266 +#define NR_IRQS AVALANCHE_INT_END + 1
4267 +#else
4268 #define NR_IRQS 128 /* Largest number of ints of all machines. */
4269 +#endif
4270
4271 #ifdef CONFIG_I8259
4272 static inline int irq_cannonicalize(int irq)
4273 diff -urN kernel-base/include/asm-mips/page.h kernel-current/include/asm-mips/page.h
4274 --- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
4275 +++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260000 +0200
4276 @@ -129,7 +129,11 @@
4277
4278 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
4279 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
4280 +#ifdef CONFIG_AR7_PAGING
4281 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
4282 +#else
4283 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
4284 +#endif
4285 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
4286
4287 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
4288 diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-current/include/asm-mips/pgtable-32.h
4289 --- kernel-base/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200
4290 +++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260000 +0200
4291 @@ -108,7 +108,18 @@
4292 * and a page entry and page directory to the page they refer to.
4293 */
4294
4295 -#ifdef CONFIG_CPU_VR41XX
4296 +#if defined(CONFIG_AR7_PAGING)
4297 +#define mk_pte(page, pgprot) \
4298 +({ \
4299 + pte_t __pte; \
4300 + \
4301 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
4302 + CONFIG_AR7_MEMORY) | \
4303 + pgprot_val(pgprot); \
4304 + \
4305 + __pte; \
4306 +})
4307 +#elif defined(CONFIG_CPU_VR41XX)
4308 #define mk_pte(page, pgprot) \
4309 ({ \
4310 pte_t __pte; \
4311 @@ -130,6 +141,7 @@
4312 })
4313 #endif
4314
4315 +
4316 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
4317 {
4318 #ifdef CONFIG_CPU_VR41XX
4319 @@ -175,7 +187,10 @@
4320 set_pte(ptep, __pte(0));
4321 }
4322
4323 -#ifdef CONFIG_CPU_VR41XX
4324 +#if defined(CONFIG_AR7_PAGING)
4325 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
4326 +#define pte_page(x) phys_to_page(pte_val(x))
4327 +#elif defined(CONFIG_CPU_VR41XX)
4328 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
4329 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
4330 #else
4331 diff -urN kernel-base/include/asm-mips/serial.h kernel-current/include/asm-mips/serial.h
4332 --- kernel-base/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200
4333 +++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260000 +0200
4334 @@ -65,6 +65,15 @@
4335
4336 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
4337
4338 +#ifdef CONFIG_AR7
4339 +#include <asm/ar7/ar7.h>
4340 +#define AR7_SERIAL_PORT_DEFNS \
4341 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
4342 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
4343 +#else
4344 +#define AR7_SERIAL_PORT_DEFNS
4345 +#endif
4346 +
4347 #ifdef CONFIG_MIPS_JAZZ
4348 #define _JAZZ_SERIAL_INIT(int, base) \
4349 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
4350 @@ -468,6 +477,7 @@
4351 #endif
4352
4353 #define SERIAL_PORT_DFNS \
4354 + AR7_SERIAL_PORT_DEFNS \
4355 ATLAS_SERIAL_PORT_DEFNS \
4356 AU1000_SERIAL_PORT_DEFNS \
4357 COBALT_SERIAL_PORT_DEFNS \
4358 diff -urN kernel-base/Makefile kernel-current/Makefile
4359 --- kernel-base/Makefile 2005-07-10 03:00:44.799179096 +0200
4360 +++ kernel-current/Makefile 2005-07-10 06:40:39.626260000 +0200
4361 @@ -91,7 +91,7 @@
4362
4363 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
4364
4365 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
4366 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
4367 -fno-strict-aliasing -fno-common
4368 ifndef CONFIG_FRAME_POINTER
4369 CFLAGS += -fomit-frame-pointer
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