target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h

   1 /*
   2  * Misc useful routines to access NIC local SROM/OTP .
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #ifndef _bcmsrom_h_
  16 #define _bcmsrom_h_
  17
  18 /* Maximum srom: 4 Kilobits == 512 bytes */
  19 #define SROM_MAX                512
  20
  21
  22 #define SROM_WORDS              64
  23
  24 #define SROM3_SWRGN_OFF         28      /* s/w region offset in words */
  25
  26 #define SROM_SSID               2
  27
  28 #define SROM_WL1LHMAXP          29
  29
  30 #define SROM_WL1LPAB0           30
  31 #define SROM_WL1LPAB1           31
  32 #define SROM_WL1LPAB2           32
  33
  34 #define SROM_WL1HPAB0           33
  35 #define SROM_WL1HPAB1           34
  36 #define SROM_WL1HPAB2           35
  37
  38 #define SROM_MACHI_IL0          36
  39 #define SROM_MACMID_IL0         37
  40 #define SROM_MACLO_IL0          38
  41 #define SROM_MACHI_ET0          39
  42 #define SROM_MACMID_ET0         40
  43 #define SROM_MACLO_ET0          41
  44 #define SROM_MACHI_ET1          42
  45 #define SROM_MACMID_ET1         43
  46 #define SROM_MACLO_ET1          44
  47 #define SROM3_MACHI             37
  48 #define SROM3_MACMID            38
  49 #define SROM3_MACLO             39
  50
  51 #define SROM_BXARSSI2G          40
  52 #define SROM_BXARSSI5G          41
  53
  54 #define SROM_TRI52G             42
  55 #define SROM_TRI5GHL            43
  56
  57 #define SROM_RXPO52G            45
  58
  59 #define SROM2_ENETPHY           45
  60
  61 #define SROM_AABREV             46
  62 /* Fields in AABREV */
  63 #define SROM_BR_MASK            0x00ff
  64 #define SROM_CC_MASK            0x0f00
  65 #define SROM_CC_SHIFT           8
  66 #define SROM_AA0_MASK           0x3000
  67 #define SROM_AA0_SHIFT          12
  68 #define SROM_AA1_MASK           0xc000
  69 #define SROM_AA1_SHIFT          14
  70
  71 #define SROM_WL0PAB0            47
  72 #define SROM_WL0PAB1            48
  73 #define SROM_WL0PAB2            49
  74
  75 #define SROM_LEDBH10            50
  76 #define SROM_LEDBH32            51
  77
  78 #define SROM_WL10MAXP           52
  79
  80 #define SROM_WL1PAB0            53
  81 #define SROM_WL1PAB1            54
  82 #define SROM_WL1PAB2            55
  83
  84 #define SROM_ITT                56
  85
  86 #define SROM_BFL                57
  87 #define SROM_BFL2               28
  88 #define SROM3_BFL2              61
  89
  90 #define SROM_AG10               58
  91
  92 #define SROM_CCODE              59
  93
  94 #define SROM_OPO                60
  95
  96 #define SROM3_LEDDC             62
  97
  98 #define SROM_CRCREV             63
  99
 100 /* SROM Rev 4: Reallocate the software part of the srom to accomodate
 101  * MIMO features. It assumes up to two PCIE functions and 440 bytes
 102  * of useable srom i.e. the useable storage in chips with OTP that
 103  * implements hardware redundancy.
 104  */
 105
 106 #define SROM4_WORDS             220
 107
 108 #define SROM4_SIGN              32
 109 #define SROM4_SIGNATURE         0x5372
 110
 111 #define SROM4_BREV              33
 112
 113 #define SROM4_BFL0              34
 114 #define SROM4_BFL1              35
 115 #define SROM4_BFL2              36
 116 #define SROM4_BFL3              37
 117 #define SROM5_BFL0              37
 118 #define SROM5_BFL1              38
 119 #define SROM5_BFL2              39
 120 #define SROM5_BFL3              40
 121
 122 #define SROM4_MACHI             38
 123 #define SROM4_MACMID            39
 124 #define SROM4_MACLO             40
 125 #define SROM5_MACHI             41
 126 #define SROM5_MACMID            42
 127 #define SROM5_MACLO             43
 128
 129 #define SROM4_CCODE             41
 130 #define SROM4_REGREV            42
 131 #define SROM5_CCODE             34
 132 #define SROM5_REGREV            35
 133
 134 #define SROM4_LEDBH10           43
 135 #define SROM4_LEDBH32           44
 136 #define SROM5_LEDBH10           59
 137 #define SROM5_LEDBH32           60
 138
 139 #define SROM4_LEDDC             45
 140 #define SROM5_LEDDC             45
 141
 142 #define SROM4_AA                46
 143 #define SROM4_AA2G_MASK         0x00ff
 144 #define SROM4_AA2G_SHIFT        0
 145 #define SROM4_AA5G_MASK         0xff00
 146 #define SROM4_AA5G_SHIFT        8
 147
 148 #define SROM4_AG10              47
 149 #define SROM4_AG32              48
 150
 151 #define SROM4_TXPID2G           49
 152 #define SROM4_TXPID5G           51
 153 #define SROM4_TXPID5GL          53
 154 #define SROM4_TXPID5GH          55
 155
 156 #define SROM4_TXRXC             61
 157 #define SROM4_TXCHAIN_MASK      0x000f
 158 #define SROM4_TXCHAIN_SHIFT     0
 159 #define SROM4_RXCHAIN_MASK      0x00f0
 160 #define SROM4_RXCHAIN_SHIFT     4
 161 #define SROM4_SWITCH_MASK       0xff00
 162 #define SROM4_SWITCH_SHIFT      8
 163
 164 /* Per-path fields */
 165 #define MAX_PATH                4
 166 #define SROM4_PATH0             64
 167 #define SROM4_PATH1             87
 168 #define SROM4_PATH2             110
 169 #define SROM4_PATH3             133
 170
 171 #define SROM4_2G_ITT_MAXP       0
 172 #define SROM4_2G_PA             1
 173 #define SROM4_5G_ITT_MAXP       5
 174 #define SROM4_5GLH_MAXP         6
 175 #define SROM4_5G_PA             7
 176 #define SROM4_5GL_PA            11
 177 #define SROM4_5GH_PA            15
 178
 179 /* Fields in the ITT_MAXP and 5GLH_MAXP words */
 180 #define B2G_MAXP_MASK           0xff
 181 #define B2G_ITT_SHIFT           8
 182 #define B5G_MAXP_MASK           0xff
 183 #define B5G_ITT_SHIFT           8
 184 #define B5GH_MAXP_MASK          0xff
 185 #define B5GL_MAXP_SHIFT         8
 186
 187 /* All the miriad power offsets */
 188 #define SROM4_2G_CCKPO          156
 189 #define SROM4_2G_OFDMPO         157
 190 #define SROM4_5G_OFDMPO         159
 191 #define SROM4_5GL_OFDMPO        161
 192 #define SROM4_5GH_OFDMPO        163
 193 #define SROM4_2G_MCSPO          165
 194 #define SROM4_5G_MCSPO          173
 195 #define SROM4_5GL_MCSPO         181
 196 #define SROM4_5GH_MCSPO         189
 197 #define SROM4_CDDPO             197
 198 #define SROM4_STBCPO            198
 199 #define SROM4_BW40PO            199
 200 #define SROM4_BWDUPPO           200
 201
 202 #define SROM4_CRCREV            219
 203
 204
 205 /*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
 206  * This is acombined srom for both MIMO and SISO boards, usable in
 207  * the .130 4Kilobit OTP with hardware redundancy.
 208  */
 209
 210 #define SROM8_SIGN              64
 211
 212 #define SROM8_BREV              65
 213
 214 #define SROM8_BFL0              66
 215 #define SROM8_BFL1              67
 216 #define SROM8_BFL2              68
 217 #define SROM8_BFL3              69
 218
 219 #define SROM8_MACHI             70
 220 #define SROM8_MACMID            71
 221 #define SROM8_MACLO             72
 222
 223 #define SROM8_CCODE             73
 224 #define SROM8_REGREV            74
 225
 226 #define SROM8_LEDBH10           75
 227 #define SROM8_LEDBH32           76
 228
 229 #define SROM8_LEDDC             77
 230
 231 #define SROM8_AA                78
 232
 233 #define SROM8_AG10              79
 234 #define SROM8_AG32              80
 235
 236 #define SROM8_TXRXC             81
 237
 238 #define SROM8_BXARSSI2G         82
 239 #define SROM8_BXARSSI5G         83
 240 #define SROM8_TRI52G            84
 241 #define SROM8_TRI5GHL           85
 242 #define SROM8_RXPO52G           86
 243
 244 /* Per-path offsets & fields */
 245 #define SROM8_PATH0             96
 246 #define SROM8_PATH1             112
 247 #define SROM8_PATH2             128
 248 #define SROM8_PATH3             144
 249
 250 #define SROM8_2G_ITT_MAXP       0
 251 #define SROM8_2G_PA             1
 252 #define SROM8_5G_ITT_MAXP       4
 253 #define SROM8_5GLH_MAXP         5
 254 #define SROM8_5G_PA             6
 255 #define SROM8_5GL_PA            9
 256 #define SROM8_5GH_PA            12
 257
 258 /* All the miriad power offsets */
 259 #define SROM8_2G_CCKPO          160
 260
 261 #define SROM8_2G_OFDMPO         161
 262 #define SROM8_5G_OFDMPO         163
 263 #define SROM8_5GL_OFDMPO        165
 264 #define SROM8_5GH_OFDMPO        167
 265
 266 #define SROM8_2G_MCSPO          169
 267 #define SROM8_5G_MCSPO          177
 268 #define SROM8_5GL_MCSPO         185
 269 #define SROM8_5GH_MCSPO         193
 270
 271 #define SROM8_CDDPO             201
 272 #define SROM8_STBCPO            202
 273 #define SROM8_BW40PO            203
 274 #define SROM8_BWDUPPO           204
 275
 276 /* SISO PA parameters are in the path0 spaces */
 277 #define SROM8_SISO              96
 278
 279 /* Legacy names for SISO PA paramters */
 280 #define SROM8_W0_ITTMAXP        (SROM8_SISO + SROM8_2G_ITT_MAXP)
 281 #define SROM8_W0_PAB0           (SROM8_SISO + SROM8_2G_PA)
 282 #define SROM8_W0_PAB1           (SROM8_SISO + SROM8_2G_PA + 1)
 283 #define SROM8_W0_PAB2           (SROM8_SISO + SROM8_2G_PA + 2)
 284 #define SROM8_W1_ITTMAXP        (SROM8_SISO + SROM8_5G_ITT_MAXP)
 285 #define SROM8_W1_MAXP_LCHC      (SROM8_SISO + SROM8_5GLH_MAXP)
 286 #define SROM8_W1_PAB0           (SROM8_SISO + SROM8_5G_PA)
 287 #define SROM8_W1_PAB1           (SROM8_SISO + SROM8_5G_PA + 1)
 288 #define SROM8_W1_PAB2           (SROM8_SISO + SROM8_5G_PA + 2)
 289 #define SROM8_W1_PAB0_LC        (SROM8_SISO + SROM8_5GL_PA)
 290 #define SROM8_W1_PAB1_LC        (SROM8_SISO + SROM8_5GL_PA + 1)
 291 #define SROM8_W1_PAB2_LC        (SROM8_SISO + SROM8_5GL_PA + 2)
 292 #define SROM8_W1_PAB0_HC        (SROM8_SISO + SROM8_5GH_PA)
 293 #define SROM8_W1_PAB1_HC        (SROM8_SISO + SROM8_5GH_PA + 1)
 294 #define SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
 295
 296 #define SROM8_CRCREV            219
 297
 298 /* Prototypes */
 299 extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 300                          char **vars, uint *count);
 301
 302 extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 303                      uint byteoff, uint nbytes, uint16 *buf);
 304 extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 305                       uint byteoff, uint nbytes, uint16 *buf);
 306
 307 extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
 308                          char **vars, uint *count);
 309
 310 #endif  /* _bcmsrom_h_ */