target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/sbconfig.h

   1 /*
   2  * Broadcom SiliconBackplane hardware register definitions.
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #ifndef _SBCONFIG_H
  16 #define _SBCONFIG_H
  17 #include "linuxver.h"
  18
  19 /* cpp contortions to concatenate w/arg prescan */
  20 #ifndef PAD
  21 #define _PADLINE(line)  pad ## line
  22 #define _XSTR(line)     _PADLINE(line)
  23 #define PAD             _XSTR(__LINE__)
  24 #endif
  25
  26 /*
  27  * SiliconBackplane Address Map.
  28  * All regions may not exist on all chips.
  29  */
  30 #define SB_SDRAM_BASE           0x00000000      /* Physical SDRAM */
  31 #define SB_PCI_MEM              0x08000000      /* Host Mode sb2pcitranslation0 (64 MB) */
  32 #define SB_PCI_MEM_SZ           (64 * 1024 * 1024)
  33 #define SB_PCI_CFG              0x0c000000      /* Host Mode sb2pcitranslation1 (64 MB) */
  34 #define SB_SDRAM_SWAPPED        0x10000000      /* Byteswapped Physical SDRAM */
  35 #define SB_ENUM_BASE            0x18000000      /* Enumeration space base */
  36 #define SB_ENUM_LIM             0x18010000      /* Enumeration space limit */
  37
  38 #define SB_FLASH2               0x1c000000      /* Flash Region 2 (region 1 shadowed here) */
  39 #define SB_FLASH2_SZ            0x02000000      /* Size of Flash Region 2 */
  40 #define SB_EXTIF_BASE           0x1f000000      /* External Interface region base address */
  41 #define SB_ARMCM3_ROM           0x1e000000      /* ARM Cortex-M3 ROM */
  42 #define SB_FLASH1               0x1fc00000      /* MIPS Flash Region 1 */
  43 #define SB_FLASH1_SZ            0x00400000      /* MIPS Size of Flash Region 1 */
  44 #define SB_ARM7S_ROM            0x20000000      /* ARM7TDMI-S ROM */
  45 #define SB_ARMCM3_SRAM2         0x60000000      /* ARM Cortex-M3 SRAM Region 2 */
  46 #define SB_ARM7S_SRAM2          0x80000000      /* ARM7TDMI-S SRAM Region 2 */
  47 #define SB_ARM_FLASH1           0xffff0000      /* ARM Flash Region 1 */
  48 #define SB_ARM_FLASH1_SZ        0x00010000      /* ARM Size of Flash Region 1 */
  49
  50 #define SB_PCI_DMA              0x40000000      /* Client Mode sb2pcitranslation2 (1 GB) */
  51 #define SB_PCI_DMA_SZ           0x40000000      /* Client Mode sb2pcitranslation2 size in bytes */
  52 #define SB_PCIE_DMA_L32         0x00000000      /* PCIE Client Mode sb2pcitranslation2
  53                                                  * (2 ZettaBytes), low 32 bits
  54                                                  */
  55 #define SB_PCIE_DMA_H32         0x80000000      /* PCIE Client Mode sb2pcitranslation2
  56                                                  * (2 ZettaBytes), high 32 bits
  57                                                  */
  58 #define SB_EUART                (SB_EXTIF_BASE + 0x00800000)
  59 #define SB_LED                  (SB_EXTIF_BASE + 0x00900000)
  60
  61
  62 /* enumeration space related defs */
  63 #define SB_CORE_SIZE            0x1000          /* each core gets 4Kbytes for registers */
  64 #define SB_MAXCORES             ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
  65 #define SB_MAXFUNCS             4               /* max. # functions per core */
  66 #define SBCONFIGOFF             0xf00           /* core sbconfig regs are top 256bytes of regs */
  67 #define SBCONFIGSIZE            256             /* sizeof (sbconfig_t) */
  68
  69 /* mips address */
  70 #define SB_EJTAG                0xff200000      /* MIPS EJTAG space (2M) */
  71
  72 /*
  73  * Sonics Configuration Space Registers.
  74  */
  75 #define SBIPSFLAG               0x08
  76 #define SBTPSFLAG               0x18
  77 #define SBTMERRLOGA             0x48            /* sonics >= 2.3 */
  78 #define SBTMERRLOG              0x50            /* sonics >= 2.3 */
  79 #define SBADMATCH3              0x60
  80 #define SBADMATCH2              0x68
  81 #define SBADMATCH1              0x70
  82 #define SBIMSTATE               0x90
  83 #define SBINTVEC                0x94
  84 #define SBTMSTATELOW            0x98
  85 #define SBTMSTATEHIGH           0x9c
  86 #define SBBWA0                  0xa0
  87 #define SBIMCONFIGLOW           0xa8
  88 #define SBIMCONFIGHIGH          0xac
  89 #define SBADMATCH0              0xb0
  90 #define SBTMCONFIGLOW           0xb8
  91 #define SBTMCONFIGHIGH          0xbc
  92 #define SBBCONFIG               0xc0
  93 #define SBBSTATE                0xc8
  94 #define SBACTCNFG               0xd8
  95 #define SBFLAGST                0xe8
  96 #define SBIDLOW                 0xf8
  97 #define SBIDHIGH                0xfc
  98
  99 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
 100  * a few registers *below* that line. I think it would be very confusing to try
 101  * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
 102  */
 103
 104 #define SBIMERRLOGA             0xea8
 105 #define SBIMERRLOG              0xeb0
 106 #define SBTMPORTCONNID0         0xed8
 107 #define SBTMPORTLOCK0           0xef8
 108
 109 #ifndef _LANGUAGE_ASSEMBLY
 110
 111 typedef volatile struct _sbconfig {
 112         uint32  PAD[2];
 113         uint32  sbipsflag;              /* initiator port ocp slave flag */
 114         uint32  PAD[3];
 115         uint32  sbtpsflag;              /* target port ocp slave flag */
 116         uint32  PAD[11];
 117         uint32  sbtmerrloga;            /* (sonics >= 2.3) */
 118         uint32  PAD;
 119         uint32  sbtmerrlog;             /* (sonics >= 2.3) */
 120         uint32  PAD[3];
 121         uint32  sbadmatch3;             /* address match3 */
 122         uint32  PAD;
 123         uint32  sbadmatch2;             /* address match2 */
 124         uint32  PAD;
 125         uint32  sbadmatch1;             /* address match1 */
 126         uint32  PAD[7];
 127         uint32  sbimstate;              /* initiator agent state */
 128         uint32  sbintvec;               /* interrupt mask */
 129         uint32  sbtmstatelow;           /* target state */
 130         uint32  sbtmstatehigh;          /* target state */
 131         uint32  sbbwa0;                 /* bandwidth allocation table0 */
 132         uint32  PAD;
 133         uint32  sbimconfiglow;          /* initiator configuration */
 134         uint32  sbimconfighigh;         /* initiator configuration */
 135         uint32  sbadmatch0;             /* address match0 */
 136         uint32  PAD;
 137         uint32  sbtmconfiglow;          /* target configuration */
 138         uint32  sbtmconfighigh;         /* target configuration */
 139         uint32  sbbconfig;              /* broadcast configuration */
 140         uint32  PAD;
 141         uint32  sbbstate;               /* broadcast state */
 142         uint32  PAD[3];
 143         uint32  sbactcnfg;              /* activate configuration */
 144         uint32  PAD[3];
 145         uint32  sbflagst;               /* current sbflags */
 146         uint32  PAD[3];
 147         uint32  sbidlow;                /* identification */
 148         uint32  sbidhigh;               /* identification */
 149 } sbconfig_t;
 150
 151 #endif /* _LANGUAGE_ASSEMBLY */
 152
 153 /* sbipsflag */
 154 #define SBIPS_INT1_MASK         0x3f            /* which sbflags get routed to mips interrupt 1 */
 155 #define SBIPS_INT1_SHIFT        0
 156 #define SBIPS_INT2_MASK         0x3f00          /* which sbflags get routed to mips interrupt 2 */
 157 #define SBIPS_INT2_SHIFT        8
 158 #define SBIPS_INT3_MASK         0x3f0000        /* which sbflags get routed to mips interrupt 3 */
 159 #define SBIPS_INT3_SHIFT        16
 160 #define SBIPS_INT4_MASK         0x3f000000      /* which sbflags get routed to mips interrupt 4 */
 161 #define SBIPS_INT4_SHIFT        24
 162
 163 /* sbtpsflag */
 164 #define SBTPS_NUM0_MASK         0x3f            /* interrupt sbFlag # generated by this core */
 165 #define SBTPS_F0EN0             0x40            /* interrupt is always sent on the backplane */
 166
 167 /* sbtmerrlog */
 168 #define SBTMEL_CM               0x00000007      /* command */
 169 #define SBTMEL_CI               0x0000ff00      /* connection id */
 170 #define SBTMEL_EC               0x0f000000      /* error code */
 171 #define SBTMEL_ME               0x80000000      /* multiple error */
 172
 173 /* sbimstate */
 174 #define SBIM_PC                 0xf             /* pipecount */
 175 #define SBIM_AP_MASK            0x30            /* arbitration policy */
 176 #define SBIM_AP_BOTH            0x00            /* use both timeslaces and token */
 177 #define SBIM_AP_TS              0x10            /* use timesliaces only */
 178 #define SBIM_AP_TK              0x20            /* use token only */
 179 #define SBIM_AP_RSV             0x30            /* reserved */
 180 #define SBIM_IBE                0x20000         /* inbanderror */
 181 #define SBIM_TO                 0x40000         /* timeout */
 182 #define SBIM_BY                 0x01800000      /* busy (sonics >= 2.3) */
 183 #define SBIM_RJ                 0x02000000      /* reject (sonics >= 2.3) */
 184
 185 /* sbtmstatelow */
 186 #define SBTML_RESET             0x1             /* reset */
 187 #define SBTML_REJ_MASK          0x6             /* reject */
 188 #define SBTML_REJ_SHIFT         1
 189 #define SBTML_CLK               0x10000         /* clock enable */
 190 #define SBTML_FGC               0x20000         /* force gated clocks on */
 191 #define SBTML_FL_MASK           0x3ffc0000      /* core-specific flags */
 192 #define SBTML_PE                0x40000000      /* pme enable */
 193 #define SBTML_BE                0x80000000      /* bist enable */
 194
 195 /* sbtmstatehigh */
 196 #define SBTMH_SERR              0x1             /* serror */
 197 #define SBTMH_INT               0x2             /* interrupt */
 198 #define SBTMH_BUSY              0x4             /* busy */
 199 #define SBTMH_TO                0x00000020      /* timeout (sonics >= 2.3) */
 200 #define SBTMH_FL_MASK           0x0fff0000      /* core-specific flags */
 201 #define SBTMH_DMA64             0x10000000      /* supports DMA with 64-bit addresses */
 202 #define SBTMH_GCR               0x20000000      /* gated clock request */
 203 #define SBTMH_BISTF             0x40000000      /* bist failed */
 204 #define SBTMH_BISTD             0x80000000      /* bist done */
 205
 206
 207 /* sbbwa0 */
 208 #define SBBWA_TAB0_MASK         0xffff          /* lookup table 0 */
 209 #define SBBWA_TAB1_MASK         0xffff          /* lookup table 1 */
 210 #define SBBWA_TAB1_SHIFT        16
 211
 212 /* sbimconfiglow */
 213 #define SBIMCL_STO_MASK         0x7             /* service timeout */
 214 #define SBIMCL_RTO_MASK         0x70            /* request timeout */
 215 #define SBIMCL_RTO_SHIFT        4
 216 #define SBIMCL_CID_MASK         0xff0000        /* connection id */
 217 #define SBIMCL_CID_SHIFT        16
 218
 219 /* sbimconfighigh */
 220 #define SBIMCH_IEM_MASK         0xc             /* inband error mode */
 221 #define SBIMCH_TEM_MASK         0x30            /* timeout error mode */
 222 #define SBIMCH_TEM_SHIFT        4
 223 #define SBIMCH_BEM_MASK         0xc0            /* bus error mode */
 224 #define SBIMCH_BEM_SHIFT        6
 225
 226 /* sbadmatch0 */
 227 #define SBAM_TYPE_MASK          0x3             /* address type */
 228 #define SBAM_AD64               0x4             /* reserved */
 229 #define SBAM_ADINT0_MASK        0xf8            /* type0 size */
 230 #define SBAM_ADINT0_SHIFT       3
 231 #define SBAM_ADINT1_MASK        0x1f8           /* type1 size */
 232 #define SBAM_ADINT1_SHIFT       3
 233 #define SBAM_ADINT2_MASK        0x1f8           /* type2 size */
 234 #define SBAM_ADINT2_SHIFT       3
 235 #define SBAM_ADEN               0x400           /* enable */
 236 #define SBAM_ADNEG              0x800           /* negative decode */
 237 #define SBAM_BASE0_MASK         0xffffff00      /* type0 base address */
 238 #define SBAM_BASE0_SHIFT        8
 239 #define SBAM_BASE1_MASK         0xfffff000      /* type1 base address for the core */
 240 #define SBAM_BASE1_SHIFT        12
 241 #define SBAM_BASE2_MASK         0xffff0000      /* type2 base address for the core */
 242 #define SBAM_BASE2_SHIFT        16
 243
 244 /* sbtmconfiglow */
 245 #define SBTMCL_CD_MASK          0xff            /* clock divide */
 246 #define SBTMCL_CO_MASK          0xf800          /* clock offset */
 247 #define SBTMCL_CO_SHIFT         11
 248 #define SBTMCL_IF_MASK          0xfc0000        /* interrupt flags */
 249 #define SBTMCL_IF_SHIFT         18
 250 #define SBTMCL_IM_MASK          0x3000000       /* interrupt mode */
 251 #define SBTMCL_IM_SHIFT         24
 252
 253 /* sbtmconfighigh */
 254 #define SBTMCH_BM_MASK          0x3             /* busy mode */
 255 #define SBTMCH_RM_MASK          0x3             /* retry mode */
 256 #define SBTMCH_RM_SHIFT         2
 257 #define SBTMCH_SM_MASK          0x30            /* stop mode */
 258 #define SBTMCH_SM_SHIFT         4
 259 #define SBTMCH_EM_MASK          0x300           /* sb error mode */
 260 #define SBTMCH_EM_SHIFT         8
 261 #define SBTMCH_IM_MASK          0xc00           /* int mode */
 262 #define SBTMCH_IM_SHIFT         10
 263
 264 /* sbbconfig */
 265 #define SBBC_LAT_MASK           0x3             /* sb latency */
 266 #define SBBC_MAX0_MASK          0xf0000         /* maxccntr0 */
 267 #define SBBC_MAX0_SHIFT         16
 268 #define SBBC_MAX1_MASK          0xf00000        /* maxccntr1 */
 269 #define SBBC_MAX1_SHIFT         20
 270
 271 /* sbbstate */
 272 #define SBBS_SRD                0x1             /* st reg disable */
 273 #define SBBS_HRD                0x2             /* hold reg disable */
 274
 275 /* sbidlow */
 276 #define SBIDL_CS_MASK           0x3             /* config space */
 277 #define SBIDL_AR_MASK           0x38            /* # address ranges supported */
 278 #define SBIDL_AR_SHIFT          3
 279 #define SBIDL_SYNCH             0x40            /* sync */
 280 #define SBIDL_INIT              0x80            /* initiator */
 281 #define SBIDL_MINLAT_MASK       0xf00           /* minimum backplane latency */
 282 #define SBIDL_MINLAT_SHIFT      8
 283 #define SBIDL_MAXLAT            0xf000          /* maximum backplane latency */
 284 #define SBIDL_MAXLAT_SHIFT      12
 285 #define SBIDL_FIRST             0x10000         /* this initiator is first */
 286 #define SBIDL_CW_MASK           0xc0000         /* cycle counter width */
 287 #define SBIDL_CW_SHIFT          18
 288 #define SBIDL_TP_MASK           0xf00000        /* target ports */
 289 #define SBIDL_TP_SHIFT          20
 290 #define SBIDL_IP_MASK           0xf000000       /* initiator ports */
 291 #define SBIDL_IP_SHIFT          24
 292 #define SBIDL_RV_MASK           0xf0000000      /* sonics backplane revision code */
 293 #define SBIDL_RV_SHIFT          28
 294 #define SBIDL_RV_2_2            0x00000000      /* version 2.2 or earlier */
 295 #define SBIDL_RV_2_3            0x10000000      /* version 2.3 */
 296
 297 /* sbidhigh */
 298 #define SBIDH_RC_MASK           0x000f          /* revision code */
 299 #define SBIDH_RCE_MASK          0x7000          /* revision code extension field */
 300 #define SBIDH_RCE_SHIFT         8
 301 #define SBCOREREV(sbidh) \
 302         ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
 303 #define SBIDH_CC_MASK           0x8ff0          /* core code */
 304 #define SBIDH_CC_SHIFT          4
 305 #define SBIDH_VC_MASK           0xffff0000      /* vendor code */
 306 #define SBIDH_VC_SHIFT          16
 307
 308 #define SB_COMMIT               0xfd8           /* update buffered registers value */
 309
 310 /* vendor codes */
 311 #define SB_VEND_BCM             0x4243          /* Broadcom's SB vendor code */
 312
 313 /* core codes */
 314 #define SB_NODEV                0x700           /* Invalid coreid */
 315 #define SB_CC                   0x800           /* chipcommon core */
 316 #define SB_ILINE20              0x801           /* iline20 core */
 317 #define SB_SDRAM                0x803           /* sdram core */
 318 #define SB_PCI                  0x804           /* pci core */
 319 #define SB_MIPS                 0x805           /* mips core */
 320 #define SB_ENET                 0x806           /* enet mac core */
 321 #define SB_CODEC                0x807           /* v90 codec core */
 322 #define SB_USB                  0x808           /* usb 1.1 host/device core */
 323 #define SB_ADSL                 0x809           /* ADSL core */
 324 #define SB_ILINE100             0x80a           /* iline100 core */
 325 #define SB_IPSEC                0x80b           /* ipsec core */
 326 #define SB_PCMCIA               0x80d           /* pcmcia core */
 327 #define SB_SOCRAM               0x80e           /* internal memory core */
 328 #define SB_MEMC                 0x80f           /* memc sdram core */
 329 #define SB_EXTIF                0x811           /* external interface core */
 330 #define SB_D11                  0x812           /* 802.11 MAC core */
 331 #define SB_MIPS33               0x816           /* mips3302 core */
 332 #define SB_USB11H               0x817           /* usb 1.1 host core */
 333 #define SB_USB11D               0x818           /* usb 1.1 device core */
 334 #define SB_USB20H               0x819           /* usb 2.0 host core */
 335 #define SB_USB20D               0x81a           /* usb 2.0 device core */
 336 #define SB_SDIOH                0x81b           /* sdio host core */
 337 #define SB_ROBO                 0x81c           /* roboswitch core */
 338 #define SB_ATA100               0x81d           /* parallel ATA core */
 339 #define SB_SATAXOR              0x81e           /* serial ATA & XOR DMA core */
 340 #define SB_GIGETH               0x81f           /* gigabit ethernet core */
 341 #define SB_PCIE                 0x820           /* pci express core */
 342 #define SB_MIMO                 0x821           /* MIMO phy core */
 343 #define SB_SRAMC                0x822           /* SRAM controller core */
 344 #define SB_MINIMAC              0x823           /* MINI MAC/phy core */
 345 #define SB_ARM7S                0x825           /* ARM7tdmi-s core */
 346 #define SB_SDIOD                0x829           /* SDIO device core */
 347 #define SB_ARMCM3               0x82a           /* ARM Cortex M3 core */
 348 #define SB_OCP                  0x830           /* OCP2OCP bridge core */
 349 #define SB_SC                   0x831           /* shared common core */
 350 #define SB_AHB                  0x832           /* OCP2AHB bridge core */
 351
 352 #define SB_CC_IDX               0               /* chipc, when present, is always core 0 */
 353
 354 /* Not an enumeration space register, but common to all cores to
 355  * communicate w/PMU regarding Silicon Backplane clocking.
 356  */
 357 #define SB_CLK_CTL_ST           0x1e0           /* clock control and status */
 358
 359 /* clk_ctl_st register */
 360 #define CCS_FORCEALP            0x00000001      /* force ALP request */
 361 #define CCS_FORCEHT             0x00000002      /* force HT request */
 362 #define CCS_FORCEILP            0x00000004      /* force ILP request */
 363 #define CCS_ALPAREQ             0x00000008      /* ALP Avail Request */
 364 #define CCS_HTAREQ              0x00000010      /* HT Avail Request */
 365 #define CCS_FORCEHWREQOFF       0x00000020      /* Force HW Clock Request Off */
 366 #define CCS_ALPAVAIL            0x00010000      /* ALP is available */
 367 #define CCS_HTAVAIL             0x00020000      /* HT is available */
 368 #define CCS0_HTAVAIL            0x00010000      /* HT avail in chipc and pcmcia on 4328a0 */
 369 #define CCS0_ALPAVAIL           0x00020000      /* ALP avail in chipc and pcmcia on 4328a0 */
 370
 371 /* Not really related to Silicon Backplane, but a couple of software
 372  * conventions for the use the flash space:
 373  */
 374
 375 /* Minumum amount of flash we support */
 376 #define FLASH_MIN               0x00020000      /* Minimum flash size */
 377
 378 /* A boot/binary may have an embedded block that describes its size  */
 379 #define BISZ_OFFSET             0x3e0           /* At this offset into the binary */
 380 #define BISZ_MAGIC              0x4249535a      /* Marked with this value: 'BISZ' */
 381 #define BISZ_MAGIC_IDX          0               /* Word 0: magic */
 382 #define BISZ_TXTST_IDX          1               /*      1: text start */
 383 #define BISZ_TXTEND_IDX         2               /*      2: text end */
 384 #define BISZ_DATAST_IDX         3               /*      3: data start */
 385 #define BISZ_DATAEND_IDX        4               /*      4: data end */
 386 #define BISZ_BSSST_IDX          5               /*      5: bss start */
 387 #define BISZ_BSSEND_IDX         6               /*      6: bss end */
 388 #define BISZ_SIZE               7               /* descriptor size in 32-bit intergers */
 389
 390 #endif  /* _SBCONFIG_H */