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ar71xx: ag71xx: remove MII interface setup code
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
347 {
348 u32 t;
349
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
357 }
358
359 static void ag71xx_dma_reset(struct ag71xx *ag)
360 {
361 u32 val;
362 int i;
363
364 ag71xx_dump_dma_regs(ag);
365
366 /* stop RX and TX */
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
369
370 /*
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
373 */
374 mdelay(1);
375
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
379
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
384 }
385
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 if (val)
392 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
393 ag->dev->name, val);
394
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396
397 /* mask out reserved bits */
398 val &= ~0xff000000;
399
400 if (val)
401 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
402 ag->dev->name, val);
403
404 ag71xx_dump_dma_regs(ag);
405 }
406
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
409
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
417 FIFO_CFG4_VT)
418
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
425
426 static void ag71xx_hw_stop(struct ag71xx *ag)
427 {
428 /* disable all interrupts and stop the rx/tx engine */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
430 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
431 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
432 }
433
434 static void ag71xx_hw_setup(struct ag71xx *ag)
435 {
436 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
437
438 /* setup MAC configuration registers */
439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
440
441 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
442 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
443
444 /* setup max frame length */
445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
446
447 /* setup FIFO configuration registers */
448 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
449 if (pdata->is_ar724x) {
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
452 } else {
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
455 }
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
458 }
459
460 static void ag71xx_hw_init(struct ag71xx *ag)
461 {
462 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
463 u32 reset_mask = pdata->reset_bit;
464
465 ag71xx_hw_stop(ag);
466
467 if (pdata->is_ar724x) {
468 u32 reset_phy = reset_mask;
469
470 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
471 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
472
473 ar71xx_device_stop(reset_phy);
474 mdelay(50);
475 ar71xx_device_start(reset_phy);
476 mdelay(200);
477 }
478
479 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
480 udelay(20);
481
482 ar71xx_device_stop(reset_mask);
483 mdelay(100);
484 ar71xx_device_start(reset_mask);
485 mdelay(200);
486
487 ag71xx_hw_setup(ag);
488
489 ag71xx_dma_reset(ag);
490 }
491
492 static void ag71xx_fast_reset(struct ag71xx *ag)
493 {
494 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
495 struct net_device *dev = ag->dev;
496 u32 reset_mask = pdata->reset_bit;
497 u32 rx_ds, tx_ds;
498 u32 mii_reg;
499
500 reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
501
502 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
503 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
504 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
505
506 ar71xx_device_stop(reset_mask);
507 udelay(10);
508 ar71xx_device_start(reset_mask);
509 udelay(10);
510
511 ag71xx_dma_reset(ag);
512 ag71xx_hw_setup(ag);
513
514 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
515 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
516 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
517
518 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
519 }
520
521 static void ag71xx_hw_start(struct ag71xx *ag)
522 {
523 /* start RX engine */
524 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
525
526 /* enable interrupts */
527 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
528 }
529
530 void ag71xx_link_adjust(struct ag71xx *ag)
531 {
532 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
533 u32 cfg2;
534 u32 ifctl;
535 u32 fifo5;
536 u32 mii_speed;
537
538 if (!ag->link) {
539 ag71xx_hw_stop(ag);
540 netif_carrier_off(ag->dev);
541 if (netif_msg_link(ag))
542 printk(KERN_INFO "%s: link down\n", ag->dev->name);
543 return;
544 }
545
546 if (pdata->is_ar724x)
547 ag71xx_fast_reset(ag);
548
549 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
550 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
551 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
552
553 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
554 ifctl &= ~(MAC_IFCTL_SPEED);
555
556 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
557 fifo5 &= ~FIFO_CFG5_BM;
558
559 switch (ag->speed) {
560 case SPEED_1000:
561 mii_speed = MII_CTRL_SPEED_1000;
562 cfg2 |= MAC_CFG2_IF_1000;
563 fifo5 |= FIFO_CFG5_BM;
564 break;
565 case SPEED_100:
566 mii_speed = MII_CTRL_SPEED_100;
567 cfg2 |= MAC_CFG2_IF_10_100;
568 ifctl |= MAC_IFCTL_SPEED;
569 break;
570 case SPEED_10:
571 mii_speed = MII_CTRL_SPEED_10;
572 cfg2 |= MAC_CFG2_IF_10_100;
573 break;
574 default:
575 BUG();
576 return;
577 }
578
579 if (pdata->is_ar91xx)
580 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
581 else if (pdata->is_ar724x)
582 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
583 else
584 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
585
586 if (pdata->set_pll)
587 pdata->set_pll(ag->speed);
588
589 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
590
591 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
592 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
593 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
594 ag71xx_hw_start(ag);
595
596 netif_carrier_on(ag->dev);
597 if (netif_msg_link(ag))
598 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
599 ag->dev->name,
600 ag71xx_speed_str(ag),
601 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
602
603 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
604 ag->dev->name,
605 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
606 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
607 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
608
609 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
610 ag->dev->name,
611 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
612 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
613 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
614
615 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
616 ag->dev->name,
617 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
618 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
619 ag71xx_mii_ctrl_rr(ag));
620 }
621
622 static int ag71xx_open(struct net_device *dev)
623 {
624 struct ag71xx *ag = netdev_priv(dev);
625 int ret;
626
627 ret = ag71xx_rings_init(ag);
628 if (ret)
629 goto err;
630
631 napi_enable(&ag->napi);
632
633 netif_carrier_off(dev);
634 ag71xx_phy_start(ag);
635
636 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
637 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
638
639 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
640
641 netif_start_queue(dev);
642
643 return 0;
644
645 err:
646 ag71xx_rings_cleanup(ag);
647 return ret;
648 }
649
650 static int ag71xx_stop(struct net_device *dev)
651 {
652 struct ag71xx *ag = netdev_priv(dev);
653 unsigned long flags;
654
655 netif_carrier_off(dev);
656 ag71xx_phy_stop(ag);
657
658 spin_lock_irqsave(&ag->lock, flags);
659
660 netif_stop_queue(dev);
661
662 ag71xx_hw_stop(ag);
663 ag71xx_dma_reset(ag);
664
665 napi_disable(&ag->napi);
666 del_timer_sync(&ag->oom_timer);
667
668 spin_unlock_irqrestore(&ag->lock, flags);
669
670 ag71xx_rings_cleanup(ag);
671
672 return 0;
673 }
674
675 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
676 struct net_device *dev)
677 {
678 struct ag71xx *ag = netdev_priv(dev);
679 struct ag71xx_ring *ring = &ag->tx_ring;
680 struct ag71xx_desc *desc;
681 dma_addr_t dma_addr;
682 int i;
683
684 i = ring->curr % ring->size;
685 desc = ring->buf[i].desc;
686
687 if (!ag71xx_desc_empty(desc))
688 goto err_drop;
689
690 if (ag71xx_has_ar8216(ag))
691 ag71xx_add_ar8216_header(ag, skb);
692
693 if (skb->len <= 0) {
694 DBG("%s: packet len is too small\n", ag->dev->name);
695 goto err_drop;
696 }
697
698 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
699 DMA_TO_DEVICE);
700
701 ring->buf[i].skb = skb;
702 ring->buf[i].timestamp = jiffies;
703
704 /* setup descriptor fields */
705 desc->data = (u32) dma_addr;
706 desc->ctrl = (skb->len & DESC_PKTLEN_M);
707
708 /* flush descriptor */
709 wmb();
710
711 ring->curr++;
712 if (ring->curr == (ring->dirty + ring->size)) {
713 DBG("%s: tx queue full\n", ag->dev->name);
714 netif_stop_queue(dev);
715 }
716
717 DBG("%s: packet injected into TX queue\n", ag->dev->name);
718
719 /* enable TX engine */
720 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
721
722 return NETDEV_TX_OK;
723
724 err_drop:
725 dev->stats.tx_dropped++;
726
727 dev_kfree_skb(skb);
728 return NETDEV_TX_OK;
729 }
730
731 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
732 {
733 struct ag71xx *ag = netdev_priv(dev);
734 int ret;
735
736 switch (cmd) {
737 case SIOCETHTOOL:
738 if (ag->phy_dev == NULL)
739 break;
740
741 spin_lock_irq(&ag->lock);
742 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
743 spin_unlock_irq(&ag->lock);
744 return ret;
745
746 case SIOCSIFHWADDR:
747 if (copy_from_user
748 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
749 return -EFAULT;
750 return 0;
751
752 case SIOCGIFHWADDR:
753 if (copy_to_user
754 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
755 return -EFAULT;
756 return 0;
757
758 case SIOCGMIIPHY:
759 case SIOCGMIIREG:
760 case SIOCSMIIREG:
761 if (ag->phy_dev == NULL)
762 break;
763
764 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
765
766 default:
767 break;
768 }
769
770 return -EOPNOTSUPP;
771 }
772
773 static void ag71xx_oom_timer_handler(unsigned long data)
774 {
775 struct net_device *dev = (struct net_device *) data;
776 struct ag71xx *ag = netdev_priv(dev);
777
778 napi_schedule(&ag->napi);
779 }
780
781 static void ag71xx_tx_timeout(struct net_device *dev)
782 {
783 struct ag71xx *ag = netdev_priv(dev);
784
785 if (netif_msg_tx_err(ag))
786 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
787
788 schedule_work(&ag->restart_work);
789 }
790
791 static void ag71xx_restart_work_func(struct work_struct *work)
792 {
793 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
794
795 if (ag71xx_get_pdata(ag)->is_ar724x) {
796 ag->link = 0;
797 ag71xx_link_adjust(ag);
798 return;
799 }
800
801 ag71xx_stop(ag->dev);
802 ag71xx_open(ag->dev);
803 }
804
805 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
806 {
807 u32 rx_sm, tx_sm, rx_fd;
808
809 if (likely(time_before(jiffies, timestamp + HZ/10)))
810 return false;
811
812 if (!netif_carrier_ok(ag->dev))
813 return false;
814
815 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
816 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
817 return true;
818
819 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
820 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
821 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
822 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
823 return true;
824
825 return false;
826 }
827
828 static int ag71xx_tx_packets(struct ag71xx *ag)
829 {
830 struct ag71xx_ring *ring = &ag->tx_ring;
831 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
832 int sent;
833
834 DBG("%s: processing TX ring\n", ag->dev->name);
835
836 sent = 0;
837 while (ring->dirty != ring->curr) {
838 unsigned int i = ring->dirty % ring->size;
839 struct ag71xx_desc *desc = ring->buf[i].desc;
840 struct sk_buff *skb = ring->buf[i].skb;
841
842 if (!ag71xx_desc_empty(desc)) {
843 if (pdata->is_ar7240 &&
844 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
845 schedule_work(&ag->restart_work);
846 break;
847 }
848
849 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
850
851 ag->dev->stats.tx_bytes += skb->len;
852 ag->dev->stats.tx_packets++;
853
854 dev_kfree_skb_any(skb);
855 ring->buf[i].skb = NULL;
856
857 ring->dirty++;
858 sent++;
859 }
860
861 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
862
863 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
864 netif_wake_queue(ag->dev);
865
866 return sent;
867 }
868
869 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
870 {
871 struct net_device *dev = ag->dev;
872 struct ag71xx_ring *ring = &ag->rx_ring;
873 int done = 0;
874
875 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
876 dev->name, limit, ring->curr, ring->dirty);
877
878 while (done < limit) {
879 unsigned int i = ring->curr % ring->size;
880 struct ag71xx_desc *desc = ring->buf[i].desc;
881 struct sk_buff *skb;
882 int pktlen;
883 int err = 0;
884
885 if (ag71xx_desc_empty(desc))
886 break;
887
888 if ((ring->dirty + ring->size) == ring->curr) {
889 ag71xx_assert(0);
890 break;
891 }
892
893 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
894
895 skb = ring->buf[i].skb;
896 pktlen = ag71xx_desc_pktlen(desc);
897 pktlen -= ETH_FCS_LEN;
898
899 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
900 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
901
902 dev->last_rx = jiffies;
903 dev->stats.rx_packets++;
904 dev->stats.rx_bytes += pktlen;
905
906 skb_put(skb, pktlen);
907 if (ag71xx_has_ar8216(ag))
908 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
909
910 if (err) {
911 dev->stats.rx_dropped++;
912 kfree_skb(skb);
913 } else {
914 skb->dev = dev;
915 skb->ip_summed = CHECKSUM_NONE;
916 if (ag->phy_dev) {
917 ag->phy_dev->netif_receive_skb(skb);
918 } else {
919 skb->protocol = eth_type_trans(skb, dev);
920 netif_receive_skb(skb);
921 }
922 }
923
924 ring->buf[i].skb = NULL;
925 done++;
926
927 ring->curr++;
928 }
929
930 ag71xx_ring_rx_refill(ag);
931
932 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
933 dev->name, ring->curr, ring->dirty, done);
934
935 return done;
936 }
937
938 static int ag71xx_poll(struct napi_struct *napi, int limit)
939 {
940 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
941 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
942 struct net_device *dev = ag->dev;
943 struct ag71xx_ring *rx_ring;
944 unsigned long flags;
945 u32 status;
946 int tx_done;
947 int rx_done;
948
949 pdata->ddr_flush();
950 tx_done = ag71xx_tx_packets(ag);
951
952 DBG("%s: processing RX ring\n", dev->name);
953 rx_done = ag71xx_rx_packets(ag, limit);
954
955 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
956
957 rx_ring = &ag->rx_ring;
958 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
959 goto oom;
960
961 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
962 if (unlikely(status & RX_STATUS_OF)) {
963 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
964 dev->stats.rx_fifo_errors++;
965
966 /* restart RX */
967 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
968 }
969
970 if (rx_done < limit) {
971 if (status & RX_STATUS_PR)
972 goto more;
973
974 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
975 if (status & TX_STATUS_PS)
976 goto more;
977
978 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
979 dev->name, rx_done, tx_done, limit);
980
981 napi_complete(napi);
982
983 /* enable interrupts */
984 spin_lock_irqsave(&ag->lock, flags);
985 ag71xx_int_enable(ag, AG71XX_INT_POLL);
986 spin_unlock_irqrestore(&ag->lock, flags);
987 return rx_done;
988 }
989
990 more:
991 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
992 dev->name, rx_done, tx_done, limit);
993 return rx_done;
994
995 oom:
996 if (netif_msg_rx_err(ag))
997 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
998
999 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1000 napi_complete(napi);
1001 return 0;
1002 }
1003
1004 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1005 {
1006 struct net_device *dev = dev_id;
1007 struct ag71xx *ag = netdev_priv(dev);
1008 u32 status;
1009
1010 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1011 ag71xx_dump_intr(ag, "raw", status);
1012
1013 if (unlikely(!status))
1014 return IRQ_NONE;
1015
1016 if (unlikely(status & AG71XX_INT_ERR)) {
1017 if (status & AG71XX_INT_TX_BE) {
1018 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1019 dev_err(&dev->dev, "TX BUS error\n");
1020 }
1021 if (status & AG71XX_INT_RX_BE) {
1022 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1023 dev_err(&dev->dev, "RX BUS error\n");
1024 }
1025 }
1026
1027 if (likely(status & AG71XX_INT_POLL)) {
1028 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1029 DBG("%s: enable polling mode\n", dev->name);
1030 napi_schedule(&ag->napi);
1031 }
1032
1033 ag71xx_debugfs_update_int_stats(ag, status);
1034
1035 return IRQ_HANDLED;
1036 }
1037
1038 static void ag71xx_set_multicast_list(struct net_device *dev)
1039 {
1040 /* TODO */
1041 }
1042
1043 #ifdef CONFIG_NET_POLL_CONTROLLER
1044 /*
1045 * Polling 'interrupt' - used by things like netconsole to send skbs
1046 * without having to re-enable interrupts. It's not called while
1047 * the interrupt routine is executing.
1048 */
1049 static void ag71xx_netpoll(struct net_device *dev)
1050 {
1051 disable_irq(dev->irq);
1052 ag71xx_interrupt(dev->irq, dev);
1053 enable_irq(dev->irq);
1054 }
1055 #endif
1056
1057 static const struct net_device_ops ag71xx_netdev_ops = {
1058 .ndo_open = ag71xx_open,
1059 .ndo_stop = ag71xx_stop,
1060 .ndo_start_xmit = ag71xx_hard_start_xmit,
1061 .ndo_set_multicast_list = ag71xx_set_multicast_list,
1062 .ndo_do_ioctl = ag71xx_do_ioctl,
1063 .ndo_tx_timeout = ag71xx_tx_timeout,
1064 .ndo_change_mtu = eth_change_mtu,
1065 .ndo_set_mac_address = eth_mac_addr,
1066 .ndo_validate_addr = eth_validate_addr,
1067 #ifdef CONFIG_NET_POLL_CONTROLLER
1068 .ndo_poll_controller = ag71xx_netpoll,
1069 #endif
1070 };
1071
1072 static int __devinit ag71xx_probe(struct platform_device *pdev)
1073 {
1074 struct net_device *dev;
1075 struct resource *res;
1076 struct ag71xx *ag;
1077 struct ag71xx_platform_data *pdata;
1078 int err;
1079
1080 pdata = pdev->dev.platform_data;
1081 if (!pdata) {
1082 dev_err(&pdev->dev, "no platform data specified\n");
1083 err = -ENXIO;
1084 goto err_out;
1085 }
1086
1087 if (pdata->mii_bus_dev == NULL) {
1088 dev_err(&pdev->dev, "no MII bus device specified\n");
1089 err = -EINVAL;
1090 goto err_out;
1091 }
1092
1093 dev = alloc_etherdev(sizeof(*ag));
1094 if (!dev) {
1095 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1096 err = -ENOMEM;
1097 goto err_out;
1098 }
1099
1100 SET_NETDEV_DEV(dev, &pdev->dev);
1101
1102 ag = netdev_priv(dev);
1103 ag->pdev = pdev;
1104 ag->dev = dev;
1105 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1106 AG71XX_DEFAULT_MSG_ENABLE);
1107 spin_lock_init(&ag->lock);
1108
1109 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1110 if (!res) {
1111 dev_err(&pdev->dev, "no mac_base resource found\n");
1112 err = -ENXIO;
1113 goto err_out;
1114 }
1115
1116 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1117 if (!ag->mac_base) {
1118 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1119 err = -ENOMEM;
1120 goto err_free_dev;
1121 }
1122
1123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1124 if (!res) {
1125 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1126 err = -ENXIO;
1127 goto err_unmap_base;
1128 }
1129
1130 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1131 if (!ag->mii_ctrl) {
1132 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1133 err = -ENOMEM;
1134 goto err_unmap_base;
1135 }
1136
1137 dev->irq = platform_get_irq(pdev, 0);
1138 err = request_irq(dev->irq, ag71xx_interrupt,
1139 IRQF_DISABLED,
1140 dev->name, dev);
1141 if (err) {
1142 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1143 goto err_unmap_mii_ctrl;
1144 }
1145
1146 dev->base_addr = (unsigned long)ag->mac_base;
1147 dev->netdev_ops = &ag71xx_netdev_ops;
1148 dev->ethtool_ops = &ag71xx_ethtool_ops;
1149
1150 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1151
1152 init_timer(&ag->oom_timer);
1153 ag->oom_timer.data = (unsigned long) dev;
1154 ag->oom_timer.function = ag71xx_oom_timer_handler;
1155
1156 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1157 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1158
1159 ag->stop_desc = dma_alloc_coherent(NULL,
1160 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1161
1162 if (!ag->stop_desc)
1163 goto err_free_irq;
1164
1165 ag->stop_desc->data = 0;
1166 ag->stop_desc->ctrl = 0;
1167 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1168
1169 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1170
1171 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1172
1173 err = register_netdev(dev);
1174 if (err) {
1175 dev_err(&pdev->dev, "unable to register net device\n");
1176 goto err_free_desc;
1177 }
1178
1179 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1180 dev->name, dev->base_addr, dev->irq);
1181
1182 ag71xx_dump_regs(ag);
1183
1184 ag71xx_hw_init(ag);
1185
1186 ag71xx_dump_regs(ag);
1187
1188 err = ag71xx_phy_connect(ag);
1189 if (err)
1190 goto err_unregister_netdev;
1191
1192 err = ag71xx_debugfs_init(ag);
1193 if (err)
1194 goto err_phy_disconnect;
1195
1196 platform_set_drvdata(pdev, dev);
1197
1198 return 0;
1199
1200 err_phy_disconnect:
1201 ag71xx_phy_disconnect(ag);
1202 err_unregister_netdev:
1203 unregister_netdev(dev);
1204 err_free_desc:
1205 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1206 ag->stop_desc_dma);
1207 err_free_irq:
1208 free_irq(dev->irq, dev);
1209 err_unmap_mii_ctrl:
1210 iounmap(ag->mii_ctrl);
1211 err_unmap_base:
1212 iounmap(ag->mac_base);
1213 err_free_dev:
1214 kfree(dev);
1215 err_out:
1216 platform_set_drvdata(pdev, NULL);
1217 return err;
1218 }
1219
1220 static int __devexit ag71xx_remove(struct platform_device *pdev)
1221 {
1222 struct net_device *dev = platform_get_drvdata(pdev);
1223
1224 if (dev) {
1225 struct ag71xx *ag = netdev_priv(dev);
1226
1227 ag71xx_debugfs_exit(ag);
1228 ag71xx_phy_disconnect(ag);
1229 unregister_netdev(dev);
1230 free_irq(dev->irq, dev);
1231 iounmap(ag->mii_ctrl);
1232 iounmap(ag->mac_base);
1233 kfree(dev);
1234 platform_set_drvdata(pdev, NULL);
1235 }
1236
1237 return 0;
1238 }
1239
1240 static struct platform_driver ag71xx_driver = {
1241 .probe = ag71xx_probe,
1242 .remove = __exit_p(ag71xx_remove),
1243 .driver = {
1244 .name = AG71XX_DRV_NAME,
1245 }
1246 };
1247
1248 static int __init ag71xx_module_init(void)
1249 {
1250 int ret;
1251
1252 ret = ag71xx_debugfs_root_init();
1253 if (ret)
1254 goto err_out;
1255
1256 ret = ag71xx_mdio_driver_init();
1257 if (ret)
1258 goto err_debugfs_exit;
1259
1260 ret = platform_driver_register(&ag71xx_driver);
1261 if (ret)
1262 goto err_mdio_exit;
1263
1264 return 0;
1265
1266 err_mdio_exit:
1267 ag71xx_mdio_driver_exit();
1268 err_debugfs_exit:
1269 ag71xx_debugfs_root_exit();
1270 err_out:
1271 return ret;
1272 }
1273
1274 static void __exit ag71xx_module_exit(void)
1275 {
1276 platform_driver_unregister(&ag71xx_driver);
1277 ag71xx_mdio_driver_exit();
1278 ag71xx_debugfs_root_exit();
1279 }
1280
1281 module_init(ag71xx_module_init);
1282 module_exit(ag71xx_module_exit);
1283
1284 MODULE_VERSION(AG71XX_DRV_VERSION);
1285 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1286 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1287 MODULE_LICENSE("GPL v2");
1288 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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