target/linux/pxa/patches-2.6.21/009-bkpxa-pxa-cpu.patch

   1 Status: WORKS
   2 PXA CPU enhancements
   3
   4 from patch 1667:
   5 - 64K PTEs
   6 from hh.org-cvs:
   7 - support in pxa_gpio_mode for active low
   8
   9 #
  10 # Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
  11 #
  12
  13 --- a/arch/arm/mm/proc-xscale.S
  14 +++ b/arch/arm/mm/proc-xscale.S
  15 @@ -474,11 +474,62 @@ ENTRY(cpu_xscale_set_pte_ext)
  16         movne   r2, #0                          @ no -> fault
  17
  18         str     r2, [r0]                        @ hardware version
  19 +
  20 +       @ We try to map 64K page entries when possible.
  21 +       @ We do that for kernel space only since the usage pattern from
  22 +       @ the setting of VM area is quite simple.  User space is not worth
  23 +       @ the implied complexity because of ever randomly changing PTEs
  24 +       @ (page aging, swapout, etc) requiring constant coherency checks.
  25 +       @ Since PTEs are usually set in increasing order, we test the
  26 +       @ possibility for a large page only when given the last PTE of a
  27 +       @ 64K boundary.
  28 +       tsteq   r1, #L_PTE_USER
  29 +       andeq   r1, r0, #(15 << 2)
  30 +       teqeq   r1, #(15 << 2)
  31 +       beq     1f
  32 +
  33         mov     ip, #0
  34         mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
  35         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
  36         mov     pc, lr
  37
  38 +       @ See if we have 16 identical PTEs but with consecutive base addresses
  39 +1:     bic     r3, r2, #0x0000f000
  40 +       mov     r1, #0x0000f000
  41 +2:     eor     r2, r2, r3
  42 +       teq     r2, r1
  43 +       bne     4f
  44 +       subs    r1, r1, #0x00001000
  45 +       ldr     r2, [r0, #-4]!
  46 +       bne     2b
  47 +       eors    r2, r2, r3
  48 +       bne     4f
  49 +
  50 +       @ Now create our LARGE PTE from the current EXT one.
  51 +       bic     r3, r3, #PTE_TYPE_MASK
  52 +       orr     r3, r3, #PTE_TYPE_LARGE
  53 +       and     r2, r3, #0x30                   @ EXT_AP --> LARGE_AP0
  54 +       orr     r2, r2, r2, lsl #2              @ add LARGE_AP1
  55 +       orr     r2, r2, r2, lsl #4              @ add LARGE_AP3 + LARGE_AP2
  56 +       and     r1, r3, #0x3c0                  @ EXT_TEX
  57 +       bic     r3, r3, #0x3c0
  58 +       orr     r2, r2, r1, lsl #(12 - 6)       @ --> LARGE_TEX
  59 +       orr     r2, r2, r3                      @ add remaining bits
  60 +
  61 +       @ then put it in the pagetable
  62 +       mov     r3, r2
  63 +3:     strd    r2, [r0], #8
  64 +       tst     r0, #(15 << 2)
  65 +       bne     3b
  66 +
  67 +       @ Then sync the 2 corresponding cache lines
  68 +       sub     r0, r0, #(16 << 2)
  69 +       mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
  70 +4:     orr     r0, r0, #(15 << 2)
  71 +       mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
  72 +       mov     ip, #0
  73 +       mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
  74 +       mov     pc, lr
  75
  76         .ltorg
  77
  78 --- a/include/asm-arm/arch-pxa/pxa-regs.h
  79 +++ b/include/asm-arm/arch-pxa/pxa-regs.h
  80 @@ -1345,6 +1345,7 @@
  81  #define GPIO_ALT_FN_2_OUT      0x280
  82  #define GPIO_ALT_FN_3_IN       0x300
  83  #define GPIO_ALT_FN_3_OUT      0x380
  84 +#define GPIO_ACTIVE_LOW         0x1000
  85  #define GPIO_MD_MASK_NR                0x07f
  86  #define GPIO_MD_MASK_DIR       0x080
  87  #define GPIO_MD_MASK_FN                0x300
  88 @@ -1597,6 +1598,25 @@
  89  #define PWER_GPIO15    PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
  90  #define PWER_RTC       0x80000000      /* RTC alarm wake-up enable        */
  91
  92 +#define PWER_GPIO(Nb)  (1 << Nb)       /* GPIO [0..15] wake-up enable     */
  93 +#define PWER_GPIO0     PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
  94 +#define PWER_GPIO1     PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
  95 +#define PWER_GPIO2     PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
  96 +#define PWER_GPIO3     PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
  97 +#define PWER_GPIO4     PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
  98 +#define PWER_GPIO5     PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
  99 +#define PWER_GPIO6     PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
 100 +#define PWER_GPIO7     PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
 101 +#define PWER_GPIO8     PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
 102 +#define PWER_GPIO9     PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
 103 +#define PWER_GPIO10    PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
 104 +#define PWER_GPIO11    PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
 105 +#define PWER_GPIO12    PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
 106 +#define PWER_GPIO13    PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
 107 +#define PWER_GPIO14    PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
 108 +#define PWER_GPIO15    PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
 109 +#define PWER_RTC       0x80000000      /* RTC alarm wake-up enable        */
 110 +
 111
 112  /*
 113   * SSP Serial Port Registers