target/linux/adm5120/files/drivers/usb/host/adm5120.h

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 /*
  11  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  12  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  13  * host controller implementation.
  14  */
  15 typedef __u32 __bitwise __hc32;
  16 typedef __u16 __bitwise __hc16;
  17
  18 /*
  19  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  20  * See OHCI spec, section 4.2
  21  *
  22  * This is a "Queue Head" for those transfers, which is why
  23  * both EHCI and UHCI call similar structures a "QH".
  24  */
  25
  26 #define TD_DATALEN_MAX  4096
  27
  28 #define ED_ALIGN        16
  29 #define ED_MASK ((u32)~(ED_ALIGN-1))    /* strip hw status in low addr bits */
  30
  31 struct ed {
  32         /* first fields are hardware-specified */
  33         __hc32                  hwINFO;      /* endpoint config bitmap */
  34         /* info bits defined by hcd */
  35 #define ED_DEQUEUE      (1 << 27)
  36         /* info bits defined by the hardware */
  37 #define ED_MPS_SHIFT    16
  38 #define ED_MPS_MASK     ((1 << 11)-1)
  39 #define ED_MPS_GET(x)   (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
  40 #define ED_ISO          (1 << 15)               /* isochronous endpoint */
  41 #define ED_SKIP         (1 << 14)
  42 #define ED_SPEED_FULL   (1 << 13)               /* fullspeed device */
  43 #define ED_INT          (1 << 11)               /* interrupt endpoint */
  44 #define ED_EN_SHIFT     7                       /* endpoint shift */
  45 #define ED_EN_MASK      ((1 << 4)-1)            /* endpoint mask */
  46 #define ED_EN_GET(x)    (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
  47 #define ED_FA_MASK      ((1 << 7)-1)            /* function address mask */
  48 #define ED_FA_GET(x)    ((x) & ED_FA_MASK)
  49         __hc32                  hwTailP;        /* tail of TD list */
  50         __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  51 #define ED_C            (0x02)                  /* toggle carry */
  52 #define ED_H            (0x01)                  /* halted */
  53         __hc32                  hwNextED;       /* next ED in list */
  54
  55         /* rest are purely for the driver's use */
  56         dma_addr_t              dma;            /* addr of ED */
  57         struct td               *dummy;         /* next TD to activate */
  58
  59         struct urb_priv         *urb_active;    /* active URB */
  60         struct list_head        urb_pending;    /* pending URBs */
  61
  62         struct list_head        ed_list;        /* list of all EDs*/
  63         struct list_head        rm_list;        /* for remove list */
  64
  65         /* host's view of schedule */
  66         struct ed               *ed_next;       /* on schedule list */
  67         struct ed               *ed_prev;       /* for non-interrupt EDs */
  68         struct ed               *ed_rm_next;    /* on rm list */
  69
  70         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  71          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  72          */
  73         u8                      state;
  74 #define ED_NEW          0x00            /* just allocated */
  75 #define ED_IDLE         0x01            /* linked into HC, but not running */
  76 #define ED_OPER         0x02            /* linked into HC and running */
  77 #define ED_UNLINK       0x03            /* being unlinked from HC */
  78
  79         u8                      type;           /* PIPE_{BULK,...} */
  80
  81         /* periodic scheduling params (for intr and iso) */
  82         u8                      branch;
  83         u16                     interval;
  84         u16                     load;
  85         u16                     last_iso;       /* iso only */
  86
  87         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  88         u16                     tick;
  89 } __attribute__ ((aligned(ED_ALIGN)));
  90
  91 /*
  92  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  93  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  94  * and 4.3.2 (iso)
  95  */
  96
  97 #define TD_ALIGN        32
  98 #define TD_MASK ((u32)~(TD_ALIGN-1))    /* strip hw status in low addr bits */
  99
 100 struct td {
 101         /* first fields are hardware-specified */
 102         __hc32          hwINFO;         /* transfer info bitmask */
 103
 104         /* hwINFO bits */
 105 #define TD_OWN          (1 << 31)               /* owner of the descriptor */
 106 #define TD_CC_SHIFT     27                      /* condition code */
 107 #define TD_CC_MASK      0xf
 108 #define TD_CC           (TD_CC_MASK << TD_CC_SHIFT)
 109 #define TD_CC_GET(x)    (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
 110
 111 #define TD_EC_SHIFT     25                      /* error count */
 112 #define TD_EC_MASK      0x3
 113 #define TD_EC           (TD_EC_MASK << TD_EC_SHIFT)
 114 #define TD_EC_GET(x)    ((x >> TD_EC_SHIFT) & TD_EC_MASK)
 115 #define TD_T_SHIFT      23                      /* data toggle state */
 116 #define TD_T_MASK       0x3
 117 #define TD_T            (TD_T_MASK << TD_T_SHIFT)
 118 #define TD_T_DATA0      (0x2 << TD_T_SHIFT)     /* DATA0 */
 119 #define TD_T_DATA1      (0x3 << TD_T_SHIFT)     /* DATA1 */
 120 #define TD_T_CARRY      (0x0 << TD_T_SHIFT)     /* uses ED_C */
 121 #define TD_T_GET(x)     (((x) >> TD_T_SHIFT) & TD_T_MASK)
 122 #define TD_DP_SHIFT     21                      /* direction/pid */
 123 #define TD_DP_MASK      0x3
 124 #define TD_DP           (TD_DP_MASK << TD_DP_SHIFT)
 125 #define TD_DP_SETUP     (0x0 << TD_DP_SHIFT)    /* SETUP pid */
 126 #define TD_DP_OUT       (0x1 << TD_DP_SHIFT)    /* OUT pid */
 127 #define TD_DP_IN        (0x2 << TD_DP_SHIFT)    /* IN pid */
 128 #define TD_DP_GET(x)    (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
 129 #define TD_ISI_SHIFT    8                       /* Interrupt Service Interval */
 130 #define TD_ISI_MASK     0x3f
 131 #define TD_ISI_GET(x)   (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
 132 #define TD_FN_MASK      0x3f                    /* frame number */
 133 #define TD_FN_GET(x)    ((x) & TD_FN_MASK)
 134
 135         __hc32          hwDBP;          /* Data Buffer Pointer (or 0) */
 136         __hc32          hwCBL;          /* Controller/Buffer Length */
 137
 138         /* hwCBL bits */
 139 #define TD_BL_MASK      0xffff          /* buffer length */
 140 #define TD_BL_GET(x)    ((x) & TD_BL_MASK)
 141 #define TD_IE           (1 << 16)       /* interrupt enable */
 142         __hc32          hwNextTD;       /* Next TD Pointer */
 143
 144         /* rest are purely for the driver's use */
 145         __u8            index;
 146 /*      struct ed       *ed;*/
 147         struct urb      *urb;
 148
 149         dma_addr_t      td_dma;         /* addr of this TD */
 150         dma_addr_t      data_dma;       /* addr of data it points to */
 151
 152 } __attribute__ ((aligned(TD_ALIGN)));  /* c/b/i need 16; only iso needs 32 */
 153
 154 /*
 155  * Hardware transfer status codes -- CC from td->hwINFO
 156  */
 157 #define TD_CC_NOERROR           0x00
 158 #define TD_CC_CRC               0x01
 159 #define TD_CC_BITSTUFFING       0x02
 160 #define TD_CC_DATATOGGLEM       0x03
 161 #define TD_CC_STALL             0x04
 162 #define TD_CC_DEVNOTRESP        0x05
 163 #define TD_CC_PIDCHECKFAIL      0x06
 164 #define TD_CC_UNEXPECTEDPID     0x07
 165 #define TD_CC_DATAOVERRUN       0x08
 166 #define TD_CC_DATAUNDERRUN      0x09
 167     /* 0x0A, 0x0B reserved for hardware */
 168 #define TD_CC_BUFFEROVERRUN     0x0C
 169 #define TD_CC_BUFFERUNDERRUN    0x0D
 170     /* 0x0E, 0x0F reserved for HCD */
 171 #define TD_CC_HCD0              0x0E
 172 #define TD_CC_NOTACCESSED       0x0F
 173
 174 /*
 175  * preshifted status codes
 176  */
 177 #define TD_SCC_NOTACCESSED      (TD_CC_NOTACCESSED << TD_CC_SHIFT)
 178
 179
 180 /* map OHCI TD status codes (CC) to errno values */
 181 static const int cc_to_error [16] = {
 182         /* No  Error  */        0,
 183         /* CRC Error  */        -EILSEQ,
 184         /* Bit Stuff  */        -EPROTO,
 185         /* Data Togg  */        -EILSEQ,
 186         /* Stall      */        -EPIPE,
 187         /* DevNotResp */        -ETIME,
 188         /* PIDCheck   */        -EPROTO,
 189         /* UnExpPID   */        -EPROTO,
 190         /* DataOver   */        -EOVERFLOW,
 191         /* DataUnder  */        -EREMOTEIO,
 192         /* (for hw)   */        -EIO,
 193         /* (for hw)   */        -EIO,
 194         /* BufferOver */        -ECOMM,
 195         /* BuffUnder  */        -ENOSR,
 196         /* (for HCD)  */        -EALREADY,
 197         /* (for HCD)  */        -EALREADY
 198 };
 199
 200 #define NUM_INTS        32
 201
 202 /*
 203  * This is the structure of the OHCI controller's memory mapped I/O region.
 204  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 205  * Layout is in section 7 (and appendix B) of the spec.
 206  */
 207 struct admhcd_regs {
 208         __hc32  gencontrol;     /* General Control */
 209         __hc32  int_status;     /* Interrupt Status */
 210         __hc32  int_enable;     /* Interrupt Enable */
 211         __hc32  reserved00;
 212         __hc32  host_control;   /* Host General Control */
 213         __hc32  reserved01;
 214         __hc32  fminterval;     /* Frame Interval */
 215         __hc32  fmnumber;       /* Frame Number */
 216         __hc32  reserved02;
 217         __hc32  reserved03;
 218         __hc32  reserved04;
 219         __hc32  reserved05;
 220         __hc32  reserved06;
 221         __hc32  reserved07;
 222         __hc32  reserved08;
 223         __hc32  reserved09;
 224         __hc32  reserved10;
 225         __hc32  reserved11;
 226         __hc32  reserved12;
 227         __hc32  reserved13;
 228         __hc32  reserved14;
 229         __hc32  reserved15;
 230         __hc32  reserved16;
 231         __hc32  reserved17;
 232         __hc32  reserved18;
 233         __hc32  reserved19;
 234         __hc32  reserved20;
 235         __hc32  reserved21;
 236         __hc32  lsthresh;       /* Low Speed Threshold */
 237         __hc32  rhdesc;         /* Root Hub Descriptor */
 238 #define MAX_ROOT_PORTS  2
 239         __hc32  portstatus[MAX_ROOT_PORTS]; /* Port Status */
 240         __hc32  hosthead;       /* Host Descriptor Head */
 241 } __attribute__ ((aligned(32)));
 242
 243 /*
 244  * General Control register bits
 245  */
 246 #define ADMHC_CTRL_UHFE (1 << 0)        /* USB Host Function Enable */
 247 #define ADMHC_CTRL_SIR  (1 << 1)        /* Software Interrupt request */
 248 #define ADMHC_CTRL_DMAA (1 << 2)        /* DMA Arbitration Control */
 249 #define ADMHC_CTRL_SR   (1 << 3)        /* Software Reset */
 250
 251 /*
 252  * Host General Control register bits
 253  */
 254 #define ADMHC_HC_BUSS           0x3             /* USB bus state */
 255 #define   ADMHC_BUSS_RESET      0x0
 256 #define   ADMHC_BUSS_RESUME     0x1
 257 #define   ADMHC_BUSS_OPER       0x2
 258 #define   ADMHC_BUSS_SUSPEND    0x3
 259 #define ADMHC_HC_DMAE           (1 << 2)        /* DMA enable */
 260
 261 /*
 262  * Interrupt Status/Enable register bits
 263  */
 264 #define ADMHC_INTR_SOFI (1 << 4)        /* start of frame */
 265 #define ADMHC_INTR_RESI (1 << 5)        /* resume detected */
 266 #define ADMHC_INTR_BABI (1 << 8)        /* babble detected */
 267 #define ADMHC_INTR_INSM (1 << 9)        /* root hub status change */
 268 #define ADMHC_INTR_SO   (1 << 10)       /* scheduling overrun */
 269 #define ADMHC_INTR_FNO  (1 << 11)       /* frame number overflow */
 270 #define ADMHC_INTR_TDC  (1 << 20)       /* transfer descriptor completed */
 271 #define ADMHC_INTR_SWI  (1 << 29)       /* software interrupt */
 272 #define ADMHC_INTR_FATI (1 << 30)       /* fatal error */
 273 #define ADMHC_INTR_INTA (1 << 31)       /* interrupt active */
 274
 275 #define ADMHC_INTR_MIE  (1 << 31)       /* master interrupt enable */
 276
 277 /*
 278  * SOF Frame Interval register bits
 279  */
 280 #define ADMHC_SFI_FI_MASK       ((1 << 14)-1)   /* Frame Interval value */
 281 #define ADMHC_SFI_FSLDP_SHIFT   16
 282 #define ADMHC_SFI_FSLDP_MASK    ((1 << 15)-1)
 283 #define ADMHC_SFI_FIT           (1 << 31)       /* Frame Interval Toggle */
 284
 285 /*
 286  * SOF Frame Number register bits
 287  */
 288 #define ADMHC_SFN_FN_MASK       ((1 << 16)-1)   /* Frame Number Mask */
 289 #define ADMHC_SFN_FR_SHIFT      16              /* Frame Remaining Shift */
 290 #define ADMHC_SFN_FR_MASK       ((1 << 14)-1)   /* Frame Remaining Mask */
 291 #define ADMHC_SFN_FRT           (1 << 31)       /* Frame Remaining Toggle */
 292
 293 /*
 294  * Root Hub Descriptor register bits
 295  */
 296 #define ADMHC_RH_NUMP   0xff            /* number of ports */
 297 #define ADMHC_RH_PSM    (1 << 8)        /* power switching mode */
 298 #define ADMHC_RH_NPS    (1 << 9)        /* no power switching */
 299 #define ADMHC_RH_OCPM   (1 << 10)       /* over current protection mode */
 300 #define ADMHC_RH_NOCP   (1 << 11)       /* no over current protection */
 301 #define ADMHC_RH_PPCM   (0xff << 16)    /* port power control */
 302
 303 #define ADMHC_RH_LPS    (1 << 24)       /* local power switch */
 304 #define ADMHC_RH_OCI    (1 << 25)       /* over current indicator */
 305
 306 /* status change bits */
 307 #define ADMHC_RH_LPSC   (1 << 26)       /* local power switch change */
 308 #define ADMHC_RH_OCIC   (1 << 27)       /* over current indicator change */
 309
 310 #define ADMHC_RH_DRWE   (1 << 28)       /* device remote wakeup enable */
 311 #define ADMHC_RH_CRWE   (1 << 29)       /* clear remote wakeup enable */
 312
 313 #define ADMHC_RH_CGP    (1 << 24)       /* clear global power */
 314 #define ADMHC_RH_SGP    (1 << 26)       /* set global power */
 315
 316 /*
 317  * Port Status register bits
 318  */
 319 #define ADMHC_PS_CCS    (1 << 0)        /* current connect status */
 320 #define ADMHC_PS_PES    (1 << 1)        /* port enable status */
 321 #define ADMHC_PS_PSS    (1 << 2)        /* port suspend status */
 322 #define ADMHC_PS_POCI   (1 << 3)        /* port over current indicator */
 323 #define ADMHC_PS_PRS    (1 << 4)        /* port reset status */
 324 #define ADMHC_PS_PPS    (1 << 8)        /* port power status */
 325 #define ADMHC_PS_LSDA   (1 << 9)        /* low speed device attached */
 326
 327 /* status change bits */
 328 #define ADMHC_PS_CSC    (1 << 16)       /* connect status change */
 329 #define ADMHC_PS_PESC   (1 << 17)       /* port enable status change */
 330 #define ADMHC_PS_PSSC   (1 << 18)       /* port suspend status change */
 331 #define ADMHC_PS_OCIC   (1 << 19)       /* over current indicator change */
 332 #define ADMHC_PS_PRSC   (1 << 20)       /* port reset status change */
 333
 334 /* port feature bits */
 335 #define ADMHC_PS_CPE    (1 << 0)        /* clear port enable */
 336 #define ADMHC_PS_SPE    (1 << 1)        /* set port enable */
 337 #define ADMHC_PS_SPS    (1 << 2)        /* set port suspend */
 338 #define ADMHC_PS_CPS    (1 << 3)        /* clear suspend status */
 339 #define ADMHC_PS_SPR    (1 << 4)        /* set port reset */
 340 #define ADMHC_PS_SPP    (1 << 8)        /* set port power */
 341 #define ADMHC_PS_CPP    (1 << 9)        /* clear port power */
 342
 343 /*
 344  * the POTPGT value is not defined in the ADMHC, so define a dummy value
 345  */
 346 #define ADMHC_POTPGT    2               /* in ms */
 347
 348 /* hcd-private per-urb state */
 349 struct urb_priv {
 350         struct ed               *ed;
 351         struct urb              *urb;
 352         struct list_head        pending;        /* URBs on the same ED */
 353
 354         u32                     td_cnt;         /* # tds in this request */
 355         u32                     td_idx;         /* index of the current td */
 356         struct td               *td[0];         /* all TDs in this request */
 357 };
 358
 359 #define TD_HASH_SIZE    64    /* power'o'two */
 360 /* sizeof (struct td) ~= 64 == 2^6 ... */
 361 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 362
 363 /*
 364  * This is the full ADMHCD controller description
 365  *
 366  * Note how the "proper" USB information is just
 367  * a subset of what the full implementation needs. (Linus)
 368  */
 369
 370 struct admhcd {
 371         spinlock_t              lock;
 372         spinlock_t              dma_lock;
 373         u32                     dma_state;
 374
 375         /*
 376          * I/O memory used to communicate with the HC (dma-consistent)
 377          */
 378         struct admhcd_regs __iomem *regs;
 379
 380         /*
 381          * hcd adds to schedule for a live hc any time, but removals finish
 382          * only at the start of the next frame.
 383          */
 384         struct ed               *ed_head;
 385         struct ed               *ed_tails[4];
 386
 387         struct ed               *ed_rm_list;    /* to be removed */
 388         struct ed               *periodic[NUM_INTS];    /* shadow int_table */
 389
 390 #if 0   /* TODO: remove? */
 391         /*
 392          * OTG controllers and transceivers need software interaction;
 393          * other external transceivers should be software-transparent
 394          */
 395         struct otg_transceiver  *transceiver;
 396 #endif
 397
 398         /*
 399          * memory management for queue data structures
 400          */
 401         struct dma_pool         *td_cache;
 402         struct dma_pool         *ed_cache;
 403         struct td               *td_hash[TD_HASH_SIZE];
 404
 405         /*
 406          * driver state
 407          */
 408         int                     num_ports;
 409         int                     load[NUM_INTS];
 410         u32                     host_control;   /* copy of the host_control reg */
 411         unsigned long           next_statechange;       /* suspend/resume */
 412         u32                     fminterval;             /* saved register */
 413         unsigned                autostop:1;     /* rh auto stopping/stopped */
 414
 415         unsigned long           flags;          /* for HC bugs */
 416 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 417 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 418 #define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 419 #define OHCI_QUIRK_BE_DESC      0x08                    /* BE descriptors */
 420 #define OHCI_QUIRK_BE_MMIO      0x10                    /* BE registers */
 421 #define OHCI_QUIRK_ZFMICRO      0x20                    /* Compaq ZFMicro chipset*/
 422         // there are also chip quirks/bugs in init logic
 423 };
 424
 425 /* convert between an hcd pointer and the corresponding ahcd_hcd */
 426 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
 427 {
 428         return (struct admhcd *)(hcd->hcd_priv);
 429 }
 430 static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
 431 {
 432         return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
 433 }
 434
 435 /*-------------------------------------------------------------------------*/
 436
 437 #ifndef DEBUG
 438 #define STUB_DEBUG_FILES
 439 #endif  /* DEBUG */
 440
 441 #if 0
 442 #define admhc_dbg(ahcd, fmt, args...) \
 443         dev_dbg(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
 444 #define admhc_err(ahcd, fmt, args...) \
 445         dev_err(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
 446 #define ahcd_info(ahcd, fmt, args...) \
 447         dev_info(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
 448 #define admhc_warn(ahcd, fmt, args...) \
 449         dev_warn(admhcd_to_hcd(ahcd)->self.controller , fmt , ## args )
 450
 451 #ifdef ADMHC_VERBOSE_DEBUG
 452 #       define admhc_vdbg admhc_dbg
 453 #else
 454 #       define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
 455 #endif
 456 #else
 457 #define admhc_dbg(ahcd, fmt, args...) \
 458         printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
 459 #define admhc_err(ahcd, fmt, args...) \
 460         printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
 461 #define ahcd_info(ahcd, fmt, args...) \
 462         printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
 463 #define admhc_warn(ahcd, fmt, args...) \
 464         printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
 465
 466 #ifdef ADMHC_VERBOSE_DEBUG
 467 #       define admhc_vdbg admhc_dbg
 468 #else
 469 #       define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
 470 #endif
 471 #endif
 472
 473 /*-------------------------------------------------------------------------*/
 474
 475 /*
 476  * While most USB host controllers implement their registers and
 477  * in-memory communication descriptors in little-endian format,
 478  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 479  * processors) implement them in big endian format.
 480  *
 481  * In addition some more exotic implementations like the Toshiba
 482  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
 483  * they have a different endianness for registers vs. in-memory
 484  * descriptors.
 485  *
 486  * This attempts to support either format at compile time without a
 487  * runtime penalty, or both formats with the additional overhead
 488  * of checking a flag bit.
 489  *
 490  * That leads to some tricky Kconfig rules howevber. There are
 491  * different defaults based on some arch/ppc platforms, though
 492  * the basic rules are:
 493  *
 494  * Controller type              Kconfig options needed
 495  * ---------------              ----------------------
 496  * little endian                CONFIG_USB_ADMHC_LITTLE_ENDIAN
 497  *
 498  * fully big endian             CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
 499  *                              CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 500  *
 501  * mixed endian                 CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
 502  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
 503  *
 504  * (If you have a mixed endian controller, you -must- also define
 505  * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
 506  * both your mixed endian and a fully big endian controller support in
 507  * the same kernel image).
 508  */
 509
 510 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
 511 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 512 #define big_endian_desc(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_DESC)
 513 #else
 514 #define big_endian_desc(ahcd)   1               /* only big endian */
 515 #endif
 516 #else
 517 #define big_endian_desc(ahcd)   0               /* only little endian */
 518 #endif
 519
 520 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 521 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 522 #define big_endian_mmio(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_MMIO)
 523 #else
 524 #define big_endian_mmio(ahcd)   1               /* only big endian */
 525 #endif
 526 #else
 527 #define big_endian_mmio(ahcd)   0               /* only little endian */
 528 #endif
 529
 530 /*
 531  * Big-endian read/write functions are arch-specific.
 532  * Other arches can be added if/when they're needed.
 533  *
 534  * REVISIT: arch/powerpc now has readl/writel_be, so the
 535  * definition below can die once the STB04xxx support is
 536  * finally ported over.
 537  */
 538 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
 539 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 540 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 541 #endif
 542
 543 static inline unsigned int admhc_readl(const struct admhcd *ahcd,
 544         __hc32 __iomem *regs)
 545 {
 546 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 547         return big_endian_mmio(ahcd) ?
 548                 readl_be(regs) :
 549                 readl(regs);
 550 #else
 551         return readl(regs);
 552 #endif
 553 }
 554
 555 static inline void admhc_writel(const struct admhcd *ahcd,
 556         const unsigned int val, __hc32 __iomem *regs)
 557 {
 558 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 559         big_endian_mmio(ahcd) ?
 560                 writel_be(val, regs) :
 561                 writel(val, regs);
 562 #else
 563                 writel(val, regs);
 564 #endif
 565 }
 566
 567 static inline void admhc_writel_flush(const struct admhcd *ahcd)
 568 {
 569 #if 0   /* TODO: needed? */
 570         (void) admhc_readl(ahcd, &ahcd->regs->control);
 571 #endif
 572 }
 573
 574
 575 /*-------------------------------------------------------------------------*/
 576
 577 /* cpu to ahcd */
 578 static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
 579 {
 580         return big_endian_desc(ahcd) ?
 581                 (__force __hc16)cpu_to_be16(x) :
 582                 (__force __hc16)cpu_to_le16(x);
 583 }
 584
 585 static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
 586 {
 587         return big_endian_desc(ahcd) ?
 588                 cpu_to_be16p(x) :
 589                 cpu_to_le16p(x);
 590 }
 591
 592 static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
 593 {
 594         return big_endian_desc(ahcd) ?
 595                 (__force __hc32)cpu_to_be32(x) :
 596                 (__force __hc32)cpu_to_le32(x);
 597 }
 598
 599 static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
 600 {
 601         return big_endian_desc(ahcd) ?
 602                 cpu_to_be32p(x) :
 603                 cpu_to_le32p(x);
 604 }
 605
 606 /* ahcd to cpu */
 607 static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
 608 {
 609         return big_endian_desc(ahcd) ?
 610                 be16_to_cpu((__force __be16)x) :
 611                 le16_to_cpu((__force __le16)x);
 612 }
 613
 614 static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
 615 {
 616         return big_endian_desc(ahcd) ?
 617                 be16_to_cpup((__force __be16 *)x) :
 618                 le16_to_cpup((__force __le16 *)x);
 619 }
 620
 621 static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
 622 {
 623         return big_endian_desc(ahcd) ?
 624                 be32_to_cpu((__force __be32)x) :
 625                 le32_to_cpu((__force __le32)x);
 626 }
 627
 628 static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
 629 {
 630         return big_endian_desc(ahcd) ?
 631                 be32_to_cpup((__force __be32 *)x) :
 632                 le32_to_cpup((__force __le32 *)x);
 633 }
 634
 635 /*-------------------------------------------------------------------------*/
 636
 637 static inline u16 admhc_frame_no(const struct admhcd *ahcd)
 638 {
 639         u32     t;
 640
 641         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
 642         return (u16)t;
 643 }
 644
 645 static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
 646 {
 647         u32     t;
 648
 649         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
 650         t &= ADMHC_SFN_FR_MASK;
 651         return (u16)t;
 652 }
 653
 654 /*-------------------------------------------------------------------------*/
 655
 656 static inline void admhc_disable(struct admhcd *ahcd)
 657 {
 658         admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
 659 }
 660
 661 #define FI                      0x2edf          /* 12000 bits per frame (-1) */
 662 #define FSLDP(fi)               (0x7fff & ((6 * ((fi) - 210)) / 7))
 663 #define FIT                     ADMHC_SFI_FIT
 664 #define LSTHRESH                0x628           /* lowspeed bit threshold */
 665
 666 static inline void periodic_reinit(struct admhcd *ahcd)
 667 {
 668         u32     fi = ahcd->fminterval & ADMHC_SFI_FI_MASK;
 669         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 670
 671         /* TODO: adjust FSLargestDataPacket value too? */
 672         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 673                                         &ahcd->regs->fminterval);
 674 }
 675
 676 static inline u32 admhc_get_rhdesc(struct admhcd *ahcd)
 677 {
 678         return admhc_readl(ahcd, &ahcd->regs->rhdesc);
 679 }
 680
 681 static inline u32 admhc_get_portstatus(struct admhcd *ahcd, int port)
 682 {
 683         return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
 684 }
 685
 686 static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
 687 {
 688         /* FIXME: read-only bits must be masked out */
 689         admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
 690 }
 691
 692 static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
 693 {
 694         u32     t;
 695
 696         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 697         t &= ~(ints);
 698         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 699         /* TODO: flush writes ?*/
 700 }
 701
 702 static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
 703 {
 704         u32     t;
 705
 706         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 707         t |= ints;
 708         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 709         /* TODO: flush writes ?*/
 710 }
 711
 712 static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
 713 {
 714         admhc_writel(ahcd, ints, &ahcd->regs->int_status);
 715 }
 716
 717 static inline void admhc_dma_enable(struct admhcd *ahcd)
 718 {
 719         u32 t;
 720
 721         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 722         if (t & ADMHC_HC_DMAE)
 723                 return;
 724
 725         t |= ADMHC_HC_DMAE;
 726         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 727         admhc_dbg(ahcd,"DMA enabled\n");
 728 }
 729
 730 static inline void admhc_dma_disable(struct admhcd *ahcd)
 731 {
 732         u32 t;
 733
 734         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 735         if (!(t & ADMHC_HC_DMAE))
 736                 return;
 737
 738         t &= ~ADMHC_HC_DMAE;
 739         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 740         admhc_dbg(ahcd,"DMA disabled\n");
 741 }
 742
 743 static inline void admhc_dma_lock(struct admhcd *ahcd)
 744 {
 745         spin_lock(ahcd->dma_lock);
 746
 747         ahcd->dma_state = admhc_readl(ahcd, &ahcd->regs->host_control);
 748         admhc_writel(ahcd, 0, &ahcd->regs->hosthead);
 749         admhc_writel(ahcd, ahcd->dma_state & ~ADMHC_HC_DMAE,
 750                                 &ahcd->regs->host_control);
 751         admhc_dbg(ahcd,"DMA locked\n");
 752 }
 753
 754 static inline void admhc_dma_unlock(struct admhcd *ahcd)
 755 {
 756         admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
 757         admhc_writel(ahcd, ahcd->dma_state, &ahcd->regs->host_control);
 758         admhc_dbg(ahcd,"DMA unlocked\n");
 759         spin_unlock(ahcd->dma_lock);
 760 }