target/linux/lantiq/patches/100-board.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -139,6 +139,9 @@
   4
   5           otherwise choose R3000.
   6
   7 +config LANTIQ
   8 +       bool "Lantiq MIPS"
   9 +
  10  config MACH_JAZZ
  11         bool "Jazz family of machines"
  12         select ARC
  13 @@ -695,6 +698,7 @@
  14  source "arch/mips/vr41xx/Kconfig"
  15  source "arch/mips/cavium-octeon/Kconfig"
  16  source "arch/mips/loongson/Kconfig"
  17 +source "arch/mips/lantiq/Kconfig"
  18
  19  endmenu
  20
  21 --- a/arch/mips/Makefile
  22 +++ b/arch/mips/Makefile
  23 @@ -339,6 +339,17 @@
  24  load-$(CONFIG_MIPS_COBALT)     += 0xffffffff80080000
  25
  26  #
  27 +# Lantiq
  28 +#
  29 +load-$(CONFIG_LANTIQ) += 0xffffffff80002000
  30 +core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
  31 +cflags-$(CONFIG_LANTIQ)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq
  32 +core-$(CONFIG_SOC_LANTIQ_FALCON) += arch/mips/lantiq/falcon/
  33 +cflags-$(CONFIG_SOC_LANTIQ_FALCON)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
  34 +core-$(CONFIG_SOC_LANTIQ_XWAY) += arch/mips/lantiq/xway/
  35 +cflags-$(CONFIG_SOC_LANTIQ_XWAY)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
  36 +
  37 +#
  38  # DECstation family
  39  #
  40  core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
  41 --- /dev/null
  42 +++ b/arch/mips/lantiq/Kconfig
  43 @@ -0,0 +1,36 @@
  44 +if LANTIQ
  45 +
  46 +config SOC_LANTIQ
  47 +       bool
  48 +       select DMA_NONCOHERENT
  49 +       select IRQ_CPU
  50 +       select CEVT_R4K
  51 +       select CSRC_R4K
  52 +       select SYS_HAS_CPU_MIPS32_R1
  53 +       select SYS_HAS_CPU_MIPS32_R2
  54 +       select SYS_SUPPORTS_BIG_ENDIAN
  55 +       select SYS_SUPPORTS_32BIT_KERNEL
  56 +       select SYS_SUPPORTS_MULTITHREADING
  57 +       select SYS_HAS_EARLY_PRINTK
  58 +       select HW_HAS_PCI
  59 +       select ARCH_REQUIRE_GPIOLIB
  60 +       select SWAP_IO_SPACE
  61 +       select MIPS_MACHINE
  62 +
  63 +choice
  64 +       prompt "SoC Type"
  65 +       default SOC_LANTIQ_XWAY
  66 +
  67 +#config SOC_LANTIQ_FALCON
  68 +#      bool "FALCON"
  69 +#      select SOC_LANTIQ
  70 +
  71 +config SOC_LANTIQ_XWAY
  72 +       bool "XWAY"
  73 +       select SOC_LANTIQ
  74 +endchoice
  75 +
  76 +#source "arch/mips/lantiq/falcon/Kconfig"
  77 +source "arch/mips/lantiq/xway/Kconfig"
  78 +
  79 +endif
  80 --- /dev/null
  81 +++ b/arch/mips/lantiq/Makefile
  82 @@ -0,0 +1,2 @@
  83 +obj-y := irq.o setup.o clk.o prom.o
  84 +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  85 --- /dev/null
  86 +++ b/arch/mips/lantiq/irq.c
  87 @@ -0,0 +1,218 @@
  88 +/*
  89 + *  This program is free software; you can redistribute it and/or modify it
  90 + *  under the terms of the GNU General Public License version 2 as published
  91 + *  by the Free Software Foundation.
  92 + *
  93 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  94 + */
  95 +
  96 +#include <linux/module.h>
  97 +#include <linux/interrupt.h>
  98 +
  99 +#include <asm/bootinfo.h>
 100 +#include <asm/irq_cpu.h>
 101 +
 102 +#include <lantiq.h>
 103 +#include <irq.h>
 104 +
 105 +#define LQ_ICU_BASE_ADDR       (KSEG1 | 0x1F880200)
 106 +
 107 +#define LQ_ICU_IM0_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
 108 +#define LQ_ICU_IM0_IER         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
 109 +#define LQ_ICU_IM0_IOSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
 110 +#define LQ_ICU_IM0_IRSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
 111 +#define LQ_ICU_IM0_IMR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
 112 +
 113 +#define LQ_ICU_IM1_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
 114 +#define LQ_ICU_IM2_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
 115 +#define LQ_ICU_IM3_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
 116 +#define LQ_ICU_IM4_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
 117 +
 118 +#define LQ_ICU_OFFSET          (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
 119 +
 120 +#define LQ_EBU_BASE_ADDR       0xBE105300
 121 +#define LQ_EBU_PCC_ISTAT       ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
 122 +
 123 +void
 124 +lq_disable_irq(unsigned int irq_nr)
 125 +{
 126 +       u32 *ier = LQ_ICU_IM0_IER;
 127 +       irq_nr -= INT_NUM_IRQ0;
 128 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 129 +       irq_nr %= INT_NUM_IM_OFFSET;
 130 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 131 +}
 132 +EXPORT_SYMBOL(lq_disable_irq);
 133 +
 134 +void
 135 +lq_mask_and_ack_irq(unsigned int irq_nr)
 136 +{
 137 +       u32 *ier = LQ_ICU_IM0_IER;
 138 +       u32 *isr = LQ_ICU_IM0_ISR;
 139 +       irq_nr -= INT_NUM_IRQ0;
 140 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 141 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 142 +       irq_nr %= INT_NUM_IM_OFFSET;
 143 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 144 +       lq_w32((1 << irq_nr), isr);
 145 +}
 146 +EXPORT_SYMBOL(lq_mask_and_ack_irq);
 147 +
 148 +static void
 149 +lq_ack_irq(unsigned int irq_nr)
 150 +{
 151 +       u32 *isr = LQ_ICU_IM0_ISR;
 152 +       irq_nr -= INT_NUM_IRQ0;
 153 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 154 +       irq_nr %= INT_NUM_IM_OFFSET;
 155 +       lq_w32((1 << irq_nr), isr);
 156 +}
 157 +
 158 +void
 159 +lq_enable_irq(unsigned int irq_nr)
 160 +{
 161 +       u32 *ier = LQ_ICU_IM0_IER;
 162 +       irq_nr -= INT_NUM_IRQ0;
 163 +       ier += LQ_ICU_OFFSET  * (irq_nr / INT_NUM_IM_OFFSET);
 164 +       irq_nr %= INT_NUM_IM_OFFSET;
 165 +       lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
 166 +}
 167 +EXPORT_SYMBOL(lq_enable_irq);
 168 +
 169 +static unsigned int
 170 +lq_startup_irq(unsigned int irq)
 171 +{
 172 +       lq_enable_irq(irq);
 173 +       return 0;
 174 +}
 175 +
 176 +static void
 177 +lq_end_irq(unsigned int irq)
 178 +{
 179 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 180 +               lq_enable_irq(irq);
 181 +}
 182 +
 183 +static struct irq_chip
 184 +lq_irq_type = {
 185 +       "lq_irq",
 186 +       .startup = lq_startup_irq,
 187 +       .enable = lq_enable_irq,
 188 +       .disable = lq_disable_irq,
 189 +       .unmask = lq_enable_irq,
 190 +       .ack = lq_ack_irq,
 191 +       .mask = lq_disable_irq,
 192 +       .mask_ack = lq_mask_and_ack_irq,
 193 +       .end = lq_end_irq,
 194 +};
 195 +
 196 +static void
 197 +lq_hw_irqdispatch(int module)
 198 +{
 199 +       u32 irq;
 200 +
 201 +       irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
 202 +       if (irq == 0)
 203 +               return;
 204 +
 205 +       /* silicon bug causes only the msb set to 1 to be valid. all
 206 +          other bits might be bogus */
 207 +       irq = __fls(irq);
 208 +       do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 209 +       if ((irq == 22) && (module == 0))
 210 +               lq_w32(lq_r32(LQ_EBU_PCC_ISTAT) | 0x10,
 211 +                       LQ_EBU_PCC_ISTAT);
 212 +}
 213 +
 214 +#define DEFINE_HWx_IRQDISPATCH(x) \
 215 +static void lq_hw ## x ## _irqdispatch(void)\
 216 +{\
 217 +       lq_hw_irqdispatch(x); \
 218 +}
 219 +static void lq_hw5_irqdispatch(void)
 220 +{
 221 +       do_IRQ(MIPS_CPU_TIMER_IRQ);
 222 +}
 223 +DEFINE_HWx_IRQDISPATCH(0)
 224 +DEFINE_HWx_IRQDISPATCH(1)
 225 +DEFINE_HWx_IRQDISPATCH(2)
 226 +DEFINE_HWx_IRQDISPATCH(3)
 227 +DEFINE_HWx_IRQDISPATCH(4)
 228 +/*DEFINE_HWx_IRQDISPATCH(5)*/
 229 +
 230 +asmlinkage void
 231 +plat_irq_dispatch(void)
 232 +{
 233 +       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 234 +       unsigned int i;
 235 +
 236 +       if (pending & CAUSEF_IP7)
 237 +       {
 238 +               do_IRQ(MIPS_CPU_TIMER_IRQ);
 239 +               goto out;
 240 +       } else {
 241 +               for (i = 0; i < 5; i++)
 242 +               {
 243 +                       if (pending & (CAUSEF_IP2 << i))
 244 +                       {
 245 +                               lq_hw_irqdispatch(i);
 246 +                               goto out;
 247 +                       }
 248 +               }
 249 +       }
 250 +       printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 251 +
 252 +out:
 253 +       return;
 254 +}
 255 +
 256 +static struct irqaction
 257 +cascade = {
 258 +       .handler = no_action,
 259 +       .flags = IRQF_DISABLED,
 260 +       .name = "cascade",
 261 +};
 262 +
 263 +void __init
 264 +arch_init_irq(void)
 265 +{
 266 +       int i;
 267 +
 268 +       for (i = 0; i < 5; i++)
 269 +               lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
 270 +
 271 +       mips_cpu_irq_init();
 272 +
 273 +       for (i = 2; i <= 6; i++)
 274 +               setup_irq(i, &cascade);
 275 +
 276 +       if (cpu_has_vint) {
 277 +               printk(KERN_INFO "Setting up vectored interrupts\n");
 278 +               set_vi_handler(2, lq_hw0_irqdispatch);
 279 +               set_vi_handler(3, lq_hw1_irqdispatch);
 280 +               set_vi_handler(4, lq_hw2_irqdispatch);
 281 +               set_vi_handler(5, lq_hw3_irqdispatch);
 282 +               set_vi_handler(6, lq_hw4_irqdispatch);
 283 +               set_vi_handler(7, lq_hw5_irqdispatch);
 284 +       }
 285 +
 286 +       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 287 +               set_irq_chip_and_handler(i, &lq_irq_type,
 288 +                       handle_level_irq);
 289 +
 290 +       #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 291 +       set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 292 +               IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 293 +       #else
 294 +       set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 295 +               IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 296 +       #endif
 297 +}
 298 +
 299 +void __cpuinit
 300 +arch_fixup_c0_irqs(void)
 301 +{
 302 +       /* FIXME: check for CPUID and only do fix for specific chips/versions */
 303 +       cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 304 +       cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 305 +}
 306 --- /dev/null
 307 +++ b/arch/mips/lantiq/setup.c
 308 @@ -0,0 +1,47 @@
 309 +/*
 310 + *  This program is free software; you can redistribute it and/or modify it
 311 + *  under the terms of the GNU General Public License version 2 as published
 312 + *  by the Free Software Foundation.
 313 + *
 314 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 315 + */
 316 +
 317 +#include <linux/kernel.h>
 318 +#include <linux/module.h>
 319 +#include <linux/io.h>
 320 +#include <linux/ioport.h>
 321 +
 322 +#include <lantiq.h>
 323 +#include <lantiq_regs.h>
 324 +
 325 +void __init
 326 +plat_mem_setup(void)
 327 +{
 328 +       /* assume 16M as default */
 329 +       int memsize = 16;
 330 +       char **envp = (char **) KSEG1ADDR(fw_arg2);
 331 +       u32 status;
 332 +
 333 +       /* make sure to have no "reverse endian" for user mode! */
 334 +       status = read_c0_status();
 335 +       status &= (~(1<<25));
 336 +       write_c0_status(status);
 337 +
 338 +       ioport_resource.start = IOPORT_RESOURCE_START;
 339 +       ioport_resource.end = IOPORT_RESOURCE_END;
 340 +       iomem_resource.start = IOMEM_RESOURCE_START;
 341 +       iomem_resource.end = IOMEM_RESOURCE_END;
 342 +
 343 +       while (*envp)
 344 +       {
 345 +               char *e = (char *)KSEG1ADDR(*envp);
 346 +               if (!strncmp(e, "memsize=", 8))
 347 +               {
 348 +                       e += 8;
 349 +                       memsize = simple_strtoul(e, NULL, 10);
 350 +               }
 351 +               envp++;
 352 +       }
 353 +       memsize *= 1024 * 1024;
 354 +       add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
 355 +}
 356 --- /dev/null
 357 +++ b/arch/mips/lantiq/clk.c
 358 @@ -0,0 +1,141 @@
 359 +/*
 360 + *  This program is free software; you can redistribute it and/or modify it
 361 + *  under the terms of the GNU General Public License version 2 as published
 362 + *  by the Free Software Foundation.
 363 + *
 364 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 365 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 366 + */
 367 +
 368 +#include <linux/io.h>
 369 +#include <linux/module.h>
 370 +#include <linux/init.h>
 371 +#include <linux/kernel.h>
 372 +#include <linux/types.h>
 373 +#include <linux/clk.h>
 374 +#include <linux/err.h>
 375 +#include <linux/list.h>
 376 +
 377 +#include <asm/time.h>
 378 +#include <asm/irq.h>
 379 +#include <asm/div64.h>
 380 +
 381 +#include <lantiq.h>
 382 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 383 +#include <xway.h>
 384 +#endif
 385 +
 386 +extern unsigned long lq_get_cpu_hz(void);
 387 +extern unsigned long lq_get_fpi_hz(void);
 388 +extern unsigned long lq_get_io_region_clock(void);
 389 +
 390 +struct clk {
 391 +       const char *name;
 392 +       unsigned long rate;
 393 +       unsigned long (*get_rate) (void);
 394 +};
 395 +
 396 +static struct clk *cpu_clk = 0;
 397 +static int cpu_clk_cnt = 0;
 398 +
 399 +static unsigned int r4k_offset;
 400 +static unsigned int r4k_cur;
 401 +
 402 +static struct clk cpu_clk_generic[] = {
 403 +       {
 404 +               .name = "cpu",
 405 +               .get_rate = lq_get_cpu_hz,
 406 +       }, {
 407 +               .name = "fpi",
 408 +               .get_rate = lq_get_fpi_hz,
 409 +       }, {
 410 +               .name = "io",
 411 +               .get_rate = lq_get_io_region_clock,
 412 +       },
 413 +};
 414 +
 415 +void
 416 +clk_init(void)
 417 +{
 418 +       int i;
 419 +       cpu_clk = cpu_clk_generic;
 420 +       cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
 421 +       for(i = 0; i < cpu_clk_cnt; i++)
 422 +               printk("%s: %ld\n", cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
 423 +}
 424 +
 425 +static inline int
 426 +clk_good(struct clk *clk)
 427 +{
 428 +       return clk && !IS_ERR(clk);
 429 +}
 430 +
 431 +unsigned long
 432 +clk_get_rate(struct clk *clk)
 433 +{
 434 +       if (unlikely(!clk_good(clk)))
 435 +               return 0;
 436 +
 437 +       if (clk->rate != 0)
 438 +               return clk->rate;
 439 +
 440 +       if (clk->get_rate != NULL)
 441 +               return clk->get_rate();
 442 +
 443 +       return 0;
 444 +}
 445 +EXPORT_SYMBOL(clk_get_rate);
 446 +
 447 +struct clk*
 448 +clk_get(struct device *dev, const char *id)
 449 +{
 450 +       int i;
 451 +       for(i = 0; i < cpu_clk_cnt; i++)
 452 +               if (!strcmp(id, cpu_clk[i].name))
 453 +                       return &cpu_clk[i];
 454 +       BUG();
 455 +       return ERR_PTR(-ENOENT);
 456 +}
 457 +EXPORT_SYMBOL(clk_get);
 458 +
 459 +void
 460 +clk_put(struct clk *clk)
 461 +{
 462 +       /* not used */
 463 +}
 464 +EXPORT_SYMBOL(clk_put);
 465 +
 466 +static inline u32
 467 +lq_get_counter_resolution(void)
 468 +{
 469 +       u32 res;
 470 +       __asm__ __volatile__(
 471 +               ".set   push\n"
 472 +               ".set   mips32r2\n"
 473 +               ".set   noreorder\n"
 474 +               "rdhwr  %0, $3\n"
 475 +               "ehb\n"
 476 +               ".set pop\n"
 477 +               : "=&r" (res)
 478 +               : /* no input */
 479 +               : "memory");
 480 +       instruction_hazard();
 481 +       return res;
 482 +}
 483 +
 484 +void __init
 485 +plat_time_init(void)
 486 +{
 487 +       struct clk *clk = clk_get(0, "cpu");
 488 +       mips_hpt_frequency = clk_get_rate(clk) / lq_get_counter_resolution();
 489 +       r4k_cur = (read_c0_count() + r4k_offset);
 490 +       write_c0_compare(r4k_cur);
 491 +
 492 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 493 +#define LQ_GPTU_GPT_CLC                        ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
 494 +       lq_pmu_enable(PMU_GPT);
 495 +       lq_pmu_enable(PMU_FPI);
 496 +
 497 +       lq_w32(0x100, LQ_GPTU_GPT_CLC);
 498 +#endif
 499 +}
 500 --- /dev/null
 501 +++ b/arch/mips/lantiq/prom.c
 502 @@ -0,0 +1,118 @@
 503 +/*
 504 + *  This program is free software; you can redistribute it and/or modify it
 505 + *  under the terms of the GNU General Public License version 2 as published
 506 + *  by the Free Software Foundation.
 507 + *
 508 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 509 + */
 510 +
 511 +#include <linux/module.h>
 512 +#include <linux/clk.h>
 513 +#include <asm/bootinfo.h>
 514 +#include <asm/time.h>
 515 +
 516 +#include <lantiq.h>
 517 +
 518 +#include "prom.h"
 519 +
 520 +static struct lq_soc_info soc_info;
 521 +
 522 +/* for Multithreading (APRP) on MIPS34K */
 523 +unsigned long physical_memsize;
 524 +
 525 +/* all access to the ebu must be locked */
 526 +DEFINE_SPINLOCK(ebu_lock);
 527 +EXPORT_SYMBOL_GPL(ebu_lock);
 528 +
 529 +extern void clk_init(void);
 530 +
 531 +unsigned int
 532 +lq_get_cpu_ver(void)
 533 +{
 534 +       return soc_info.rev;
 535 +}
 536 +EXPORT_SYMBOL(lq_get_cpu_ver);
 537 +
 538 +unsigned int
 539 +lq_get_soc_type(void)
 540 +{
 541 +       return soc_info.type;
 542 +}
 543 +EXPORT_SYMBOL(lq_get_soc_type);
 544 +
 545 +const char*
 546 +get_system_type(void)
 547 +{
 548 +       return soc_info.sys_type;
 549 +}
 550 +
 551 +void
 552 +prom_free_prom_memory(void)
 553 +{
 554 +}
 555 +
 556 +#ifdef CONFIG_IMAGE_CMDLINE_HACK
 557 +extern char __image_cmdline[];
 558 +
 559 +static void __init
 560 +prom_init_image_cmdline(void)
 561 +{
 562 +       char *p = __image_cmdline;
 563 +       int replace = 0;
 564 +
 565 +       if (*p == '-') {
 566 +               replace = 1;
 567 +               p++;
 568 +       }
 569 +
 570 +       if (*p == '\0')
 571 +               return;
 572 +
 573 +       if (replace) {
 574 +               strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
 575 +       } else {
 576 +               strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
 577 +               strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
 578 +       }
 579 +}
 580 +#else
 581 +static void __init prom_init_image_cmdline(void) { return; }
 582 +#endif
 583 +
 584 +static void __init
 585 +prom_init_cmdline(void)
 586 +{
 587 +       int argc = fw_arg0;
 588 +       char **argv = (char**)KSEG1ADDR(fw_arg1);
 589 +       int i;
 590 +
 591 +       arcs_cmdline[0] = '\0';
 592 +       if(argc)
 593 +               for (i = 1; i < argc; i++)
 594 +               {
 595 +                       strlcat(arcs_cmdline, (char*)KSEG1ADDR(argv[i]), COMMAND_LINE_SIZE);
 596 +                       if(i + 1 != argc)
 597 +                               strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 598 +               }
 599 +
 600 +       if (!*arcs_cmdline)
 601 +               strcpy(&(arcs_cmdline[0]),
 602 +                       "console=ttyS1,115200 rootfstype=squashfs,jffs2");
 603 +       prom_init_image_cmdline();
 604 +}
 605 +
 606 +void __init
 607 +prom_init(void)
 608 +{
 609 +       struct clk *clk;
 610 +       lq_soc_detect(&soc_info);
 611 +
 612 +       clk_init();
 613 +       clk = clk_get(0, "cpu");
 614 +       snprintf(soc_info.sys_type, LQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
 615 +               soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
 616 +       soc_info.sys_type[LQ_SYS_TYPE_LEN - 1] = '\0';
 617 +       printk("SoC: %s\n", soc_info.sys_type);
 618 +
 619 +       prom_init_cmdline();
 620 +}
 621 --- /dev/null
 622 +++ b/arch/mips/lantiq/prom.h
 623 @@ -0,0 +1,24 @@
 624 +/*
 625 + *  This program is free software; you can redistribute it and/or modify it
 626 + *  under the terms of the GNU General Public License version 2 as published
 627 + *  by the Free Software Foundation.
 628 + *
 629 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 630 + */
 631 +
 632 +#ifndef _LQ_PROM_H__
 633 +#define _LQ_PROM_H__
 634 +
 635 +#define LQ_SYS_TYPE_LEN        0x100
 636 +
 637 +struct lq_soc_info {
 638 +       unsigned char *name;
 639 +       unsigned int rev;
 640 +       unsigned int partnum;
 641 +       unsigned int type;
 642 +       unsigned char sys_type[LQ_SYS_TYPE_LEN];
 643 +};
 644 +
 645 +void lq_soc_detect(struct lq_soc_info *i);
 646 +
 647 +#endif