package/broadcom-57xx/src/hndgige.c

   1 /*
   2  * HND SiliconBackplane Gigabit Ethernet core software interface
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  */
  13
  14 #include <typedefs.h>
  15 #include <osl.h>
  16 #include <pcicfg.h>
  17 #include <sbconfig.h>
  18 #include <sbutils.h>
  19 #include "sbgige.h"
  20 #include <hndpci.h>
  21 #include "hndgige.h"
  22
  23 uint32
  24 sb_base(uint32 admatch)
  25 {
  26         uint32 base;
  27         uint type;
  28
  29         type = admatch & SBAM_TYPE_MASK;
  30         ASSERT(type < 3);
  31
  32         base = 0;
  33
  34         if (type == 0) {
  35                 base = admatch & SBAM_BASE0_MASK;
  36         } else if (type == 1) {
  37                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
  38                 base = admatch & SBAM_BASE1_MASK;
  39         } else if (type == 2) {
  40                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
  41                 base = admatch & SBAM_BASE2_MASK;
  42         }
  43
  44         return (base);
  45 }
  46
  47 /*
  48  * Setup the gige core.
  49  * Resetting the core will lose all settings.
  50  */
  51 void
  52 sb_gige_init(sb_t *sbh, uint32 unit, bool *rgmii)
  53 {
  54         volatile pci_config_regs *pci;
  55         sbgige_pcishim_t *ocp;
  56         sbconfig_t *sb;
  57         osl_t *osh;
  58         uint32 statelow;
  59         uint32 statehigh;
  60         uint32 base;
  61         uint32 idx;
  62         void *regs;
  63
  64         /* Sanity checks */
  65         ASSERT(sbh);
  66         ASSERT(rgmii);
  67
  68         idx = sb_coreidx(sbh);
  69
  70         /* point to the gige core registers */
  71         regs = sb_setcore(sbh, SB_GIGETH, unit);
  72         ASSERT(regs);
  73
  74         osh = sb_osh(sbh);
  75
  76         pci = &((sbgige_t *)regs)->pcicfg;
  77         ocp = &((sbgige_t *)regs)->pcishim;
  78         sb = &((sbgige_t *)regs)->sbconfig;
  79
  80         /* Enable the core clock and memory access */
  81         if (!sb_iscoreup(sbh))
  82                 sb_core_reset(sbh, 0, 0);
  83
  84         /*
  85          * Setup the 64K memory-mapped region base address through BAR0.
  86          * Leave the other BAR values alone.
  87          */
  88         base = sb_base(R_REG(osh, &sb->sbadmatch1));
  89         W_REG(osh, &pci->base[0], base);
  90         W_REG(osh, &pci->base[1], 0);
  91
  92         /*
  93          * Enable the PCI memory access anyway. Any PCI config commands
  94          * issued before the core is enabled will go to the emulation
  95          * only and will not go to the real PCI config registers.
  96          */
  97         OR_REG(osh, &pci->command, 2);
  98
  99         /*
 100          * Enable the posted write flush scheme as follows:
 101          *
 102          * - Enable flush on any core register read
 103          * - Enable timeout on the flush
 104          * - Disable the interrupt mask when flushing
 105          *
 106          * This differs from the default setting only in that interrupts are
 107          * not masked.  Since posted writes are not flushed on interrupt, the
 108          * driver must explicitly request a flush in its interrupt handling
 109          * by reading a core register.
 110          */
 111         W_REG(osh, &ocp->FlushStatusControl, 0x68);
 112
 113         /*
 114          * Determine whether the GbE is in GMII or RGMII mode.  This is
 115          * indicated in bit 16 of the SBTMStateHigh register, which is
 116          * part of the core-specific flags field.
 117          *
 118          * For GMII, bypass the Rx/Tx DLLs, i.e. add no delay to RXC/GTXC
 119          * within the core.  For RGMII, do not bypass the DLLs, resulting
 120          * in added delay for RXC/GTXC.  The SBTMStateLow register contains
 121          * the controls for doing this in the core-specific flags field:
 122          *
 123          *   bit 24 - Enable DLL controls
 124          *   bit 20 - Bypass Rx DLL
 125          *   bit 19 - Bypass Tx DLL
 126          */
 127         statelow = R_REG(osh, &sb->sbtmstatelow);       /* DLL controls */
 128         statehigh = R_REG(osh, &sb->sbtmstatehigh);     /* GMII/RGMII mode */
 129         if ((statehigh & (1 << 16)) != 0)       /* RGMII */
 130         {
 131                 statelow &= ~(1 << 20);         /* no Rx bypass (delay) */
 132                 statelow &= ~(1 << 19);         /* no Tx bypass (delay) */
 133                 *rgmii = TRUE;
 134         }
 135         else                                    /* GMII */
 136         {
 137                 statelow |= (1 << 20);          /* Rx bypass (no delay) */
 138                 statelow |= (1 << 19);          /* Tx bypass (no delay) */
 139                 *rgmii = FALSE;
 140         }
 141         statelow |= (1 << 24);                  /* enable DLL controls */
 142         W_REG(osh, &sb->sbtmstatelow, statelow);
 143
 144         sb_setcoreidx(sbh, idx);
 145 }