package/uboot-lantiq/files/board/arcadyan/arv752DWP22/arv752.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Thomas Langer, Ralph Hempel
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <command.h>
  29 #include <netdev.h>
  30 #include <miiphy.h>
  31 #include <asm/addrspace.h>
  32 #include <asm/danube.h>
  33 #include <asm/reboot.h>
  34 #include <asm/io.h>
  35 #if defined(CONFIG_CMD_HTTPD)
  36 #include <httpd.h>
  37 #endif
  38 #if defined(CONFIG_PCI)
  39 #include <pci.h>
  40 #endif
  41 #include "athrs26_phy.h"
  42
  43 extern ulong ifx_get_ddr_hz(void);
  44 extern ulong ifx_get_cpuclk(void);
  45
  46 /* IDs and registers of known external switches */
  47 void _machine_restart(void)
  48 {
  49         *DANUBE_RCU_RST_REQ |=1<<30;
  50 }
  51
  52 #ifdef CONFIG_SYS_RAMBOOT
  53 phys_size_t initdram(int board_type)
  54 {
  55         return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
  56 }
  57 #elif defined(CONFIG_USE_DDR_RAM)
  58 phys_size_t initdram(int board_type)
  59 {
  60         return (CONFIG_SYS_MAX_RAM);
  61 }
  62 #else
  63
  64 static ulong max_sdram_size(void)     /* per Chip Select */
  65 {
  66         /* The only supported SDRAM data width is 16bit.
  67          */
  68 #define CFG_DW  4
  69
  70         /* The only supported number of SDRAM banks is 4.
  71          */
  72 #define CFG_NB  4
  73
  74         ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
  75         int   cols   = cfgpb0 & 0xF;
  76         int   rows   = (cfgpb0 & 0xF0) >> 4;
  77         ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
  78
  79         return size;
  80 }
  81
  82 /*
  83  * Check memory range for valid RAM. A simple memory test determines
  84  * the actually available RAM size between addresses `base' and
  85  * `base + maxsize'.
  86  */
  87
  88 static long int dram_size(long int *base, long int maxsize)
  89 {
  90         volatile long int *addr;
  91         ulong cnt, val;
  92         ulong save[32];                 /* to make test non-destructive */
  93         unsigned char i = 0;
  94
  95         for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
  96                 addr = base + cnt;              /* pointer arith! */
  97
  98                 save[i++] = *addr;
  99                 *addr = ~cnt;
 100         }
 101
 102         /* write 0 to base address */
 103         addr = base;
 104         save[i] = *addr;
 105         *addr = 0;
 106
 107         /* check at base address */
 108         if ((val = *addr) != 0) {
 109                 *addr = save[i];
 110                 return (0);
 111         }
 112
 113         for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
 114                 addr = base + cnt;              /* pointer arith! */
 115
 116                 val = *addr;
 117                 *addr = save[--i];
 118
 119                 if (val != (~cnt)) {
 120                         return (cnt * sizeof (long));
 121                 }
 122         }
 123         return (maxsize);
 124 }
 125
 126 phys_size_t initdram(int board_type)
 127 {
 128         int   rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
 129         ulong size, max_size       = 0;
 130         ulong our_address;
 131
 132         /* load t9 into our_address */
 133         asm volatile ("move %0, $25" : "=r" (our_address) :);
 134
 135         /* Can't probe for RAM size unless we are running from Flash.
 136          * find out whether running from DRAM or Flash.
 137          */
 138         if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
 139         {
 140                 return max_sdram_size();
 141         }
 142
 143         for (cols = 0x8; cols <= 0xC; cols++)
 144         {
 145                 for (rows = 0xB; rows <= 0xD; rows++)
 146                 {
 147                         *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 148                                                   (rows << 4) | cols;
 149                         size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 150                                                   max_sdram_size());
 151
 152                         if (size > max_size)
 153                         {
 154                                 best_val = *DANUBE_SDRAM_MC_CFGPB0;
 155                                 max_size = size;
 156                         }
 157                 }
 158         }
 159
 160         *DANUBE_SDRAM_MC_CFGPB0 = best_val;
 161         return max_size;
 162 }
 163 #endif
 164
 165 int checkboard (void)
 166 {
 167         unsigned long chipid = *DANUBE_MPS_CHIPID;
 168         int part_num;
 169
 170         puts ("Board: ARV75DW22 - Easybox 803\n");
 171         puts ("SoC: ");
 172
 173         part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
 174         switch (part_num)
 175         {
 176         case 0x129:
 177         case 0x12D:
 178         case 0x12b:
 179                 puts("Danube/Twinpass/Vinax-VE ");
 180                 break;
 181         default:
 182                 printf ("unknown, chip part number 0x%03X ", part_num);
 183                 break;
 184         }
 185         printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
 186
 187         printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
 188         printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
 189
 190         return 0;
 191 }
 192
 193 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 194 int board_early_init_f(void)
 195 {
 196 #ifdef CONFIG_EBU_ADDSEL0
 197         (*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
 198 #endif
 199 #ifdef CONFIG_EBU_ADDSEL1
 200         (*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
 201 #endif
 202 #ifdef CONFIG_EBU_ADDSEL2
 203         (*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
 204 #endif
 205 #ifdef CONFIG_EBU_ADDSEL3
 206         (*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
 207 #endif
 208 #ifdef CONFIG_EBU_BUSCON0
 209         (*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
 210 #endif
 211 #ifdef CONFIG_EBU_BUSCON1
 212         (*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
 213 #endif
 214 #ifdef CONFIG_EBU_BUSCON2
 215         (*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
 216 #endif
 217 #ifdef CONFIG_EBU_BUSCON3
 218         (*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
 219 #endif
 220
 221         return 0;
 222 }
 223 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 224
 225
 226 #ifdef CONFIG_EXTRA_SWITCH
 227 static int external_switch_init(void)
 228 {
 229         // switch reset pin on arv752
 230         *DANUBE_GPIO_P1_ALTSEL0 &= ~8;
 231         *DANUBE_GPIO_P1_ALTSEL1 &= ~8;
 232         *DANUBE_GPIO_P1_OD |= 8;
 233         *DANUBE_GPIO_P1_DIR |= 8;
 234         *DANUBE_GPIO_P1_OUT |= 8;
 235
 236         puts("initializing ar8216 switch... ");
 237         if (athrs26_phy_setup(0)==0) {
 238            printf("initialized\n");
 239            return 0;
 240         }
 241         puts("failed ... \n");
 242         return 0;
 243 }
 244 #endif /* CONFIG_EXTRA_SWITCH */
 245
 246 int board_eth_init(bd_t *bis)
 247 {
 248 #if defined(CONFIG_IFX_ETOP)
 249         uchar enetaddr[6];
 250         if (!eth_getenv_enetaddr("ethaddr", enetaddr))
 251                eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
 252
 253         *DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
 254         *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
 255
 256         if (lq_eth_initialize(bis))
 257                 return -1;
 258
 259         *DANUBE_RCU_RST_REQ |=1;
 260         udelay(200000);
 261         *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
 262         udelay(1000);
 263
 264 #ifdef CONFIG_EXTRA_SWITCH
 265         if (external_switch_init()<0)
 266                 return -1;
 267 #endif /* CONFIG_EXTRA_SWITCH */
 268 #endif /* CONFIG_IFX_ETOP */
 269
 270         return 0;
 271 }
 272
 273 #if defined(CONFIG_CMD_HTTPD)
 274 int do_http_upgrade(const unsigned char *data, const ulong size)
 275 {
 276         char buf[128];
 277
 278         if(getenv ("ram_addr") == NULL)
 279                 return -1;
 280         if(getenv ("kernel_addr") == NULL)
 281                 return -1;
 282         /* check the image */
 283         if(run_command("imi ${ram_addr}", 0) < 0) {
 284                 return -1;
 285         }
 286         /* write the image to the flash */
 287         puts("http ugrade ...\n");
 288         sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
 289         return run_command(buf, 0);
 290 }
 291
 292 int do_http_progress(const int state)
 293 {
 294         /* toggle LED's here */
 295         switch(state) {
 296                 case HTTP_PROGRESS_START:
 297                 puts("http start\n");
 298                 break;
 299                 case HTTP_PROGRESS_TIMEOUT:
 300                 puts(".");
 301                 break;
 302                 case HTTP_PROGRESS_UPLOAD_READY:
 303                 puts("http upload ready\n");
 304                 break;
 305                 case HTTP_PROGRESS_UGRADE_READY:
 306                 puts("http ugrade ready\n");
 307                 break;
 308                 case HTTP_PROGRESS_UGRADE_FAILED:
 309                 puts("http ugrade failed\n");
 310                 break;
 311         }
 312         return 0;
 313 }
 314
 315 unsigned long do_http_tmp_address(void)
 316 {
 317         char *s = getenv ("ram_addr");
 318         if (s) {
 319                 ulong tmp = simple_strtoul (s, NULL, 16);
 320                 return tmp;
 321         }
 322         return 0 /*0x80a00000*/;
 323 }
 324
 325 #endif