package/uboot-lantiq/files/board/arcadyan/arv752DWP22/lowlevel_init.S

   1 /*
   2  *  Memory sub-system initialization code for Danube board.
   3  *  Andre Messerschmidt
   4  *  Copyright (c) 2005  Infineon Technologies AG
   5  *
   6  *  Based on Inca-IP code
   7  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /* History:
  28       peng liu May 25, 2006, for PLL setting after reset, 05252006
  29  */
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/regdef.h>
  33
  34 #if 0
  35
  36 #if defined(CONFIG_USE_DDR_RAM)
  37
  38 #if defined(CONFIG_USE_DDR_RAM_CFG_111M)
  39 #include "ddr_settings_r111.h"
  40 #define DDR111
  41 #elif defined(CONFIG_USE_DDR_RAM_CFG_166M)
  42 #include "ddr_settings_r166.h"
  43 #define DDR166
  44 #elif defined(CONFIG_USE_DDR_RAM_CFG_e111M)
  45 #include "ddr_settings_e111.h"
  46 #define DDR111
  47 #elif defined(CONFIG_USE_DDR_RAM_CFG_e166M)
  48 #include "ddr_settings_e166.h"
  49 #define DDR166
  50 #elif defined(CONFIG_USE_DDR_RAM_CFG_promos400)
  51 #include "ddr_settings_PROMOSDDR400.h"
  52 #define DDR166
  53 #elif defined(CONFIG_USE_DDR_RAM_CFG_samsung166)
  54 #include "ddr_settings_Samsung_166.h"
  55 #define DDR166
  56 #elif defined(CONFIG_USE_DDR_RAM_CFG_psc166)
  57 #include "ddr_settings_psc_166.h"
  58 #define DDR166
  59 #else
  60 #warning "missing definition for ddr_settings.h, use default!"
  61 #include "ddr_settings.h"
  62 #endif
  63 #endif /* CONFIG_USE_DDR_RAM */
  64
  65 #else
  66
  67 #include "ddr_settings_psc_166.h"
  68 #define DDR166
  69
  70 #endif
  71
  72 #if defined(CONFIG_USE_DDR_RAM) &&  !defined(MC_DC0_VALUE)
  73 #error "missing include of ddr_settings.h"
  74 #endif
  75
  76 #define EBU_MODUL_BASE          0xBE105300
  77 #define EBU_CLC(value)          0x0000(value)
  78 #define EBU_CON(value)          0x0010(value)
  79 #define EBU_ADDSEL0(value)      0x0020(value)
  80 #define EBU_ADDSEL1(value)      0x0024(value)
  81 #define EBU_ADDSEL2(value)      0x0028(value)
  82 #define EBU_ADDSEL3(value)      0x002C(value)
  83 #define EBU_BUSCON0(value)      0x0060(value)
  84 #define EBU_BUSCON1(value)      0x0064(value)
  85 #define EBU_BUSCON2(value)      0x0068(value)
  86 #define EBU_BUSCON3(value)      0x006C(value)
  87
  88 #define MC_MODUL_BASE           0xBF800000
  89 #define MC_ERRCAUSE(value)      0x0010(value)
  90 #define MC_ERRADDR(value)       0x0020(value)
  91 #define MC_CON(value)           0x0060(value)
  92
  93 #define MC_SRAM_ENABLE          0x00000004
  94 #define MC_SDRAM_ENABLE         0x00000002
  95 #define MC_DDRRAM_ENABLE        0x00000001
  96
  97 #define MC_SDR_MODUL_BASE       0xBF800200
  98 #define MC_IOGP(value)          0x0000(value)
  99 #define MC_CTRLENA(value)       0x0010(value)
 100 #define MC_MRSCODE(value)       0x0020(value)
 101 #define MC_CFGDW(value)         0x0030(value)
 102 #define MC_CFGPB0(value)        0x0040(value)
 103 #define MC_LATENCY(value)       0x0080(value)
 104 #define MC_TREFRESH(value)      0x0090(value)
 105 #define MC_SELFRFSH(value)      0x00A0(value)
 106
 107 #define MC_DDR_MODUL_BASE       0xBF801000
 108 #define MC_DC00(value)          0x0000(value)
 109 #define MC_DC01(value)          0x0010(value)
 110 #define MC_DC02(value)          0x0020(value)
 111 #define MC_DC03(value)          0x0030(value)
 112 #define MC_DC04(value)          0x0040(value)
 113 #define MC_DC05(value)          0x0050(value)
 114 #define MC_DC06(value)          0x0060(value)
 115 #define MC_DC07(value)          0x0070(value)
 116 #define MC_DC08(value)          0x0080(value)
 117 #define MC_DC09(value)          0x0090(value)
 118 #define MC_DC10(value)          0x00A0(value)
 119 #define MC_DC11(value)          0x00B0(value)
 120 #define MC_DC12(value)          0x00C0(value)
 121 #define MC_DC13(value)          0x00D0(value)
 122 #define MC_DC14(value)          0x00E0(value)
 123 #define MC_DC15(value)          0x00F0(value)
 124 #define MC_DC16(value)          0x0100(value)
 125 #define MC_DC17(value)          0x0110(value)
 126 #define MC_DC18(value)          0x0120(value)
 127 #define MC_DC19(value)          0x0130(value)
 128 #define MC_DC20(value)          0x0140(value)
 129 #define MC_DC21(value)          0x0150(value)
 130 #define MC_DC22(value)          0x0160(value)
 131 #define MC_DC23(value)          0x0170(value)
 132 #define MC_DC24(value)          0x0180(value)
 133 #define MC_DC25(value)          0x0190(value)
 134 #define MC_DC26(value)          0x01A0(value)
 135 #define MC_DC27(value)          0x01B0(value)
 136 #define MC_DC28(value)          0x01C0(value)
 137 #define MC_DC29(value)          0x01D0(value)
 138 #define MC_DC30(value)          0x01E0(value)
 139 #define MC_DC31(value)          0x01F0(value)
 140 #define MC_DC32(value)          0x0200(value)
 141 #define MC_DC33(value)          0x0210(value)
 142 #define MC_DC34(value)          0x0220(value)
 143 #define MC_DC35(value)          0x0230(value)
 144 #define MC_DC36(value)          0x0240(value)
 145 #define MC_DC37(value)          0x0250(value)
 146 #define MC_DC38(value)          0x0260(value)
 147 #define MC_DC39(value)          0x0270(value)
 148 #define MC_DC40(value)          0x0280(value)
 149 #define MC_DC41(value)          0x0290(value)
 150 #define MC_DC42(value)          0x02A0(value)
 151 #define MC_DC43(value)          0x02B0(value)
 152 #define MC_DC44(value)          0x02C0(value)
 153 #define MC_DC45(value)          0x02D0(value)
 154 #define MC_DC46(value)          0x02E0(value)
 155
 156 #define RCU_OFFSET  0xBF203000
 157 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 158 #define RCU_STS          (RCU_OFFSET + 0x0014)
 159
 160 #define CGU_OFFSET  0xBF103000
 161 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 162 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 163 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 164 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 165 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 166 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 167 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 168 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 169 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 170 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 171 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 172 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 173 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 174 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 175
 176 //05252006
 177 #define  pll0_35MHz_CONFIG 0x9D861059
 178 #define  pll1_35MHz_CONFIG 0x1A260CD9
 179 #define  pll2_35MHz_CONFIG 0x8000f1e5
 180 #define  pll0_36MHz_CONFIG 0x1000125D
 181 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 182 #define  pll2_36MHz_CONFIG 0x8002f2a1
 183 //05252006
 184
 185 //06063001-joelin disable the PCI CFRAME mask -start
 186 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 187 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 188
 189 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 190 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 191 */
 192 #define PCI_CR_PR_OFFSET  0xBE105400
 193 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 194 #define PCI_CONFIG_SPACE  0xB7000000
 195 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 196 //06063001-joelin disable the PCI CFRAME mask -end
 197         .set    noreorder
 198
 199
 200 /*
 201  * void ebu_init(void)
 202  */
 203         .globl  ebu_init
 204         .ent    ebu_init
 205 ebu_init:
 206
 207 #if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
 208         defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
 209         defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
 210         defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
 211
 212         li      t1, EBU_MODUL_BASE
 213 #if defined(CONFIG_EBU_ADDSEL0)
 214         li      t2, CONFIG_EBU_ADDSEL0
 215         sw      t2, EBU_ADDSEL0(t1)
 216 #endif
 217 #if defined(CONFIG_EBU_ADDSEL1)
 218         li      t2, CONFIG_EBU_ADDSEL1
 219         sw      t2, EBU_ADDSEL1(t1)
 220 #endif
 221 #if defined(CONFIG_EBU_ADDSEL2)
 222         li      t2, CONFIG_EBU_ADDSEL2
 223         sw      t2, EBU_ADDSEL2(t1)
 224 #endif
 225 #if defined(CONFIG_EBU_ADDSEL3)
 226         li      t2, CONFIG_EBU_ADDSEL3
 227         sw      t2, EBU_ADDSEL3(t1)
 228 #endif
 229
 230 #if defined(CONFIG_EBU_BUSCON0)
 231         li      t2, CONFIG_EBU_BUSCON0
 232         sw      t2, EBU_BUSCON0(t1)
 233 #endif
 234 #if defined(CONFIG_EBU_BUSCON1)
 235         li      t2, CONFIG_EBU_BUSCON1
 236         sw      t2, EBU_BUSCON1(t1)
 237 #endif
 238 #if defined(CONFIG_EBU_BUSCON2)
 239         li      t2, CONFIG_EBU_BUSCON2
 240         sw      t2, EBU_BUSCON2(t1)
 241 #endif
 242 #if defined(CONFIG_EBU_BUSCON3)
 243         li      t2, CONFIG_EBU_BUSCON3
 244         sw      t2, EBU_BUSCON3(t1)
 245 #endif
 246
 247 #endif
 248
 249         j       ra
 250         nop
 251
 252         .end    ebu_init
 253
 254
 255 /*
 256  * void cgu_init(long)
 257  *
 258  * a0 has the clock value
 259  */
 260         .globl  cgu_init
 261         .ent    cgu_init
 262 cgu_init:
 263         li  t2, CGU_SYS
 264         lw  t2,0(t2)
 265         beq t2,a0,freq_up2date
 266         nop
 267
 268         li  t2, RCU_STS
 269         lw  t2, 0(t2)
 270         and t2,0x00020000
 271         beq t2,0x00020000,boot_36MHZ
 272         nop
 273 //05252006
 274         li  t1, PLL0_CFG
 275         li  t2, pll0_35MHz_CONFIG
 276         sw      t2,0(t1)
 277         li  t1, PLL1_CFG
 278         li  t2, pll1_35MHz_CONFIG
 279         sw      t2,0(t1)
 280         li  t1, PLL2_CFG
 281         li  t2, pll2_35MHz_CONFIG
 282         sw      t2,0(t1)
 283         li  t1, CGU_SYS
 284         sw      a0,0(t1)
 285         li  t1, RCU_RST_REQ
 286         li  t2, 0x40000008
 287         sw      t2,0(t1)
 288         b   wait_reset
 289         nop
 290 boot_36MHZ:
 291         li  t1, PLL0_CFG
 292         li  t2, pll0_36MHz_CONFIG
 293         sw      t2,0(t1)
 294         li  t1, PLL1_CFG
 295         li  t2, pll1_36MHz_CONFIG
 296         sw      t2,0(t1)
 297         li  t1, PLL2_CFG
 298         li  t2, pll2_36MHz_CONFIG
 299         sw      t2,0(t1)
 300         li  t1, CGU_SYS
 301         sw      a0,0(t1)
 302         li  t1, RCU_RST_REQ
 303         li  t2, 0x40000008
 304         sw      t2,0(t1)
 305 //05252006
 306
 307 wait_reset:
 308         b   wait_reset
 309         nop
 310 freq_up2date:
 311         j ra
 312         nop
 313
 314         .end    cgu_init
 315
 316 #ifndef CONFIG_USE_DDR_RAM
 317 /*
 318  * void sdram_init(long)
 319  *
 320  * a0 has the clock value
 321  */
 322         .globl  sdram_init
 323         .ent    sdram_init
 324 sdram_init:
 325
 326         /* SDRAM Initialization
 327          */
 328         li      t1, MC_MODUL_BASE
 329
 330         /* Clear Error log registers */
 331         sw      zero, MC_ERRCAUSE(t1)
 332         sw      zero, MC_ERRADDR(t1)
 333
 334         /* Enable SDRAM module in memory controller */
 335         li      t3, MC_SDRAM_ENABLE
 336         lw      t2, MC_CON(t1)
 337         or      t3, t2, t3
 338         sw      t3, MC_CON(t1)
 339
 340         li      t1, MC_SDR_MODUL_BASE
 341
 342         /* disable the controller */
 343         li      t2, 0
 344         sw      t2, MC_CTRLENA(t1)
 345
 346         li      t2, 0x822
 347         sw      t2, MC_IOGP(t1)
 348
 349         li      t2, 0x2
 350         sw      t2, MC_CFGDW(t1)
 351
 352         /* Set CAS Latency */
 353         li      t2, 0x00000020
 354         sw      t2, MC_MRSCODE(t1)
 355
 356         /* Set CS0 to SDRAM parameters */
 357         li      t2, 0x000014d8
 358         sw      t2, MC_CFGPB0(t1)
 359
 360         /* Set SDRAM latency parameters */
 361         li      t2, 0x00036325;   /* BC PC100 */
 362         sw      t2, MC_LATENCY(t1)
 363
 364         /* Set SDRAM refresh rate */
 365         li      t2, 0x00000C30
 366         sw      t2, MC_TREFRESH(t1)
 367
 368         /* Clear Power-down registers */
 369         sw      zero, MC_SELFRFSH(t1)
 370
 371         /* Finally enable the controller */
 372         li      t2, 1
 373         sw      t2, MC_CTRLENA(t1)
 374
 375         j       ra
 376         nop
 377
 378         .end    sdram_init
 379
 380 #endif /* !CONFIG_USE_DDR_RAM */
 381
 382 #ifdef CONFIG_USE_DDR_RAM
 383 /*
 384  * void ddrram_init(long)
 385  *
 386  * a0 has the clock value
 387  */
 388         .globl  ddrram_init
 389         .ent    ddrram_init
 390 ddrram_init:
 391
 392         /* DDR-DRAM Initialization
 393          */
 394         li      t1, MC_MODUL_BASE
 395
 396         /* Clear Error log registers */
 397         sw      zero, MC_ERRCAUSE(t1)
 398         sw      zero, MC_ERRADDR(t1)
 399
 400         /* Enable DDR module in memory controller */
 401         li      t3, MC_DDRRAM_ENABLE
 402         lw      t2, MC_CON(t1)
 403         or      t3, t2, t3
 404         sw      t3, MC_CON(t1)
 405
 406         li      t1, MC_DDR_MODUL_BASE
 407
 408         /* Write configuration to DDR controller registers */
 409         li      t2, MC_DC0_VALUE
 410         sw      t2, MC_DC00(t1)
 411
 412         li      t2, MC_DC1_VALUE
 413         sw      t2, MC_DC01(t1)
 414
 415         li      t2, MC_DC2_VALUE
 416         sw      t2, MC_DC02(t1)
 417
 418         li      t2, MC_DC3_VALUE
 419         sw      t2, MC_DC03(t1)
 420
 421         li      t2, MC_DC4_VALUE
 422         sw      t2, MC_DC04(t1)
 423
 424         li      t2, MC_DC5_VALUE
 425         sw      t2, MC_DC05(t1)
 426
 427         li      t2, MC_DC6_VALUE
 428         sw      t2, MC_DC06(t1)
 429
 430         li      t2, MC_DC7_VALUE
 431         sw      t2, MC_DC07(t1)
 432
 433         li      t2, MC_DC8_VALUE
 434         sw      t2, MC_DC08(t1)
 435
 436         li      t2, MC_DC9_VALUE
 437         sw      t2, MC_DC09(t1)
 438
 439         li      t2, MC_DC10_VALUE
 440         sw      t2, MC_DC10(t1)
 441
 442         li      t2, MC_DC11_VALUE
 443         sw      t2, MC_DC11(t1)
 444
 445         li      t2, MC_DC12_VALUE
 446         sw      t2, MC_DC12(t1)
 447
 448         li      t2, MC_DC13_VALUE
 449         sw      t2, MC_DC13(t1)
 450
 451         li      t2, MC_DC14_VALUE
 452         sw      t2, MC_DC14(t1)
 453
 454         li      t2, MC_DC15_VALUE
 455         sw      t2, MC_DC15(t1)
 456
 457         li      t2, MC_DC16_VALUE
 458         sw      t2, MC_DC16(t1)
 459
 460         li      t2, MC_DC17_VALUE
 461         sw      t2, MC_DC17(t1)
 462
 463         li      t2, MC_DC18_VALUE
 464         sw      t2, MC_DC18(t1)
 465
 466         li      t2, MC_DC19_VALUE
 467         sw      t2, MC_DC19(t1)
 468
 469         li      t2, MC_DC20_VALUE
 470         sw      t2, MC_DC20(t1)
 471
 472         li      t2, MC_DC21_VALUE
 473         sw      t2, MC_DC21(t1)
 474
 475         li      t2, MC_DC22_VALUE
 476         sw      t2, MC_DC22(t1)
 477
 478         li      t2, MC_DC23_VALUE
 479         sw      t2, MC_DC23(t1)
 480
 481         li      t2, MC_DC24_VALUE
 482         sw      t2, MC_DC24(t1)
 483
 484         li      t2, MC_DC25_VALUE
 485         sw      t2, MC_DC25(t1)
 486
 487         li      t2, MC_DC26_VALUE
 488         sw      t2, MC_DC26(t1)
 489
 490         li      t2, MC_DC27_VALUE
 491         sw      t2, MC_DC27(t1)
 492
 493         li      t2, MC_DC28_VALUE
 494         sw      t2, MC_DC28(t1)
 495
 496         li      t2, MC_DC29_VALUE
 497         sw      t2, MC_DC29(t1)
 498
 499         li      t2, MC_DC30_VALUE
 500         sw      t2, MC_DC30(t1)
 501
 502         li      t2, MC_DC31_VALUE
 503         sw      t2, MC_DC31(t1)
 504
 505         li      t2, MC_DC32_VALUE
 506         sw      t2, MC_DC32(t1)
 507
 508         li      t2, MC_DC33_VALUE
 509         sw      t2, MC_DC33(t1)
 510
 511         li      t2, MC_DC34_VALUE
 512         sw      t2, MC_DC34(t1)
 513
 514         li      t2, MC_DC35_VALUE
 515         sw      t2, MC_DC35(t1)
 516
 517         li      t2, MC_DC36_VALUE
 518         sw      t2, MC_DC36(t1)
 519
 520         li      t2, MC_DC37_VALUE
 521         sw      t2, MC_DC37(t1)
 522
 523         li      t2, MC_DC38_VALUE
 524         sw      t2, MC_DC38(t1)
 525
 526         li      t2, MC_DC39_VALUE
 527         sw      t2, MC_DC39(t1)
 528
 529         li      t2, MC_DC40_VALUE
 530         sw      t2, MC_DC40(t1)
 531
 532         li      t2, MC_DC41_VALUE
 533         sw      t2, MC_DC41(t1)
 534
 535         li      t2, MC_DC42_VALUE
 536         sw      t2, MC_DC42(t1)
 537
 538         li      t2, MC_DC43_VALUE
 539         sw      t2, MC_DC43(t1)
 540
 541         li      t2, MC_DC44_VALUE
 542         sw      t2, MC_DC44(t1)
 543
 544         li      t2, MC_DC45_VALUE
 545         sw      t2, MC_DC45(t1)
 546
 547         li      t2, MC_DC46_VALUE
 548         sw      t2, MC_DC46(t1)
 549
 550         li      t2, 0x00000100
 551         sw      t2, MC_DC03(t1)
 552
 553         j       ra
 554         nop
 555
 556         .end    ddrram_init
 557 #endif /* CONFIG_USE_DDR_RAM */
 558
 559         .globl  lowlevel_init
 560         .ent    lowlevel_init
 561 lowlevel_init:
 562         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 563          */
 564         move    t0, ra
 565         /* We rely on the fact that non of the following ..._init() functions
 566          * modify t0
 567          */
 568 #if defined(CONFIG_SYS_EBU_BOOT)
 569 #if defined(DDR166)
 570         /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
 571         li  a0,0xe8
 572 #elif defined(DDR133)
 573         /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
 574         li  a0,0xe9
 575 #else /* defined(DDR111) */
 576         /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
 577         li  a0,0xea
 578 #endif
 579         bal     cgu_init
 580         nop
 581 #endif /* CONFIG_SYS_EBU_BOOT */
 582
 583         bal     ebu_init
 584         nop
 585
 586 //06063001-joelin disable the PCI CFRAME mask-start
 587 #ifdef DISABLE_CFRAME
 588         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 589         li  t2, 0x80000000
 590         sw      t2,0(t1)
 591
 592         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 593         li  t2, 0x103
 594         sw  t2,0(t1)
 595
 596         li  t1, CS_CFM                  //mw b700006c 0
 597         li  t2, 0x00
 598         sw  t2, 0(t1)
 599
 600         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 601         li  t2, 0x1000103
 602         sw  t2, 0(t1)
 603 #endif
 604 //06063001-joelin disable the PCI CFRAME mask-end
 605
 606 #ifdef CONFIG_SYS_EBU_BOOT
 607 #ifndef CONFIG_SYS_RAMBOOT
 608 #ifdef CONFIG_USE_DDR_RAM
 609         bal     ddrram_init
 610         nop
 611 #else
 612         bal     sdram_init
 613         nop
 614 #endif
 615 #endif /* CONFIG_SYS_RAMBOOT */
 616 #endif /* CONFIG_SYS_EBU_BOOT */
 617
 618         move    ra, t0
 619         j       ra
 620         nop
 621
 622         .end    lowlevel_init