[toolchain] uClibc: remove references to $(CONFIG_LARGEFILE)
[openwrt.git] / package / uboot-lantiq / files / board / infineon / easy50812 / lowlevel_init.S
1 /*
2 * Memory sub-system initialization code for AR9 board.
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 * Copyright (c) 2005 Andre Messerschmidt Infineon
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25 /* History:
26 peng liu May 25, 2006, for PLL setting after reset, 05252006
27 */
28 #include <config.h>
29 #include <version.h>
30 #include <asm/regdef.h>
31
32 #if defined(CONFIG_USE_DDR_RAM)
33
34 #if defined(CONFIG_CPU_111M_RAM_111M) || defined(CONFIG_CPU_333M_RAM_111M)
35 # include "ar9_ddr111_settings.h"
36 #elif defined(CONFIG_CPU_166M_RAM_166M) || defined(CONFIG_CPU_333M_RAM_166M) || defined(CONFIG_CPU_500M_RAM_166M)
37 # include "ar9_ddr166_settings.h"
38 #elif defined(CONFIG_CPU_442M_RAM_147M)
39 # include "ar9_ddr166_settings.h"
40 #elif defined(CONFIG_CPU_393M_RAM_196M)
41 # ifdef CONFIG_ETRON_RAM
42 # include "etron_ddr196_settings.h"
43 # else
44 # include "ar9_ddr196_settings.h"
45 # endif
46 #elif defined(CONFIG_CPU_442M_RAM_221M)
47 # include "ar9_ddr221_settings.h"
48 #elif defined(CONFIG_CPU_500M_RAM_250M)
49 # include "ar9_ddr250_settings.h"
50 #else
51 # warning "missing definition for ddr_settings.h, use default!"
52 # include "ar9_ddr_settings.h"
53 #endif
54 #endif /* CONFIG_USE_DDR_RAM */
55
56 #if defined(CONFIG_USE_DDR_RAM) && !defined(MC_DC0_VALUE)
57 #error "missing include of ddr_settings.h"
58 #endif
59
60 #define EBU_MODUL_BASE 0xBE105300
61 #define EBU_CLC(value) 0x0000(value)
62 #define EBU_CON(value) 0x0010(value)
63 #define EBU_ADDSEL0(value) 0x0020(value)
64 #define EBU_ADDSEL1(value) 0x0024(value)
65 #define EBU_ADDSEL2(value) 0x0028(value)
66 #define EBU_ADDSEL3(value) 0x002C(value)
67 #define EBU_BUSCON0(value) 0x0060(value)
68 #define EBU_BUSCON1(value) 0x0064(value)
69 #define EBU_BUSCON2(value) 0x0068(value)
70 #define EBU_BUSCON3(value) 0x006C(value)
71
72 #define MC_MODUL_BASE 0xBF800000
73 #define MC_ERRCAUSE(value) 0x0010(value)
74 #define MC_ERRADDR(value) 0x0020(value)
75 #define MC_CON(value) 0x0060(value)
76
77 #define MC_SRAM_ENABLE 0x00000004
78 #define MC_SDRAM_ENABLE 0x00000002
79 #define MC_DDRRAM_ENABLE 0x00000001
80
81 #define MC_SDR_MODUL_BASE 0xBF800200
82 #define MC_IOGP(value) 0x0000(value)
83 #define MC_CTRLENA(value) 0x0010(value)
84 #define MC_MRSCODE(value) 0x0020(value)
85 #define MC_CFGDW(value) 0x0030(value)
86 #define MC_CFGPB0(value) 0x0040(value)
87 #define MC_LATENCY(value) 0x0080(value)
88 #define MC_TREFRESH(value) 0x0090(value)
89 #define MC_SELFRFSH(value) 0x00A0(value)
90
91 #define MC_DDR_MODUL_BASE 0xBF801000
92 #define MC_DC00(value) 0x0000(value)
93 #define MC_DC01(value) 0x0010(value)
94 #define MC_DC02(value) 0x0020(value)
95 #define MC_DC03(value) 0x0030(value)
96 #define MC_DC04(value) 0x0040(value)
97 #define MC_DC05(value) 0x0050(value)
98 #define MC_DC06(value) 0x0060(value)
99 #define MC_DC07(value) 0x0070(value)
100 #define MC_DC08(value) 0x0080(value)
101 #define MC_DC09(value) 0x0090(value)
102 #define MC_DC10(value) 0x00A0(value)
103 #define MC_DC11(value) 0x00B0(value)
104 #define MC_DC12(value) 0x00C0(value)
105 #define MC_DC13(value) 0x00D0(value)
106 #define MC_DC14(value) 0x00E0(value)
107 #define MC_DC15(value) 0x00F0(value)
108 #define MC_DC16(value) 0x0100(value)
109 #define MC_DC17(value) 0x0110(value)
110 #define MC_DC18(value) 0x0120(value)
111 #define MC_DC19(value) 0x0130(value)
112 #define MC_DC20(value) 0x0140(value)
113 #define MC_DC21(value) 0x0150(value)
114 #define MC_DC22(value) 0x0160(value)
115 #define MC_DC23(value) 0x0170(value)
116 #define MC_DC24(value) 0x0180(value)
117 #define MC_DC25(value) 0x0190(value)
118 #define MC_DC26(value) 0x01A0(value)
119 #define MC_DC27(value) 0x01B0(value)
120 #define MC_DC28(value) 0x01C0(value)
121 #define MC_DC29(value) 0x01D0(value)
122 #define MC_DC30(value) 0x01E0(value)
123 #define MC_DC31(value) 0x01F0(value)
124 #define MC_DC32(value) 0x0200(value)
125 #define MC_DC33(value) 0x0210(value)
126 #define MC_DC34(value) 0x0220(value)
127 #define MC_DC35(value) 0x0230(value)
128 #define MC_DC36(value) 0x0240(value)
129 #define MC_DC37(value) 0x0250(value)
130 #define MC_DC38(value) 0x0260(value)
131 #define MC_DC39(value) 0x0270(value)
132 #define MC_DC40(value) 0x0280(value)
133 #define MC_DC41(value) 0x0290(value)
134 #define MC_DC42(value) 0x02A0(value)
135 #define MC_DC43(value) 0x02B0(value)
136 #define MC_DC44(value) 0x02C0(value)
137 #define MC_DC45(value) 0x02D0(value)
138 #define MC_DC46(value) 0x02E0(value)
139
140 #define RCU_OFFSET 0xBF203000
141 #define RCU_RST_REQ (RCU_OFFSET + 0x0010)
142 #define RCU_STS (RCU_OFFSET + 0x0014)
143
144 #define CGU_OFFSET 0xBF103000
145 #define PLL0_CFG (CGU_OFFSET + 0x0004)
146 #define PLL1_CFG (CGU_OFFSET + 0x0008)
147 #define PLL2_CFG (CGU_OFFSET + 0x000C)
148 #define CGU_SYS (CGU_OFFSET + 0x0010)
149 #define CGU_UPDATE (CGU_OFFSET + 0x0014)
150 #define IF_CLK (CGU_OFFSET + 0x0018)
151 #define CGU_SMD (CGU_OFFSET + 0x0020)
152 #define CGU_CT1SR (CGU_OFFSET + 0x0028)
153 #define CGU_CT2SR (CGU_OFFSET + 0x002C)
154 #define CGU_PCMCR (CGU_OFFSET + 0x0030)
155 #define PCI_CR_PCI (CGU_OFFSET + 0x0034)
156 #define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
157 #define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
158 #define CLK_MEASURE (CGU_OFFSET + 0x003C)
159
160 #define pll1_36MHz_CONFIG 0x9800f25f
161
162 .set noreorder
163
164
165 /*
166 * void ebu_init(void)
167 */
168 .globl ebu_init
169 .ent ebu_init
170 ebu_init:
171
172 #if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
173 defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
174 defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
175 defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
176
177 li t1, EBU_MODUL_BASE
178 #if defined(CONFIG_EBU_ADDSEL0)
179 li t2, CONFIG_EBU_ADDSEL0
180 sw t2, EBU_ADDSEL0(t1)
181 #endif
182 #if defined(CONFIG_EBU_ADDSEL1)
183 li t2, CONFIG_EBU_ADDSEL1
184 sw t2, EBU_ADDSEL1(t1)
185 #endif
186 #if defined(CONFIG_EBU_ADDSEL2)
187 li t2, CONFIG_EBU_ADDSEL2
188 sw t2, EBU_ADDSEL2(t1)
189 #endif
190 #if defined(CONFIG_EBU_ADDSEL3)
191 li t2, CONFIG_EBU_ADDSEL3
192 sw t2, EBU_ADDSEL3(t1)
193 #endif
194
195 #if defined(CONFIG_EBU_BUSCON0)
196 li t2, CONFIG_EBU_BUSCON0
197 sw t2, EBU_BUSCON0(t1)
198 #endif
199 #if defined(CONFIG_EBU_BUSCON1)
200 li t2, CONFIG_EBU_BUSCON1
201 sw t2, EBU_BUSCON1(t1)
202 #endif
203 #if defined(CONFIG_EBU_BUSCON2)
204 li t2, CONFIG_EBU_BUSCON2
205 sw t2, EBU_BUSCON2(t1)
206 #endif
207 #if defined(CONFIG_EBU_BUSCON3)
208 li t2, CONFIG_EBU_BUSCON3
209 sw t2, EBU_BUSCON3(t1)
210 #endif
211
212 #endif
213
214 j ra
215 nop
216
217 .end ebu_init
218
219
220 /*
221 * void cgu_init(long)
222 *
223 * a0 has the clock value
224 */
225 .globl cgu_init
226 .ent cgu_init
227 cgu_init:
228 li t2, CGU_SYS
229 lw t2,0(t2)
230 beq t2,a0,freq_up2date
231 nop
232 li t1, CGU_SYS
233 sw a0,0(t1)
234
235 #if defined(CONFIG_CPU_333M_RAM_166M) && defined(CONFIG_USE_PLL1)
236 li t1, PLL1_CFG
237 li a1, pll1_36MHz_CONFIG
238 sw a1, 0(t1)
239 #endif
240
241 #if defined(CONFIG_CLASS_II_DDR_PAD)
242 li t1, CGU_SMD
243 li a1, 0x200000
244 sw a1, 0(t1) // Turn on DDR PAD Class II to INC drive.
245 #endif
246
247 li t1, RCU_RST_REQ
248 li t2, 0x40000008
249 sw t2,0(t1)
250 b wait_reset
251 nop
252
253 wait_reset:
254 b wait_reset
255 nop
256
257 freq_up2date:
258 j ra
259 nop
260 .end cgu_init
261
262
263 #ifndef CONFIG_USE_DDR_RAM
264 /*
265 * void sdram_init(long)
266 *
267 * a0 has the clock value
268 */
269 .globl sdram_init
270 .ent sdram_init
271 sdram_init:
272
273 /* SDRAM Initialization
274 */
275 li t1, MC_MODUL_BASE
276
277 /* Clear Error log registers */
278 sw zero, MC_ERRCAUSE(t1)
279 sw zero, MC_ERRADDR(t1)
280
281 /* Enable SDRAM module in memory controller */
282 li t3, MC_SDRAM_ENABLE
283 lw t2, MC_CON(t1)
284 or t3, t2, t3
285 sw t3, MC_CON(t1)
286
287 li t1, MC_SDR_MODUL_BASE
288
289 /* disable the controller */
290 li t2, 0
291 sw t2, MC_CTRLENA(t1)
292
293 li t2, 0x822
294 sw t2, MC_IOGP(t1)
295
296 li t2, 0x2
297 sw t2, MC_CFGDW(t1)
298
299 /* Set CAS Latency */
300 li t2, 0x00000020
301 sw t2, MC_MRSCODE(t1)
302
303 /* Set CS0 to SDRAM parameters */
304 li t2, 0x000014d8
305 sw t2, MC_CFGPB0(t1)
306
307 /* Set SDRAM latency parameters */
308 li t2, 0x00036325; /* BC PC100 */
309 sw t2, MC_LATENCY(t1)
310
311 /* Set SDRAM refresh rate */
312 li t2, 0x00000C30
313 sw t2, MC_TREFRESH(t1)
314
315 /* Clear Power-down registers */
316 sw zero, MC_SELFRFSH(t1)
317
318 /* Finally enable the controller */
319 li t2, 1
320 sw t2, MC_CTRLENA(t1)
321
322 j ra
323 nop
324
325 .end sdram_init
326
327 #endif /* !CONFIG_USE_DDR_RAM */
328
329 #ifdef CONFIG_USE_DDR_RAM
330 /*
331 * void ddrram_init(long)
332 *
333 * a0 has the clock value
334 */
335 .globl ddrram_init
336 .ent ddrram_init
337 ddrram_init:
338
339 /* DDR-DRAM Initialization
340 */
341 li t1, MC_MODUL_BASE
342
343 /* Clear Error log registers */
344 sw zero, MC_ERRCAUSE(t1)
345 sw zero, MC_ERRADDR(t1)
346
347 /* Enable DDR module in memory controller */
348 li t3, MC_DDRRAM_ENABLE
349 lw t2, MC_CON(t1)
350 or t3, t2, t3
351 sw t3, MC_CON(t1)
352
353 li t1, MC_DDR_MODUL_BASE
354
355 /* Write configuration to DDR controller registers */
356 li t2, MC_DC0_VALUE
357 sw t2, MC_DC00(t1)
358
359 li t2, MC_DC1_VALUE
360 sw t2, MC_DC01(t1)
361
362 li t2, MC_DC2_VALUE
363 sw t2, MC_DC02(t1)
364
365 li t2, MC_DC3_VALUE
366 sw t2, MC_DC03(t1)
367
368 li t2, MC_DC4_VALUE
369 sw t2, MC_DC04(t1)
370
371 li t2, MC_DC5_VALUE
372 sw t2, MC_DC05(t1)
373
374 li t2, MC_DC6_VALUE
375 sw t2, MC_DC06(t1)
376
377 li t2, MC_DC7_VALUE
378 sw t2, MC_DC07(t1)
379
380 li t2, MC_DC8_VALUE
381 sw t2, MC_DC08(t1)
382
383 li t2, MC_DC9_VALUE
384 sw t2, MC_DC09(t1)
385
386 li t2, MC_DC10_VALUE
387 sw t2, MC_DC10(t1)
388
389 li t2, MC_DC11_VALUE
390 sw t2, MC_DC11(t1)
391
392 li t2, MC_DC12_VALUE
393 sw t2, MC_DC12(t1)
394
395 li t2, MC_DC13_VALUE
396 sw t2, MC_DC13(t1)
397
398 li t2, MC_DC14_VALUE
399 sw t2, MC_DC14(t1)
400
401 li t2, MC_DC15_VALUE
402 sw t2, MC_DC15(t1)
403
404 li t2, MC_DC16_VALUE
405 sw t2, MC_DC16(t1)
406
407 li t2, MC_DC17_VALUE
408 sw t2, MC_DC17(t1)
409
410 li t2, MC_DC18_VALUE
411 sw t2, MC_DC18(t1)
412
413 li t2, MC_DC19_VALUE
414 sw t2, MC_DC19(t1)
415
416 li t2, MC_DC20_VALUE
417 sw t2, MC_DC20(t1)
418
419 li t2, MC_DC21_VALUE
420 sw t2, MC_DC21(t1)
421
422 li t2, MC_DC22_VALUE
423 sw t2, MC_DC22(t1)
424
425 li t2, MC_DC23_VALUE
426 sw t2, MC_DC23(t1)
427
428 li t2, MC_DC24_VALUE
429 sw t2, MC_DC24(t1)
430
431 li t2, MC_DC25_VALUE
432 sw t2, MC_DC25(t1)
433
434 li t2, MC_DC26_VALUE
435 sw t2, MC_DC26(t1)
436
437 li t2, MC_DC27_VALUE
438 sw t2, MC_DC27(t1)
439
440 li t2, MC_DC28_VALUE
441 sw t2, MC_DC28(t1)
442
443 li t2, MC_DC29_VALUE
444 sw t2, MC_DC29(t1)
445
446 li t2, MC_DC30_VALUE
447 sw t2, MC_DC30(t1)
448
449 li t2, MC_DC31_VALUE
450 sw t2, MC_DC31(t1)
451
452 li t2, MC_DC32_VALUE
453 sw t2, MC_DC32(t1)
454
455 li t2, MC_DC33_VALUE
456 sw t2, MC_DC33(t1)
457
458 li t2, MC_DC34_VALUE
459 sw t2, MC_DC34(t1)
460
461 li t2, MC_DC35_VALUE
462 sw t2, MC_DC35(t1)
463
464 li t2, MC_DC36_VALUE
465 sw t2, MC_DC36(t1)
466
467 li t2, MC_DC37_VALUE
468 sw t2, MC_DC37(t1)
469
470 li t2, MC_DC38_VALUE
471 sw t2, MC_DC38(t1)
472
473 li t2, MC_DC39_VALUE
474 sw t2, MC_DC39(t1)
475
476 li t2, MC_DC40_VALUE
477 sw t2, MC_DC40(t1)
478
479 li t2, MC_DC41_VALUE
480 sw t2, MC_DC41(t1)
481
482 li t2, MC_DC42_VALUE
483 sw t2, MC_DC42(t1)
484
485 li t2, MC_DC43_VALUE
486 sw t2, MC_DC43(t1)
487
488 li t2, MC_DC44_VALUE
489 sw t2, MC_DC44(t1)
490
491 li t2, MC_DC45_VALUE
492 sw t2, MC_DC45(t1)
493
494 li t2, MC_DC46_VALUE
495 sw t2, MC_DC46(t1)
496
497 li t2, 0x00000100
498 sw t2, MC_DC03(t1)
499
500 j ra
501 nop
502
503 .end ddrram_init
504 #endif /* CONFIG_USE_DDR_RAM */
505
506 .globl lowlevel_init
507 .ent lowlevel_init
508 lowlevel_init:
509 /* EBU, CGU and SDRAM/DDR-RAM Initialization.
510 */
511 move t0, ra
512 /* We rely on the fact that non of the following ..._init() functions
513 * modify t0
514 */
515 #if defined(CONFIG_SYS_EBU_BOOT)
516 /*
517 using PPL1 value
518 */
519 li a0,0x90
520 bal cgu_init
521 nop
522 #endif /* CONFIG_SYS_EBU_BOOT */
523
524 bal ebu_init
525 nop
526
527 #ifdef CONFIG_SYS_EBU_BOOT
528 #ifndef CONFIG_SYS_RAMBOOT
529 #ifdef CONFIG_USE_DDR_RAM
530 bal ddrram_init
531 nop
532 #else
533 bal sdram_init
534 nop
535 #endif
536 #endif /* CONFIG_SYS_RAMBOOT */
537 #endif /* CONFIG_SYS_EBU_BOOT */
538
539 move ra, t0
540 j ra
541 nop
542
543 .end lowlevel_init
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