target/linux/rdc/files-2.6.30/arch/x86/mach-rdc321x/gpio.c

   1 /*
   2  *  GPIO support for RDC SoC R3210/R8610
   3  *
   4  *  Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
   5  *  Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  */
  22
  23
  24 #include <linux/spinlock.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/module.h>
  28 #include <linux/gpio.h>
  29
  30 #include <asm/rdc321x_gpio.h>
  31 #include <asm/rdc321x_defs.h>
  32
  33
  34 /* spin lock to protect our private copy of GPIO data register plus
  35    the access to PCI conf registers. */
  36 static DEFINE_SPINLOCK(gpio_lock);
  37
  38 /* copy of GPIO data registers */
  39 static u32 gpio_data_reg1;
  40 static u32 gpio_data_reg2;
  41
  42 static inline void rdc321x_conf_write(unsigned addr, u32 value)
  43 {
  44         outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
  45         outl(value, RDC3210_CFGREG_DATA);
  46 }
  47
  48 static inline void rdc321x_conf_or(unsigned addr, u32 value)
  49 {
  50         outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
  51         value |= inl(RDC3210_CFGREG_DATA);
  52         outl(value, RDC3210_CFGREG_DATA);
  53 }
  54
  55 static inline u32 rdc321x_conf_read(unsigned addr)
  56 {
  57         outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
  58
  59         return inl(RDC3210_CFGREG_DATA);
  60 }
  61
  62 /* configure pin as GPIO */
  63 static void rdc321x_configure_gpio(unsigned gpio)
  64 {
  65         unsigned long flags;
  66
  67         spin_lock_irqsave(&gpio_lock, flags);
  68         rdc321x_conf_or(gpio < 32
  69                 ? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2,
  70                 1 << (gpio & 0x1f));
  71         spin_unlock_irqrestore(&gpio_lock, flags);
  72 }
  73
  74 /* read GPIO pin */
  75 static int rdc_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
  76 {
  77         u32 reg;
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&gpio_lock, flags);
  81         reg = rdc321x_conf_read(gpio < 32
  82                 ? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2);
  83         spin_unlock_irqrestore(&gpio_lock, flags);
  84
  85         return (1 << (gpio & 0x1f)) & reg ? 1 : 0;
  86 }
  87
  88 /* set GPIO pin to value */
  89 static void rdc_gpio_set_value(struct gpio_chip *chip,
  90                                 unsigned gpio, int value)
  91 {
  92         unsigned long flags;
  93         u32 reg;
  94
  95         reg = 1 << (gpio & 0x1f);
  96         if (gpio < 32) {
  97                 spin_lock_irqsave(&gpio_lock, flags);
  98                 if (value)
  99                         gpio_data_reg1 |= reg;
 100                 else
 101                         gpio_data_reg1 &= ~reg;
 102                 rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1);
 103                 spin_unlock_irqrestore(&gpio_lock, flags);
 104         } else {
 105                 spin_lock_irqsave(&gpio_lock, flags);
 106                 if (value)
 107                         gpio_data_reg2 |= reg;
 108                 else
 109                         gpio_data_reg2 &= ~reg;
 110                 rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2);
 111                 spin_unlock_irqrestore(&gpio_lock, flags);
 112         }
 113 }
 114
 115 /* configure GPIO pin as input */
 116 static int rdc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 117 {
 118         rdc321x_configure_gpio(gpio);
 119
 120         return 0;
 121 }
 122
 123 /* configure GPIO pin as output and set value */
 124 static int rdc_gpio_direction_output(struct gpio_chip *chip,
 125                                 unsigned gpio, int value)
 126 {
 127         rdc321x_configure_gpio(gpio);
 128         gpio_set_value(gpio, value);
 129
 130         return 0;
 131 }
 132
 133 static struct gpio_chip rdc321x_gpio_chip = {
 134         .label                  = "rdc321x-gpio",
 135         .direction_input        = rdc_gpio_direction_input,
 136         .direction_output       = rdc_gpio_direction_output,
 137         .get                    = rdc_gpio_get_value,
 138         .set                    = rdc_gpio_set_value,
 139         .base                   = 0,
 140         .ngpio                  = RDC321X_MAX_GPIO,
 141 };
 142
 143 /* initially setup the 2 copies of the gpio data registers.
 144    This function is called before the platform setup code. */
 145 static int __init rdc321x_gpio_setup(void)
 146 {
 147         /* this might not be, what others (BIOS, bootloader, etc.)
 148            wrote to these registers before, but it's a good guess. Still
 149            better than just using 0xffffffff. */
 150
 151         gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
 152         gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
 153
 154         printk(KERN_INFO "rdc321x: registering %d GPIOs\n", rdc321x_gpio_chip.ngpio);
 155         return gpiochip_add(&rdc321x_gpio_chip);
 156 }
 157
 158 arch_initcall(rdc321x_gpio_setup);