disable delayed branch optimization for kernel - seems to improve stability on v1...
[openwrt.git] / package / linux / kernel-patches / 007-arch_mips_kernel_cpu-probe_c
1 --- linux-mips-cvs/arch/mips/kernel/cpu-probe.c 2005-01-31 12:59:30.000000000 +0100
2 +++ linux-broadcom/arch/mips/kernel/cpu-probe.c 2005-01-31 13:13:14.000000000 +0100
3 @@ -175,7 +175,7 @@
4
5 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
6 {
7 - switch (c->processor_id & 0xff00) {
8 + switch (c->processor_id & PRID_IMP_MASK) {
9 case PRID_IMP_R2000:
10 c->cputype = CPU_R2000;
11 c->isa_level = MIPS_CPU_ISA_I;
12 @@ -185,7 +185,7 @@
13 c->tlbsize = 64;
14 break;
15 case PRID_IMP_R3000:
16 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
17 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
18 if (cpu_has_confreg())
19 c->cputype = CPU_R3081E;
20 else
21 @@ -200,12 +200,12 @@
22 break;
23 case PRID_IMP_R4000:
24 if (read_c0_config() & CONF_SC) {
25 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
26 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
27 c->cputype = CPU_R4400PC;
28 else
29 c->cputype = CPU_R4000PC;
30 } else {
31 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
32 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
33 c->cputype = CPU_R4400SC;
34 else
35 c->cputype = CPU_R4000SC;
36 @@ -451,7 +451,7 @@
37 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
38 {
39 decode_config1(c);
40 - switch (c->processor_id & 0xff00) {
41 + switch (c->processor_id & PRID_IMP_MASK) {
42 case PRID_IMP_4KC:
43 c->cputype = CPU_4KC;
44 c->isa_level = MIPS_CPU_ISA_M32;
45 @@ -492,10 +492,10 @@
46 {
47 decode_config1(c);
48 c->options |= MIPS_CPU_PREFETCH;
49 - switch (c->processor_id & 0xff00) {
50 + switch (c->processor_id & PRID_IMP_MASK) {
51 case PRID_IMP_AU1_REV1:
52 case PRID_IMP_AU1_REV2:
53 - switch ((c->processor_id >> 24) & 0xff) {
54 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
55 case 0:
56 c->cputype = CPU_AU1000;
57 break;
58 @@ -523,10 +523,34 @@
59 }
60 }
61
62 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
63 +{
64 + decode_config1(c);
65 + c->options |= MIPS_CPU_PREFETCH;
66 + switch (c->processor_id & PRID_IMP_MASK) {
67 + case PRID_IMP_BCM4710:
68 + c->cputype = CPU_BCM4710;
69 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
70 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
71 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
72 + break;
73 + case PRID_IMP_4KC:
74 + case PRID_IMP_BCM3302:
75 + c->cputype = CPU_BCM3302;
76 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
77 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
78 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
79 + break;
80 + default:
81 + c->cputype = CPU_UNKNOWN;
82 + break;
83 + }
84 +}
85 +
86 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
87 {
88 decode_config1(c);
89 - switch (c->processor_id & 0xff00) {
90 + switch (c->processor_id & PRID_IMP_MASK) {
91 case PRID_IMP_SB1:
92 c->cputype = CPU_SB1;
93 c->isa_level = MIPS_CPU_ISA_M64;
94 @@ -548,7 +572,7 @@
95 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
96 {
97 decode_config1(c);
98 - switch (c->processor_id & 0xff00) {
99 + switch (c->processor_id & PRID_IMP_MASK) {
100 case PRID_IMP_SR71000:
101 c->cputype = CPU_SR71000;
102 c->isa_level = MIPS_CPU_ISA_M64;
103 @@ -573,7 +597,7 @@
104 c->cputype = CPU_UNKNOWN;
105
106 c->processor_id = read_c0_prid();
107 - switch (c->processor_id & 0xff0000) {
108 + switch (c->processor_id & PRID_COMP_MASK) {
109
110 case PRID_COMP_LEGACY:
111 cpu_probe_legacy(c);
112 @@ -584,6 +608,9 @@
113 case PRID_COMP_ALCHEMY:
114 cpu_probe_alchemy(c);
115 break;
116 + case PRID_COMP_BROADCOM:
117 + cpu_probe_broadcom(c);
118 + break;
119 case PRID_COMP_SIBYTE:
120 cpu_probe_sibyte(c);
121 break;
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