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[atheros] enable mtu & mac config options
[openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * ADM5120 HCD (Host Controller Driver) for USB
3 *
4 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was derived from: drivers/usb/host/ohci-hcd.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ahcd fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published
17 * by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38 #include <linux/debugfs.h>
39
40 #include <asm/io.h>
41 #include <asm/irq.h>
42 #include <asm/system.h>
43 #include <asm/unaligned.h>
44 #include <asm/byteorder.h>
45
46 #include "../core/hcd.h"
47 #include "../core/hub.h"
48
49 #define DRIVER_VERSION "0.27.0"
50 #define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
51 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
52
53 /*-------------------------------------------------------------------------*/
54
55 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
56
57 /* For initializing controller (mask in an HCFS mode too) */
58 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59
60 #define ADMHC_INTR_INIT \
61 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
62 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
63
64 /*-------------------------------------------------------------------------*/
65
66 static const char hcd_name [] = "admhc-hcd";
67
68 #define STATECHANGE_DELAY msecs_to_jiffies(300)
69
70 #include "adm5120.h"
71
72 static void admhc_dump(struct admhcd *ahcd, int verbose);
73 static int admhc_init(struct admhcd *ahcd);
74 static void admhc_stop(struct usb_hcd *hcd);
75
76 #include "adm5120-dbg.c"
77 #include "adm5120-mem.c"
78 #include "adm5120-pm.c"
79 #include "adm5120-hub.c"
80 #include "adm5120-q.c"
81
82 /*-------------------------------------------------------------------------*/
83
84 /*
85 * queue up an urb for anything except the root hub
86 */
87 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
88 gfp_t mem_flags)
89 {
90 struct admhcd *ahcd = hcd_to_admhcd(hcd);
91 struct ed *ed;
92 struct urb_priv *urb_priv;
93 unsigned int pipe = urb->pipe;
94 int td_cnt = 0;
95 unsigned long flags;
96 int ret = 0;
97
98 #ifdef ADMHC_VERBOSE_DEBUG
99 spin_lock_irqsave(&ahcd->lock, flags);
100 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
101 spin_unlock_irqrestore(&ahcd->lock, flags);
102 #endif
103
104 /* every endpoint has an ed, locate and maybe (re)initialize it */
105 ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
106 if (!ed)
107 return -ENOMEM;
108
109 /* for the private part of the URB we need the number of TDs */
110 switch (ed->type) {
111 case PIPE_CONTROL:
112 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
113 /* td_submit_urb() doesn't yet handle these */
114 return -EMSGSIZE;
115
116 /* 1 TD for setup, 1 for ACK, plus ... */
117 td_cnt = 2;
118 /* FALLTHROUGH */
119 case PIPE_BULK:
120 /* one TD for every 4096 Bytes (can be upto 8K) */
121 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
122 /* ... and for any remaining bytes ... */
123 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
124 td_cnt++;
125 /* ... and maybe a zero length packet to wrap it up */
126 if (td_cnt == 0)
127 td_cnt++;
128 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
129 && (urb->transfer_buffer_length
130 % usb_maxpacket(urb->dev, pipe,
131 usb_pipeout (pipe))) == 0)
132 td_cnt++;
133 break;
134 case PIPE_INTERRUPT:
135 /*
136 * for Interrupt IN/OUT transactions, each ED contains
137 * only 1 TD.
138 * TODO: check transfer_buffer_length?
139 */
140 td_cnt = 1;
141 break;
142 case PIPE_ISOCHRONOUS:
143 /* number of packets from URB */
144 td_cnt = urb->number_of_packets;
145 break;
146 }
147
148 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
149 if (!urb_priv)
150 return -ENOMEM;
151
152 urb_priv->ed = ed;
153
154 spin_lock_irqsave(&ahcd->lock, flags);
155 /* don't submit to a dead HC */
156 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
157 ret = -ENODEV;
158 goto fail;
159 }
160 if (!HC_IS_RUNNING(hcd->state)) {
161 ret = -ENODEV;
162 goto fail;
163 }
164
165 ret = usb_hcd_link_urb_to_ep(hcd, urb);
166 if (ret)
167 goto fail;
168
169 /* schedule the ed if needed */
170 if (ed->state == ED_IDLE) {
171 ret = ed_schedule(ahcd, ed);
172 if (ret < 0) {
173 usb_hcd_unlink_urb_from_ep(hcd, urb);
174 goto fail;
175 }
176 if (ed->type == PIPE_ISOCHRONOUS) {
177 u16 frame = admhc_frame_no(ahcd);
178
179 /* delay a few frames before the first TD */
180 frame += max_t (u16, 8, ed->interval);
181 frame &= ~(ed->interval - 1);
182 frame |= ed->branch;
183 urb->start_frame = frame;
184
185 /* yes, only URB_ISO_ASAP is supported, and
186 * urb->start_frame is never used as input.
187 */
188 }
189 } else if (ed->type == PIPE_ISOCHRONOUS)
190 urb->start_frame = ed->last_iso + ed->interval;
191
192 /* fill the TDs and link them to the ed; and
193 * enable that part of the schedule, if needed
194 * and update count of queued periodic urbs
195 */
196 urb->hcpriv = urb_priv;
197 td_submit_urb(ahcd, urb);
198
199 #ifdef ADMHC_VERBOSE_DEBUG
200 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
201 #endif
202
203 fail:
204 if (ret)
205 urb_priv_free(ahcd, urb_priv);
206
207 spin_unlock_irqrestore(&ahcd->lock, flags);
208 return ret;
209 }
210
211 /*
212 * decouple the URB from the HC queues (TDs, urb_priv);
213 * reporting is always done
214 * asynchronously, and we might be dealing with an urb that's
215 * partially transferred, or an ED with other urbs being unlinked.
216 */
217 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
218 int status)
219 {
220 struct admhcd *ahcd = hcd_to_admhcd(hcd);
221 unsigned long flags;
222 int ret;
223
224 spin_lock_irqsave(&ahcd->lock, flags);
225
226 #ifdef ADMHC_VERBOSE_DEBUG
227 urb_print(ahcd, urb, "DEQUEUE", 1, status);
228 #endif
229 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
230 if (ret) {
231 /* Do nothing */
232 ;
233 } else if (HC_IS_RUNNING(hcd->state)) {
234 struct urb_priv *urb_priv;
235
236 /* Unless an IRQ completed the unlink while it was being
237 * handed to us, flag it for unlink and giveback, and force
238 * some upcoming INTR_SF to call finish_unlinks()
239 */
240 urb_priv = urb->hcpriv;
241 if (urb_priv) {
242 if (urb_priv->ed->state == ED_OPER)
243 start_ed_unlink(ahcd, urb_priv->ed);
244 }
245 } else {
246 /*
247 * with HC dead, we won't respect hc queue pointers
248 * any more ... just clean up every urb's memory.
249 */
250 if (urb->hcpriv)
251 finish_urb(ahcd, urb, status);
252 }
253 spin_unlock_irqrestore(&ahcd->lock, flags);
254
255 return ret;
256 }
257
258 /*-------------------------------------------------------------------------*/
259
260 /* frees config/altsetting state for endpoints,
261 * including ED memory, dummy TD, and bulk/intr data toggle
262 */
263
264 static void admhc_endpoint_disable(struct usb_hcd *hcd,
265 struct usb_host_endpoint *ep)
266 {
267 struct admhcd *ahcd = hcd_to_admhcd(hcd);
268 unsigned long flags;
269 struct ed *ed = ep->hcpriv;
270 unsigned limit = 1000;
271
272 /* ASSERT: any requests/urbs are being unlinked */
273 /* ASSERT: nobody can be submitting urbs for this any more */
274
275 if (!ed)
276 return;
277
278 #ifdef ADMHC_VERBOSE_DEBUG
279 spin_lock_irqsave(&ahcd->lock, flags);
280 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
281 spin_unlock_irqrestore(&ahcd->lock, flags);
282 #endif
283
284 rescan:
285 spin_lock_irqsave(&ahcd->lock, flags);
286
287 if (!HC_IS_RUNNING(hcd->state)) {
288 sanitize:
289 ed->state = ED_IDLE;
290 finish_unlinks(ahcd, 0);
291 }
292
293 switch (ed->state) {
294 case ED_UNLINK: /* wait for hw to finish? */
295 /* major IRQ delivery trouble loses INTR_SOFI too... */
296 if (limit-- == 0) {
297 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
298 goto sanitize;
299 }
300 spin_unlock_irqrestore(&ahcd->lock, flags);
301 schedule_timeout_uninterruptible(1);
302 goto rescan;
303 case ED_IDLE: /* fully unlinked */
304 if (list_empty(&ed->td_list)) {
305 td_free (ahcd, ed->dummy);
306 ed_free (ahcd, ed);
307 break;
308 }
309 /* else FALL THROUGH */
310 default:
311 /* caller was supposed to have unlinked any requests;
312 * that's not our job. can't recover; must leak ed.
313 */
314 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
315 ed, ep->desc.bEndpointAddress, ed->state,
316 list_empty(&ed->td_list) ? "" : " (has tds)");
317 td_free(ahcd, ed->dummy);
318 break;
319 }
320
321 ep->hcpriv = NULL;
322
323 spin_unlock_irqrestore(&ahcd->lock, flags);
324 return;
325 }
326
327 static int admhc_get_frame_number(struct usb_hcd *hcd)
328 {
329 struct admhcd *ahcd = hcd_to_admhcd(hcd);
330
331 return admhc_frame_no(ahcd);
332 }
333
334 static void admhc_usb_reset(struct admhcd *ahcd)
335 {
336 #if 0
337 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
338 ahcd->hc_control &= OHCI_CTRL_RWC;
339 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
340 #else
341 /* FIXME */
342 ahcd->host_control = ADMHC_BUSS_RESET;
343 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
344 #endif
345 }
346
347 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
348 * other cases where the next software may expect clean state from the
349 * "firmware". this is bus-neutral, unlike shutdown() methods.
350 */
351 static void
352 admhc_shutdown(struct usb_hcd *hcd)
353 {
354 struct admhcd *ahcd;
355
356 ahcd = hcd_to_admhcd(hcd);
357 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
358 admhc_dma_disable(ahcd);
359 admhc_usb_reset(ahcd);
360 /* flush the writes */
361 admhc_writel_flush(ahcd);
362 }
363
364 /*-------------------------------------------------------------------------*
365 * HC functions
366 *-------------------------------------------------------------------------*/
367
368 static void admhc_eds_cleanup(struct admhcd *ahcd)
369 {
370 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
371 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
372 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
373 }
374
375 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
376 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
377 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
378 }
379
380 if (ahcd->ed_tails[PIPE_CONTROL]) {
381 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
382 ahcd->ed_tails[PIPE_CONTROL] = NULL;
383 }
384
385 if (ahcd->ed_tails[PIPE_BULK]) {
386 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
387 ahcd->ed_tails[PIPE_BULK] = NULL;
388 }
389
390 ahcd->ed_head = NULL;
391 }
392
393 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
394
395 static int admhc_eds_init(struct admhcd *ahcd)
396 {
397 struct ed *ed;
398
399 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
400 if (!ed)
401 goto err;
402
403 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
404
405 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
406 if (!ed)
407 goto err;
408
409 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
410 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
411 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
412 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
413
414 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
415 if (!ed)
416 goto err;
417
418 ahcd->ed_tails[PIPE_CONTROL] = ed;
419 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
420 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
421 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
422
423 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
424 if (!ed)
425 goto err;
426
427 ahcd->ed_tails[PIPE_BULK] = ed;
428 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
429 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
430 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
431
432 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
433
434 #ifdef ADMHC_VERBOSE_DEBUG
435 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
436 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
437 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
438 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
439 #endif
440
441 return 0;
442
443 err:
444 admhc_eds_cleanup(ahcd);
445 return -ENOMEM;
446 }
447
448 /* init memory, and kick BIOS/SMM off */
449
450 static int admhc_init(struct admhcd *ahcd)
451 {
452 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
453 int ret;
454
455 admhc_disable(ahcd);
456 ahcd->regs = hcd->regs;
457
458 /* Disable HC interrupts */
459 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
460
461 /* Read the number of ports unless overridden */
462 if (ahcd->num_ports == 0)
463 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
464
465 ret = admhc_mem_init(ahcd);
466 if (ret)
467 goto err;
468
469 /* init dummy endpoints */
470 ret = admhc_eds_init(ahcd);
471 if (ret)
472 goto err;
473
474 create_debug_files(ahcd);
475
476 return 0;
477
478 err:
479 admhc_stop(hcd);
480 return ret;
481 }
482
483 /*-------------------------------------------------------------------------*/
484
485 /* Start an OHCI controller, set the BUS operational
486 * resets USB and controller
487 * enable interrupts
488 */
489 static int admhc_run(struct admhcd *ahcd)
490 {
491 u32 temp;
492 int first = ahcd->fminterval == 0;
493 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
494
495 admhc_disable(ahcd);
496
497 /* boot firmware should have set this up (5.1.1.3.1) */
498 if (first) {
499 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
500 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
501 if (ahcd->fminterval != FI)
502 admhc_dbg(ahcd, "fminterval delta %d\n",
503 ahcd->fminterval - FI);
504 ahcd->fminterval |=
505 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
506 /* also: power/overcurrent flags in rhdesc */
507 }
508
509 #if 0 /* TODO: not applicable */
510 /* Reset USB nearly "by the book". RemoteWakeupConnected was
511 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
512 * or if bus glue did the same (e.g. for PCI add-in cards with
513 * PCI PM support).
514 */
515 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
516 && !device_may_wakeup(hcd->self.controller))
517 device_init_wakeup(hcd->self.controller, 1);
518 #endif
519
520 switch (ahcd->host_control & ADMHC_HC_BUSS) {
521 case ADMHC_BUSS_OPER:
522 temp = 0;
523 break;
524 case ADMHC_BUSS_SUSPEND:
525 /* FALLTHROUGH ? */
526 case ADMHC_BUSS_RESUME:
527 ahcd->host_control = ADMHC_BUSS_RESUME;
528 temp = 10 /* msec wait */;
529 break;
530 /* case ADMHC_BUSS_RESET: */
531 default:
532 ahcd->host_control = ADMHC_BUSS_RESET;
533 temp = 50 /* msec wait */;
534 break;
535 }
536 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
537
538 /* flush the writes */
539 admhc_writel_flush(ahcd);
540
541 msleep(temp);
542 temp = admhc_read_rhdesc(ahcd);
543 if (!(temp & ADMHC_RH_NPS)) {
544 /* power down each port */
545 for (temp = 0; temp < ahcd->num_ports; temp++)
546 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
547 }
548 /* flush those writes */
549 admhc_writel_flush(ahcd);
550
551 /* 2msec timelimit here means no irqs/preempt */
552 spin_lock_irq(&ahcd->lock);
553
554 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
555 temp = 30; /* ... allow extra time */
556 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
557 if (--temp == 0) {
558 spin_unlock_irq(&ahcd->lock);
559 admhc_err(ahcd, "USB HC reset timed out!\n");
560 return -1;
561 }
562 udelay(1);
563 }
564
565 /* enable HOST mode, before access any host specific register */
566 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
567
568 /* Tell the controller where the descriptor list is */
569 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
570
571 periodic_reinit(ahcd);
572
573 /* use rhsc irqs after khubd is fully initialized */
574 hcd->poll_rh = 1;
575 hcd->uses_new_polling = 1;
576
577 #if 0
578 /* wake on ConnectStatusChange, matching external hubs */
579 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
580 #else
581 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
582 #endif
583
584 /* Choose the interrupts we care about now, others later on demand */
585 admhc_intr_ack(ahcd, ~0);
586 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
587
588 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
589
590 /* flush those writes */
591 admhc_writel_flush(ahcd);
592
593 /* start controller operations */
594 ahcd->host_control = ADMHC_BUSS_OPER;
595 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
596
597 temp = 20;
598 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
599 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
600 if (--temp == 0) {
601 spin_unlock_irq(&ahcd->lock);
602 admhc_err(ahcd, "unable to setup operational mode!\n");
603 return -1;
604 }
605 mdelay(1);
606 }
607
608 hcd->state = HC_STATE_RUNNING;
609
610 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
611
612 #if 0
613 /* FIXME: enabling DMA is always failed here for an unknown reason */
614 admhc_dma_enable(ahcd);
615
616 temp = 200;
617 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
618 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
619 if (--temp == 0) {
620 spin_unlock_irq(&ahcd->lock);
621 admhc_err(ahcd, "unable to enable DMA!\n");
622 admhc_dump(ahcd, 1);
623 return -1;
624 }
625 mdelay(1);
626 }
627
628 #endif
629
630 spin_unlock_irq(&ahcd->lock);
631
632 mdelay(ADMHC_POTPGT);
633
634 return 0;
635 }
636
637 /*-------------------------------------------------------------------------*/
638
639 /* an interrupt happens */
640
641 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
642 {
643 struct admhcd *ahcd = hcd_to_admhcd(hcd);
644 struct admhcd_regs __iomem *regs = ahcd->regs;
645 u32 ints;
646
647 ints = admhc_readl(ahcd, &regs->int_status);
648 if ((ints & ADMHC_INTR_INTA) == 0) {
649 /* no unmasked interrupt status is set */
650 return IRQ_NONE;
651 }
652
653 ints &= admhc_readl(ahcd, &regs->int_enable);
654
655 if (ints & ADMHC_INTR_FATI) {
656 /* e.g. due to PCI Master/Target Abort */
657 admhc_disable(ahcd);
658 admhc_err(ahcd, "Fatal Error, controller disabled\n");
659 admhc_dump(ahcd, 1);
660 admhc_usb_reset(ahcd);
661 }
662
663 if (ints & ADMHC_INTR_BABI) {
664 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
665 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
666 admhc_err(ahcd, "Babble Detected\n");
667 }
668
669 if (ints & ADMHC_INTR_INSM) {
670 admhc_vdbg(ahcd, "Root Hub Status Change\n");
671 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
672 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
673
674 /* NOTE: Vendors didn't always make the same implementation
675 * choices for RHSC. Many followed the spec; RHSC triggers
676 * on an edge, like setting and maybe clearing a port status
677 * change bit. With others it's level-triggered, active
678 * until khubd clears all the port status change bits. We'll
679 * always disable it here and rely on polling until khubd
680 * re-enables it.
681 */
682 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
683 usb_hcd_poll_rh_status(hcd);
684 } else if (ints & ADMHC_INTR_RESI) {
685 /* For connect and disconnect events, we expect the controller
686 * to turn on RHSC along with RD. But for remote wakeup events
687 * this might not happen.
688 */
689 admhc_vdbg(ahcd, "Resume Detect\n");
690 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
691 hcd->poll_rh = 1;
692 if (ahcd->autostop) {
693 spin_lock(&ahcd->lock);
694 admhc_rh_resume(ahcd);
695 spin_unlock(&ahcd->lock);
696 } else
697 usb_hcd_resume_root_hub(hcd);
698 }
699
700 if (ints & ADMHC_INTR_TDC) {
701 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
702 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
703 if (HC_IS_RUNNING(hcd->state))
704 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
705 spin_lock(&ahcd->lock);
706 admhc_td_complete(ahcd);
707 spin_unlock(&ahcd->lock);
708 if (HC_IS_RUNNING(hcd->state))
709 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
710 }
711
712 if (ints & ADMHC_INTR_SO) {
713 /* could track INTR_SO to reduce available PCI/... bandwidth */
714 admhc_vdbg(ahcd, "Schedule Overrun\n");
715 }
716
717 #if 1
718 spin_lock(&ahcd->lock);
719 if (ahcd->ed_rm_list)
720 finish_unlinks(ahcd, admhc_frame_no(ahcd));
721
722 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
723 && HC_IS_RUNNING(hcd->state))
724 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
725 spin_unlock(&ahcd->lock);
726 #else
727 if (ints & ADMHC_INTR_SOFI) {
728 admhc_vdbg(ahcd, "Start Of Frame\n");
729 spin_lock(&ahcd->lock);
730
731 /* handle any pending ED removes */
732 finish_unlinks(ahcd, admhc_frameno(ahcd));
733
734 /* leaving INTR_SOFI enabled when there's still unlinking
735 * to be done in the (next frame).
736 */
737 if ((ahcd->ed_rm_list == NULL) ||
738 HC_IS_RUNNING(hcd->state) == 0)
739 /*
740 * disable INTR_SOFI if there are no unlinking to be
741 * done (in the next frame)
742 */
743 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
744
745 spin_unlock(&ahcd->lock);
746 }
747 #endif
748
749 if (HC_IS_RUNNING(hcd->state)) {
750 admhc_intr_ack(ahcd, ints);
751 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
752 admhc_writel_flush(ahcd);
753 }
754
755 return IRQ_HANDLED;
756 }
757
758 /*-------------------------------------------------------------------------*/
759
760 static void admhc_stop(struct usb_hcd *hcd)
761 {
762 struct admhcd *ahcd = hcd_to_admhcd(hcd);
763
764 admhc_dump(ahcd, 1);
765
766 flush_scheduled_work();
767
768 admhc_usb_reset(ahcd);
769 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
770
771 free_irq(hcd->irq, hcd);
772 hcd->irq = -1;
773
774 remove_debug_files(ahcd);
775 admhc_eds_cleanup(ahcd);
776 admhc_mem_cleanup(ahcd);
777 }
778
779 /*-------------------------------------------------------------------------*/
780
781 #ifdef CONFIG_ADM5120
782 #include "adm5120-drv.c"
783 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
784 #endif
785
786 #if !defined(PLATFORM_DRIVER)
787 #error "missing bus glue for admhc-hcd"
788 #endif
789
790 #define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
791
792 static int __init admhc_hcd_mod_init(void)
793 {
794 int ret = 0;
795
796 if (usb_disabled())
797 return -ENODEV;
798
799 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
800 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
801 sizeof (struct ed), sizeof (struct td));
802
803 #ifdef DEBUG
804 admhc_debug_root = debugfs_create_dir("admhc", NULL);
805 if (!admhc_debug_root) {
806 ret = -ENOENT;
807 goto error_debug;
808 }
809 #endif
810
811 #ifdef PLATFORM_DRIVER
812 ret = platform_driver_register(&PLATFORM_DRIVER);
813 if (ret < 0)
814 goto error_platform;
815 #endif
816
817 return ret;
818
819 #ifdef PLATFORM_DRIVER
820 platform_driver_unregister(&PLATFORM_DRIVER);
821 error_platform:
822 #endif
823
824 #ifdef DEBUG
825 debugfs_remove(admhc_debug_root);
826 admhc_debug_root = NULL;
827 error_debug:
828 #endif
829 return ret;
830 }
831 module_init(admhc_hcd_mod_init);
832
833 static void __exit admhc_hcd_mod_exit(void)
834 {
835 platform_driver_unregister(&PLATFORM_DRIVER);
836 #ifdef DEBUG
837 debugfs_remove(admhc_debug_root);
838 #endif
839 }
840 module_exit(admhc_hcd_mod_exit);
841
842 MODULE_AUTHOR(DRIVER_AUTHOR);
843 MODULE_DESCRIPTION(DRIVER_INFO);
844 MODULE_VERSION(DRIVER_VERSION);
845 MODULE_LICENSE("GPL v2");
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