target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 /*
   2  *  Ralink RT288x SoC PCI register definitions
   3  *
   4  *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
   5  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/io.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/mach-ralink/rt288x.h>
  20 #include <asm/mach-ralink/rt288x_regs.h>
  21
  22 #define RT2880_PCI_MEM_BASE     0x20000000
  23 #define RT2880_PCI_MEM_SIZE     0x10000000
  24 #define RT2880_PCI_IO_BASE      0x00460000
  25 #define RT2880_PCI_IO_SIZE      0x00010000
  26
  27 #define RT2880_PCI_REG_PCICFG_ADDR      0x00
  28 #define RT2880_PCI_REG_PCIMSK_ADDR      0x0c
  29 #define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
  30 #define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
  31 #define RT2880_PCI_REG_CONFIG_ADDR      0x20
  32 #define RT2880_PCI_REG_CONFIG_DATA      0x24
  33 #define RT2880_PCI_REG_MEMBASE          0x28
  34 #define RT2880_PCI_REG_IOBASE           0x2c
  35 #define RT2880_PCI_REG_ID               0x30
  36 #define RT2880_PCI_REG_CLASS            0x34
  37 #define RT2880_PCI_REG_SUBID            0x38
  38 #define RT2880_PCI_REG_ARBCTL           0x80
  39
  40 static void __iomem *rt2880_pci_base;
  41 static DEFINE_SPINLOCK(rt2880_pci_lock);
  42
  43 static u32 rt2880_pci_reg_read(u32 reg)
  44 {
  45         return readl(rt2880_pci_base + reg);
  46 }
  47
  48 static void rt2880_pci_reg_write(u32 val, u32 reg)
  49 {
  50         writel(val, rt2880_pci_base + reg);
  51 }
  52
  53 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  54                                          unsigned int func, unsigned int where)
  55 {
  56         return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  57                 0x80000000);
  58 }
  59
  60 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  61                                   int where, int size, u32 *val)
  62 {
  63         unsigned long flags;
  64         u32 address;
  65         u32 data;
  66
  67         address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  68                                          PCI_FUNC(devfn), where);
  69
  70         spin_lock_irqsave(&rt2880_pci_lock, flags);
  71         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  72         data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  73         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
  74
  75         switch (size) {
  76         case 1:
  77                 *val = (data >> ((where & 3) << 3)) & 0xff;
  78                 break;
  79         case 2:
  80                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  81                 break;
  82         case 4:
  83                 *val = data;
  84                 break;
  85         }
  86
  87         return PCIBIOS_SUCCESSFUL;
  88 }
  89
  90 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  91                                    int where, int size, u32 val)
  92 {
  93         unsigned long flags;
  94         u32 address;
  95         u32 data;
  96
  97         address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  98                                          PCI_FUNC(devfn), where);
  99
 100         spin_lock_irqsave(&rt2880_pci_lock, flags);
 101         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 102         data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 103
 104         switch (size) {
 105         case 1:
 106                 data = (data & ~(0xff << ((where & 3) << 3))) |
 107                        (val << ((where & 3) << 3));
 108                 break;
 109         case 2:
 110                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 111                        (val << ((where & 3) << 3));
 112                 break;
 113         case 4:
 114                 data = val;
 115                 break;
 116         }
 117
 118         rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
 119         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 120
 121         return PCIBIOS_SUCCESSFUL;
 122 }
 123
 124 static struct pci_ops rt2880_pci_ops = {
 125         .read   = rt2880_pci_config_read,
 126         .write  = rt2880_pci_config_write,
 127 };
 128
 129 static struct resource rt2880_pci_mem_resource = {
 130         .name   = "PCI MEM space",
 131         .start  = RT2880_PCI_MEM_BASE,
 132         .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
 133         .flags  = IORESOURCE_MEM,
 134 };
 135
 136 static struct resource rt2880_pci_io_resource = {
 137         .name   = "PCI IO space",
 138         .start  = RT2880_PCI_IO_BASE,
 139         .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
 140         .flags  = IORESOURCE_IO,
 141 };
 142
 143 static struct pci_controller rt2880_pci_controller = {
 144         .pci_ops        = &rt2880_pci_ops,
 145         .mem_resource   = &rt2880_pci_mem_resource,
 146         .io_resource    = &rt2880_pci_io_resource,
 147 };
 148
 149 static inline u32 rt2880_pci_read_u32(unsigned long reg)
 150 {
 151         unsigned long flags;
 152         u32 address;
 153         u32 ret;
 154
 155         address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 156
 157         spin_lock_irqsave(&rt2880_pci_lock, flags);
 158         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 159         ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 160         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 161
 162         return ret;
 163 }
 164
 165 static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
 166 {
 167         unsigned long flags;
 168         u32 address;
 169
 170         address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 171
 172         spin_lock_irqsave(&rt2880_pci_lock, flags);
 173         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 174         rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 175         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 176 }
 177
 178 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 179 {
 180         u16 cmd;
 181         int irq = -1;
 182
 183         if (dev->bus->number != 0)
 184                 return irq;
 185
 186         switch (PCI_SLOT(dev->devfn)) {
 187         case 0x00:
 188                 rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 189                 (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 190                 break;
 191         case 0x11:
 192                 irq = RT288X_CPU_IRQ_PCI;
 193                 break;
 194         default:
 195                 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 196                        __FILE__, __func__, __LINE__);
 197                 BUG();
 198                 break;
 199         }
 200
 201         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 202         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 203         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 204         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 205                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 206                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 207         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 208         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 209                               dev->irq);
 210         return irq;
 211 }
 212
 213 int __init rt288x_register_pci(void)
 214 {
 215         void __iomem *io_map_base;
 216         int i;
 217
 218         rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 219
 220         io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
 221         rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
 222         set_io_port_base((unsigned long) io_map_base);
 223
 224         ioport_resource.start = RT2880_PCI_IO_BASE;
 225         ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
 226
 227         rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 228         for(i = 0; i < 0xfffff; i++) {}
 229
 230         rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 231         rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 232         rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
 233         rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
 234         rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 235         rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 236         rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 237         rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 238         rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 239
 240         rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 241         (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 242
 243         register_pci_controller(&rt2880_pci_controller);
 244         return 0;
 245 }
 246
 247 int pcibios_plat_dev_init(struct pci_dev *dev)
 248 {
 249         return 0;
 250 }