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[openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include "ar8216.h"
36
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
41
42 struct ar8216_priv;
43
44 #define AR8XXX_CAP_GIGE BIT(0)
45
46 struct ar8xxx_chip {
47 unsigned long caps;
48
49 int (*hw_init)(struct ar8216_priv *priv);
50 void (*init_globals)(struct ar8216_priv *priv);
51 void (*init_port)(struct ar8216_priv *priv, int port);
52 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
53 u32 ingress, u32 members, u32 pvid);
54 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
55 int (*atu_flush)(struct ar8216_priv *priv);
56 void (*vtu_flush)(struct ar8216_priv *priv);
57 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
58 };
59
60 struct ar8216_priv {
61 struct switch_dev dev;
62 struct phy_device *phy;
63 u32 (*read)(struct ar8216_priv *priv, int reg);
64 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
65 const struct net_device_ops *ndo_old;
66 struct net_device_ops ndo;
67 struct mutex reg_mutex;
68 int chip_type;
69 const struct ar8xxx_chip *chip;
70 bool initialized;
71 bool port4_phy;
72 char buf[80];
73
74 bool init;
75 bool mii_lo_first;
76
77 /* all fields below are cleared on reset */
78 bool vlan;
79 u16 vlan_id[AR8X16_MAX_VLANS];
80 u8 vlan_table[AR8X16_MAX_VLANS];
81 u8 vlan_tagged;
82 u16 pvid[AR8X16_MAX_PORTS];
83 };
84
85 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
86
87 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
88 {
89 return priv->chip->caps & AR8XXX_CAP_GIGE;
90 }
91
92 static inline void
93 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
94 {
95 regaddr >>= 1;
96 *r1 = regaddr & 0x1e;
97
98 regaddr >>= 5;
99 *r2 = regaddr & 0x7;
100
101 regaddr >>= 3;
102 *page = regaddr & 0x1ff;
103 }
104
105 static u32
106 ar8216_mii_read(struct ar8216_priv *priv, int reg)
107 {
108 struct phy_device *phy = priv->phy;
109 struct mii_bus *bus = phy->bus;
110 u16 r1, r2, page;
111 u16 lo, hi;
112
113 split_addr((u32) reg, &r1, &r2, &page);
114
115 mutex_lock(&bus->mdio_lock);
116
117 bus->write(bus, 0x18, 0, page);
118 usleep_range(1000, 2000); /* wait for the page switch to propagate */
119 lo = bus->read(bus, 0x10 | r2, r1);
120 hi = bus->read(bus, 0x10 | r2, r1 + 1);
121
122 mutex_unlock(&bus->mdio_lock);
123
124 return (hi << 16) | lo;
125 }
126
127 static void
128 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
129 {
130 struct phy_device *phy = priv->phy;
131 struct mii_bus *bus = phy->bus;
132 u16 r1, r2, r3;
133 u16 lo, hi;
134
135 split_addr((u32) reg, &r1, &r2, &r3);
136 lo = val & 0xffff;
137 hi = (u16) (val >> 16);
138
139 mutex_lock(&bus->mdio_lock);
140
141 bus->write(bus, 0x18, 0, r3);
142 usleep_range(1000, 2000); /* wait for the page switch to propagate */
143 if (priv->mii_lo_first) {
144 bus->write(bus, 0x10 | r2, r1, lo);
145 bus->write(bus, 0x10 | r2, r1 + 1, hi);
146 } else {
147 bus->write(bus, 0x10 | r2, r1 + 1, hi);
148 bus->write(bus, 0x10 | r2, r1, lo);
149 }
150
151 mutex_unlock(&bus->mdio_lock);
152 }
153
154 static void
155 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
156 u16 dbg_addr, u16 dbg_data)
157 {
158 struct mii_bus *bus = priv->phy->bus;
159
160 mutex_lock(&bus->mdio_lock);
161 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
162 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
163 mutex_unlock(&bus->mdio_lock);
164 }
165
166 static u32
167 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
168 {
169 u32 v;
170
171 lockdep_assert_held(&priv->reg_mutex);
172
173 v = priv->read(priv, reg);
174 v &= ~mask;
175 v |= val;
176 priv->write(priv, reg, v);
177
178 return v;
179 }
180
181 static void
182 ar8216_read_port_link(struct ar8216_priv *priv, int port,
183 struct switch_port_link *link)
184 {
185 u32 status;
186 u32 speed;
187
188 memset(link, '\0', sizeof(*link));
189
190 status = priv->chip->read_port_status(priv, port);
191
192 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
193 if (link->aneg) {
194 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
195 if (!link->link)
196 return;
197 } else {
198 link->link = true;
199 }
200
201 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
202 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
203 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
204
205 speed = (status & AR8216_PORT_STATUS_SPEED) >>
206 AR8216_PORT_STATUS_SPEED_S;
207
208 switch (speed) {
209 case AR8216_PORT_SPEED_10M:
210 link->speed = SWITCH_PORT_SPEED_10;
211 break;
212 case AR8216_PORT_SPEED_100M:
213 link->speed = SWITCH_PORT_SPEED_100;
214 break;
215 case AR8216_PORT_SPEED_1000M:
216 link->speed = SWITCH_PORT_SPEED_1000;
217 break;
218 default:
219 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
220 break;
221 }
222 }
223
224 static int
225 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
226 {
227 struct ar8216_priv *priv = dev->phy_ptr;
228 unsigned char *buf;
229
230 if (unlikely(!priv))
231 goto error;
232
233 if (!priv->vlan)
234 goto send;
235
236 if (unlikely(skb_headroom(skb) < 2)) {
237 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
238 goto error;
239 }
240
241 buf = skb_push(skb, 2);
242 buf[0] = 0x10;
243 buf[1] = 0x80;
244
245 send:
246 return priv->ndo_old->ndo_start_xmit(skb, dev);
247
248 error:
249 dev_kfree_skb_any(skb);
250 return 0;
251 }
252
253 static int
254 ar8216_mangle_rx(struct sk_buff *skb, int napi)
255 {
256 struct ar8216_priv *priv;
257 struct net_device *dev;
258 unsigned char *buf;
259 int port, vlan;
260
261 dev = skb->dev;
262 if (!dev)
263 goto error;
264
265 priv = dev->phy_ptr;
266 if (!priv)
267 goto error;
268
269 /* don't strip the header if vlan mode is disabled */
270 if (!priv->vlan)
271 goto recv;
272
273 /* strip header, get vlan id */
274 buf = skb->data;
275 skb_pull(skb, 2);
276
277 /* check for vlan header presence */
278 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
279 goto recv;
280
281 port = buf[0] & 0xf;
282
283 /* no need to fix up packets coming from a tagged source */
284 if (priv->vlan_tagged & (1 << port))
285 goto recv;
286
287 /* lookup port vid from local table, the switch passes an invalid vlan id */
288 vlan = priv->vlan_id[priv->pvid[port]];
289
290 buf[14 + 2] &= 0xf0;
291 buf[14 + 2] |= vlan >> 8;
292 buf[15 + 2] = vlan & 0xff;
293
294 recv:
295 skb->protocol = eth_type_trans(skb, skb->dev);
296
297 if (napi)
298 return netif_receive_skb(skb);
299 else
300 return netif_rx(skb);
301
302 error:
303 /* no vlan? eat the packet! */
304 dev_kfree_skb_any(skb);
305 return NET_RX_DROP;
306 }
307
308 static int
309 ar8216_netif_rx(struct sk_buff *skb)
310 {
311 return ar8216_mangle_rx(skb, 0);
312 }
313
314 static int
315 ar8216_netif_receive_skb(struct sk_buff *skb)
316 {
317 return ar8216_mangle_rx(skb, 1);
318 }
319
320 static int
321 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
322 {
323 int timeout = 20;
324 u32 t = 0;
325
326 while (1) {
327 t = priv->read(priv, reg);
328 if ((t & mask) == val)
329 return 0;
330
331 if (timeout-- <= 0)
332 break;
333
334 udelay(10);
335 }
336
337 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
338 (unsigned int) reg, t, mask, val);
339 return -ETIMEDOUT;
340 }
341
342 static void
343 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
344 {
345 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
346 return;
347 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
348 val &= AR8216_VTUDATA_MEMBER;
349 val |= AR8216_VTUDATA_VALID;
350 priv->write(priv, AR8216_REG_VTU_DATA, val);
351 }
352 op |= AR8216_VTU_ACTIVE;
353 priv->write(priv, AR8216_REG_VTU, op);
354 }
355
356 static void
357 ar8216_vtu_flush(struct ar8216_priv *priv)
358 {
359 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
360 }
361
362 static void
363 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
364 {
365 u32 op;
366
367 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
368 ar8216_vtu_op(priv, op, port_mask);
369 }
370
371 static int
372 ar8216_atu_flush(struct ar8216_priv *priv)
373 {
374 int ret;
375
376 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
377 if (!ret)
378 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
379
380 return ret;
381 }
382
383 static u32
384 ar8216_read_port_status(struct ar8216_priv *priv, int port)
385 {
386 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
387 }
388
389 static void
390 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
391 u32 members, u32 pvid)
392 {
393 u32 header;
394
395 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
396 header = AR8216_PORT_CTRL_HEADER;
397 else
398 header = 0;
399
400 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
401 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
402 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
403 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
404 AR8216_PORT_CTRL_LEARN | header |
405 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
406 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
407
408 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
409 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
410 AR8216_PORT_VLAN_DEFAULT_ID,
411 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
412 (ingress << AR8216_PORT_VLAN_MODE_S) |
413 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
414 }
415
416 static int
417 ar8216_hw_init(struct ar8216_priv *priv)
418 {
419 return 0;
420 }
421
422 static void
423 ar8216_init_globals(struct ar8216_priv *priv)
424 {
425 /* standard atheros magic */
426 priv->write(priv, 0x38, 0xc000050e);
427
428 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
429 AR8216_GCTRL_MTU, 1518 + 8 + 2);
430 }
431
432 static void
433 ar8216_init_port(struct ar8216_priv *priv, int port)
434 {
435 /* Enable port learning and tx */
436 priv->write(priv, AR8216_REG_PORT_CTRL(port),
437 AR8216_PORT_CTRL_LEARN |
438 (4 << AR8216_PORT_CTRL_STATE_S));
439
440 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
441
442 if (port == AR8216_PORT_CPU) {
443 priv->write(priv, AR8216_REG_PORT_STATUS(port),
444 AR8216_PORT_STATUS_LINK_UP |
445 (ar8xxx_has_gige(priv) ?
446 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
447 AR8216_PORT_STATUS_TXMAC |
448 AR8216_PORT_STATUS_RXMAC |
449 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
450 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
451 AR8216_PORT_STATUS_DUPLEX);
452 } else {
453 priv->write(priv, AR8216_REG_PORT_STATUS(port),
454 AR8216_PORT_STATUS_LINK_AUTO);
455 }
456 }
457
458 static const struct ar8xxx_chip ar8216_chip = {
459 .hw_init = ar8216_hw_init,
460 .init_globals = ar8216_init_globals,
461 .init_port = ar8216_init_port,
462 .setup_port = ar8216_setup_port,
463 .read_port_status = ar8216_read_port_status,
464 .atu_flush = ar8216_atu_flush,
465 .vtu_flush = ar8216_vtu_flush,
466 .vtu_load_vlan = ar8216_vtu_load_vlan,
467 };
468
469 static void
470 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
471 u32 members, u32 pvid)
472 {
473 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
474 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
475 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
476 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
477 AR8216_PORT_CTRL_LEARN |
478 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
479 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
480
481 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
482 AR8236_PORT_VLAN_DEFAULT_ID,
483 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
484
485 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
486 AR8236_PORT_VLAN2_VLAN_MODE |
487 AR8236_PORT_VLAN2_MEMBER,
488 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
489 (members << AR8236_PORT_VLAN2_MEMBER_S));
490 }
491
492 static int
493 ar8236_hw_init(struct ar8216_priv *priv)
494 {
495 int i;
496 struct mii_bus *bus;
497
498 if (priv->initialized)
499 return 0;
500
501 /* Initialize the PHYs */
502 bus = priv->phy->bus;
503 for (i = 0; i < 5; i++) {
504 mdiobus_write(bus, i, MII_ADVERTISE,
505 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
506 ADVERTISE_PAUSE_ASYM);
507 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
508 }
509 msleep(1000);
510
511 priv->initialized = true;
512 return 0;
513 }
514
515 static void
516 ar8236_init_globals(struct ar8216_priv *priv)
517 {
518 /* enable jumbo frames */
519 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
520 AR8316_GCTRL_MTU, 9018 + 8 + 2);
521 }
522
523 static const struct ar8xxx_chip ar8236_chip = {
524 .hw_init = ar8236_hw_init,
525 .init_globals = ar8236_init_globals,
526 .init_port = ar8216_init_port,
527 .setup_port = ar8236_setup_port,
528 .read_port_status = ar8216_read_port_status,
529 .atu_flush = ar8216_atu_flush,
530 .vtu_flush = ar8216_vtu_flush,
531 .vtu_load_vlan = ar8216_vtu_load_vlan,
532 };
533
534 static int
535 ar8316_hw_init(struct ar8216_priv *priv)
536 {
537 int i;
538 u32 val, newval;
539 struct mii_bus *bus;
540
541 val = priv->read(priv, 0x8);
542
543 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
544 if (priv->port4_phy) {
545 /* value taken from Ubiquiti RouterStation Pro */
546 newval = 0x81461bea;
547 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
548 } else {
549 newval = 0x01261be2;
550 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
551 }
552 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
553 /* value taken from AVM Fritz!Box 7390 sources */
554 newval = 0x010e5b71;
555 } else {
556 /* no known value for phy interface */
557 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
558 priv->phy->interface);
559 return -EINVAL;
560 }
561
562 if (val == newval)
563 goto out;
564
565 priv->write(priv, 0x8, newval);
566
567 /* Initialize the ports */
568 bus = priv->phy->bus;
569 for (i = 0; i < 5; i++) {
570 if ((i == 4) && priv->port4_phy &&
571 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
572 /* work around for phy4 rgmii mode */
573 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
574 /* rx delay */
575 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
576 /* tx delay */
577 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
578 msleep(1000);
579 }
580
581 /* initialize the port itself */
582 mdiobus_write(bus, i, MII_ADVERTISE,
583 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
584 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
585 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
586 msleep(1000);
587 }
588
589 out:
590 priv->initialized = true;
591 return 0;
592 }
593
594 static void
595 ar8316_init_globals(struct ar8216_priv *priv)
596 {
597 /* standard atheros magic */
598 priv->write(priv, 0x38, 0xc000050e);
599
600 /* enable cpu port to receive multicast and broadcast frames */
601 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
602
603 /* enable jumbo frames */
604 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
605 AR8316_GCTRL_MTU, 9018 + 8 + 2);
606 }
607
608 static const struct ar8xxx_chip ar8316_chip = {
609 .caps = AR8XXX_CAP_GIGE,
610 .hw_init = ar8316_hw_init,
611 .init_globals = ar8316_init_globals,
612 .init_port = ar8216_init_port,
613 .setup_port = ar8216_setup_port,
614 .read_port_status = ar8216_read_port_status,
615 .atu_flush = ar8216_atu_flush,
616 .vtu_flush = ar8216_vtu_flush,
617 .vtu_load_vlan = ar8216_vtu_load_vlan,
618 };
619
620 static u32
621 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
622 {
623 u32 t;
624
625 if (!cfg)
626 return 0;
627
628 t = 0;
629 switch (cfg->mode) {
630 case AR8327_PAD_NC:
631 break;
632
633 case AR8327_PAD_MAC2MAC_MII:
634 t = AR8327_PAD_MAC_MII_EN;
635 if (cfg->rxclk_sel)
636 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
637 if (cfg->txclk_sel)
638 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
639 break;
640
641 case AR8327_PAD_MAC2MAC_GMII:
642 t = AR8327_PAD_MAC_GMII_EN;
643 if (cfg->rxclk_sel)
644 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
645 if (cfg->txclk_sel)
646 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
647 break;
648
649 case AR8327_PAD_MAC_SGMII:
650 t = AR8327_PAD_SGMII_EN;
651 break;
652
653 case AR8327_PAD_MAC2PHY_MII:
654 t = AR8327_PAD_PHY_MII_EN;
655 if (cfg->rxclk_sel)
656 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
657 if (cfg->txclk_sel)
658 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
659 break;
660
661 case AR8327_PAD_MAC2PHY_GMII:
662 t = AR8327_PAD_PHY_GMII_EN;
663 if (cfg->pipe_rxclk_sel)
664 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
665 if (cfg->rxclk_sel)
666 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
667 if (cfg->txclk_sel)
668 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
669 break;
670
671 case AR8327_PAD_MAC_RGMII:
672 t = AR8327_PAD_RGMII_EN;
673 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
674 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
675 if (cfg->rxclk_delay_en)
676 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
677 if (cfg->txclk_delay_en)
678 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
679 break;
680
681 case AR8327_PAD_PHY_GMII:
682 t = AR8327_PAD_PHYX_GMII_EN;
683 break;
684
685 case AR8327_PAD_PHY_RGMII:
686 t = AR8327_PAD_PHYX_RGMII_EN;
687 break;
688
689 case AR8327_PAD_PHY_MII:
690 t = AR8327_PAD_PHYX_MII_EN;
691 break;
692 }
693
694 return t;
695 }
696
697 static int
698 ar8327_hw_init(struct ar8216_priv *priv)
699 {
700 struct ar8327_platform_data *pdata;
701 u32 t;
702 int i;
703
704 pdata = priv->phy->dev.platform_data;
705 if (!pdata)
706 return -EINVAL;
707
708 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
709 priv->write(priv, AR8327_REG_PAD0_MODE, t);
710 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
711 priv->write(priv, AR8327_REG_PAD5_MODE, t);
712 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
713 priv->write(priv, AR8327_REG_PAD6_MODE, t);
714
715 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
716
717 /* fixup PHYs */
718 for (i = 0; i < AR8327_NUM_PHYS; i++) {
719 /* For 100M waveform */
720 ar8216_phy_dbg_write(priv, i, 0, 0x02ea);
721
722 /* Turn on Gigabit clock */
723 ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0);
724 }
725
726 return 0;
727 }
728
729 static void
730 ar8327_init_globals(struct ar8216_priv *priv)
731 {
732 u32 t;
733
734 /* enable CPU port and disable mirror port */
735 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
736 AR8327_FWD_CTRL0_MIRROR_PORT;
737 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
738
739 /* forward multicast and broadcast frames to CPU */
740 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
741 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
742 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
743
744 /* setup MTU */
745 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
746 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
747 }
748
749 static void
750 ar8327_init_cpuport(struct ar8216_priv *priv)
751 {
752 struct ar8327_platform_data *pdata;
753 struct ar8327_port_cfg *cfg;
754 u32 t;
755
756 pdata = priv->phy->dev.platform_data;
757 if (!pdata)
758 return;
759
760 cfg = &pdata->cpuport_cfg;
761 if (!cfg->force_link) {
762 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
763 AR8216_PORT_STATUS_LINK_AUTO);
764 return;
765 }
766
767 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
768 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
769 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
770 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
771 switch (cfg->speed) {
772 case AR8327_PORT_SPEED_10:
773 t |= AR8216_PORT_SPEED_10M;
774 break;
775 case AR8327_PORT_SPEED_100:
776 t |= AR8216_PORT_SPEED_100M;
777 break;
778 case AR8327_PORT_SPEED_1000:
779 t |= AR8216_PORT_SPEED_1000M;
780 break;
781 }
782
783 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
784 }
785
786 static void
787 ar8327_init_port(struct ar8216_priv *priv, int port)
788 {
789 u32 t;
790
791 if (port == AR8216_PORT_CPU) {
792 ar8327_init_cpuport(priv);
793 } else {
794 t = AR8216_PORT_STATUS_LINK_AUTO;
795 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
796 }
797
798 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
799
800 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
801
802 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
803 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
804
805 t = AR8327_PORT_LOOKUP_LEARN;
806 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
807 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
808 }
809
810 static u32
811 ar8327_read_port_status(struct ar8216_priv *priv, int port)
812 {
813 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
814 }
815
816 static int
817 ar8327_atu_flush(struct ar8216_priv *priv)
818 {
819 int ret;
820
821 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
822 AR8327_ATU_FUNC_BUSY, 0);
823 if (!ret)
824 priv->write(priv, AR8327_REG_ATU_FUNC,
825 AR8327_ATU_FUNC_OP_FLUSH);
826
827 return ret;
828 }
829
830 static void
831 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
832 {
833 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
834 AR8327_VTU_FUNC1_BUSY, 0))
835 return;
836
837 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
838 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
839
840 op |= AR8327_VTU_FUNC1_BUSY;
841 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
842 }
843
844 static void
845 ar8327_vtu_flush(struct ar8216_priv *priv)
846 {
847 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
848 }
849
850 static void
851 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
852 {
853 u32 op;
854 u32 val;
855 int i;
856
857 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
858 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
859 for (i = 0; i < AR8327_NUM_PORTS; i++) {
860 u32 mode;
861
862 if ((port_mask & BIT(i)) == 0)
863 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
864 else if (priv->vlan == 0)
865 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
866 else if (priv->vlan_tagged & BIT(i))
867 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
868 else
869 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
870
871 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
872 }
873 ar8327_vtu_op(priv, op, val);
874 }
875
876 static void
877 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
878 u32 members, u32 pvid)
879 {
880 u32 t;
881 u32 mode;
882
883 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
884 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
885 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
886
887 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
888 switch (egress) {
889 case AR8216_OUT_KEEP:
890 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
891 break;
892 case AR8216_OUT_STRIP_VLAN:
893 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
894 break;
895 case AR8216_OUT_ADD_VLAN:
896 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
897 break;
898 }
899
900 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
901 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
902 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
903
904 t = members;
905 t |= AR8327_PORT_LOOKUP_LEARN;
906 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
907 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
908 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
909 }
910
911 static const struct ar8xxx_chip ar8327_chip = {
912 .caps = AR8XXX_CAP_GIGE,
913 .hw_init = ar8327_hw_init,
914 .init_globals = ar8327_init_globals,
915 .init_port = ar8327_init_port,
916 .setup_port = ar8327_setup_port,
917 .read_port_status = ar8327_read_port_status,
918 .atu_flush = ar8327_atu_flush,
919 .vtu_flush = ar8327_vtu_flush,
920 .vtu_load_vlan = ar8327_vtu_load_vlan,
921 };
922
923 static int
924 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
925 struct switch_val *val)
926 {
927 struct ar8216_priv *priv = to_ar8216(dev);
928 priv->vlan = !!val->value.i;
929 return 0;
930 }
931
932 static int
933 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
934 struct switch_val *val)
935 {
936 struct ar8216_priv *priv = to_ar8216(dev);
937 val->value.i = priv->vlan;
938 return 0;
939 }
940
941
942 static int
943 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
944 {
945 struct ar8216_priv *priv = to_ar8216(dev);
946
947 /* make sure no invalid PVIDs get set */
948
949 if (vlan >= dev->vlans)
950 return -EINVAL;
951
952 priv->pvid[port] = vlan;
953 return 0;
954 }
955
956 static int
957 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
958 {
959 struct ar8216_priv *priv = to_ar8216(dev);
960 *vlan = priv->pvid[port];
961 return 0;
962 }
963
964 static int
965 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
966 struct switch_val *val)
967 {
968 struct ar8216_priv *priv = to_ar8216(dev);
969 priv->vlan_id[val->port_vlan] = val->value.i;
970 return 0;
971 }
972
973 static int
974 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
975 struct switch_val *val)
976 {
977 struct ar8216_priv *priv = to_ar8216(dev);
978 val->value.i = priv->vlan_id[val->port_vlan];
979 return 0;
980 }
981
982 static int
983 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
984 struct switch_port_link *link)
985 {
986 struct ar8216_priv *priv = to_ar8216(dev);
987
988 ar8216_read_port_link(priv, port, link);
989 return 0;
990 }
991
992 static int
993 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
994 {
995 struct ar8216_priv *priv = to_ar8216(dev);
996 u8 ports = priv->vlan_table[val->port_vlan];
997 int i;
998
999 val->len = 0;
1000 for (i = 0; i < dev->ports; i++) {
1001 struct switch_port *p;
1002
1003 if (!(ports & (1 << i)))
1004 continue;
1005
1006 p = &val->value.ports[val->len++];
1007 p->id = i;
1008 if (priv->vlan_tagged & (1 << i))
1009 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1010 else
1011 p->flags = 0;
1012 }
1013 return 0;
1014 }
1015
1016 static int
1017 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1018 {
1019 struct ar8216_priv *priv = to_ar8216(dev);
1020 u8 *vt = &priv->vlan_table[val->port_vlan];
1021 int i, j;
1022
1023 *vt = 0;
1024 for (i = 0; i < val->len; i++) {
1025 struct switch_port *p = &val->value.ports[i];
1026
1027 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1028 priv->vlan_tagged |= (1 << p->id);
1029 } else {
1030 priv->vlan_tagged &= ~(1 << p->id);
1031 priv->pvid[p->id] = val->port_vlan;
1032
1033 /* make sure that an untagged port does not
1034 * appear in other vlans */
1035 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1036 if (j == val->port_vlan)
1037 continue;
1038 priv->vlan_table[j] &= ~(1 << p->id);
1039 }
1040 }
1041
1042 *vt |= 1 << p->id;
1043 }
1044 return 0;
1045 }
1046
1047 static int
1048 ar8216_sw_hw_apply(struct switch_dev *dev)
1049 {
1050 struct ar8216_priv *priv = to_ar8216(dev);
1051 u8 portmask[AR8X16_MAX_PORTS];
1052 int i, j;
1053
1054 mutex_lock(&priv->reg_mutex);
1055 /* flush all vlan translation unit entries */
1056 priv->chip->vtu_flush(priv);
1057
1058 memset(portmask, 0, sizeof(portmask));
1059 if (!priv->init) {
1060 /* calculate the port destination masks and load vlans
1061 * into the vlan translation unit */
1062 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1063 u8 vp = priv->vlan_table[j];
1064
1065 if (!vp)
1066 continue;
1067
1068 for (i = 0; i < dev->ports; i++) {
1069 u8 mask = (1 << i);
1070 if (vp & mask)
1071 portmask[i] |= vp & ~mask;
1072 }
1073
1074 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1075 priv->vlan_table[j]);
1076 }
1077 } else {
1078 /* vlan disabled:
1079 * isolate all ports, but connect them to the cpu port */
1080 for (i = 0; i < dev->ports; i++) {
1081 if (i == AR8216_PORT_CPU)
1082 continue;
1083
1084 portmask[i] = 1 << AR8216_PORT_CPU;
1085 portmask[AR8216_PORT_CPU] |= (1 << i);
1086 }
1087 }
1088
1089 /* update the port destination mask registers and tag settings */
1090 for (i = 0; i < dev->ports; i++) {
1091 int egress, ingress;
1092 int pvid;
1093
1094 if (priv->vlan) {
1095 pvid = priv->vlan_id[priv->pvid[i]];
1096 if (priv->vlan_tagged & (1 << i))
1097 egress = AR8216_OUT_ADD_VLAN;
1098 else
1099 egress = AR8216_OUT_STRIP_VLAN;
1100 ingress = AR8216_IN_SECURE;
1101 } else {
1102 pvid = i;
1103 egress = AR8216_OUT_KEEP;
1104 ingress = AR8216_IN_PORT_ONLY;
1105 }
1106
1107 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1108 pvid);
1109 }
1110 mutex_unlock(&priv->reg_mutex);
1111 return 0;
1112 }
1113
1114 static int
1115 ar8216_sw_reset_switch(struct switch_dev *dev)
1116 {
1117 struct ar8216_priv *priv = to_ar8216(dev);
1118 int i;
1119
1120 mutex_lock(&priv->reg_mutex);
1121 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1122 offsetof(struct ar8216_priv, vlan));
1123
1124 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1125 priv->vlan_id[i] = i;
1126
1127 /* Configure all ports */
1128 for (i = 0; i < dev->ports; i++)
1129 priv->chip->init_port(priv, i);
1130
1131 priv->chip->init_globals(priv);
1132 mutex_unlock(&priv->reg_mutex);
1133
1134 return ar8216_sw_hw_apply(dev);
1135 }
1136
1137 static struct switch_attr ar8216_globals[] = {
1138 {
1139 .type = SWITCH_TYPE_INT,
1140 .name = "enable_vlan",
1141 .description = "Enable VLAN mode",
1142 .set = ar8216_sw_set_vlan,
1143 .get = ar8216_sw_get_vlan,
1144 .max = 1
1145 },
1146 };
1147
1148 static struct switch_attr ar8216_port[] = {
1149 };
1150
1151 static struct switch_attr ar8216_vlan[] = {
1152 {
1153 .type = SWITCH_TYPE_INT,
1154 .name = "vid",
1155 .description = "VLAN ID (0-4094)",
1156 .set = ar8216_sw_set_vid,
1157 .get = ar8216_sw_get_vid,
1158 .max = 4094,
1159 },
1160 };
1161
1162 static const struct switch_dev_ops ar8216_sw_ops = {
1163 .attr_global = {
1164 .attr = ar8216_globals,
1165 .n_attr = ARRAY_SIZE(ar8216_globals),
1166 },
1167 .attr_port = {
1168 .attr = ar8216_port,
1169 .n_attr = ARRAY_SIZE(ar8216_port),
1170 },
1171 .attr_vlan = {
1172 .attr = ar8216_vlan,
1173 .n_attr = ARRAY_SIZE(ar8216_vlan),
1174 },
1175 .get_port_pvid = ar8216_sw_get_pvid,
1176 .set_port_pvid = ar8216_sw_set_pvid,
1177 .get_vlan_ports = ar8216_sw_get_ports,
1178 .set_vlan_ports = ar8216_sw_set_ports,
1179 .apply_config = ar8216_sw_hw_apply,
1180 .reset_switch = ar8216_sw_reset_switch,
1181 .get_port_link = ar8216_sw_get_port_link,
1182 };
1183
1184 static int
1185 ar8216_id_chip(struct ar8216_priv *priv)
1186 {
1187 u32 val;
1188 u16 id;
1189 int i;
1190
1191 priv->chip_type = UNKNOWN;
1192
1193 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1194 if (val == ~0)
1195 return -ENODEV;
1196
1197 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1198 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1199 u16 t;
1200
1201 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1202 if (val == ~0)
1203 return -ENODEV;
1204
1205 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1206 if (t != id)
1207 return -ENODEV;
1208 }
1209
1210 switch (id) {
1211 case 0x0101:
1212 priv->chip_type = AR8216;
1213 priv->chip = &ar8216_chip;
1214 break;
1215 case 0x0301:
1216 priv->chip_type = AR8236;
1217 priv->chip = &ar8236_chip;
1218 break;
1219 case 0x1000:
1220 case 0x1001:
1221 priv->chip_type = AR8316;
1222 priv->chip = &ar8316_chip;
1223 break;
1224 case 0x1202:
1225 priv->chip_type = AR8327;
1226 priv->mii_lo_first = true;
1227 priv->chip = &ar8327_chip;
1228 break;
1229 default:
1230 printk(KERN_DEBUG
1231 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1232 (int)(id >> AR8216_CTRL_VERSION_S),
1233 (int)(id & AR8216_CTRL_REVISION),
1234 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1235 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1236
1237 return -ENODEV;
1238 }
1239
1240 return 0;
1241 }
1242
1243 static int
1244 ar8216_config_init(struct phy_device *pdev)
1245 {
1246 struct ar8216_priv *priv = pdev->priv;
1247 struct net_device *dev = pdev->attached_dev;
1248 struct switch_dev *swdev;
1249 int ret;
1250
1251 if (!priv) {
1252 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1253 if (priv == NULL)
1254 return -ENOMEM;
1255 }
1256
1257 priv->phy = pdev;
1258
1259 ret = ar8216_id_chip(priv);
1260 if (ret)
1261 goto err_free_priv;
1262
1263 if (pdev->addr != 0) {
1264 if (ar8xxx_has_gige(priv)) {
1265 pdev->supported |= SUPPORTED_1000baseT_Full;
1266 pdev->advertising |= ADVERTISED_1000baseT_Full;
1267 }
1268
1269 if (priv->chip_type == AR8316) {
1270 /* check if we're attaching to the switch twice */
1271 pdev = pdev->bus->phy_map[0];
1272 if (!pdev) {
1273 kfree(priv);
1274 return 0;
1275 }
1276
1277 /* switch device has not been initialized, reuse priv */
1278 if (!pdev->priv) {
1279 priv->port4_phy = true;
1280 pdev->priv = priv;
1281 return 0;
1282 }
1283
1284 kfree(priv);
1285
1286 /* switch device has been initialized, reinit */
1287 priv = pdev->priv;
1288 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1289 priv->initialized = false;
1290 priv->port4_phy = true;
1291 ar8316_hw_init(priv);
1292 return 0;
1293 }
1294
1295 kfree(priv);
1296 return 0;
1297 }
1298
1299 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
1300 pdev->attached_dev->name, priv->chip_type);
1301
1302 if (ar8xxx_has_gige(priv))
1303 pdev->supported = SUPPORTED_1000baseT_Full;
1304 else
1305 pdev->supported = SUPPORTED_100baseT_Full;
1306 pdev->advertising = pdev->supported;
1307
1308 mutex_init(&priv->reg_mutex);
1309 priv->read = ar8216_mii_read;
1310 priv->write = ar8216_mii_write;
1311
1312 pdev->priv = priv;
1313
1314 swdev = &priv->dev;
1315 swdev->cpu_port = AR8216_PORT_CPU;
1316 swdev->ops = &ar8216_sw_ops;
1317 swdev->ports = AR8216_NUM_PORTS;
1318
1319 if (priv->chip_type == AR8316) {
1320 swdev->name = "Atheros AR8316";
1321 swdev->vlans = AR8X16_MAX_VLANS;
1322
1323 if (priv->port4_phy) {
1324 /* port 5 connected to the other mac, therefore unusable */
1325 swdev->ports = (AR8216_NUM_PORTS - 1);
1326 }
1327 } else if (priv->chip_type == AR8236) {
1328 swdev->name = "Atheros AR8236";
1329 swdev->vlans = AR8216_NUM_VLANS;
1330 swdev->ports = AR8216_NUM_PORTS;
1331 } else if (priv->chip_type == AR8327) {
1332 swdev->name = "Atheros AR8327";
1333 swdev->vlans = AR8X16_MAX_VLANS;
1334 swdev->ports = AR8327_NUM_PORTS;
1335 } else {
1336 swdev->name = "Atheros AR8216";
1337 swdev->vlans = AR8216_NUM_VLANS;
1338 }
1339
1340 ret = register_switch(&priv->dev, pdev->attached_dev);
1341 if (ret)
1342 goto err_free_priv;
1343
1344 priv->init = true;
1345
1346 ret = priv->chip->hw_init(priv);
1347 if (ret)
1348 goto err_free_priv;
1349
1350 ret = ar8216_sw_reset_switch(&priv->dev);
1351 if (ret)
1352 goto err_free_priv;
1353
1354 dev->phy_ptr = priv;
1355
1356 /* VID fixup only needed on ar8216 */
1357 if (pdev->addr == 0 && priv->chip_type == AR8216) {
1358 pdev->pkt_align = 2;
1359 pdev->netif_receive_skb = ar8216_netif_receive_skb;
1360 pdev->netif_rx = ar8216_netif_rx;
1361 priv->ndo_old = dev->netdev_ops;
1362 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
1363 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
1364 dev->netdev_ops = &priv->ndo;
1365 }
1366
1367 priv->init = false;
1368
1369 return 0;
1370
1371 err_free_priv:
1372 kfree(priv);
1373 return ret;
1374 }
1375
1376 static int
1377 ar8216_read_status(struct phy_device *phydev)
1378 {
1379 struct ar8216_priv *priv = phydev->priv;
1380 struct switch_port_link link;
1381 int ret;
1382
1383 if (phydev->addr != 0)
1384 return genphy_read_status(phydev);
1385
1386 ar8216_read_port_link(priv, phydev->addr, &link);
1387 phydev->link = !!link.link;
1388 if (!phydev->link)
1389 return 0;
1390
1391 switch (link.speed) {
1392 case SWITCH_PORT_SPEED_10:
1393 phydev->speed = SPEED_10;
1394 break;
1395 case SWITCH_PORT_SPEED_100:
1396 phydev->speed = SPEED_100;
1397 break;
1398 case SWITCH_PORT_SPEED_1000:
1399 phydev->speed = SPEED_1000;
1400 break;
1401 default:
1402 phydev->speed = 0;
1403 }
1404 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1405
1406 /* flush the address translation unit */
1407 mutex_lock(&priv->reg_mutex);
1408 ret = priv->chip->atu_flush(priv);
1409 mutex_unlock(&priv->reg_mutex);
1410
1411 phydev->state = PHY_RUNNING;
1412 netif_carrier_on(phydev->attached_dev);
1413 phydev->adjust_link(phydev->attached_dev);
1414
1415 return ret;
1416 }
1417
1418 static int
1419 ar8216_config_aneg(struct phy_device *phydev)
1420 {
1421 if (phydev->addr == 0)
1422 return 0;
1423
1424 return genphy_config_aneg(phydev);
1425 }
1426
1427 static int
1428 ar8216_probe(struct phy_device *pdev)
1429 {
1430 struct ar8216_priv priv;
1431
1432 priv.phy = pdev;
1433 return ar8216_id_chip(&priv);
1434 }
1435
1436 static void
1437 ar8216_remove(struct phy_device *pdev)
1438 {
1439 struct ar8216_priv *priv = pdev->priv;
1440 struct net_device *dev = pdev->attached_dev;
1441
1442 if (!priv)
1443 return;
1444
1445 if (priv->ndo_old && dev)
1446 dev->netdev_ops = priv->ndo_old;
1447 if (pdev->addr == 0)
1448 unregister_switch(&priv->dev);
1449 kfree(priv);
1450 }
1451
1452 static struct phy_driver ar8216_driver = {
1453 .phy_id = 0x004d0000,
1454 .name = "Atheros AR8216/AR8236/AR8316",
1455 .phy_id_mask = 0xffff0000,
1456 .features = PHY_BASIC_FEATURES,
1457 .probe = ar8216_probe,
1458 .remove = ar8216_remove,
1459 .config_init = &ar8216_config_init,
1460 .config_aneg = &ar8216_config_aneg,
1461 .read_status = &ar8216_read_status,
1462 .driver = { .owner = THIS_MODULE },
1463 };
1464
1465 int __init
1466 ar8216_init(void)
1467 {
1468 return phy_driver_register(&ar8216_driver);
1469 }
1470
1471 void __exit
1472 ar8216_exit(void)
1473 {
1474 phy_driver_unregister(&ar8216_driver);
1475 }
1476
1477 module_init(ar8216_init);
1478 module_exit(ar8216_exit);
1479 MODULE_LICENSE("GPL");
1480
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